siop_pci.c revision 1.7
1 /* $NetBSD: siop_pci.c,v 1.7 2000/05/10 17:22:46 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, 21 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 23 * AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/kernel.h> 41 42 #include <machine/endian.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 48 #include <dev/scsipi/scsipi_all.h> 49 #include <dev/scsipi/scsipiconf.h> 50 51 #include <dev/ic/siopvar.h> 52 53 /* structure describing each chip */ 54 struct siop_product_desc { 55 u_int32_t product; 56 int revision; 57 const char *name; 58 int features; /* features are defined in siopvar.h */ 59 u_int8_t maxburst; 60 u_int8_t maxoff; /* maximum supported offset */ 61 u_int8_t clock_div; /* clock divider to use for async. logic */ 62 u_int8_t clock_period; /* clock period (ns * 10) */ 63 }; 64 65 /* List (array, really :) of chips we know how to handle */ 66 const struct siop_product_desc siop_products[] = { 67 { PCI_PRODUCT_SYMBIOS_810, 68 0x00, 69 "Symbios Logic 53c810 (fast scsi)", 70 SF_PCI_RL, 71 4, 8, 3, 250 72 }, 73 { PCI_PRODUCT_SYMBIOS_810, 74 0x10, 75 "Symbios Logic 53c810a (fast scsi)", 76 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF, 77 4, 8, 3, 250 78 }, 79 { PCI_PRODUCT_SYMBIOS_815, 80 0x00, 81 "Symbios Logic 53c815 (fast scsi)", 82 SF_PCI_RL | SF_PCI_BOF, 83 4, 8, 3, 250 84 }, 85 { PCI_PRODUCT_SYMBIOS_820, 86 0x00, 87 "Symbios Logic 53c820 (fast wide scsi)", 88 SF_PCI_RL | SF_BUS_WIDE, 89 4, 8, 3, 250 90 }, 91 { PCI_PRODUCT_SYMBIOS_825, 92 0x00, 93 "Symbios Logic 53c825 (fast wide scsi)", 94 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 95 4, 8, 3, 250 96 }, 97 { PCI_PRODUCT_SYMBIOS_825, 98 0x10, 99 "Symbios Logic 53c825a (fast wide scsi)", 100 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 101 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 102 SF_BUS_WIDE, 103 7, 8, 3, 250 104 }, 105 { PCI_PRODUCT_SYMBIOS_860, 106 0x00, 107 "Symbios Logic 53c860 (ultra scsi)", 108 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 109 SF_CHIP_PF | 110 SF_BUS_ULTRA, 111 4, 8, 5, 125 112 }, 113 { PCI_PRODUCT_SYMBIOS_875, 114 0x00, 115 "Symbios Logic 53c875 (ultra-wide scsi)", 116 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 117 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 118 SF_BUS_ULTRA | SF_BUS_WIDE, 119 7, 16, 5, 125 120 }, 121 { PCI_PRODUCT_SYMBIOS_875, 122 0x02, 123 "Symbios Logic 53c875 (ultra-wide scsi)", 124 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 125 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 126 SF_BUS_ULTRA | SF_BUS_WIDE, 127 7, 16, 5, 125 128 }, 129 { PCI_PRODUCT_SYMBIOS_875J, 130 0x00, 131 "Symbios Logic 53c875j (ultra-wide scsi)", 132 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 133 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 134 SF_BUS_ULTRA | SF_BUS_WIDE, 135 7, 16, 5, 125 136 }, 137 { PCI_PRODUCT_SYMBIOS_885, 138 0x00, 139 "Symbios Logic 53c885 (ultra-wide scsi)", 140 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 141 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 142 SF_BUS_ULTRA | SF_BUS_WIDE, 143 7, 16, 5, 125 144 }, 145 { PCI_PRODUCT_SYMBIOS_895, 146 0x00, 147 "Symbios Logic 53c895 (ultra2-wide scsi)", 148 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 149 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 150 SF_BUS_ULTRA2 | SF_BUS_WIDE, 151 7, 31, 7, 62 152 }, 153 { PCI_PRODUCT_SYMBIOS_896, 154 0x00, 155 "Symbios Logic 53c896 (ultra2-wide scsi)", 156 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 157 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 158 SF_BUS_ULTRA2 | SF_BUS_WIDE, 159 7, 31, 7, 62 160 }, 161 { 0, 162 0x00, 163 NULL, 164 0x00, 165 0, 0, 0, 0 166 }, 167 }; 168 169 const struct siop_product_desc * siop_lookup_product __P((u_int32_t, int)); 170 171 const struct siop_product_desc * 172 siop_lookup_product(id, rev) 173 u_int32_t id; 174 int rev; 175 { 176 const struct siop_product_desc *pp; 177 const struct siop_product_desc *rp = NULL; 178 179 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 180 return NULL; 181 182 for (pp = siop_products; pp->name != NULL; pp++) { 183 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 184 if (rp == NULL || pp->revision > rp->revision) 185 rp = pp; 186 } 187 return rp; 188 } 189 190 /* Driver internal state */ 191 struct siop_pci_softc { 192 struct siop_softc siop; 193 pci_chipset_tag_t sc_pc; /* PCI registers info */ 194 pcitag_t sc_tag; 195 void *sc_ih; /* PCI interrupt handle */ 196 const struct siop_product_desc *sc_pp; /* Adapter description */ 197 }; 198 199 int siop_pci_match __P((struct device *, struct cfdata *, void *)); 200 void siop_pci_attach __P((struct device *, struct device *, void *)); 201 202 struct cfattach siop_pci_ca = { 203 sizeof(struct siop_pci_softc), siop_pci_match, siop_pci_attach 204 }; 205 206 int 207 siop_pci_match(parent, match, aux) 208 struct device *parent; 209 struct cfdata *match; 210 void *aux; 211 { 212 struct pci_attach_args *pa = aux; 213 const struct siop_product_desc *pp; 214 215 /* look if it's a known product */ 216 pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 217 if (pp) 218 return 1; 219 return 0; 220 } 221 222 void 223 siop_pci_attach(parent, self, aux) 224 struct device *parent, *self; 225 void *aux; 226 { 227 struct pci_attach_args *pa = aux; 228 pci_chipset_tag_t pc = pa->pa_pc; 229 pcitag_t tag = pa->pa_tag; 230 struct siop_pci_softc *sc = (struct siop_pci_softc *)self; 231 const char *intrstr; 232 pci_intr_handle_t intrhandle; 233 bus_space_tag_t iot, memt; 234 bus_space_handle_t ioh, memh; 235 pcireg_t memtype; 236 int memh_valid, ioh_valid; 237 bus_addr_t ioaddr, memaddr; 238 239 sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 240 if (sc->sc_pp == NULL) { 241 printf("sym: broken match/attach!!\n"); 242 return; 243 } 244 printf(": %s\n", sc->sc_pp->name); 245 sc->sc_pc = pc; 246 sc->sc_tag = tag; 247 sc->siop.sc_dmat = pa->pa_dmat; 248 249 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 250 switch (memtype) { 251 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 252 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 253 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 254 &memt, &memh, &memaddr, NULL) == 0); 255 break; 256 default: 257 memh_valid = 0; 258 } 259 260 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 261 &iot, &ioh, &ioaddr, NULL) == 0); 262 263 if (memh_valid) { 264 sc->siop.sc_rt = memt; 265 sc->siop.sc_rh = memh; 266 sc->siop.sc_raddr = memaddr; 267 } else if (ioh_valid) { 268 sc->siop.sc_rt = iot; 269 sc->siop.sc_rh = ioh; 270 sc->siop.sc_raddr = ioaddr; 271 } else { 272 printf("%s: unable to map device registers\n", 273 sc->siop.sc_dev.dv_xname); 274 return; 275 } 276 277 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 278 pa->pa_intrline, &intrhandle) != 0) { 279 printf("%s: couldn't map interrupt\n", 280 sc->siop.sc_dev.dv_xname); 281 return; 282 } 283 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 284 sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 285 siop_intr, &sc->siop); 286 if (sc->sc_ih != NULL) { 287 printf("%s: interrupting at %s\n", 288 sc->siop.sc_dev.dv_xname, 289 intrstr ? intrstr : "unknown interrupt"); 290 } else { 291 printf("%s: couldn't establish interrupt", 292 sc->siop.sc_dev.dv_xname); 293 if (intrstr != NULL) 294 printf(" at %s", intrstr); 295 printf("\n"); 296 return; 297 } 298 /* copy interesting infos about the chip */ 299 sc->siop.features = sc->sc_pp->features; 300 sc->siop.maxburst = sc->sc_pp->maxburst; 301 sc->siop.maxoff = sc->sc_pp->maxoff; 302 sc->siop.clock_div = sc->sc_pp->clock_div; 303 sc->siop.clock_period = sc->sc_pp->clock_period; 304 /* attach generic code */ 305 siop_attach(&sc->siop); 306 } 307
Indexes created Mon Sep 29 21:09:56 GMT 2025