siop_pci_common.c revision 1.25 1 1.25 thorpej /* $NetBSD: siop_pci_common.c,v 1.25 2005/06/28 00:28:42 thorpej Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 2000 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer * 3. All advertising materials mentioning features or use of this software
15 1.1 bouyer * must display the following acknowledgement:
16 1.15 bouyer * This product includes software developed by Manuel Bouyer.
17 1.1 bouyer * 4. The name of the author may not be used to endorse or promote products
18 1.1 bouyer * derived from this software without specific prior written permission.
19 1.1 bouyer *
20 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 1.24 perry * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 1.1 bouyer */
31 1.1 bouyer
32 1.1 bouyer /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
33 1.9 lukem
34 1.9 lukem #include <sys/cdefs.h>
35 1.25 thorpej __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.25 2005/06/28 00:28:42 thorpej Exp $");
36 1.1 bouyer
37 1.1 bouyer #include <sys/param.h>
38 1.1 bouyer #include <sys/systm.h>
39 1.1 bouyer #include <sys/device.h>
40 1.1 bouyer #include <sys/malloc.h>
41 1.1 bouyer #include <sys/buf.h>
42 1.1 bouyer #include <sys/kernel.h>
43 1.19 thorpej
44 1.19 thorpej #include <uvm/uvm_extern.h>
45 1.1 bouyer
46 1.1 bouyer #include <machine/endian.h>
47 1.1 bouyer
48 1.1 bouyer #include <dev/pci/pcireg.h>
49 1.1 bouyer #include <dev/pci/pcivar.h>
50 1.1 bouyer #include <dev/pci/pcidevs.h>
51 1.1 bouyer
52 1.1 bouyer #include <dev/scsipi/scsipi_all.h>
53 1.1 bouyer #include <dev/scsipi/scsipiconf.h>
54 1.1 bouyer
55 1.1 bouyer #include <dev/ic/siopreg.h>
56 1.11 bouyer #include <dev/ic/siopvar_common.h>
57 1.1 bouyer #include <dev/pci/siop_pci_common.h>
58 1.1 bouyer
59 1.1 bouyer /* List (array, really :) of chips we know how to handle */
60 1.25 thorpej static const struct siop_product_desc siop_products[] = {
61 1.1 bouyer { PCI_PRODUCT_SYMBIOS_810,
62 1.1 bouyer 0x00,
63 1.1 bouyer "Symbios Logic 53c810 (fast scsi)",
64 1.1 bouyer SF_PCI_RL | SF_CHIP_LS,
65 1.3 bouyer 4, 8, 3, 250, 0
66 1.1 bouyer },
67 1.1 bouyer { PCI_PRODUCT_SYMBIOS_810,
68 1.1 bouyer 0x10,
69 1.1 bouyer "Symbios Logic 53c810a (fast scsi)",
70 1.1 bouyer SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
71 1.3 bouyer 4, 8, 3, 250, 0
72 1.1 bouyer },
73 1.1 bouyer { PCI_PRODUCT_SYMBIOS_815,
74 1.1 bouyer 0x00,
75 1.1 bouyer "Symbios Logic 53c815 (fast scsi)",
76 1.1 bouyer SF_PCI_RL | SF_PCI_BOF,
77 1.3 bouyer 4, 8, 3, 250, 0
78 1.1 bouyer },
79 1.1 bouyer { PCI_PRODUCT_SYMBIOS_820,
80 1.1 bouyer 0x00,
81 1.1 bouyer "Symbios Logic 53c820 (fast wide scsi)",
82 1.1 bouyer SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
83 1.3 bouyer 4, 8, 3, 250, 0
84 1.1 bouyer },
85 1.1 bouyer { PCI_PRODUCT_SYMBIOS_825,
86 1.1 bouyer 0x00,
87 1.1 bouyer "Symbios Logic 53c825 (fast wide scsi)",
88 1.1 bouyer SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
89 1.3 bouyer 4, 8, 3, 250, 0
90 1.1 bouyer },
91 1.1 bouyer { PCI_PRODUCT_SYMBIOS_825,
92 1.1 bouyer 0x10,
93 1.1 bouyer "Symbios Logic 53c825a (fast wide scsi)",
94 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
95 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
96 1.1 bouyer SF_BUS_WIDE,
97 1.3 bouyer 7, 8, 3, 250, 4096
98 1.1 bouyer },
99 1.1 bouyer { PCI_PRODUCT_SYMBIOS_860,
100 1.1 bouyer 0x00,
101 1.1 bouyer "Symbios Logic 53c860 (ultra scsi)",
102 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
103 1.1 bouyer SF_CHIP_PF | SF_CHIP_LS |
104 1.1 bouyer SF_BUS_ULTRA,
105 1.3 bouyer 4, 8, 5, 125, 0
106 1.1 bouyer },
107 1.1 bouyer { PCI_PRODUCT_SYMBIOS_875,
108 1.1 bouyer 0x00,
109 1.1 bouyer "Symbios Logic 53c875 (ultra-wide scsi)",
110 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
111 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
112 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
113 1.3 bouyer 7, 16, 5, 125, 4096
114 1.1 bouyer },
115 1.1 bouyer { PCI_PRODUCT_SYMBIOS_875,
116 1.1 bouyer 0x02,
117 1.1 bouyer "Symbios Logic 53c875 (ultra-wide scsi)",
118 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
119 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
120 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
121 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
122 1.3 bouyer 7, 16, 5, 125, 4096
123 1.1 bouyer },
124 1.1 bouyer { PCI_PRODUCT_SYMBIOS_875J,
125 1.1 bouyer 0x00,
126 1.1 bouyer "Symbios Logic 53c875j (ultra-wide scsi)",
127 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
128 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
129 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
130 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
131 1.3 bouyer 7, 16, 5, 125, 4096
132 1.1 bouyer },
133 1.1 bouyer { PCI_PRODUCT_SYMBIOS_885,
134 1.1 bouyer 0x00,
135 1.1 bouyer "Symbios Logic 53c885 (ultra-wide scsi)",
136 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
137 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
138 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
139 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
140 1.3 bouyer 7, 16, 5, 125, 4096
141 1.1 bouyer },
142 1.1 bouyer { PCI_PRODUCT_SYMBIOS_895,
143 1.1 bouyer 0x00,
144 1.1 bouyer "Symbios Logic 53c895 (ultra2-wide scsi)",
145 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
146 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
147 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
148 1.1 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE,
149 1.3 bouyer 7, 31, 7, 62, 4096
150 1.1 bouyer },
151 1.1 bouyer { PCI_PRODUCT_SYMBIOS_896,
152 1.1 bouyer 0x00,
153 1.1 bouyer "Symbios Logic 53c896 (ultra2-wide scsi)",
154 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
155 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
156 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
157 1.1 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE,
158 1.3 bouyer 7, 31, 7, 62, 8192
159 1.6 thorpej },
160 1.6 thorpej { PCI_PRODUCT_SYMBIOS_895A,
161 1.6 thorpej 0x00,
162 1.6 thorpej "Symbios Logic 53c895a (ultra2-wide scsi)",
163 1.6 thorpej SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
164 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
165 1.6 thorpej SF_CHIP_LS | SF_CHIP_10REGS |
166 1.6 thorpej SF_BUS_ULTRA2 | SF_BUS_WIDE,
167 1.7 bouyer 7, 31, 7, 62, 8192
168 1.7 bouyer },
169 1.7 bouyer { PCI_PRODUCT_SYMBIOS_1010,
170 1.7 bouyer 0x00,
171 1.16 thorpej "Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)",
172 1.14 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
173 1.14 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
174 1.14 bouyer SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR |
175 1.17 bouyer SF_CHIP_GEBUG |
176 1.14 bouyer SF_BUS_ULTRA3 | SF_BUS_WIDE,
177 1.14 bouyer 7, 31, 0, 62, 8192
178 1.14 bouyer },
179 1.14 bouyer { PCI_PRODUCT_SYMBIOS_1010,
180 1.14 bouyer 0x01,
181 1.16 thorpej "Symbios Logic 53c1010-33 (ultra3-wide scsi)",
182 1.10 briggs SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
183 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
184 1.14 bouyer SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
185 1.17 bouyer SF_CHIP_GEBUG |
186 1.14 bouyer SF_BUS_ULTRA3 | SF_BUS_WIDE,
187 1.14 bouyer 7, 62, 0, 62, 8192
188 1.10 briggs },
189 1.10 briggs { PCI_PRODUCT_SYMBIOS_1010_2,
190 1.10 briggs 0x00,
191 1.16 thorpej "Symbios Logic 53c1010-66 (ultra3-wide scsi)",
192 1.7 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
193 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
194 1.14 bouyer SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
195 1.22 bouyer SF_CHIP_AAIP |
196 1.24 perry SF_BUS_ULTRA3 | SF_BUS_WIDE,
197 1.14 bouyer 7, 62, 0, 62, 8192
198 1.6 thorpej },
199 1.6 thorpej { PCI_PRODUCT_SYMBIOS_1510D,
200 1.6 thorpej 0x00,
201 1.6 thorpej "Symbios Logic 53c1510d (ultra2-wide scsi)",
202 1.6 thorpej SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
203 1.6 thorpej SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
204 1.6 thorpej SF_CHIP_LS | SF_CHIP_10REGS |
205 1.6 thorpej SF_BUS_ULTRA2 | SF_BUS_WIDE,
206 1.6 thorpej 7, 31, 7, 62, 4096
207 1.1 bouyer },
208 1.1 bouyer { 0,
209 1.1 bouyer 0x00,
210 1.1 bouyer NULL,
211 1.1 bouyer 0x00,
212 1.3 bouyer 0, 0, 0, 0, 0
213 1.1 bouyer },
214 1.1 bouyer };
215 1.1 bouyer
216 1.1 bouyer const struct siop_product_desc *
217 1.25 thorpej siop_lookup_product(u_int32_t id, int rev)
218 1.1 bouyer {
219 1.1 bouyer const struct siop_product_desc *pp;
220 1.1 bouyer const struct siop_product_desc *rp = NULL;
221 1.1 bouyer
222 1.1 bouyer if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
223 1.1 bouyer return NULL;
224 1.1 bouyer
225 1.1 bouyer for (pp = siop_products; pp->name != NULL; pp++) {
226 1.1 bouyer if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
227 1.1 bouyer if (rp == NULL || pp->revision > rp->revision)
228 1.1 bouyer rp = pp;
229 1.1 bouyer }
230 1.1 bouyer return rp;
231 1.1 bouyer }
232 1.1 bouyer
233 1.1 bouyer int
234 1.25 thorpej siop_pci_attach_common(struct siop_pci_common_softc *pci_sc,
235 1.25 thorpej struct siop_common_softc *siop_sc, struct pci_attach_args *pa,
236 1.25 thorpej int (*intr)(void *))
237 1.1 bouyer {
238 1.1 bouyer pci_chipset_tag_t pc = pa->pa_pc;
239 1.24 perry pcitag_t tag = pa->pa_tag;
240 1.1 bouyer const char *intrstr;
241 1.1 bouyer pci_intr_handle_t intrhandle;
242 1.1 bouyer bus_space_tag_t iot, memt;
243 1.1 bouyer bus_space_handle_t ioh, memh;
244 1.1 bouyer pcireg_t memtype;
245 1.1 bouyer int memh_valid, ioh_valid;
246 1.1 bouyer bus_addr_t ioaddr, memaddr;
247 1.1 bouyer
248 1.18 thorpej aprint_naive(": SCSI controller\n");
249 1.18 thorpej
250 1.11 bouyer pci_sc->sc_pp =
251 1.11 bouyer siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
252 1.11 bouyer if (pci_sc->sc_pp == NULL) {
253 1.18 thorpej aprint_error("sym: broken match/attach!!\n");
254 1.1 bouyer return 0;
255 1.1 bouyer }
256 1.2 bouyer /* copy interesting infos about the chip */
257 1.11 bouyer siop_sc->features = pci_sc->sc_pp->features;
258 1.13 bouyer #ifdef SIOP_SYMLED /* XXX Should be a devprop! */
259 1.13 bouyer siop_sc->features |= SF_CHIP_LED0;
260 1.13 bouyer #endif
261 1.11 bouyer siop_sc->maxburst = pci_sc->sc_pp->maxburst;
262 1.11 bouyer siop_sc->maxoff = pci_sc->sc_pp->maxoff;
263 1.11 bouyer siop_sc->clock_div = pci_sc->sc_pp->clock_div;
264 1.11 bouyer siop_sc->clock_period = pci_sc->sc_pp->clock_period;
265 1.11 bouyer siop_sc->ram_size = pci_sc->sc_pp->ram_size;
266 1.11 bouyer
267 1.11 bouyer siop_sc->sc_reset = siop_pci_reset;
268 1.18 thorpej aprint_normal(": %s\n", pci_sc->sc_pp->name);
269 1.11 bouyer pci_sc->sc_pc = pc;
270 1.11 bouyer pci_sc->sc_tag = tag;
271 1.11 bouyer siop_sc->sc_dmat = pa->pa_dmat;
272 1.1 bouyer
273 1.1 bouyer memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
274 1.1 bouyer switch (memtype) {
275 1.1 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
276 1.1 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
277 1.1 bouyer memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
278 1.1 bouyer &memt, &memh, &memaddr, NULL) == 0);
279 1.1 bouyer break;
280 1.1 bouyer default:
281 1.1 bouyer memh_valid = 0;
282 1.1 bouyer }
283 1.1 bouyer
284 1.1 bouyer ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
285 1.1 bouyer &iot, &ioh, &ioaddr, NULL) == 0);
286 1.1 bouyer
287 1.1 bouyer if (memh_valid) {
288 1.11 bouyer siop_sc->sc_rt = memt;
289 1.11 bouyer siop_sc->sc_rh = memh;
290 1.11 bouyer siop_sc->sc_raddr = memaddr;
291 1.1 bouyer } else if (ioh_valid) {
292 1.11 bouyer siop_sc->sc_rt = iot;
293 1.11 bouyer siop_sc->sc_rh = ioh;
294 1.11 bouyer siop_sc->sc_raddr = ioaddr;
295 1.1 bouyer } else {
296 1.18 thorpej aprint_error("%s: unable to map device registers\n",
297 1.11 bouyer siop_sc->sc_dev.dv_xname);
298 1.1 bouyer return 0;
299 1.1 bouyer }
300 1.1 bouyer
301 1.11 bouyer if (siop_sc->features & SF_CHIP_RAM) {
302 1.4 matt int bar;
303 1.4 matt switch (memtype) {
304 1.4 matt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
305 1.4 matt bar = 0x18;
306 1.4 matt break;
307 1.4 matt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
308 1.4 matt bar = 0x1c;
309 1.20 christos break;
310 1.20 christos default:
311 1.20 christos aprint_error("%s: invalid memory type %d\n",
312 1.20 christos siop_sc->sc_dev.dv_xname, memtype);
313 1.21 christos return 0;
314 1.4 matt }
315 1.4 matt if (pci_mapreg_map(pa, bar, memtype, 0,
316 1.11 bouyer &siop_sc->sc_ramt, &siop_sc->sc_ramh,
317 1.11 bouyer &siop_sc->sc_scriptaddr, NULL) == 0) {
318 1.18 thorpej aprint_normal("%s: using on-board RAM\n",
319 1.11 bouyer siop_sc->sc_dev.dv_xname);
320 1.2 bouyer } else {
321 1.18 thorpej aprint_error("%s: can't map on-board RAM\n",
322 1.11 bouyer siop_sc->sc_dev.dv_xname);
323 1.11 bouyer siop_sc->features &= ~SF_CHIP_RAM;
324 1.2 bouyer }
325 1.2 bouyer }
326 1.2 bouyer
327 1.5 sommerfe if (pci_intr_map(pa, &intrhandle) != 0) {
328 1.18 thorpej aprint_error("%s: couldn't map interrupt\n",
329 1.11 bouyer siop_sc->sc_dev.dv_xname);
330 1.1 bouyer return 0;
331 1.1 bouyer }
332 1.1 bouyer intrstr = pci_intr_string(pa->pa_pc, intrhandle);
333 1.11 bouyer pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
334 1.11 bouyer intr, siop_sc);
335 1.11 bouyer if (pci_sc->sc_ih != NULL) {
336 1.18 thorpej aprint_normal("%s: interrupting at %s\n",
337 1.11 bouyer siop_sc->sc_dev.dv_xname,
338 1.1 bouyer intrstr ? intrstr : "unknown interrupt");
339 1.1 bouyer } else {
340 1.18 thorpej aprint_error("%s: couldn't establish interrupt",
341 1.11 bouyer siop_sc->sc_dev.dv_xname);
342 1.1 bouyer if (intrstr != NULL)
343 1.18 thorpej aprint_normal(" at %s", intrstr);
344 1.18 thorpej aprint_normal("\n");
345 1.1 bouyer return 0;
346 1.1 bouyer }
347 1.1 bouyer return 1;
348 1.1 bouyer }
349 1.1 bouyer
350 1.1 bouyer void
351 1.25 thorpej siop_pci_reset(struct siop_common_softc *sc)
352 1.1 bouyer {
353 1.1 bouyer int dmode;
354 1.1 bouyer
355 1.1 bouyer dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);
356 1.1 bouyer if (sc->features & SF_PCI_RL)
357 1.1 bouyer dmode |= DMODE_ERL;
358 1.1 bouyer if (sc->features & SF_PCI_RM)
359 1.1 bouyer dmode |= DMODE_ERMP;
360 1.1 bouyer if (sc->features & SF_PCI_BOF)
361 1.1 bouyer dmode |= DMODE_BOF;
362 1.1 bouyer if (sc->features & SF_PCI_CLS)
363 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
364 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |
365 1.1 bouyer DCNTL_CLSE);
366 1.1 bouyer if (sc->features & SF_PCI_WRI)
367 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
368 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
369 1.1 bouyer CTEST3_WRIE);
370 1.1 bouyer if (sc->maxburst) {
371 1.1 bouyer int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,
372 1.1 bouyer SIOP_CTEST5);
373 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
374 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &
375 1.1 bouyer ~CTEST4_BDIS);
376 1.1 bouyer dmode &= ~DMODE_BL_MASK;
377 1.1 bouyer dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;
378 1.1 bouyer ctest5 &= ~CTEST5_BBCK;
379 1.1 bouyer ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
380 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
381 1.1 bouyer } else {
382 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
383 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
384 1.1 bouyer CTEST4_BDIS);
385 1.1 bouyer }
386 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);
387 1.1 bouyer }
388