siop_pci_common.c revision 1.3.2.5
1 1.3.2.5 bouyer /* $NetBSD: siop_pci_common.c,v 1.3.2.5 2001/01/18 09:23:30 bouyer Exp $ */ 2 1.3.2.2 bouyer 3 1.3.2.2 bouyer /* 4 1.3.2.2 bouyer * Copyright (c) 2000 Manuel Bouyer. 5 1.3.2.2 bouyer * 6 1.3.2.2 bouyer * Redistribution and use in source and binary forms, with or without 7 1.3.2.2 bouyer * modification, are permitted provided that the following conditions 8 1.3.2.2 bouyer * are met: 9 1.3.2.2 bouyer * 1. Redistributions of source code must retain the above copyright 10 1.3.2.2 bouyer * notice, this list of conditions and the following disclaimer. 11 1.3.2.2 bouyer * 2. Redistributions in binary form must reproduce the above copyright 12 1.3.2.2 bouyer * notice, this list of conditions and the following disclaimer in the 13 1.3.2.2 bouyer * documentation and/or other materials provided with the distribution. 14 1.3.2.2 bouyer * 3. All advertising materials mentioning features or use of this software 15 1.3.2.2 bouyer * must display the following acknowledgement: 16 1.3.2.2 bouyer * This product includes software developed by Manuel Bouyer 17 1.3.2.2 bouyer * 4. The name of the author may not be used to endorse or promote products 18 1.3.2.2 bouyer * derived from this software without specific prior written permission. 19 1.3.2.2 bouyer * 20 1.3.2.2 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 1.3.2.2 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 1.3.2.2 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 1.3.2.2 bouyer * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 1.3.2.2 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 1.3.2.2 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 1.3.2.2 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 1.3.2.2 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 1.3.2.2 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 1.3.2.2 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 1.3.2.2 bouyer */ 31 1.3.2.2 bouyer 32 1.3.2.2 bouyer /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 33 1.3.2.2 bouyer 34 1.3.2.2 bouyer #include <sys/param.h> 35 1.3.2.2 bouyer #include <sys/systm.h> 36 1.3.2.2 bouyer #include <sys/device.h> 37 1.3.2.2 bouyer #include <sys/malloc.h> 38 1.3.2.2 bouyer #include <sys/buf.h> 39 1.3.2.2 bouyer #include <sys/kernel.h> 40 1.3.2.2 bouyer 41 1.3.2.2 bouyer #include <machine/endian.h> 42 1.3.2.2 bouyer 43 1.3.2.2 bouyer #include <dev/pci/pcireg.h> 44 1.3.2.2 bouyer #include <dev/pci/pcivar.h> 45 1.3.2.2 bouyer #include <dev/pci/pcidevs.h> 46 1.3.2.2 bouyer 47 1.3.2.2 bouyer #include <dev/scsipi/scsipi_all.h> 48 1.3.2.2 bouyer #include <dev/scsipi/scsipiconf.h> 49 1.3.2.2 bouyer 50 1.3.2.2 bouyer #include <dev/ic/siopreg.h> 51 1.3.2.2 bouyer #include <dev/ic/siopvar.h> 52 1.3.2.2 bouyer #include <dev/pci/siop_pci_common.h> 53 1.3.2.2 bouyer 54 1.3.2.2 bouyer /* List (array, really :) of chips we know how to handle */ 55 1.3.2.2 bouyer const struct siop_product_desc siop_products[] = { 56 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_810, 57 1.3.2.2 bouyer 0x00, 58 1.3.2.2 bouyer "Symbios Logic 53c810 (fast scsi)", 59 1.3.2.2 bouyer SF_PCI_RL | SF_CHIP_LS, 60 1.3.2.2 bouyer 4, 8, 3, 250, 0 61 1.3.2.2 bouyer }, 62 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_810, 63 1.3.2.2 bouyer 0x10, 64 1.3.2.2 bouyer "Symbios Logic 53c810a (fast scsi)", 65 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 66 1.3.2.2 bouyer 4, 8, 3, 250, 0 67 1.3.2.2 bouyer }, 68 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_815, 69 1.3.2.2 bouyer 0x00, 70 1.3.2.2 bouyer "Symbios Logic 53c815 (fast scsi)", 71 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_BOF, 72 1.3.2.2 bouyer 4, 8, 3, 250, 0 73 1.3.2.2 bouyer }, 74 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_820, 75 1.3.2.2 bouyer 0x00, 76 1.3.2.2 bouyer "Symbios Logic 53c820 (fast wide scsi)", 77 1.3.2.2 bouyer SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 78 1.3.2.2 bouyer 4, 8, 3, 250, 0 79 1.3.2.2 bouyer }, 80 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_825, 81 1.3.2.2 bouyer 0x00, 82 1.3.2.2 bouyer "Symbios Logic 53c825 (fast wide scsi)", 83 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 84 1.3.2.2 bouyer 4, 8, 3, 250, 0 85 1.3.2.2 bouyer }, 86 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_825, 87 1.3.2.2 bouyer 0x10, 88 1.3.2.2 bouyer "Symbios Logic 53c825a (fast wide scsi)", 89 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 90 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 91 1.3.2.2 bouyer SF_BUS_WIDE, 92 1.3.2.2 bouyer 7, 8, 3, 250, 4096 93 1.3.2.2 bouyer }, 94 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_860, 95 1.3.2.2 bouyer 0x00, 96 1.3.2.2 bouyer "Symbios Logic 53c860 (ultra scsi)", 97 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 98 1.3.2.2 bouyer SF_CHIP_PF | SF_CHIP_LS | 99 1.3.2.2 bouyer SF_BUS_ULTRA, 100 1.3.2.2 bouyer 4, 8, 5, 125, 0 101 1.3.2.2 bouyer }, 102 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_875, 103 1.3.2.2 bouyer 0x00, 104 1.3.2.2 bouyer "Symbios Logic 53c875 (ultra-wide scsi)", 105 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 106 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 107 1.3.2.2 bouyer SF_BUS_ULTRA | SF_BUS_WIDE, 108 1.3.2.2 bouyer 7, 16, 5, 125, 4096 109 1.3.2.2 bouyer }, 110 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_875, 111 1.3.2.2 bouyer 0x02, 112 1.3.2.2 bouyer "Symbios Logic 53c875 (ultra-wide scsi)", 113 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 114 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 115 1.3.2.2 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 116 1.3.2.2 bouyer SF_BUS_ULTRA | SF_BUS_WIDE, 117 1.3.2.2 bouyer 7, 16, 5, 125, 4096 118 1.3.2.2 bouyer }, 119 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_875J, 120 1.3.2.2 bouyer 0x00, 121 1.3.2.2 bouyer "Symbios Logic 53c875j (ultra-wide scsi)", 122 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 123 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 124 1.3.2.2 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 125 1.3.2.2 bouyer SF_BUS_ULTRA | SF_BUS_WIDE, 126 1.3.2.2 bouyer 7, 16, 5, 125, 4096 127 1.3.2.2 bouyer }, 128 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_885, 129 1.3.2.2 bouyer 0x00, 130 1.3.2.2 bouyer "Symbios Logic 53c885 (ultra-wide scsi)", 131 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 132 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 133 1.3.2.2 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 134 1.3.2.2 bouyer SF_BUS_ULTRA | SF_BUS_WIDE, 135 1.3.2.2 bouyer 7, 16, 5, 125, 4096 136 1.3.2.2 bouyer }, 137 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_895, 138 1.3.2.2 bouyer 0x00, 139 1.3.2.2 bouyer "Symbios Logic 53c895 (ultra2-wide scsi)", 140 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 141 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 142 1.3.2.2 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 143 1.3.2.2 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE, 144 1.3.2.2 bouyer 7, 31, 7, 62, 4096 145 1.3.2.2 bouyer }, 146 1.3.2.2 bouyer { PCI_PRODUCT_SYMBIOS_896, 147 1.3.2.2 bouyer 0x00, 148 1.3.2.2 bouyer "Symbios Logic 53c896 (ultra2-wide scsi)", 149 1.3.2.2 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 150 1.3.2.2 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 151 1.3.2.2 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 152 1.3.2.2 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE, 153 1.3.2.2 bouyer 7, 31, 7, 62, 8192 154 1.3.2.2 bouyer }, 155 1.3.2.5 bouyer { PCI_PRODUCT_SYMBIOS_895A, 156 1.3.2.5 bouyer 0x00, 157 1.3.2.5 bouyer "Symbios Logic 53c895a (ultra2-wide scsi)", 158 1.3.2.5 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 159 1.3.2.5 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 160 1.3.2.5 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 161 1.3.2.5 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE, 162 1.3.2.5 bouyer 7, 31, 7, 62, 8192 163 1.3.2.5 bouyer }, 164 1.3.2.5 bouyer { PCI_PRODUCT_SYMBIOS_1510D, 165 1.3.2.5 bouyer 0x00, 166 1.3.2.5 bouyer "Symbios Logic 53c1510d (ultra2-wide scsi)", 167 1.3.2.5 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 168 1.3.2.5 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 169 1.3.2.5 bouyer SF_CHIP_LS | SF_CHIP_10REGS | 170 1.3.2.5 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE, 171 1.3.2.5 bouyer 7, 31, 7, 62, 4096 172 1.3.2.5 bouyer }, 173 1.3.2.2 bouyer { 0, 174 1.3.2.2 bouyer 0x00, 175 1.3.2.2 bouyer NULL, 176 1.3.2.2 bouyer 0x00, 177 1.3.2.2 bouyer 0, 0, 0, 0, 0 178 1.3.2.2 bouyer }, 179 1.3.2.2 bouyer }; 180 1.3.2.2 bouyer 181 1.3.2.2 bouyer const struct siop_product_desc * 182 1.3.2.2 bouyer siop_lookup_product(id, rev) 183 1.3.2.2 bouyer u_int32_t id; 184 1.3.2.2 bouyer int rev; 185 1.3.2.2 bouyer { 186 1.3.2.2 bouyer const struct siop_product_desc *pp; 187 1.3.2.2 bouyer const struct siop_product_desc *rp = NULL; 188 1.3.2.2 bouyer 189 1.3.2.2 bouyer if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 190 1.3.2.2 bouyer return NULL; 191 1.3.2.2 bouyer 192 1.3.2.2 bouyer for (pp = siop_products; pp->name != NULL; pp++) { 193 1.3.2.2 bouyer if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 194 1.3.2.2 bouyer if (rp == NULL || pp->revision > rp->revision) 195 1.3.2.2 bouyer rp = pp; 196 1.3.2.2 bouyer } 197 1.3.2.2 bouyer return rp; 198 1.3.2.2 bouyer } 199 1.3.2.2 bouyer 200 1.3.2.2 bouyer int 201 1.3.2.2 bouyer siop_pci_attach_common(sc, pa) 202 1.3.2.2 bouyer struct siop_pci_softc *sc; 203 1.3.2.2 bouyer struct pci_attach_args *pa; 204 1.3.2.2 bouyer { 205 1.3.2.2 bouyer pci_chipset_tag_t pc = pa->pa_pc; 206 1.3.2.2 bouyer pcitag_t tag = pa->pa_tag; 207 1.3.2.2 bouyer const char *intrstr; 208 1.3.2.2 bouyer pci_intr_handle_t intrhandle; 209 1.3.2.2 bouyer bus_space_tag_t iot, memt; 210 1.3.2.2 bouyer bus_space_handle_t ioh, memh; 211 1.3.2.2 bouyer pcireg_t memtype; 212 1.3.2.2 bouyer int memh_valid, ioh_valid; 213 1.3.2.2 bouyer bus_addr_t ioaddr, memaddr; 214 1.3.2.2 bouyer 215 1.3.2.2 bouyer sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 216 1.3.2.2 bouyer if (sc->sc_pp == NULL) { 217 1.3.2.2 bouyer printf("sym: broken match/attach!!\n"); 218 1.3.2.2 bouyer return 0; 219 1.3.2.2 bouyer } 220 1.3.2.2 bouyer /* copy interesting infos about the chip */ 221 1.3.2.2 bouyer sc->siop.features = sc->sc_pp->features; 222 1.3.2.2 bouyer sc->siop.maxburst = sc->sc_pp->maxburst; 223 1.3.2.2 bouyer sc->siop.maxoff = sc->sc_pp->maxoff; 224 1.3.2.2 bouyer sc->siop.clock_div = sc->sc_pp->clock_div; 225 1.3.2.2 bouyer sc->siop.clock_period = sc->sc_pp->clock_period; 226 1.3.2.2 bouyer sc->siop.ram_size = sc->sc_pp->ram_size; 227 1.3.2.2 bouyer 228 1.3.2.2 bouyer sc->siop.sc_reset = siop_pci_reset; 229 1.3.2.2 bouyer printf(": %s\n", sc->sc_pp->name); 230 1.3.2.2 bouyer sc->sc_pc = pc; 231 1.3.2.2 bouyer sc->sc_tag = tag; 232 1.3.2.2 bouyer sc->siop.sc_dmat = pa->pa_dmat; 233 1.3.2.2 bouyer 234 1.3.2.2 bouyer memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 235 1.3.2.2 bouyer switch (memtype) { 236 1.3.2.2 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 237 1.3.2.2 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 238 1.3.2.2 bouyer memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 239 1.3.2.2 bouyer &memt, &memh, &memaddr, NULL) == 0); 240 1.3.2.2 bouyer break; 241 1.3.2.2 bouyer default: 242 1.3.2.2 bouyer memh_valid = 0; 243 1.3.2.2 bouyer } 244 1.3.2.2 bouyer 245 1.3.2.2 bouyer ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 246 1.3.2.2 bouyer &iot, &ioh, &ioaddr, NULL) == 0); 247 1.3.2.2 bouyer 248 1.3.2.2 bouyer if (memh_valid) { 249 1.3.2.2 bouyer sc->siop.sc_rt = memt; 250 1.3.2.2 bouyer sc->siop.sc_rh = memh; 251 1.3.2.2 bouyer sc->siop.sc_raddr = memaddr; 252 1.3.2.2 bouyer } else if (ioh_valid) { 253 1.3.2.2 bouyer sc->siop.sc_rt = iot; 254 1.3.2.2 bouyer sc->siop.sc_rh = ioh; 255 1.3.2.2 bouyer sc->siop.sc_raddr = ioaddr; 256 1.3.2.2 bouyer } else { 257 1.3.2.2 bouyer printf("%s: unable to map device registers\n", 258 1.3.2.2 bouyer sc->siop.sc_dev.dv_xname); 259 1.3.2.2 bouyer return 0; 260 1.3.2.2 bouyer } 261 1.3.2.2 bouyer 262 1.3.2.2 bouyer if (sc->siop.features & SF_CHIP_RAM) { 263 1.3.2.3 bouyer int bar; 264 1.3.2.3 bouyer switch (memtype) { 265 1.3.2.3 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 266 1.3.2.3 bouyer bar = 0x18; 267 1.3.2.3 bouyer break; 268 1.3.2.3 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 269 1.3.2.3 bouyer bar = 0x1c; 270 1.3.2.3 bouyer break; 271 1.3.2.3 bouyer } 272 1.3.2.3 bouyer if (pci_mapreg_map(pa, bar, memtype, 0, 273 1.3.2.2 bouyer &sc->siop.sc_ramt, &sc->siop.sc_ramh, 274 1.3.2.2 bouyer &sc->siop.sc_scriptaddr, NULL) == 0) { 275 1.3.2.2 bouyer printf("%s: using on-board RAM\n", 276 1.3.2.2 bouyer sc->siop.sc_dev.dv_xname); 277 1.3.2.2 bouyer } else { 278 1.3.2.2 bouyer printf("%s: can't map on-board RAM\n", 279 1.3.2.2 bouyer sc->siop.sc_dev.dv_xname); 280 1.3.2.2 bouyer sc->siop.features &= ~SF_CHIP_RAM; 281 1.3.2.2 bouyer } 282 1.3.2.2 bouyer } 283 1.3.2.2 bouyer 284 1.3.2.4 bouyer if (pci_intr_map(pa, &intrhandle) != 0) { 285 1.3.2.2 bouyer printf("%s: couldn't map interrupt\n", 286 1.3.2.2 bouyer sc->siop.sc_dev.dv_xname); 287 1.3.2.2 bouyer return 0; 288 1.3.2.2 bouyer } 289 1.3.2.2 bouyer intrstr = pci_intr_string(pa->pa_pc, intrhandle); 290 1.3.2.2 bouyer sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 291 1.3.2.2 bouyer siop_intr, &sc->siop); 292 1.3.2.2 bouyer if (sc->sc_ih != NULL) { 293 1.3.2.2 bouyer printf("%s: interrupting at %s\n", 294 1.3.2.2 bouyer sc->siop.sc_dev.dv_xname, 295 1.3.2.2 bouyer intrstr ? intrstr : "unknown interrupt"); 296 1.3.2.2 bouyer } else { 297 1.3.2.2 bouyer printf("%s: couldn't establish interrupt", 298 1.3.2.2 bouyer sc->siop.sc_dev.dv_xname); 299 1.3.2.2 bouyer if (intrstr != NULL) 300 1.3.2.2 bouyer printf(" at %s", intrstr); 301 1.3.2.2 bouyer printf("\n"); 302 1.3.2.2 bouyer return 0; 303 1.3.2.2 bouyer } 304 1.3.2.2 bouyer return 1; 305 1.3.2.2 bouyer } 306 1.3.2.2 bouyer 307 1.3.2.2 bouyer void 308 1.3.2.2 bouyer siop_pci_reset(sc) 309 1.3.2.2 bouyer struct siop_softc *sc; 310 1.3.2.2 bouyer { 311 1.3.2.2 bouyer int dmode; 312 1.3.2.2 bouyer 313 1.3.2.2 bouyer dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 314 1.3.2.2 bouyer if (sc->features & SF_PCI_RL) 315 1.3.2.2 bouyer dmode |= DMODE_ERL; 316 1.3.2.2 bouyer if (sc->features & SF_PCI_RM) 317 1.3.2.2 bouyer dmode |= DMODE_ERMP; 318 1.3.2.2 bouyer if (sc->features & SF_PCI_BOF) 319 1.3.2.2 bouyer dmode |= DMODE_BOF; 320 1.3.2.2 bouyer if (sc->features & SF_PCI_CLS) 321 1.3.2.2 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 322 1.3.2.2 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 323 1.3.2.2 bouyer DCNTL_CLSE); 324 1.3.2.2 bouyer if (sc->features & SF_PCI_WRI) 325 1.3.2.2 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 326 1.3.2.2 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 327 1.3.2.2 bouyer CTEST3_WRIE); 328 1.3.2.2 bouyer if (sc->maxburst) { 329 1.3.2.2 bouyer int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 330 1.3.2.2 bouyer SIOP_CTEST5); 331 1.3.2.2 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 332 1.3.2.2 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 333 1.3.2.2 bouyer ~CTEST4_BDIS); 334 1.3.2.2 bouyer dmode &= ~DMODE_BL_MASK; 335 1.3.2.2 bouyer dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 336 1.3.2.2 bouyer ctest5 &= ~CTEST5_BBCK; 337 1.3.2.2 bouyer ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 338 1.3.2.2 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 339 1.3.2.2 bouyer } else { 340 1.3.2.2 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 341 1.3.2.2 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 342 1.3.2.2 bouyer CTEST4_BDIS); 343 1.3.2.2 bouyer } 344 1.3.2.2 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 345 1.3.2.2 bouyer } 346
Indexes created Thu Oct 02 14:10:14 GMT 2025