siop_pci_common.c revision 1.38 1 1.38 thorpej /* $NetBSD: siop_pci_common.c,v 1.38 2022/09/25 17:52:25 thorpej Exp $ */
2 1.1 bouyer
3 1.1 bouyer /*
4 1.1 bouyer * Copyright (c) 2000 Manuel Bouyer.
5 1.1 bouyer *
6 1.1 bouyer * Redistribution and use in source and binary forms, with or without
7 1.1 bouyer * modification, are permitted provided that the following conditions
8 1.1 bouyer * are met:
9 1.1 bouyer * 1. Redistributions of source code must retain the above copyright
10 1.1 bouyer * notice, this list of conditions and the following disclaimer.
11 1.1 bouyer * 2. Redistributions in binary form must reproduce the above copyright
12 1.1 bouyer * notice, this list of conditions and the following disclaimer in the
13 1.1 bouyer * documentation and/or other materials provided with the distribution.
14 1.1 bouyer *
15 1.1 bouyer * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 1.1 bouyer * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 1.1 bouyer * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 1.24 perry * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 1.1 bouyer * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 1.1 bouyer * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 1.1 bouyer * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 1.1 bouyer * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 1.1 bouyer * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 1.1 bouyer * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 1.1 bouyer */
26 1.1 bouyer
27 1.1 bouyer /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */
28 1.9 lukem
29 1.9 lukem #include <sys/cdefs.h>
30 1.38 thorpej __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.38 2022/09/25 17:52:25 thorpej Exp $");
31 1.1 bouyer
32 1.1 bouyer #include <sys/param.h>
33 1.1 bouyer #include <sys/systm.h>
34 1.1 bouyer #include <sys/device.h>
35 1.1 bouyer #include <sys/buf.h>
36 1.1 bouyer #include <sys/kernel.h>
37 1.19 thorpej
38 1.1 bouyer #include <machine/endian.h>
39 1.1 bouyer
40 1.1 bouyer #include <dev/pci/pcireg.h>
41 1.1 bouyer #include <dev/pci/pcivar.h>
42 1.1 bouyer #include <dev/pci/pcidevs.h>
43 1.1 bouyer
44 1.1 bouyer #include <dev/scsipi/scsipi_all.h>
45 1.1 bouyer #include <dev/scsipi/scsipiconf.h>
46 1.1 bouyer
47 1.1 bouyer #include <dev/ic/siopreg.h>
48 1.11 bouyer #include <dev/ic/siopvar_common.h>
49 1.1 bouyer #include <dev/pci/siop_pci_common.h>
50 1.1 bouyer
51 1.1 bouyer /* List (array, really :) of chips we know how to handle */
52 1.25 thorpej static const struct siop_product_desc siop_products[] = {
53 1.1 bouyer { PCI_PRODUCT_SYMBIOS_810,
54 1.1 bouyer 0x00,
55 1.1 bouyer "Symbios Logic 53c810 (fast scsi)",
56 1.1 bouyer SF_PCI_RL | SF_CHIP_LS,
57 1.3 bouyer 4, 8, 3, 250, 0
58 1.1 bouyer },
59 1.1 bouyer { PCI_PRODUCT_SYMBIOS_810,
60 1.1 bouyer 0x10,
61 1.1 bouyer "Symbios Logic 53c810a (fast scsi)",
62 1.1 bouyer SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
63 1.3 bouyer 4, 8, 3, 250, 0
64 1.1 bouyer },
65 1.36 flxd { PCI_PRODUCT_SYMBIOS_810AP,
66 1.36 flxd 0x00,
67 1.36 flxd "Symbios Logic 53c810ap (fast scsi)",
68 1.36 flxd SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS,
69 1.36 flxd 4, 8, 3, 250, 0
70 1.36 flxd },
71 1.1 bouyer { PCI_PRODUCT_SYMBIOS_815,
72 1.1 bouyer 0x00,
73 1.1 bouyer "Symbios Logic 53c815 (fast scsi)",
74 1.1 bouyer SF_PCI_RL | SF_PCI_BOF,
75 1.3 bouyer 4, 8, 3, 250, 0
76 1.1 bouyer },
77 1.1 bouyer { PCI_PRODUCT_SYMBIOS_820,
78 1.1 bouyer 0x00,
79 1.1 bouyer "Symbios Logic 53c820 (fast wide scsi)",
80 1.1 bouyer SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE,
81 1.3 bouyer 4, 8, 3, 250, 0
82 1.1 bouyer },
83 1.1 bouyer { PCI_PRODUCT_SYMBIOS_825,
84 1.1 bouyer 0x00,
85 1.1 bouyer "Symbios Logic 53c825 (fast wide scsi)",
86 1.1 bouyer SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE,
87 1.3 bouyer 4, 8, 3, 250, 0
88 1.1 bouyer },
89 1.1 bouyer { PCI_PRODUCT_SYMBIOS_825,
90 1.1 bouyer 0x10,
91 1.1 bouyer "Symbios Logic 53c825a (fast wide scsi)",
92 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
93 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
94 1.1 bouyer SF_BUS_WIDE,
95 1.3 bouyer 7, 8, 3, 250, 4096
96 1.1 bouyer },
97 1.1 bouyer { PCI_PRODUCT_SYMBIOS_860,
98 1.1 bouyer 0x00,
99 1.1 bouyer "Symbios Logic 53c860 (ultra scsi)",
100 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
101 1.1 bouyer SF_CHIP_PF | SF_CHIP_LS |
102 1.1 bouyer SF_BUS_ULTRA,
103 1.3 bouyer 4, 8, 5, 125, 0
104 1.1 bouyer },
105 1.1 bouyer { PCI_PRODUCT_SYMBIOS_875,
106 1.1 bouyer 0x00,
107 1.1 bouyer "Symbios Logic 53c875 (ultra-wide scsi)",
108 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
109 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS |
110 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
111 1.3 bouyer 7, 16, 5, 125, 4096
112 1.1 bouyer },
113 1.1 bouyer { PCI_PRODUCT_SYMBIOS_875,
114 1.1 bouyer 0x02,
115 1.1 bouyer "Symbios Logic 53c875 (ultra-wide scsi)",
116 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
117 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
118 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
119 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
120 1.3 bouyer 7, 16, 5, 125, 4096
121 1.1 bouyer },
122 1.1 bouyer { PCI_PRODUCT_SYMBIOS_875J,
123 1.1 bouyer 0x00,
124 1.1 bouyer "Symbios Logic 53c875j (ultra-wide scsi)",
125 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
126 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
127 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
128 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
129 1.3 bouyer 7, 16, 5, 125, 4096
130 1.1 bouyer },
131 1.1 bouyer { PCI_PRODUCT_SYMBIOS_885,
132 1.1 bouyer 0x00,
133 1.1 bouyer "Symbios Logic 53c885 (ultra-wide scsi)",
134 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
135 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR |
136 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
137 1.1 bouyer SF_BUS_ULTRA | SF_BUS_WIDE,
138 1.3 bouyer 7, 16, 5, 125, 4096
139 1.1 bouyer },
140 1.1 bouyer { PCI_PRODUCT_SYMBIOS_895,
141 1.1 bouyer 0x00,
142 1.1 bouyer "Symbios Logic 53c895 (ultra2-wide scsi)",
143 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
144 1.1 bouyer SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
145 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
146 1.1 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE,
147 1.3 bouyer 7, 31, 7, 62, 4096
148 1.1 bouyer },
149 1.1 bouyer { PCI_PRODUCT_SYMBIOS_896,
150 1.1 bouyer 0x00,
151 1.1 bouyer "Symbios Logic 53c896 (ultra2-wide scsi)",
152 1.1 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
153 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
154 1.1 bouyer SF_CHIP_LS | SF_CHIP_10REGS |
155 1.1 bouyer SF_BUS_ULTRA2 | SF_BUS_WIDE,
156 1.3 bouyer 7, 31, 7, 62, 8192
157 1.6 thorpej },
158 1.6 thorpej { PCI_PRODUCT_SYMBIOS_895A,
159 1.6 thorpej 0x00,
160 1.6 thorpej "Symbios Logic 53c895a (ultra2-wide scsi)",
161 1.6 thorpej SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
162 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
163 1.6 thorpej SF_CHIP_LS | SF_CHIP_10REGS |
164 1.6 thorpej SF_BUS_ULTRA2 | SF_BUS_WIDE,
165 1.7 bouyer 7, 31, 7, 62, 8192
166 1.7 bouyer },
167 1.7 bouyer { PCI_PRODUCT_SYMBIOS_1010,
168 1.7 bouyer 0x00,
169 1.16 thorpej "Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)",
170 1.14 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
171 1.14 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
172 1.14 bouyer SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR |
173 1.17 bouyer SF_CHIP_GEBUG |
174 1.14 bouyer SF_BUS_ULTRA3 | SF_BUS_WIDE,
175 1.14 bouyer 7, 31, 0, 62, 8192
176 1.14 bouyer },
177 1.14 bouyer { PCI_PRODUCT_SYMBIOS_1010,
178 1.14 bouyer 0x01,
179 1.16 thorpej "Symbios Logic 53c1010-33 (ultra3-wide scsi)",
180 1.10 briggs SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
181 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
182 1.14 bouyer SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
183 1.17 bouyer SF_CHIP_GEBUG |
184 1.14 bouyer SF_BUS_ULTRA3 | SF_BUS_WIDE,
185 1.14 bouyer 7, 62, 0, 62, 8192
186 1.10 briggs },
187 1.10 briggs { PCI_PRODUCT_SYMBIOS_1010_2,
188 1.10 briggs 0x00,
189 1.16 thorpej "Symbios Logic 53c1010-66 (ultra3-wide scsi)",
190 1.7 bouyer SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
191 1.12 bouyer SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM |
192 1.14 bouyer SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT |
193 1.22 bouyer SF_CHIP_AAIP |
194 1.24 perry SF_BUS_ULTRA3 | SF_BUS_WIDE,
195 1.14 bouyer 7, 62, 0, 62, 8192
196 1.6 thorpej },
197 1.6 thorpej { PCI_PRODUCT_SYMBIOS_1510D,
198 1.6 thorpej 0x00,
199 1.6 thorpej "Symbios Logic 53c1510d (ultra2-wide scsi)",
200 1.6 thorpej SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM |
201 1.6 thorpej SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD |
202 1.6 thorpej SF_CHIP_LS | SF_CHIP_10REGS |
203 1.6 thorpej SF_BUS_ULTRA2 | SF_BUS_WIDE,
204 1.6 thorpej 7, 31, 7, 62, 4096
205 1.1 bouyer },
206 1.1 bouyer { 0,
207 1.1 bouyer 0x00,
208 1.1 bouyer NULL,
209 1.1 bouyer 0x00,
210 1.3 bouyer 0, 0, 0, 0, 0
211 1.1 bouyer },
212 1.1 bouyer };
213 1.1 bouyer
214 1.1 bouyer const struct siop_product_desc *
215 1.31 tsutsui siop_lookup_product(uint32_t id, int rev)
216 1.1 bouyer {
217 1.1 bouyer const struct siop_product_desc *pp;
218 1.1 bouyer const struct siop_product_desc *rp = NULL;
219 1.1 bouyer
220 1.1 bouyer if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS)
221 1.1 bouyer return NULL;
222 1.1 bouyer
223 1.1 bouyer for (pp = siop_products; pp->name != NULL; pp++) {
224 1.1 bouyer if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev)
225 1.1 bouyer if (rp == NULL || pp->revision > rp->revision)
226 1.1 bouyer rp = pp;
227 1.1 bouyer }
228 1.1 bouyer return rp;
229 1.1 bouyer }
230 1.1 bouyer
231 1.1 bouyer int
232 1.25 thorpej siop_pci_attach_common(struct siop_pci_common_softc *pci_sc,
233 1.25 thorpej struct siop_common_softc *siop_sc, struct pci_attach_args *pa,
234 1.25 thorpej int (*intr)(void *))
235 1.1 bouyer {
236 1.1 bouyer pci_chipset_tag_t pc = pa->pa_pc;
237 1.24 perry pcitag_t tag = pa->pa_tag;
238 1.1 bouyer const char *intrstr;
239 1.1 bouyer pci_intr_handle_t intrhandle;
240 1.1 bouyer bus_space_tag_t iot, memt;
241 1.1 bouyer bus_space_handle_t ioh, memh;
242 1.1 bouyer pcireg_t memtype;
243 1.28 kiyohara prop_dictionary_t dict;
244 1.1 bouyer int memh_valid, ioh_valid;
245 1.1 bouyer bus_addr_t ioaddr, memaddr;
246 1.28 kiyohara bool use_pciclock;
247 1.35 christos char intrbuf[PCI_INTRSTR_LEN];
248 1.1 bouyer
249 1.18 thorpej aprint_naive(": SCSI controller\n");
250 1.18 thorpej
251 1.11 bouyer pci_sc->sc_pp =
252 1.11 bouyer siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class));
253 1.11 bouyer if (pci_sc->sc_pp == NULL) {
254 1.18 thorpej aprint_error("sym: broken match/attach!!\n");
255 1.1 bouyer return 0;
256 1.1 bouyer }
257 1.2 bouyer /* copy interesting infos about the chip */
258 1.11 bouyer siop_sc->features = pci_sc->sc_pp->features;
259 1.13 bouyer #ifdef SIOP_SYMLED /* XXX Should be a devprop! */
260 1.13 bouyer siop_sc->features |= SF_CHIP_LED0;
261 1.13 bouyer #endif
262 1.30 tsutsui dict = device_properties(siop_sc->sc_dev);
263 1.28 kiyohara if (prop_dictionary_get_bool(dict, "use_pciclock", &use_pciclock))
264 1.28 kiyohara if (use_pciclock)
265 1.28 kiyohara siop_sc->features |= SF_CHIP_USEPCIC;
266 1.11 bouyer siop_sc->maxburst = pci_sc->sc_pp->maxburst;
267 1.11 bouyer siop_sc->maxoff = pci_sc->sc_pp->maxoff;
268 1.11 bouyer siop_sc->clock_div = pci_sc->sc_pp->clock_div;
269 1.11 bouyer siop_sc->clock_period = pci_sc->sc_pp->clock_period;
270 1.11 bouyer siop_sc->ram_size = pci_sc->sc_pp->ram_size;
271 1.11 bouyer
272 1.11 bouyer siop_sc->sc_reset = siop_pci_reset;
273 1.18 thorpej aprint_normal(": %s\n", pci_sc->sc_pp->name);
274 1.11 bouyer pci_sc->sc_pc = pc;
275 1.11 bouyer pci_sc->sc_tag = tag;
276 1.11 bouyer siop_sc->sc_dmat = pa->pa_dmat;
277 1.1 bouyer
278 1.1 bouyer memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14);
279 1.1 bouyer switch (memtype) {
280 1.1 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
281 1.1 bouyer case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
282 1.1 bouyer memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0,
283 1.1 bouyer &memt, &memh, &memaddr, NULL) == 0);
284 1.1 bouyer break;
285 1.1 bouyer default:
286 1.1 bouyer memh_valid = 0;
287 1.1 bouyer }
288 1.1 bouyer
289 1.1 bouyer ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0,
290 1.1 bouyer &iot, &ioh, &ioaddr, NULL) == 0);
291 1.1 bouyer
292 1.1 bouyer if (memh_valid) {
293 1.11 bouyer siop_sc->sc_rt = memt;
294 1.11 bouyer siop_sc->sc_rh = memh;
295 1.11 bouyer siop_sc->sc_raddr = memaddr;
296 1.1 bouyer } else if (ioh_valid) {
297 1.11 bouyer siop_sc->sc_rt = iot;
298 1.11 bouyer siop_sc->sc_rh = ioh;
299 1.11 bouyer siop_sc->sc_raddr = ioaddr;
300 1.1 bouyer } else {
301 1.31 tsutsui aprint_error_dev(siop_sc->sc_dev,
302 1.31 tsutsui "unable to map device registers\n");
303 1.1 bouyer return 0;
304 1.1 bouyer }
305 1.1 bouyer
306 1.11 bouyer if (siop_sc->features & SF_CHIP_RAM) {
307 1.4 matt int bar;
308 1.4 matt switch (memtype) {
309 1.4 matt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
310 1.4 matt bar = 0x18;
311 1.4 matt break;
312 1.4 matt case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
313 1.4 matt bar = 0x1c;
314 1.20 christos break;
315 1.20 christos default:
316 1.31 tsutsui aprint_error_dev(siop_sc->sc_dev,
317 1.31 tsutsui "invalid memory type %d\n",
318 1.27 cegger memtype);
319 1.21 christos return 0;
320 1.4 matt }
321 1.4 matt if (pci_mapreg_map(pa, bar, memtype, 0,
322 1.11 bouyer &siop_sc->sc_ramt, &siop_sc->sc_ramh,
323 1.11 bouyer &siop_sc->sc_scriptaddr, NULL) == 0) {
324 1.31 tsutsui aprint_normal_dev(siop_sc->sc_dev,
325 1.31 tsutsui "using on-board RAM\n");
326 1.2 bouyer } else {
327 1.31 tsutsui aprint_error_dev(siop_sc->sc_dev,
328 1.31 tsutsui "can't map on-board RAM\n");
329 1.11 bouyer siop_sc->features &= ~SF_CHIP_RAM;
330 1.2 bouyer }
331 1.2 bouyer }
332 1.2 bouyer
333 1.5 sommerfe if (pci_intr_map(pa, &intrhandle) != 0) {
334 1.30 tsutsui aprint_error_dev(siop_sc->sc_dev, "couldn't map interrupt\n");
335 1.1 bouyer return 0;
336 1.1 bouyer }
337 1.35 christos intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
338 1.37 jdolecek pci_sc->sc_ih = pci_intr_establish_xname(pa->pa_pc, intrhandle, IPL_BIO,
339 1.37 jdolecek intr, siop_sc, device_xname(siop_sc->sc_dev));
340 1.11 bouyer if (pci_sc->sc_ih != NULL) {
341 1.30 tsutsui aprint_normal_dev(siop_sc->sc_dev, "interrupting at %s\n",
342 1.1 bouyer intrstr ? intrstr : "unknown interrupt");
343 1.1 bouyer } else {
344 1.31 tsutsui aprint_error_dev(siop_sc->sc_dev,
345 1.31 tsutsui "couldn't establish interrupt");
346 1.1 bouyer if (intrstr != NULL)
347 1.33 njoly aprint_error(" at %s", intrstr);
348 1.33 njoly aprint_error("\n");
349 1.1 bouyer return 0;
350 1.1 bouyer }
351 1.29 bouyer pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
352 1.29 bouyer pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) |
353 1.29 bouyer PCI_COMMAND_MASTER_ENABLE);
354 1.1 bouyer return 1;
355 1.1 bouyer }
356 1.1 bouyer
357 1.1 bouyer void
358 1.25 thorpej siop_pci_reset(struct siop_common_softc *sc)
359 1.1 bouyer {
360 1.1 bouyer int dmode;
361 1.1 bouyer
362 1.1 bouyer dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE);
363 1.1 bouyer if (sc->features & SF_PCI_RL)
364 1.1 bouyer dmode |= DMODE_ERL;
365 1.1 bouyer if (sc->features & SF_PCI_RM)
366 1.1 bouyer dmode |= DMODE_ERMP;
367 1.1 bouyer if (sc->features & SF_PCI_BOF)
368 1.1 bouyer dmode |= DMODE_BOF;
369 1.1 bouyer if (sc->features & SF_PCI_CLS)
370 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL,
371 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) |
372 1.1 bouyer DCNTL_CLSE);
373 1.1 bouyer if (sc->features & SF_PCI_WRI)
374 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3,
375 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) |
376 1.1 bouyer CTEST3_WRIE);
377 1.1 bouyer if (sc->maxburst) {
378 1.1 bouyer int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh,
379 1.1 bouyer SIOP_CTEST5);
380 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
381 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) &
382 1.1 bouyer ~CTEST4_BDIS);
383 1.1 bouyer dmode &= ~DMODE_BL_MASK;
384 1.1 bouyer dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK;
385 1.1 bouyer ctest5 &= ~CTEST5_BBCK;
386 1.1 bouyer ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK;
387 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5);
388 1.1 bouyer } else {
389 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4,
390 1.1 bouyer bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) |
391 1.1 bouyer CTEST4_BDIS);
392 1.1 bouyer }
393 1.1 bouyer bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode);
394 1.1 bouyer }
395