siop_pci_common.c revision 1.10
1 /* $NetBSD: siop_pci_common.c,v 1.10 2002/02/08 04:07:34 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.10 2002/02/08 04:07:34 briggs Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/kernel.h> 43 44 #include <machine/endian.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <dev/scsipi/scsipi_all.h> 51 #include <dev/scsipi/scsipiconf.h> 52 53 #include <dev/ic/siopreg.h> 54 #include <dev/ic/siopvar.h> 55 #include <dev/pci/siop_pci_common.h> 56 57 /* List (array, really :) of chips we know how to handle */ 58 const struct siop_product_desc siop_products[] = { 59 { PCI_PRODUCT_SYMBIOS_810, 60 0x00, 61 "Symbios Logic 53c810 (fast scsi)", 62 SF_PCI_RL | SF_CHIP_LS, 63 4, 8, 3, 250, 0 64 }, 65 { PCI_PRODUCT_SYMBIOS_810, 66 0x10, 67 "Symbios Logic 53c810a (fast scsi)", 68 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 69 4, 8, 3, 250, 0 70 }, 71 { PCI_PRODUCT_SYMBIOS_815, 72 0x00, 73 "Symbios Logic 53c815 (fast scsi)", 74 SF_PCI_RL | SF_PCI_BOF, 75 4, 8, 3, 250, 0 76 }, 77 { PCI_PRODUCT_SYMBIOS_820, 78 0x00, 79 "Symbios Logic 53c820 (fast wide scsi)", 80 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 81 4, 8, 3, 250, 0 82 }, 83 { PCI_PRODUCT_SYMBIOS_825, 84 0x00, 85 "Symbios Logic 53c825 (fast wide scsi)", 86 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 87 4, 8, 3, 250, 0 88 }, 89 { PCI_PRODUCT_SYMBIOS_825, 90 0x10, 91 "Symbios Logic 53c825a (fast wide scsi)", 92 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 93 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 94 SF_BUS_WIDE, 95 7, 8, 3, 250, 4096 96 }, 97 { PCI_PRODUCT_SYMBIOS_860, 98 0x00, 99 "Symbios Logic 53c860 (ultra scsi)", 100 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 101 SF_CHIP_PF | SF_CHIP_LS | 102 SF_BUS_ULTRA, 103 4, 8, 5, 125, 0 104 }, 105 { PCI_PRODUCT_SYMBIOS_875, 106 0x00, 107 "Symbios Logic 53c875 (ultra-wide scsi)", 108 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 109 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 110 SF_BUS_ULTRA | SF_BUS_WIDE, 111 7, 16, 5, 125, 4096 112 }, 113 { PCI_PRODUCT_SYMBIOS_875, 114 0x02, 115 "Symbios Logic 53c875 (ultra-wide scsi)", 116 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 117 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 118 SF_CHIP_LS | SF_CHIP_10REGS | 119 SF_BUS_ULTRA | SF_BUS_WIDE, 120 7, 16, 5, 125, 4096 121 }, 122 { PCI_PRODUCT_SYMBIOS_875J, 123 0x00, 124 "Symbios Logic 53c875j (ultra-wide scsi)", 125 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 126 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 127 SF_CHIP_LS | SF_CHIP_10REGS | 128 SF_BUS_ULTRA | SF_BUS_WIDE, 129 7, 16, 5, 125, 4096 130 }, 131 { PCI_PRODUCT_SYMBIOS_885, 132 0x00, 133 "Symbios Logic 53c885 (ultra-wide scsi)", 134 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 135 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 136 SF_CHIP_LS | SF_CHIP_10REGS | 137 SF_BUS_ULTRA | SF_BUS_WIDE, 138 7, 16, 5, 125, 4096 139 }, 140 { PCI_PRODUCT_SYMBIOS_895, 141 0x00, 142 "Symbios Logic 53c895 (ultra2-wide scsi)", 143 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 144 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 145 SF_CHIP_LS | SF_CHIP_10REGS | 146 SF_BUS_ULTRA2 | SF_BUS_WIDE, 147 7, 31, 7, 62, 4096 148 }, 149 { PCI_PRODUCT_SYMBIOS_896, 150 0x00, 151 "Symbios Logic 53c896 (ultra2-wide scsi)", 152 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 153 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 154 SF_CHIP_LS | SF_CHIP_10REGS | 155 SF_BUS_ULTRA2 | SF_BUS_WIDE, 156 7, 31, 7, 62, 8192 157 }, 158 { PCI_PRODUCT_SYMBIOS_895A, 159 0x00, 160 "Symbios Logic 53c895a (ultra2-wide scsi)", 161 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 162 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 163 SF_CHIP_LS | SF_CHIP_10REGS | 164 SF_BUS_ULTRA2 | SF_BUS_WIDE, 165 7, 31, 7, 62, 8192 166 }, 167 { PCI_PRODUCT_SYMBIOS_1010, 168 0x00, 169 "Symbios Logic 53c1010-33 (ultra2-wide scsi)", 170 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 171 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 172 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 173 SF_BUS_ULTRA2 | SF_BUS_WIDE, 174 7, 31, 7, 62, 8192 175 }, 176 { PCI_PRODUCT_SYMBIOS_1010_2, 177 0x00, 178 "Symbios Logic 53c1010-66 (ultra2-wide scsi)", 179 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 180 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 181 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 182 SF_BUS_ULTRA2 | SF_BUS_WIDE, 183 7, 31, 7, 62, 8192 184 }, 185 { PCI_PRODUCT_SYMBIOS_1510D, 186 0x00, 187 "Symbios Logic 53c1510d (ultra2-wide scsi)", 188 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 189 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 190 SF_CHIP_LS | SF_CHIP_10REGS | 191 SF_BUS_ULTRA2 | SF_BUS_WIDE, 192 7, 31, 7, 62, 4096 193 }, 194 { 0, 195 0x00, 196 NULL, 197 0x00, 198 0, 0, 0, 0, 0 199 }, 200 }; 201 202 const struct siop_product_desc * 203 siop_lookup_product(id, rev) 204 u_int32_t id; 205 int rev; 206 { 207 const struct siop_product_desc *pp; 208 const struct siop_product_desc *rp = NULL; 209 210 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 211 return NULL; 212 213 for (pp = siop_products; pp->name != NULL; pp++) { 214 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 215 if (rp == NULL || pp->revision > rp->revision) 216 rp = pp; 217 } 218 return rp; 219 } 220 221 int 222 siop_pci_attach_common(sc, pa) 223 struct siop_pci_softc *sc; 224 struct pci_attach_args *pa; 225 { 226 pci_chipset_tag_t pc = pa->pa_pc; 227 pcitag_t tag = pa->pa_tag; 228 const char *intrstr; 229 pci_intr_handle_t intrhandle; 230 bus_space_tag_t iot, memt; 231 bus_space_handle_t ioh, memh; 232 pcireg_t memtype; 233 int memh_valid, ioh_valid; 234 bus_addr_t ioaddr, memaddr; 235 236 sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 237 if (sc->sc_pp == NULL) { 238 printf("sym: broken match/attach!!\n"); 239 return 0; 240 } 241 /* copy interesting infos about the chip */ 242 sc->siop.features = sc->sc_pp->features; 243 sc->siop.maxburst = sc->sc_pp->maxburst; 244 sc->siop.maxoff = sc->sc_pp->maxoff; 245 sc->siop.clock_div = sc->sc_pp->clock_div; 246 sc->siop.clock_period = sc->sc_pp->clock_period; 247 sc->siop.ram_size = sc->sc_pp->ram_size; 248 249 sc->siop.sc_reset = siop_pci_reset; 250 printf(": %s\n", sc->sc_pp->name); 251 sc->sc_pc = pc; 252 sc->sc_tag = tag; 253 sc->siop.sc_dmat = pa->pa_dmat; 254 255 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 256 switch (memtype) { 257 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 258 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 259 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 260 &memt, &memh, &memaddr, NULL) == 0); 261 break; 262 default: 263 memh_valid = 0; 264 } 265 266 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 267 &iot, &ioh, &ioaddr, NULL) == 0); 268 269 if (memh_valid) { 270 sc->siop.sc_rt = memt; 271 sc->siop.sc_rh = memh; 272 sc->siop.sc_raddr = memaddr; 273 } else if (ioh_valid) { 274 sc->siop.sc_rt = iot; 275 sc->siop.sc_rh = ioh; 276 sc->siop.sc_raddr = ioaddr; 277 } else { 278 printf("%s: unable to map device registers\n", 279 sc->siop.sc_dev.dv_xname); 280 return 0; 281 } 282 283 if (sc->siop.features & SF_CHIP_RAM) { 284 int bar; 285 switch (memtype) { 286 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 287 bar = 0x18; 288 break; 289 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 290 bar = 0x1c; 291 break; 292 } 293 if (pci_mapreg_map(pa, bar, memtype, 0, 294 &sc->siop.sc_ramt, &sc->siop.sc_ramh, 295 &sc->siop.sc_scriptaddr, NULL) == 0) { 296 printf("%s: using on-board RAM\n", 297 sc->siop.sc_dev.dv_xname); 298 } else { 299 printf("%s: can't map on-board RAM\n", 300 sc->siop.sc_dev.dv_xname); 301 sc->siop.features &= ~SF_CHIP_RAM; 302 } 303 } 304 305 if (pci_intr_map(pa, &intrhandle) != 0) { 306 printf("%s: couldn't map interrupt\n", 307 sc->siop.sc_dev.dv_xname); 308 return 0; 309 } 310 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 311 sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 312 siop_intr, &sc->siop); 313 if (sc->sc_ih != NULL) { 314 printf("%s: interrupting at %s\n", 315 sc->siop.sc_dev.dv_xname, 316 intrstr ? intrstr : "unknown interrupt"); 317 } else { 318 printf("%s: couldn't establish interrupt", 319 sc->siop.sc_dev.dv_xname); 320 if (intrstr != NULL) 321 printf(" at %s", intrstr); 322 printf("\n"); 323 return 0; 324 } 325 return 1; 326 } 327 328 void 329 siop_pci_reset(sc) 330 struct siop_softc *sc; 331 { 332 int dmode; 333 334 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 335 if (sc->features & SF_PCI_RL) 336 dmode |= DMODE_ERL; 337 if (sc->features & SF_PCI_RM) 338 dmode |= DMODE_ERMP; 339 if (sc->features & SF_PCI_BOF) 340 dmode |= DMODE_BOF; 341 if (sc->features & SF_PCI_CLS) 342 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 343 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 344 DCNTL_CLSE); 345 if (sc->features & SF_PCI_WRI) 346 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 347 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 348 CTEST3_WRIE); 349 if (sc->maxburst) { 350 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 351 SIOP_CTEST5); 352 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 353 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 354 ~CTEST4_BDIS); 355 dmode &= ~DMODE_BL_MASK; 356 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 357 ctest5 &= ~CTEST5_BBCK; 358 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 359 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 360 } else { 361 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 362 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 363 CTEST4_BDIS); 364 } 365 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 366 } 367
Indexes created Mon Sep 22 13:09:51 GMT 2025