siop_pci_common.c revision 1.17.4.1
1 /* $NetBSD: siop_pci_common.c,v 1.17.4.1 2005/03/17 17:40:00 tron Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.17.4.1 2005/03/17 17:40:00 tron Exp $"); 36 37 #include <sys/param.h> 38 #include <sys/systm.h> 39 #include <sys/device.h> 40 #include <sys/malloc.h> 41 #include <sys/buf.h> 42 #include <sys/kernel.h> 43 44 #include <machine/endian.h> 45 46 #include <dev/pci/pcireg.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcidevs.h> 49 50 #include <dev/scsipi/scsipi_all.h> 51 #include <dev/scsipi/scsipiconf.h> 52 53 #include <dev/ic/siopreg.h> 54 #include <dev/ic/siopvar_common.h> 55 #include <dev/pci/siop_pci_common.h> 56 57 /* List (array, really :) of chips we know how to handle */ 58 const struct siop_product_desc siop_products[] = { 59 { PCI_PRODUCT_SYMBIOS_810, 60 0x00, 61 "Symbios Logic 53c810 (fast scsi)", 62 SF_PCI_RL | SF_CHIP_LS, 63 4, 8, 3, 250, 0 64 }, 65 { PCI_PRODUCT_SYMBIOS_810, 66 0x10, 67 "Symbios Logic 53c810a (fast scsi)", 68 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 69 4, 8, 3, 250, 0 70 }, 71 { PCI_PRODUCT_SYMBIOS_815, 72 0x00, 73 "Symbios Logic 53c815 (fast scsi)", 74 SF_PCI_RL | SF_PCI_BOF, 75 4, 8, 3, 250, 0 76 }, 77 { PCI_PRODUCT_SYMBIOS_820, 78 0x00, 79 "Symbios Logic 53c820 (fast wide scsi)", 80 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 81 4, 8, 3, 250, 0 82 }, 83 { PCI_PRODUCT_SYMBIOS_825, 84 0x00, 85 "Symbios Logic 53c825 (fast wide scsi)", 86 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 87 4, 8, 3, 250, 0 88 }, 89 { PCI_PRODUCT_SYMBIOS_825, 90 0x10, 91 "Symbios Logic 53c825a (fast wide scsi)", 92 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 93 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 94 SF_BUS_WIDE, 95 7, 8, 3, 250, 4096 96 }, 97 { PCI_PRODUCT_SYMBIOS_860, 98 0x00, 99 "Symbios Logic 53c860 (ultra scsi)", 100 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 101 SF_CHIP_PF | SF_CHIP_LS | 102 SF_BUS_ULTRA, 103 4, 8, 5, 125, 0 104 }, 105 { PCI_PRODUCT_SYMBIOS_875, 106 0x00, 107 "Symbios Logic 53c875 (ultra-wide scsi)", 108 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 109 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 110 SF_BUS_ULTRA | SF_BUS_WIDE, 111 7, 16, 5, 125, 4096 112 }, 113 { PCI_PRODUCT_SYMBIOS_875, 114 0x02, 115 "Symbios Logic 53c875 (ultra-wide scsi)", 116 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 117 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 118 SF_CHIP_LS | SF_CHIP_10REGS | 119 SF_BUS_ULTRA | SF_BUS_WIDE, 120 7, 16, 5, 125, 4096 121 }, 122 { PCI_PRODUCT_SYMBIOS_875J, 123 0x00, 124 "Symbios Logic 53c875j (ultra-wide scsi)", 125 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 126 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 127 SF_CHIP_LS | SF_CHIP_10REGS | 128 SF_BUS_ULTRA | SF_BUS_WIDE, 129 7, 16, 5, 125, 4096 130 }, 131 { PCI_PRODUCT_SYMBIOS_885, 132 0x00, 133 "Symbios Logic 53c885 (ultra-wide scsi)", 134 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 135 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 136 SF_CHIP_LS | SF_CHIP_10REGS | 137 SF_BUS_ULTRA | SF_BUS_WIDE, 138 7, 16, 5, 125, 4096 139 }, 140 { PCI_PRODUCT_SYMBIOS_895, 141 0x00, 142 "Symbios Logic 53c895 (ultra2-wide scsi)", 143 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 144 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 145 SF_CHIP_LS | SF_CHIP_10REGS | 146 SF_BUS_ULTRA2 | SF_BUS_WIDE, 147 7, 31, 7, 62, 4096 148 }, 149 { PCI_PRODUCT_SYMBIOS_896, 150 0x00, 151 "Symbios Logic 53c896 (ultra2-wide scsi)", 152 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 153 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 154 SF_CHIP_LS | SF_CHIP_10REGS | 155 SF_BUS_ULTRA2 | SF_BUS_WIDE, 156 7, 31, 7, 62, 8192 157 }, 158 { PCI_PRODUCT_SYMBIOS_895A, 159 0x00, 160 "Symbios Logic 53c895a (ultra2-wide scsi)", 161 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 162 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 163 SF_CHIP_LS | SF_CHIP_10REGS | 164 SF_BUS_ULTRA2 | SF_BUS_WIDE, 165 7, 31, 7, 62, 8192 166 }, 167 { PCI_PRODUCT_SYMBIOS_1010, 168 0x00, 169 "Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)", 170 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 171 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 172 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 173 SF_CHIP_GEBUG | 174 SF_BUS_ULTRA3 | SF_BUS_WIDE, 175 7, 31, 0, 62, 8192 176 }, 177 { PCI_PRODUCT_SYMBIOS_1010, 178 0x01, 179 "Symbios Logic 53c1010-33 (ultra3-wide scsi)", 180 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 181 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 182 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 183 SF_CHIP_GEBUG | 184 SF_BUS_ULTRA3 | SF_BUS_WIDE, 185 7, 62, 0, 62, 8192 186 }, 187 { PCI_PRODUCT_SYMBIOS_1010_2, 188 0x00, 189 "Symbios Logic 53c1010-66 (ultra3-wide scsi)", 190 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 191 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 192 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 193 SF_CHIP_AAIP | 194 SF_BUS_ULTRA3 | SF_BUS_WIDE, 195 7, 62, 0, 62, 8192 196 }, 197 { PCI_PRODUCT_SYMBIOS_1510D, 198 0x00, 199 "Symbios Logic 53c1510d (ultra2-wide scsi)", 200 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 201 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 202 SF_CHIP_LS | SF_CHIP_10REGS | 203 SF_BUS_ULTRA2 | SF_BUS_WIDE, 204 7, 31, 7, 62, 4096 205 }, 206 { 0, 207 0x00, 208 NULL, 209 0x00, 210 0, 0, 0, 0, 0 211 }, 212 }; 213 214 const struct siop_product_desc * 215 siop_lookup_product(id, rev) 216 u_int32_t id; 217 int rev; 218 { 219 const struct siop_product_desc *pp; 220 const struct siop_product_desc *rp = NULL; 221 222 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 223 return NULL; 224 225 for (pp = siop_products; pp->name != NULL; pp++) { 226 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 227 if (rp == NULL || pp->revision > rp->revision) 228 rp = pp; 229 } 230 return rp; 231 } 232 233 int 234 siop_pci_attach_common(pci_sc, siop_sc, pa, intr) 235 struct siop_pci_common_softc *pci_sc; 236 struct siop_common_softc *siop_sc; 237 struct pci_attach_args *pa; 238 int (*intr) __P((void*)); 239 240 { 241 pci_chipset_tag_t pc = pa->pa_pc; 242 pcitag_t tag = pa->pa_tag; 243 const char *intrstr; 244 pci_intr_handle_t intrhandle; 245 bus_space_tag_t iot, memt; 246 bus_space_handle_t ioh, memh; 247 pcireg_t memtype; 248 int memh_valid, ioh_valid; 249 bus_addr_t ioaddr, memaddr; 250 251 pci_sc->sc_pp = 252 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 253 if (pci_sc->sc_pp == NULL) { 254 printf("sym: broken match/attach!!\n"); 255 return 0; 256 } 257 /* copy interesting infos about the chip */ 258 siop_sc->features = pci_sc->sc_pp->features; 259 #ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 260 siop_sc->features |= SF_CHIP_LED0; 261 #endif 262 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 263 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 264 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 265 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 266 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 267 268 siop_sc->sc_reset = siop_pci_reset; 269 printf(": %s\n", pci_sc->sc_pp->name); 270 pci_sc->sc_pc = pc; 271 pci_sc->sc_tag = tag; 272 siop_sc->sc_dmat = pa->pa_dmat; 273 274 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 275 switch (memtype) { 276 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 277 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 278 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 279 &memt, &memh, &memaddr, NULL) == 0); 280 break; 281 default: 282 memh_valid = 0; 283 } 284 285 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 286 &iot, &ioh, &ioaddr, NULL) == 0); 287 288 if (memh_valid) { 289 siop_sc->sc_rt = memt; 290 siop_sc->sc_rh = memh; 291 siop_sc->sc_raddr = memaddr; 292 } else if (ioh_valid) { 293 siop_sc->sc_rt = iot; 294 siop_sc->sc_rh = ioh; 295 siop_sc->sc_raddr = ioaddr; 296 } else { 297 printf("%s: unable to map device registers\n", 298 siop_sc->sc_dev.dv_xname); 299 return 0; 300 } 301 302 if (siop_sc->features & SF_CHIP_RAM) { 303 int bar; 304 switch (memtype) { 305 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 306 bar = 0x18; 307 break; 308 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 309 bar = 0x1c; 310 break; 311 } 312 if (pci_mapreg_map(pa, bar, memtype, 0, 313 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 314 &siop_sc->sc_scriptaddr, NULL) == 0) { 315 printf("%s: using on-board RAM\n", 316 siop_sc->sc_dev.dv_xname); 317 } else { 318 printf("%s: can't map on-board RAM\n", 319 siop_sc->sc_dev.dv_xname); 320 siop_sc->features &= ~SF_CHIP_RAM; 321 } 322 } 323 324 if (pci_intr_map(pa, &intrhandle) != 0) { 325 printf("%s: couldn't map interrupt\n", 326 siop_sc->sc_dev.dv_xname); 327 return 0; 328 } 329 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 330 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 331 intr, siop_sc); 332 if (pci_sc->sc_ih != NULL) { 333 printf("%s: interrupting at %s\n", 334 siop_sc->sc_dev.dv_xname, 335 intrstr ? intrstr : "unknown interrupt"); 336 } else { 337 printf("%s: couldn't establish interrupt", 338 siop_sc->sc_dev.dv_xname); 339 if (intrstr != NULL) 340 printf(" at %s", intrstr); 341 printf("\n"); 342 return 0; 343 } 344 return 1; 345 } 346 347 void 348 siop_pci_reset(sc) 349 struct siop_common_softc *sc; 350 { 351 int dmode; 352 353 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 354 if (sc->features & SF_PCI_RL) 355 dmode |= DMODE_ERL; 356 if (sc->features & SF_PCI_RM) 357 dmode |= DMODE_ERMP; 358 if (sc->features & SF_PCI_BOF) 359 dmode |= DMODE_BOF; 360 if (sc->features & SF_PCI_CLS) 361 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 362 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 363 DCNTL_CLSE); 364 if (sc->features & SF_PCI_WRI) 365 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 366 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 367 CTEST3_WRIE); 368 if (sc->maxburst) { 369 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 370 SIOP_CTEST5); 371 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 372 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 373 ~CTEST4_BDIS); 374 dmode &= ~DMODE_BL_MASK; 375 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 376 ctest5 &= ~CTEST5_BBCK; 377 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 378 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 379 } else { 380 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 381 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 382 CTEST4_BDIS); 383 } 384 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 385 } 386
Indexes created Thu Oct 02 14:10:14 GMT 2025