siop_pci_common.c revision 1.33
1 /* $NetBSD: siop_pci_common.c,v 1.33 2009/11/26 15:17:10 njoly Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.33 2009/11/26 15:17:10 njoly Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/kernel.h> 38 39 #include <uvm/uvm_extern.h> 40 41 #include <machine/endian.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 47 #include <dev/scsipi/scsipi_all.h> 48 #include <dev/scsipi/scsipiconf.h> 49 50 #include <dev/ic/siopreg.h> 51 #include <dev/ic/siopvar_common.h> 52 #include <dev/pci/siop_pci_common.h> 53 54 /* List (array, really :) of chips we know how to handle */ 55 static const struct siop_product_desc siop_products[] = { 56 { PCI_PRODUCT_SYMBIOS_810, 57 0x00, 58 "Symbios Logic 53c810 (fast scsi)", 59 SF_PCI_RL | SF_CHIP_LS, 60 4, 8, 3, 250, 0 61 }, 62 { PCI_PRODUCT_SYMBIOS_810, 63 0x10, 64 "Symbios Logic 53c810a (fast scsi)", 65 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 66 4, 8, 3, 250, 0 67 }, 68 { PCI_PRODUCT_SYMBIOS_815, 69 0x00, 70 "Symbios Logic 53c815 (fast scsi)", 71 SF_PCI_RL | SF_PCI_BOF, 72 4, 8, 3, 250, 0 73 }, 74 { PCI_PRODUCT_SYMBIOS_820, 75 0x00, 76 "Symbios Logic 53c820 (fast wide scsi)", 77 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 78 4, 8, 3, 250, 0 79 }, 80 { PCI_PRODUCT_SYMBIOS_825, 81 0x00, 82 "Symbios Logic 53c825 (fast wide scsi)", 83 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 84 4, 8, 3, 250, 0 85 }, 86 { PCI_PRODUCT_SYMBIOS_825, 87 0x10, 88 "Symbios Logic 53c825a (fast wide scsi)", 89 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 90 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 91 SF_BUS_WIDE, 92 7, 8, 3, 250, 4096 93 }, 94 { PCI_PRODUCT_SYMBIOS_860, 95 0x00, 96 "Symbios Logic 53c860 (ultra scsi)", 97 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 98 SF_CHIP_PF | SF_CHIP_LS | 99 SF_BUS_ULTRA, 100 4, 8, 5, 125, 0 101 }, 102 { PCI_PRODUCT_SYMBIOS_875, 103 0x00, 104 "Symbios Logic 53c875 (ultra-wide scsi)", 105 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 106 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 107 SF_BUS_ULTRA | SF_BUS_WIDE, 108 7, 16, 5, 125, 4096 109 }, 110 { PCI_PRODUCT_SYMBIOS_875, 111 0x02, 112 "Symbios Logic 53c875 (ultra-wide scsi)", 113 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 114 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 115 SF_CHIP_LS | SF_CHIP_10REGS | 116 SF_BUS_ULTRA | SF_BUS_WIDE, 117 7, 16, 5, 125, 4096 118 }, 119 { PCI_PRODUCT_SYMBIOS_875J, 120 0x00, 121 "Symbios Logic 53c875j (ultra-wide scsi)", 122 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 123 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 124 SF_CHIP_LS | SF_CHIP_10REGS | 125 SF_BUS_ULTRA | SF_BUS_WIDE, 126 7, 16, 5, 125, 4096 127 }, 128 { PCI_PRODUCT_SYMBIOS_885, 129 0x00, 130 "Symbios Logic 53c885 (ultra-wide scsi)", 131 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 132 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 133 SF_CHIP_LS | SF_CHIP_10REGS | 134 SF_BUS_ULTRA | SF_BUS_WIDE, 135 7, 16, 5, 125, 4096 136 }, 137 { PCI_PRODUCT_SYMBIOS_895, 138 0x00, 139 "Symbios Logic 53c895 (ultra2-wide scsi)", 140 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 141 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 142 SF_CHIP_LS | SF_CHIP_10REGS | 143 SF_BUS_ULTRA2 | SF_BUS_WIDE, 144 7, 31, 7, 62, 4096 145 }, 146 { PCI_PRODUCT_SYMBIOS_896, 147 0x00, 148 "Symbios Logic 53c896 (ultra2-wide scsi)", 149 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 150 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 151 SF_CHIP_LS | SF_CHIP_10REGS | 152 SF_BUS_ULTRA2 | SF_BUS_WIDE, 153 7, 31, 7, 62, 8192 154 }, 155 { PCI_PRODUCT_SYMBIOS_895A, 156 0x00, 157 "Symbios Logic 53c895a (ultra2-wide scsi)", 158 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 159 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 160 SF_CHIP_LS | SF_CHIP_10REGS | 161 SF_BUS_ULTRA2 | SF_BUS_WIDE, 162 7, 31, 7, 62, 8192 163 }, 164 { PCI_PRODUCT_SYMBIOS_1010, 165 0x00, 166 "Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)", 167 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 168 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 169 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 170 SF_CHIP_GEBUG | 171 SF_BUS_ULTRA3 | SF_BUS_WIDE, 172 7, 31, 0, 62, 8192 173 }, 174 { PCI_PRODUCT_SYMBIOS_1010, 175 0x01, 176 "Symbios Logic 53c1010-33 (ultra3-wide scsi)", 177 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 178 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 179 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 180 SF_CHIP_GEBUG | 181 SF_BUS_ULTRA3 | SF_BUS_WIDE, 182 7, 62, 0, 62, 8192 183 }, 184 { PCI_PRODUCT_SYMBIOS_1010_2, 185 0x00, 186 "Symbios Logic 53c1010-66 (ultra3-wide scsi)", 187 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 188 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 189 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 190 SF_CHIP_AAIP | 191 SF_BUS_ULTRA3 | SF_BUS_WIDE, 192 7, 62, 0, 62, 8192 193 }, 194 { PCI_PRODUCT_SYMBIOS_1510D, 195 0x00, 196 "Symbios Logic 53c1510d (ultra2-wide scsi)", 197 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 198 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 199 SF_CHIP_LS | SF_CHIP_10REGS | 200 SF_BUS_ULTRA2 | SF_BUS_WIDE, 201 7, 31, 7, 62, 4096 202 }, 203 { 0, 204 0x00, 205 NULL, 206 0x00, 207 0, 0, 0, 0, 0 208 }, 209 }; 210 211 const struct siop_product_desc * 212 siop_lookup_product(uint32_t id, int rev) 213 { 214 const struct siop_product_desc *pp; 215 const struct siop_product_desc *rp = NULL; 216 217 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 218 return NULL; 219 220 for (pp = siop_products; pp->name != NULL; pp++) { 221 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 222 if (rp == NULL || pp->revision > rp->revision) 223 rp = pp; 224 } 225 return rp; 226 } 227 228 int 229 siop_pci_attach_common(struct siop_pci_common_softc *pci_sc, 230 struct siop_common_softc *siop_sc, struct pci_attach_args *pa, 231 int (*intr)(void *)) 232 { 233 pci_chipset_tag_t pc = pa->pa_pc; 234 pcitag_t tag = pa->pa_tag; 235 const char *intrstr; 236 pci_intr_handle_t intrhandle; 237 bus_space_tag_t iot, memt; 238 bus_space_handle_t ioh, memh; 239 pcireg_t memtype; 240 prop_dictionary_t dict; 241 int memh_valid, ioh_valid; 242 bus_addr_t ioaddr, memaddr; 243 bool use_pciclock; 244 245 aprint_naive(": SCSI controller\n"); 246 247 pci_sc->sc_pp = 248 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 249 if (pci_sc->sc_pp == NULL) { 250 aprint_error("sym: broken match/attach!!\n"); 251 return 0; 252 } 253 /* copy interesting infos about the chip */ 254 siop_sc->features = pci_sc->sc_pp->features; 255 #ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 256 siop_sc->features |= SF_CHIP_LED0; 257 #endif 258 dict = device_properties(siop_sc->sc_dev); 259 if (prop_dictionary_get_bool(dict, "use_pciclock", &use_pciclock)) 260 if (use_pciclock) 261 siop_sc->features |= SF_CHIP_USEPCIC; 262 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 263 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 264 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 265 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 266 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 267 268 siop_sc->sc_reset = siop_pci_reset; 269 aprint_normal(": %s\n", pci_sc->sc_pp->name); 270 pci_sc->sc_pc = pc; 271 pci_sc->sc_tag = tag; 272 siop_sc->sc_dmat = pa->pa_dmat; 273 274 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 275 switch (memtype) { 276 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 277 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 278 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 279 &memt, &memh, &memaddr, NULL) == 0); 280 break; 281 default: 282 memh_valid = 0; 283 } 284 285 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 286 &iot, &ioh, &ioaddr, NULL) == 0); 287 288 if (memh_valid) { 289 siop_sc->sc_rt = memt; 290 siop_sc->sc_rh = memh; 291 siop_sc->sc_raddr = memaddr; 292 } else if (ioh_valid) { 293 siop_sc->sc_rt = iot; 294 siop_sc->sc_rh = ioh; 295 siop_sc->sc_raddr = ioaddr; 296 } else { 297 aprint_error_dev(siop_sc->sc_dev, 298 "unable to map device registers\n"); 299 return 0; 300 } 301 302 if (siop_sc->features & SF_CHIP_RAM) { 303 int bar; 304 switch (memtype) { 305 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 306 bar = 0x18; 307 break; 308 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 309 bar = 0x1c; 310 break; 311 default: 312 aprint_error_dev(siop_sc->sc_dev, 313 "invalid memory type %d\n", 314 memtype); 315 return 0; 316 } 317 if (pci_mapreg_map(pa, bar, memtype, 0, 318 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 319 &siop_sc->sc_scriptaddr, NULL) == 0) { 320 aprint_normal_dev(siop_sc->sc_dev, 321 "using on-board RAM\n"); 322 } else { 323 aprint_error_dev(siop_sc->sc_dev, 324 "can't map on-board RAM\n"); 325 siop_sc->features &= ~SF_CHIP_RAM; 326 } 327 } 328 329 if (pci_intr_map(pa, &intrhandle) != 0) { 330 aprint_error_dev(siop_sc->sc_dev, "couldn't map interrupt\n"); 331 return 0; 332 } 333 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 334 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 335 intr, siop_sc); 336 if (pci_sc->sc_ih != NULL) { 337 aprint_normal_dev(siop_sc->sc_dev, "interrupting at %s\n", 338 intrstr ? intrstr : "unknown interrupt"); 339 } else { 340 aprint_error_dev(siop_sc->sc_dev, 341 "couldn't establish interrupt"); 342 if (intrstr != NULL) 343 aprint_error(" at %s", intrstr); 344 aprint_error("\n"); 345 return 0; 346 } 347 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 348 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 349 PCI_COMMAND_MASTER_ENABLE); 350 return 1; 351 } 352 353 void 354 siop_pci_reset(struct siop_common_softc *sc) 355 { 356 int dmode; 357 358 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 359 if (sc->features & SF_PCI_RL) 360 dmode |= DMODE_ERL; 361 if (sc->features & SF_PCI_RM) 362 dmode |= DMODE_ERMP; 363 if (sc->features & SF_PCI_BOF) 364 dmode |= DMODE_BOF; 365 if (sc->features & SF_PCI_CLS) 366 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 367 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 368 DCNTL_CLSE); 369 if (sc->features & SF_PCI_WRI) 370 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 371 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 372 CTEST3_WRIE); 373 if (sc->maxburst) { 374 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 375 SIOP_CTEST5); 376 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 377 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 378 ~CTEST4_BDIS); 379 dmode &= ~DMODE_BL_MASK; 380 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 381 ctest5 &= ~CTEST5_BBCK; 382 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 383 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 384 } else { 385 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 386 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 387 CTEST4_BDIS); 388 } 389 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 390 } 391
Indexes created Tue Sep 23 23:09:58 GMT 2025