siop_pci_common.c revision 1.35
1 /* $NetBSD: siop_pci_common.c,v 1.35 2014/03/29 19:28:25 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 28 29 #include <sys/cdefs.h> 30 __KERNEL_RCSID(0, "$NetBSD: siop_pci_common.c,v 1.35 2014/03/29 19:28:25 christos Exp $"); 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/device.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/kernel.h> 38 39 #include <machine/endian.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 45 #include <dev/scsipi/scsipi_all.h> 46 #include <dev/scsipi/scsipiconf.h> 47 48 #include <dev/ic/siopreg.h> 49 #include <dev/ic/siopvar_common.h> 50 #include <dev/pci/siop_pci_common.h> 51 52 /* List (array, really :) of chips we know how to handle */ 53 static const struct siop_product_desc siop_products[] = { 54 { PCI_PRODUCT_SYMBIOS_810, 55 0x00, 56 "Symbios Logic 53c810 (fast scsi)", 57 SF_PCI_RL | SF_CHIP_LS, 58 4, 8, 3, 250, 0 59 }, 60 { PCI_PRODUCT_SYMBIOS_810, 61 0x10, 62 "Symbios Logic 53c810a (fast scsi)", 63 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 64 4, 8, 3, 250, 0 65 }, 66 { PCI_PRODUCT_SYMBIOS_815, 67 0x00, 68 "Symbios Logic 53c815 (fast scsi)", 69 SF_PCI_RL | SF_PCI_BOF, 70 4, 8, 3, 250, 0 71 }, 72 { PCI_PRODUCT_SYMBIOS_820, 73 0x00, 74 "Symbios Logic 53c820 (fast wide scsi)", 75 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 76 4, 8, 3, 250, 0 77 }, 78 { PCI_PRODUCT_SYMBIOS_825, 79 0x00, 80 "Symbios Logic 53c825 (fast wide scsi)", 81 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 82 4, 8, 3, 250, 0 83 }, 84 { PCI_PRODUCT_SYMBIOS_825, 85 0x10, 86 "Symbios Logic 53c825a (fast wide scsi)", 87 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 88 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 89 SF_BUS_WIDE, 90 7, 8, 3, 250, 4096 91 }, 92 { PCI_PRODUCT_SYMBIOS_860, 93 0x00, 94 "Symbios Logic 53c860 (ultra scsi)", 95 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 96 SF_CHIP_PF | SF_CHIP_LS | 97 SF_BUS_ULTRA, 98 4, 8, 5, 125, 0 99 }, 100 { PCI_PRODUCT_SYMBIOS_875, 101 0x00, 102 "Symbios Logic 53c875 (ultra-wide scsi)", 103 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 104 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 105 SF_BUS_ULTRA | SF_BUS_WIDE, 106 7, 16, 5, 125, 4096 107 }, 108 { PCI_PRODUCT_SYMBIOS_875, 109 0x02, 110 "Symbios Logic 53c875 (ultra-wide scsi)", 111 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 112 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 113 SF_CHIP_LS | SF_CHIP_10REGS | 114 SF_BUS_ULTRA | SF_BUS_WIDE, 115 7, 16, 5, 125, 4096 116 }, 117 { PCI_PRODUCT_SYMBIOS_875J, 118 0x00, 119 "Symbios Logic 53c875j (ultra-wide scsi)", 120 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 121 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 122 SF_CHIP_LS | SF_CHIP_10REGS | 123 SF_BUS_ULTRA | SF_BUS_WIDE, 124 7, 16, 5, 125, 4096 125 }, 126 { PCI_PRODUCT_SYMBIOS_885, 127 0x00, 128 "Symbios Logic 53c885 (ultra-wide scsi)", 129 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 130 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 131 SF_CHIP_LS | SF_CHIP_10REGS | 132 SF_BUS_ULTRA | SF_BUS_WIDE, 133 7, 16, 5, 125, 4096 134 }, 135 { PCI_PRODUCT_SYMBIOS_895, 136 0x00, 137 "Symbios Logic 53c895 (ultra2-wide scsi)", 138 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 139 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 140 SF_CHIP_LS | SF_CHIP_10REGS | 141 SF_BUS_ULTRA2 | SF_BUS_WIDE, 142 7, 31, 7, 62, 4096 143 }, 144 { PCI_PRODUCT_SYMBIOS_896, 145 0x00, 146 "Symbios Logic 53c896 (ultra2-wide scsi)", 147 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 148 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 149 SF_CHIP_LS | SF_CHIP_10REGS | 150 SF_BUS_ULTRA2 | SF_BUS_WIDE, 151 7, 31, 7, 62, 8192 152 }, 153 { PCI_PRODUCT_SYMBIOS_895A, 154 0x00, 155 "Symbios Logic 53c895a (ultra2-wide scsi)", 156 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 157 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 158 SF_CHIP_LS | SF_CHIP_10REGS | 159 SF_BUS_ULTRA2 | SF_BUS_WIDE, 160 7, 31, 7, 62, 8192 161 }, 162 { PCI_PRODUCT_SYMBIOS_1010, 163 0x00, 164 "Symbios Logic 53c1010-33 rev 0 (ultra3-wide scsi)", 165 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 166 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 167 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 168 SF_CHIP_GEBUG | 169 SF_BUS_ULTRA3 | SF_BUS_WIDE, 170 7, 31, 0, 62, 8192 171 }, 172 { PCI_PRODUCT_SYMBIOS_1010, 173 0x01, 174 "Symbios Logic 53c1010-33 (ultra3-wide scsi)", 175 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 176 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 177 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 178 SF_CHIP_GEBUG | 179 SF_BUS_ULTRA3 | SF_BUS_WIDE, 180 7, 62, 0, 62, 8192 181 }, 182 { PCI_PRODUCT_SYMBIOS_1010_2, 183 0x00, 184 "Symbios Logic 53c1010-66 (ultra3-wide scsi)", 185 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 186 SF_CHIP_LEDC | SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 187 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | SF_CHIP_DT | 188 SF_CHIP_AAIP | 189 SF_BUS_ULTRA3 | SF_BUS_WIDE, 190 7, 62, 0, 62, 8192 191 }, 192 { PCI_PRODUCT_SYMBIOS_1510D, 193 0x00, 194 "Symbios Logic 53c1510d (ultra2-wide scsi)", 195 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 196 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 197 SF_CHIP_LS | SF_CHIP_10REGS | 198 SF_BUS_ULTRA2 | SF_BUS_WIDE, 199 7, 31, 7, 62, 4096 200 }, 201 { 0, 202 0x00, 203 NULL, 204 0x00, 205 0, 0, 0, 0, 0 206 }, 207 }; 208 209 const struct siop_product_desc * 210 siop_lookup_product(uint32_t id, int rev) 211 { 212 const struct siop_product_desc *pp; 213 const struct siop_product_desc *rp = NULL; 214 215 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 216 return NULL; 217 218 for (pp = siop_products; pp->name != NULL; pp++) { 219 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 220 if (rp == NULL || pp->revision > rp->revision) 221 rp = pp; 222 } 223 return rp; 224 } 225 226 int 227 siop_pci_attach_common(struct siop_pci_common_softc *pci_sc, 228 struct siop_common_softc *siop_sc, struct pci_attach_args *pa, 229 int (*intr)(void *)) 230 { 231 pci_chipset_tag_t pc = pa->pa_pc; 232 pcitag_t tag = pa->pa_tag; 233 const char *intrstr; 234 pci_intr_handle_t intrhandle; 235 bus_space_tag_t iot, memt; 236 bus_space_handle_t ioh, memh; 237 pcireg_t memtype; 238 prop_dictionary_t dict; 239 int memh_valid, ioh_valid; 240 bus_addr_t ioaddr, memaddr; 241 bool use_pciclock; 242 char intrbuf[PCI_INTRSTR_LEN]; 243 244 aprint_naive(": SCSI controller\n"); 245 246 pci_sc->sc_pp = 247 siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 248 if (pci_sc->sc_pp == NULL) { 249 aprint_error("sym: broken match/attach!!\n"); 250 return 0; 251 } 252 /* copy interesting infos about the chip */ 253 siop_sc->features = pci_sc->sc_pp->features; 254 #ifdef SIOP_SYMLED /* XXX Should be a devprop! */ 255 siop_sc->features |= SF_CHIP_LED0; 256 #endif 257 dict = device_properties(siop_sc->sc_dev); 258 if (prop_dictionary_get_bool(dict, "use_pciclock", &use_pciclock)) 259 if (use_pciclock) 260 siop_sc->features |= SF_CHIP_USEPCIC; 261 siop_sc->maxburst = pci_sc->sc_pp->maxburst; 262 siop_sc->maxoff = pci_sc->sc_pp->maxoff; 263 siop_sc->clock_div = pci_sc->sc_pp->clock_div; 264 siop_sc->clock_period = pci_sc->sc_pp->clock_period; 265 siop_sc->ram_size = pci_sc->sc_pp->ram_size; 266 267 siop_sc->sc_reset = siop_pci_reset; 268 aprint_normal(": %s\n", pci_sc->sc_pp->name); 269 pci_sc->sc_pc = pc; 270 pci_sc->sc_tag = tag; 271 siop_sc->sc_dmat = pa->pa_dmat; 272 273 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 274 switch (memtype) { 275 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 276 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 277 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 278 &memt, &memh, &memaddr, NULL) == 0); 279 break; 280 default: 281 memh_valid = 0; 282 } 283 284 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 285 &iot, &ioh, &ioaddr, NULL) == 0); 286 287 if (memh_valid) { 288 siop_sc->sc_rt = memt; 289 siop_sc->sc_rh = memh; 290 siop_sc->sc_raddr = memaddr; 291 } else if (ioh_valid) { 292 siop_sc->sc_rt = iot; 293 siop_sc->sc_rh = ioh; 294 siop_sc->sc_raddr = ioaddr; 295 } else { 296 aprint_error_dev(siop_sc->sc_dev, 297 "unable to map device registers\n"); 298 return 0; 299 } 300 301 if (siop_sc->features & SF_CHIP_RAM) { 302 int bar; 303 switch (memtype) { 304 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 305 bar = 0x18; 306 break; 307 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 308 bar = 0x1c; 309 break; 310 default: 311 aprint_error_dev(siop_sc->sc_dev, 312 "invalid memory type %d\n", 313 memtype); 314 return 0; 315 } 316 if (pci_mapreg_map(pa, bar, memtype, 0, 317 &siop_sc->sc_ramt, &siop_sc->sc_ramh, 318 &siop_sc->sc_scriptaddr, NULL) == 0) { 319 aprint_normal_dev(siop_sc->sc_dev, 320 "using on-board RAM\n"); 321 } else { 322 aprint_error_dev(siop_sc->sc_dev, 323 "can't map on-board RAM\n"); 324 siop_sc->features &= ~SF_CHIP_RAM; 325 } 326 } 327 328 if (pci_intr_map(pa, &intrhandle) != 0) { 329 aprint_error_dev(siop_sc->sc_dev, "couldn't map interrupt\n"); 330 return 0; 331 } 332 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 333 pci_sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 334 intr, siop_sc); 335 if (pci_sc->sc_ih != NULL) { 336 aprint_normal_dev(siop_sc->sc_dev, "interrupting at %s\n", 337 intrstr ? intrstr : "unknown interrupt"); 338 } else { 339 aprint_error_dev(siop_sc->sc_dev, 340 "couldn't establish interrupt"); 341 if (intrstr != NULL) 342 aprint_error(" at %s", intrstr); 343 aprint_error("\n"); 344 return 0; 345 } 346 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG, 347 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG) | 348 PCI_COMMAND_MASTER_ENABLE); 349 return 1; 350 } 351 352 void 353 siop_pci_reset(struct siop_common_softc *sc) 354 { 355 int dmode; 356 357 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 358 if (sc->features & SF_PCI_RL) 359 dmode |= DMODE_ERL; 360 if (sc->features & SF_PCI_RM) 361 dmode |= DMODE_ERMP; 362 if (sc->features & SF_PCI_BOF) 363 dmode |= DMODE_BOF; 364 if (sc->features & SF_PCI_CLS) 365 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 366 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 367 DCNTL_CLSE); 368 if (sc->features & SF_PCI_WRI) 369 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 370 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 371 CTEST3_WRIE); 372 if (sc->maxburst) { 373 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 374 SIOP_CTEST5); 375 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 376 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 377 ~CTEST4_BDIS); 378 dmode &= ~DMODE_BL_MASK; 379 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 380 ctest5 &= ~CTEST5_BBCK; 381 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 382 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 383 } else { 384 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 385 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 386 CTEST4_BDIS); 387 } 388 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 389 } 390
Indexes created Wed Sep 24 05:09:52 GMT 2025