siop_pci_common.c revision 1.8
1 /* $NetBSD: siop_pci_common.c,v 1.8 2001/03/15 17:41:28 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* SYM53c8xx PCI-SCSI I/O Processors driver: PCI front-end */ 33 34 #include <sys/param.h> 35 #include <sys/systm.h> 36 #include <sys/device.h> 37 #include <sys/malloc.h> 38 #include <sys/buf.h> 39 #include <sys/kernel.h> 40 41 #include <machine/endian.h> 42 43 #include <dev/pci/pcireg.h> 44 #include <dev/pci/pcivar.h> 45 #include <dev/pci/pcidevs.h> 46 47 #include <dev/scsipi/scsipi_all.h> 48 #include <dev/scsipi/scsipiconf.h> 49 50 #include <dev/ic/siopreg.h> 51 #include <dev/ic/siopvar.h> 52 #include <dev/pci/siop_pci_common.h> 53 54 /* List (array, really :) of chips we know how to handle */ 55 const struct siop_product_desc siop_products[] = { 56 { PCI_PRODUCT_SYMBIOS_810, 57 0x00, 58 "Symbios Logic 53c810 (fast scsi)", 59 SF_PCI_RL | SF_CHIP_LS, 60 4, 8, 3, 250, 0 61 }, 62 { PCI_PRODUCT_SYMBIOS_810, 63 0x10, 64 "Symbios Logic 53c810a (fast scsi)", 65 SF_PCI_RL | SF_PCI_BOF | SF_CHIP_PF | SF_CHIP_LS, 66 4, 8, 3, 250, 0 67 }, 68 { PCI_PRODUCT_SYMBIOS_815, 69 0x00, 70 "Symbios Logic 53c815 (fast scsi)", 71 SF_PCI_RL | SF_PCI_BOF, 72 4, 8, 3, 250, 0 73 }, 74 { PCI_PRODUCT_SYMBIOS_820, 75 0x00, 76 "Symbios Logic 53c820 (fast wide scsi)", 77 SF_PCI_RL | SF_CHIP_LS | SF_BUS_WIDE, 78 4, 8, 3, 250, 0 79 }, 80 { PCI_PRODUCT_SYMBIOS_825, 81 0x00, 82 "Symbios Logic 53c825 (fast wide scsi)", 83 SF_PCI_RL | SF_PCI_BOF | SF_BUS_WIDE, 84 4, 8, 3, 250, 0 85 }, 86 { PCI_PRODUCT_SYMBIOS_825, 87 0x10, 88 "Symbios Logic 53c825a (fast wide scsi)", 89 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 90 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 91 SF_BUS_WIDE, 92 7, 8, 3, 250, 4096 93 }, 94 { PCI_PRODUCT_SYMBIOS_860, 95 0x00, 96 "Symbios Logic 53c860 (ultra scsi)", 97 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 98 SF_CHIP_PF | SF_CHIP_LS | 99 SF_BUS_ULTRA, 100 4, 8, 5, 125, 0 101 }, 102 { PCI_PRODUCT_SYMBIOS_875, 103 0x00, 104 "Symbios Logic 53c875 (ultra-wide scsi)", 105 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 106 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_LS | SF_CHIP_10REGS | 107 SF_BUS_ULTRA | SF_BUS_WIDE, 108 7, 16, 5, 125, 4096 109 }, 110 { PCI_PRODUCT_SYMBIOS_875, 111 0x02, 112 "Symbios Logic 53c875 (ultra-wide scsi)", 113 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 114 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 115 SF_CHIP_LS | SF_CHIP_10REGS | 116 SF_BUS_ULTRA | SF_BUS_WIDE, 117 7, 16, 5, 125, 4096 118 }, 119 { PCI_PRODUCT_SYMBIOS_875J, 120 0x00, 121 "Symbios Logic 53c875j (ultra-wide scsi)", 122 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 123 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 124 SF_CHIP_LS | SF_CHIP_10REGS | 125 SF_BUS_ULTRA | SF_BUS_WIDE, 126 7, 16, 5, 125, 4096 127 }, 128 { PCI_PRODUCT_SYMBIOS_885, 129 0x00, 130 "Symbios Logic 53c885 (ultra-wide scsi)", 131 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 132 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_DBLR | 133 SF_CHIP_LS | SF_CHIP_10REGS | 134 SF_BUS_ULTRA | SF_BUS_WIDE, 135 7, 16, 5, 125, 4096 136 }, 137 { PCI_PRODUCT_SYMBIOS_895, 138 0x00, 139 "Symbios Logic 53c895 (ultra2-wide scsi)", 140 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 141 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 142 SF_CHIP_LS | SF_CHIP_10REGS | 143 SF_BUS_ULTRA2 | SF_BUS_WIDE, 144 7, 31, 7, 62, 4096 145 }, 146 { PCI_PRODUCT_SYMBIOS_896, 147 0x00, 148 "Symbios Logic 53c896 (ultra2-wide scsi)", 149 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 150 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 151 SF_CHIP_LS | SF_CHIP_10REGS | 152 SF_BUS_ULTRA2 | SF_BUS_WIDE, 153 7, 31, 7, 62, 8192 154 }, 155 { PCI_PRODUCT_SYMBIOS_895A, 156 0x00, 157 "Symbios Logic 53c895a (ultra2-wide scsi)", 158 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 159 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 160 SF_CHIP_LS | SF_CHIP_10REGS | 161 SF_BUS_ULTRA2 | SF_BUS_WIDE, 162 7, 31, 7, 62, 8192 163 }, 164 { PCI_PRODUCT_SYMBIOS_1010, 165 0x00, 166 "Symbios Logic 53c1010-33 (ultra2-wide scsi)", 167 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 168 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | 169 SF_CHIP_LS | SF_CHIP_10REGS | SF_CHIP_DFBC | SF_CHIP_DBLR | 170 SF_BUS_ULTRA2 | SF_BUS_WIDE, 171 7, 31, 7, 62, 8192 172 }, 173 { PCI_PRODUCT_SYMBIOS_1510D, 174 0x00, 175 "Symbios Logic 53c1510d (ultra2-wide scsi)", 176 SF_PCI_RL | SF_PCI_CLS | SF_PCI_WRI | SF_PCI_RM | 177 SF_CHIP_FIFO | SF_CHIP_PF | SF_CHIP_RAM | SF_CHIP_QUAD | 178 SF_CHIP_LS | SF_CHIP_10REGS | 179 SF_BUS_ULTRA2 | SF_BUS_WIDE, 180 7, 31, 7, 62, 4096 181 }, 182 { 0, 183 0x00, 184 NULL, 185 0x00, 186 0, 0, 0, 0, 0 187 }, 188 }; 189 190 const struct siop_product_desc * 191 siop_lookup_product(id, rev) 192 u_int32_t id; 193 int rev; 194 { 195 const struct siop_product_desc *pp; 196 const struct siop_product_desc *rp = NULL; 197 198 if (PCI_VENDOR(id) != PCI_VENDOR_SYMBIOS) 199 return NULL; 200 201 for (pp = siop_products; pp->name != NULL; pp++) { 202 if (PCI_PRODUCT(id) == pp->product && pp->revision <= rev) 203 if (rp == NULL || pp->revision > rp->revision) 204 rp = pp; 205 } 206 return rp; 207 } 208 209 int 210 siop_pci_attach_common(sc, pa) 211 struct siop_pci_softc *sc; 212 struct pci_attach_args *pa; 213 { 214 pci_chipset_tag_t pc = pa->pa_pc; 215 pcitag_t tag = pa->pa_tag; 216 const char *intrstr; 217 pci_intr_handle_t intrhandle; 218 bus_space_tag_t iot, memt; 219 bus_space_handle_t ioh, memh; 220 pcireg_t memtype; 221 int memh_valid, ioh_valid; 222 bus_addr_t ioaddr, memaddr; 223 224 sc->sc_pp = siop_lookup_product(pa->pa_id, PCI_REVISION(pa->pa_class)); 225 if (sc->sc_pp == NULL) { 226 printf("sym: broken match/attach!!\n"); 227 return 0; 228 } 229 /* copy interesting infos about the chip */ 230 sc->siop.features = sc->sc_pp->features; 231 sc->siop.maxburst = sc->sc_pp->maxburst; 232 sc->siop.maxoff = sc->sc_pp->maxoff; 233 sc->siop.clock_div = sc->sc_pp->clock_div; 234 sc->siop.clock_period = sc->sc_pp->clock_period; 235 sc->siop.ram_size = sc->sc_pp->ram_size; 236 237 sc->siop.sc_reset = siop_pci_reset; 238 printf(": %s\n", sc->sc_pp->name); 239 sc->sc_pc = pc; 240 sc->sc_tag = tag; 241 sc->siop.sc_dmat = pa->pa_dmat; 242 243 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, 0x14); 244 switch (memtype) { 245 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 246 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 247 memh_valid = (pci_mapreg_map(pa, 0x14, memtype, 0, 248 &memt, &memh, &memaddr, NULL) == 0); 249 break; 250 default: 251 memh_valid = 0; 252 } 253 254 ioh_valid = (pci_mapreg_map(pa, 0x10, PCI_MAPREG_TYPE_IO, 0, 255 &iot, &ioh, &ioaddr, NULL) == 0); 256 257 if (memh_valid) { 258 sc->siop.sc_rt = memt; 259 sc->siop.sc_rh = memh; 260 sc->siop.sc_raddr = memaddr; 261 } else if (ioh_valid) { 262 sc->siop.sc_rt = iot; 263 sc->siop.sc_rh = ioh; 264 sc->siop.sc_raddr = ioaddr; 265 } else { 266 printf("%s: unable to map device registers\n", 267 sc->siop.sc_dev.dv_xname); 268 return 0; 269 } 270 271 if (sc->siop.features & SF_CHIP_RAM) { 272 int bar; 273 switch (memtype) { 274 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT: 275 bar = 0x18; 276 break; 277 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT: 278 bar = 0x1c; 279 break; 280 } 281 if (pci_mapreg_map(pa, bar, memtype, 0, 282 &sc->siop.sc_ramt, &sc->siop.sc_ramh, 283 &sc->siop.sc_scriptaddr, NULL) == 0) { 284 printf("%s: using on-board RAM\n", 285 sc->siop.sc_dev.dv_xname); 286 } else { 287 printf("%s: can't map on-board RAM\n", 288 sc->siop.sc_dev.dv_xname); 289 sc->siop.features &= ~SF_CHIP_RAM; 290 } 291 } 292 293 if (pci_intr_map(pa, &intrhandle) != 0) { 294 printf("%s: couldn't map interrupt\n", 295 sc->siop.sc_dev.dv_xname); 296 return 0; 297 } 298 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 299 sc->sc_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 300 siop_intr, &sc->siop); 301 if (sc->sc_ih != NULL) { 302 printf("%s: interrupting at %s\n", 303 sc->siop.sc_dev.dv_xname, 304 intrstr ? intrstr : "unknown interrupt"); 305 } else { 306 printf("%s: couldn't establish interrupt", 307 sc->siop.sc_dev.dv_xname); 308 if (intrstr != NULL) 309 printf(" at %s", intrstr); 310 printf("\n"); 311 return 0; 312 } 313 return 1; 314 } 315 316 void 317 siop_pci_reset(sc) 318 struct siop_softc *sc; 319 { 320 int dmode; 321 322 dmode = bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE); 323 if (sc->features & SF_PCI_RL) 324 dmode |= DMODE_ERL; 325 if (sc->features & SF_PCI_RM) 326 dmode |= DMODE_ERMP; 327 if (sc->features & SF_PCI_BOF) 328 dmode |= DMODE_BOF; 329 if (sc->features & SF_PCI_CLS) 330 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL, 331 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_DCNTL) | 332 DCNTL_CLSE); 333 if (sc->features & SF_PCI_WRI) 334 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3, 335 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST3) | 336 CTEST3_WRIE); 337 if (sc->maxburst) { 338 int ctest5 = bus_space_read_1(sc->sc_rt, sc->sc_rh, 339 SIOP_CTEST5); 340 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 341 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) & 342 ~CTEST4_BDIS); 343 dmode &= ~DMODE_BL_MASK; 344 dmode |= ((sc->maxburst - 1) << DMODE_BL_SHIFT) & DMODE_BL_MASK; 345 ctest5 &= ~CTEST5_BBCK; 346 ctest5 |= (sc->maxburst - 1) & CTEST5_BBCK; 347 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST5, ctest5); 348 } else { 349 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4, 350 bus_space_read_1(sc->sc_rt, sc->sc_rh, SIOP_CTEST4) | 351 CTEST4_BDIS); 352 } 353 bus_space_write_1(sc->sc_rt, sc->sc_rh, SIOP_DMODE, dmode); 354 } 355
Indexes created Tue Sep 23 14:10:03 GMT 2025