siside.c revision 1.14
1 /* $NetBSD: siside.c,v 1.14 2005/02/27 00:27:34 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_sis_reg.h> 40 41 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 43 static void sis_setup_channel(struct ata_channel *); 44 static void sis96x_setup_channel(struct ata_channel *); 45 46 static int sis_hostbr_match(struct pci_attach_args *); 47 static int sis_south_match(struct pci_attach_args *); 48 49 static int siside_match(struct device *, struct cfdata *, void *); 50 static void siside_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 53 siside_match, siside_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_sis_products[] = { 56 { PCI_PRODUCT_SIS_5597_IDE, 57 0, 58 NULL, 59 sis_chip_map, 60 }, 61 { PCI_PRODUCT_SIS_180_SATA, 62 0, 63 NULL, 64 sis_sata_chip_map, 65 }, 66 { 0, 67 0, 68 NULL, 69 NULL 70 } 71 }; 72 73 static int 74 siside_match(struct device *parent, struct cfdata *match, void *aux) 75 { 76 struct pci_attach_args *pa = aux; 77 78 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 79 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 80 return (2); 81 } 82 return (0); 83 } 84 85 static void 86 siside_attach(struct device *parent, struct device *self, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 struct pciide_softc *sc = (struct pciide_softc *)self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 93 94 } 95 96 static struct sis_hostbr_type { 97 u_int16_t id; 98 u_int8_t rev; 99 u_int8_t udma_mode; 100 char *name; 101 u_int8_t type; 102 #define SIS_TYPE_NOUDMA 0 103 #define SIS_TYPE_66 1 104 #define SIS_TYPE_100OLD 2 105 #define SIS_TYPE_100NEW 3 106 #define SIS_TYPE_133OLD 4 107 #define SIS_TYPE_133NEW 5 108 #define SIS_TYPE_SOUTH 6 109 } sis_hostbr_type[] = { 110 /* Most infos here are from sos (at) freebsd.org */ 111 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 112 #if 0 113 /* 114 * controllers associated to a rev 0x2 530 Host to PCI Bridge 115 * have problems with UDMA (info provided by Christos) 116 */ 117 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 118 #endif 119 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 120 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 121 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 122 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 123 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 124 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 125 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 126 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 127 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 128 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 129 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 130 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 131 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 132 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 134 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 135 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 136 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 137 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 138 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 139 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 140 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 141 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 144 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 147 /* 148 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 149 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 150 */ 151 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 152 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 153 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 154 }; 155 156 static struct sis_hostbr_type *sis_hostbr_type_match; 157 158 static int 159 sis_hostbr_match(struct pci_attach_args *pa) 160 { 161 int i; 162 163 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 164 return 0; 165 sis_hostbr_type_match = NULL; 166 for (i = 0; 167 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 168 i++) { 169 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 170 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 171 sis_hostbr_type_match = &sis_hostbr_type[i]; 172 } 173 return (sis_hostbr_type_match != NULL); 174 } 175 176 static int 177 sis_south_match(struct pci_attach_args *pa) 178 { 179 180 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 181 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 182 PCI_REVISION(pa->pa_class) >= 0x10); 183 } 184 185 static void 186 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 187 { 188 struct pciide_channel *cp; 189 int channel; 190 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 191 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 192 pcireg_t rev = PCI_REVISION(pa->pa_class); 193 bus_size_t cmdsize, ctlsize; 194 195 if (pciide_chipen(sc, pa) == 0) 196 return; 197 198 aprint_normal("%s: Silicon Integrated Systems ", 199 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 200 pci_find_device(NULL, sis_hostbr_match); 201 if (sis_hostbr_type_match) { 202 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 203 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 204 pciide_pci_read(sc->sc_pc, sc->sc_tag, 205 SIS_REG_57) & 0x7f); 206 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 207 PCI_ID_REG)) == SIS_PRODUCT_5518) { 208 aprint_normal("96X UDMA%d", 209 sis_hostbr_type_match->udma_mode); 210 sc->sis_type = SIS_TYPE_133NEW; 211 sc->sc_wdcdev.sc_atac.atac_udma_cap = 212 sis_hostbr_type_match->udma_mode; 213 } else { 214 if (pci_find_device(NULL, sis_south_match)) { 215 sc->sis_type = SIS_TYPE_133OLD; 216 sc->sc_wdcdev.sc_atac.atac_udma_cap = 217 sis_hostbr_type_match->udma_mode; 218 } else { 219 sc->sis_type = SIS_TYPE_100NEW; 220 sc->sc_wdcdev.sc_atac.atac_udma_cap = 221 sis_hostbr_type_match->udma_mode; 222 } 223 } 224 } else { 225 sc->sis_type = sis_hostbr_type_match->type; 226 sc->sc_wdcdev.sc_atac.atac_udma_cap = 227 sis_hostbr_type_match->udma_mode; 228 } 229 aprint_normal(sis_hostbr_type_match->name); 230 } else { 231 aprint_normal("5597/5598"); 232 if (rev >= 0xd0) { 233 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 234 sc->sis_type = SIS_TYPE_66; 235 } else { 236 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 237 sc->sis_type = SIS_TYPE_NOUDMA; 238 } 239 } 240 aprint_normal(" IDE controller (rev. 0x%02x)\n", 241 PCI_REVISION(pa->pa_class)); 242 aprint_normal("%s: bus-master DMA support present", 243 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 244 pciide_mapreg_dma(sc, pa); 245 aprint_normal("\n"); 246 247 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 248 if (sc->sc_dma_ok) { 249 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 250 sc->sc_wdcdev.irqack = pciide_irqack; 251 if (sc->sis_type >= SIS_TYPE_66) 252 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 253 } 254 255 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 256 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 257 258 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 259 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 260 switch(sc->sis_type) { 261 case SIS_TYPE_NOUDMA: 262 case SIS_TYPE_66: 263 case SIS_TYPE_100OLD: 264 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 265 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 266 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 267 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 268 break; 269 case SIS_TYPE_100NEW: 270 case SIS_TYPE_133OLD: 271 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 272 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 273 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 274 break; 275 case SIS_TYPE_133NEW: 276 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 277 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 278 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 279 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 280 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 281 break; 282 } 283 284 wdc_allocate_regs(&sc->sc_wdcdev); 285 286 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 287 channel++) { 288 cp = &sc->pciide_channels[channel]; 289 if (pciide_chansetup(sc, channel, interface) == 0) 290 continue; 291 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 292 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 293 aprint_normal("%s: %s channel ignored (disabled)\n", 294 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 295 cp->ata_channel.ch_flags |= ATACH_DISABLED; 296 continue; 297 } 298 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 299 pciide_pci_intr); 300 } 301 } 302 303 static void 304 sis96x_setup_channel(struct ata_channel *chp) 305 { 306 struct ata_drive_datas *drvp; 307 int drive, s; 308 u_int32_t sis_tim; 309 u_int32_t idedma_ctl; 310 int regtim; 311 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 312 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 313 314 sis_tim = 0; 315 idedma_ctl = 0; 316 /* setup DMA if needed */ 317 pciide_channel_dma_setup(cp); 318 319 for (drive = 0; drive < 2; drive++) { 320 regtim = SIS_TIM133( 321 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 322 chp->ch_channel, drive); 323 drvp = &chp->ch_drive[drive]; 324 /* If no drive, skip */ 325 if ((drvp->drive_flags & DRIVE) == 0) 326 continue; 327 /* add timing values, setup DMA if needed */ 328 if (drvp->drive_flags & DRIVE_UDMA) { 329 /* use Ultra/DMA */ 330 s = splbio(); 331 drvp->drive_flags &= ~DRIVE_DMA; 332 splx(s); 333 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 334 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 335 if (drvp->UDMA_mode > 2) 336 drvp->UDMA_mode = 2; 337 } 338 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 339 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 340 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 341 } else if (drvp->drive_flags & DRIVE_DMA) { 342 /* 343 * use Multiword DMA 344 * Timings will be used for both PIO and DMA, 345 * so adjust DMA mode if needed 346 */ 347 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 348 drvp->PIO_mode = drvp->DMA_mode + 2; 349 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 350 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 351 drvp->PIO_mode - 2 : 0; 352 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 353 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 354 } else { 355 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 356 } 357 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 358 "channel %d drive %d: 0x%x (reg 0x%x)\n", 359 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 360 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 361 } 362 if (idedma_ctl != 0) { 363 /* Add software bits in status register */ 364 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 365 idedma_ctl); 366 } 367 } 368 369 static void 370 sis_setup_channel(struct ata_channel *chp) 371 { 372 struct ata_drive_datas *drvp; 373 int drive, s; 374 u_int32_t sis_tim; 375 u_int32_t idedma_ctl; 376 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 377 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 378 379 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 380 "channel %d 0x%x\n", chp->ch_channel, 381 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 382 DEBUG_PROBE); 383 sis_tim = 0; 384 idedma_ctl = 0; 385 /* setup DMA if needed */ 386 pciide_channel_dma_setup(cp); 387 388 for (drive = 0; drive < 2; drive++) { 389 drvp = &chp->ch_drive[drive]; 390 /* If no drive, skip */ 391 if ((drvp->drive_flags & DRIVE) == 0) 392 continue; 393 /* add timing values, setup DMA if needed */ 394 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 395 (drvp->drive_flags & DRIVE_UDMA) == 0) 396 goto pio; 397 398 if (drvp->drive_flags & DRIVE_UDMA) { 399 /* use Ultra/DMA */ 400 s = splbio(); 401 drvp->drive_flags &= ~DRIVE_DMA; 402 splx(s); 403 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 404 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 405 if (drvp->UDMA_mode > 2) 406 drvp->UDMA_mode = 2; 407 } 408 switch (sc->sis_type) { 409 case SIS_TYPE_66: 410 case SIS_TYPE_100OLD: 411 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 412 SIS_TIM66_UDMA_TIME_OFF(drive); 413 break; 414 case SIS_TYPE_100NEW: 415 sis_tim |= 416 sis_udma100new_tim[drvp->UDMA_mode] << 417 SIS_TIM100_UDMA_TIME_OFF(drive); 418 case SIS_TYPE_133OLD: 419 sis_tim |= 420 sis_udma133old_tim[drvp->UDMA_mode] << 421 SIS_TIM100_UDMA_TIME_OFF(drive); 422 break; 423 default: 424 aprint_error("unknown SiS IDE type %d\n", 425 sc->sis_type); 426 } 427 } else { 428 /* 429 * use Multiword DMA 430 * Timings will be used for both PIO and DMA, 431 * so adjust DMA mode if needed 432 */ 433 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 434 drvp->PIO_mode = drvp->DMA_mode + 2; 435 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 436 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 437 drvp->PIO_mode - 2 : 0; 438 if (drvp->DMA_mode == 0) 439 drvp->PIO_mode = 0; 440 } 441 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 442 pio: switch (sc->sis_type) { 443 case SIS_TYPE_NOUDMA: 444 case SIS_TYPE_66: 445 case SIS_TYPE_100OLD: 446 sis_tim |= sis_pio_act[drvp->PIO_mode] << 447 SIS_TIM66_ACT_OFF(drive); 448 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 449 SIS_TIM66_REC_OFF(drive); 450 break; 451 case SIS_TYPE_100NEW: 452 case SIS_TYPE_133OLD: 453 sis_tim |= sis_pio_act[drvp->PIO_mode] << 454 SIS_TIM100_ACT_OFF(drive); 455 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 456 SIS_TIM100_REC_OFF(drive); 457 break; 458 default: 459 aprint_error("unknown SiS IDE type %d\n", 460 sc->sis_type); 461 } 462 } 463 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 464 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 465 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 466 sis_tim); 467 if (idedma_ctl != 0) { 468 /* Add software bits in status register */ 469 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 470 idedma_ctl); 471 } 472 } 473 474 static void 475 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 476 { 477 struct pciide_channel *cp; 478 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 479 int channel; 480 bus_size_t cmdsize, ctlsize; 481 482 if (pciide_chipen(sc, pa) == 0) 483 return; 484 485 if (interface == 0) { 486 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 487 DEBUG_PROBE); 488 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 489 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 490 } 491 492 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 493 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 494 PCI_REVISION(pa->pa_class)); 495 496 aprint_normal("%s: bus-master DMA support present", 497 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 498 pciide_mapreg_dma(sc, pa); 499 aprint_normal("\n"); 500 501 if (sc->sc_dma_ok) { 502 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 503 sc->sc_wdcdev.irqack = pciide_irqack; 504 } 505 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 506 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 507 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 508 509 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 510 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 511 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 512 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 513 514 wdc_allocate_regs(&sc->sc_wdcdev); 515 516 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 517 channel++) { 518 cp = &sc->pciide_channels[channel]; 519 if (pciide_chansetup(sc, channel, interface) == 0) 520 continue; 521 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 522 pciide_pci_intr); 523 } 524 } 525
Indexes created Mon Sep 29 21:09:56 GMT 2025