siside.c revision 1.14.2.1
1 /* $NetBSD: siside.c,v 1.14.2.1 2005/06/26 11:24:34 tron Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_sis_reg.h> 40 41 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 43 static void sis_setup_channel(struct ata_channel *); 44 static void sis96x_setup_channel(struct ata_channel *); 45 46 static int sis_hostbr_match(struct pci_attach_args *); 47 static int sis_south_match(struct pci_attach_args *); 48 49 static int siside_match(struct device *, struct cfdata *, void *); 50 static void siside_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 53 siside_match, siside_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_sis_products[] = { 56 { PCI_PRODUCT_SIS_5597_IDE, 57 0, 58 NULL, 59 sis_chip_map, 60 }, 61 { PCI_PRODUCT_SIS_180_SATA, 62 0, 63 NULL, 64 sis_sata_chip_map, 65 }, 66 { 0, 67 0, 68 NULL, 69 NULL 70 } 71 }; 72 73 static int 74 siside_match(struct device *parent, struct cfdata *match, void *aux) 75 { 76 struct pci_attach_args *pa = aux; 77 78 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 79 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 80 return (2); 81 } 82 return (0); 83 } 84 85 static void 86 siside_attach(struct device *parent, struct device *self, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 struct pciide_softc *sc = (struct pciide_softc *)self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 93 94 } 95 96 static struct sis_hostbr_type { 97 u_int16_t id; 98 u_int8_t rev; 99 u_int8_t udma_mode; 100 char *name; 101 u_int8_t type; 102 #define SIS_TYPE_NOUDMA 0 103 #define SIS_TYPE_66 1 104 #define SIS_TYPE_100OLD 2 105 #define SIS_TYPE_100NEW 3 106 #define SIS_TYPE_133OLD 4 107 #define SIS_TYPE_133NEW 5 108 #define SIS_TYPE_SOUTH 6 109 } sis_hostbr_type[] = { 110 /* Most infos here are from sos (at) freebsd.org */ 111 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 112 #if 0 113 /* 114 * controllers associated to a rev 0x2 530 Host to PCI Bridge 115 * have problems with UDMA (info provided by Christos) 116 */ 117 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 118 #endif 119 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 120 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 121 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 122 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 123 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 124 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 125 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 126 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 127 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 128 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 129 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 130 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 131 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 132 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 134 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 135 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 136 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 137 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 138 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 139 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 140 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 141 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 144 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 147 /* 148 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 149 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 150 */ 151 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 152 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 153 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 154 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 155 }; 156 157 static struct sis_hostbr_type *sis_hostbr_type_match; 158 159 static int 160 sis_hostbr_match(struct pci_attach_args *pa) 161 { 162 int i; 163 pcireg_t id, reg; 164 165 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 166 return 0; 167 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503) { 168 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 169 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 170 reg | SIS96x_DETECT_MASQ); 171 id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 172 if (((PCI_PRODUCT(id) & 0xfff0) != 0x0960) 173 && (PCI_PRODUCT(id) != 0x0018)) { 174 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 175 reg); 176 } else { 177 pa->pa_id = id; 178 } 179 } 180 181 sis_hostbr_type_match = NULL; 182 for (i = 0; 183 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 184 i++) { 185 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 186 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 187 sis_hostbr_type_match = &sis_hostbr_type[i]; 188 } 189 return (sis_hostbr_type_match != NULL); 190 } 191 192 static int 193 sis_south_match(struct pci_attach_args *pa) 194 { 195 196 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 197 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 198 PCI_REVISION(pa->pa_class) >= 0x10); 199 } 200 201 static void 202 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 203 { 204 struct pciide_channel *cp; 205 int channel; 206 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 207 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 208 pcireg_t rev = PCI_REVISION(pa->pa_class); 209 bus_size_t cmdsize, ctlsize; 210 211 if (pciide_chipen(sc, pa) == 0) 212 return; 213 214 aprint_normal("%s: Silicon Integrated Systems ", 215 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 216 pci_find_device(NULL, sis_hostbr_match); 217 if (sis_hostbr_type_match) { 218 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 219 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 220 pciide_pci_read(sc->sc_pc, sc->sc_tag, 221 SIS_REG_57) & 0x7f); 222 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 223 PCI_ID_REG)) == SIS_PRODUCT_5518) { 224 aprint_normal("96X UDMA%d", 225 sis_hostbr_type_match->udma_mode); 226 sc->sis_type = SIS_TYPE_133NEW; 227 sc->sc_wdcdev.sc_atac.atac_udma_cap = 228 sis_hostbr_type_match->udma_mode; 229 } else { 230 if (pci_find_device(NULL, sis_south_match)) { 231 sc->sis_type = SIS_TYPE_133OLD; 232 sc->sc_wdcdev.sc_atac.atac_udma_cap = 233 sis_hostbr_type_match->udma_mode; 234 } else { 235 sc->sis_type = SIS_TYPE_100NEW; 236 sc->sc_wdcdev.sc_atac.atac_udma_cap = 237 sis_hostbr_type_match->udma_mode; 238 } 239 } 240 } else { 241 sc->sis_type = sis_hostbr_type_match->type; 242 sc->sc_wdcdev.sc_atac.atac_udma_cap = 243 sis_hostbr_type_match->udma_mode; 244 } 245 aprint_normal(sis_hostbr_type_match->name); 246 } else { 247 aprint_normal("5597/5598"); 248 if (rev >= 0xd0) { 249 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 250 sc->sis_type = SIS_TYPE_66; 251 } else { 252 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 253 sc->sis_type = SIS_TYPE_NOUDMA; 254 } 255 } 256 aprint_normal(" IDE controller (rev. 0x%02x)\n", 257 PCI_REVISION(pa->pa_class)); 258 aprint_normal("%s: bus-master DMA support present", 259 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 260 pciide_mapreg_dma(sc, pa); 261 aprint_normal("\n"); 262 263 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 264 if (sc->sc_dma_ok) { 265 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 266 sc->sc_wdcdev.irqack = pciide_irqack; 267 if (sc->sis_type >= SIS_TYPE_66) 268 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 269 } 270 271 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 272 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 273 274 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 275 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 276 switch(sc->sis_type) { 277 case SIS_TYPE_NOUDMA: 278 case SIS_TYPE_66: 279 case SIS_TYPE_100OLD: 280 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 281 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 282 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 283 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 284 break; 285 case SIS_TYPE_100NEW: 286 case SIS_TYPE_133OLD: 287 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 288 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 289 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 290 break; 291 case SIS_TYPE_133NEW: 292 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 293 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 294 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 295 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 296 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 297 break; 298 } 299 300 wdc_allocate_regs(&sc->sc_wdcdev); 301 302 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 303 channel++) { 304 cp = &sc->pciide_channels[channel]; 305 if (pciide_chansetup(sc, channel, interface) == 0) 306 continue; 307 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 308 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 309 aprint_normal("%s: %s channel ignored (disabled)\n", 310 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 311 cp->ata_channel.ch_flags |= ATACH_DISABLED; 312 continue; 313 } 314 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 315 pciide_pci_intr); 316 } 317 } 318 319 static void 320 sis96x_setup_channel(struct ata_channel *chp) 321 { 322 struct ata_drive_datas *drvp; 323 int drive, s; 324 u_int32_t sis_tim; 325 u_int32_t idedma_ctl; 326 int regtim; 327 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 328 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 329 330 sis_tim = 0; 331 idedma_ctl = 0; 332 /* setup DMA if needed */ 333 pciide_channel_dma_setup(cp); 334 335 for (drive = 0; drive < 2; drive++) { 336 regtim = SIS_TIM133( 337 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 338 chp->ch_channel, drive); 339 drvp = &chp->ch_drive[drive]; 340 /* If no drive, skip */ 341 if ((drvp->drive_flags & DRIVE) == 0) 342 continue; 343 /* add timing values, setup DMA if needed */ 344 if (drvp->drive_flags & DRIVE_UDMA) { 345 /* use Ultra/DMA */ 346 s = splbio(); 347 drvp->drive_flags &= ~DRIVE_DMA; 348 splx(s); 349 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 350 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 351 if (drvp->UDMA_mode > 2) 352 drvp->UDMA_mode = 2; 353 } 354 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 355 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 356 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 357 } else if (drvp->drive_flags & DRIVE_DMA) { 358 /* 359 * use Multiword DMA 360 * Timings will be used for both PIO and DMA, 361 * so adjust DMA mode if needed 362 */ 363 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 364 drvp->PIO_mode = drvp->DMA_mode + 2; 365 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 366 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 367 drvp->PIO_mode - 2 : 0; 368 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 369 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 370 } else { 371 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 372 } 373 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 374 "channel %d drive %d: 0x%x (reg 0x%x)\n", 375 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 376 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 377 } 378 if (idedma_ctl != 0) { 379 /* Add software bits in status register */ 380 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 381 idedma_ctl); 382 } 383 } 384 385 static void 386 sis_setup_channel(struct ata_channel *chp) 387 { 388 struct ata_drive_datas *drvp; 389 int drive, s; 390 u_int32_t sis_tim; 391 u_int32_t idedma_ctl; 392 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 393 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 394 395 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 396 "channel %d 0x%x\n", chp->ch_channel, 397 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 398 DEBUG_PROBE); 399 sis_tim = 0; 400 idedma_ctl = 0; 401 /* setup DMA if needed */ 402 pciide_channel_dma_setup(cp); 403 404 for (drive = 0; drive < 2; drive++) { 405 drvp = &chp->ch_drive[drive]; 406 /* If no drive, skip */ 407 if ((drvp->drive_flags & DRIVE) == 0) 408 continue; 409 /* add timing values, setup DMA if needed */ 410 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 411 (drvp->drive_flags & DRIVE_UDMA) == 0) 412 goto pio; 413 414 if (drvp->drive_flags & DRIVE_UDMA) { 415 /* use Ultra/DMA */ 416 s = splbio(); 417 drvp->drive_flags &= ~DRIVE_DMA; 418 splx(s); 419 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 420 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 421 if (drvp->UDMA_mode > 2) 422 drvp->UDMA_mode = 2; 423 } 424 switch (sc->sis_type) { 425 case SIS_TYPE_66: 426 case SIS_TYPE_100OLD: 427 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 428 SIS_TIM66_UDMA_TIME_OFF(drive); 429 break; 430 case SIS_TYPE_100NEW: 431 sis_tim |= 432 sis_udma100new_tim[drvp->UDMA_mode] << 433 SIS_TIM100_UDMA_TIME_OFF(drive); 434 case SIS_TYPE_133OLD: 435 sis_tim |= 436 sis_udma133old_tim[drvp->UDMA_mode] << 437 SIS_TIM100_UDMA_TIME_OFF(drive); 438 break; 439 default: 440 aprint_error("unknown SiS IDE type %d\n", 441 sc->sis_type); 442 } 443 } else { 444 /* 445 * use Multiword DMA 446 * Timings will be used for both PIO and DMA, 447 * so adjust DMA mode if needed 448 */ 449 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 450 drvp->PIO_mode = drvp->DMA_mode + 2; 451 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 452 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 453 drvp->PIO_mode - 2 : 0; 454 if (drvp->DMA_mode == 0) 455 drvp->PIO_mode = 0; 456 } 457 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 458 pio: switch (sc->sis_type) { 459 case SIS_TYPE_NOUDMA: 460 case SIS_TYPE_66: 461 case SIS_TYPE_100OLD: 462 sis_tim |= sis_pio_act[drvp->PIO_mode] << 463 SIS_TIM66_ACT_OFF(drive); 464 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 465 SIS_TIM66_REC_OFF(drive); 466 break; 467 case SIS_TYPE_100NEW: 468 case SIS_TYPE_133OLD: 469 sis_tim |= sis_pio_act[drvp->PIO_mode] << 470 SIS_TIM100_ACT_OFF(drive); 471 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 472 SIS_TIM100_REC_OFF(drive); 473 break; 474 default: 475 aprint_error("unknown SiS IDE type %d\n", 476 sc->sis_type); 477 } 478 } 479 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 480 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 481 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 482 sis_tim); 483 if (idedma_ctl != 0) { 484 /* Add software bits in status register */ 485 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 486 idedma_ctl); 487 } 488 } 489 490 static void 491 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 492 { 493 struct pciide_channel *cp; 494 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 495 int channel; 496 bus_size_t cmdsize, ctlsize; 497 498 if (pciide_chipen(sc, pa) == 0) 499 return; 500 501 if (interface == 0) { 502 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 503 DEBUG_PROBE); 504 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 505 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 506 } 507 508 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 509 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 510 PCI_REVISION(pa->pa_class)); 511 512 aprint_normal("%s: bus-master DMA support present", 513 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 514 pciide_mapreg_dma(sc, pa); 515 aprint_normal("\n"); 516 517 if (sc->sc_dma_ok) { 518 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 519 sc->sc_wdcdev.irqack = pciide_irqack; 520 } 521 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 522 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 523 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 524 525 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 526 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 527 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 528 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 529 530 wdc_allocate_regs(&sc->sc_wdcdev); 531 532 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 533 channel++) { 534 cp = &sc->pciide_channels[channel]; 535 if (pciide_chansetup(sc, channel, interface) == 0) 536 continue; 537 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 538 pciide_pci_intr); 539 } 540 } 541
Indexes created Mon Oct 20 20:10:13 GMT 2025