siside.c revision 1.15
1 /* $NetBSD: siside.c,v 1.15 2005/05/24 05:25:15 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.15 2005/05/24 05:25:15 lukem Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_sis_reg.h> 43 44 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 46 static void sis_setup_channel(struct ata_channel *); 47 static void sis96x_setup_channel(struct ata_channel *); 48 49 static int sis_hostbr_match(struct pci_attach_args *); 50 static int sis_south_match(struct pci_attach_args *); 51 52 static int siside_match(struct device *, struct cfdata *, void *); 53 static void siside_attach(struct device *, struct device *, void *); 54 55 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 56 siside_match, siside_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_sis_products[] = { 59 { PCI_PRODUCT_SIS_5597_IDE, 60 0, 61 NULL, 62 sis_chip_map, 63 }, 64 { PCI_PRODUCT_SIS_180_SATA, 65 0, 66 NULL, 67 sis_sata_chip_map, 68 }, 69 { 0, 70 0, 71 NULL, 72 NULL 73 } 74 }; 75 76 static int 77 siside_match(struct device *parent, struct cfdata *match, void *aux) 78 { 79 struct pci_attach_args *pa = aux; 80 81 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 82 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 83 return (2); 84 } 85 return (0); 86 } 87 88 static void 89 siside_attach(struct device *parent, struct device *self, void *aux) 90 { 91 struct pci_attach_args *pa = aux; 92 struct pciide_softc *sc = (struct pciide_softc *)self; 93 94 pciide_common_attach(sc, pa, 95 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 96 97 } 98 99 static struct sis_hostbr_type { 100 u_int16_t id; 101 u_int8_t rev; 102 u_int8_t udma_mode; 103 char *name; 104 u_int8_t type; 105 #define SIS_TYPE_NOUDMA 0 106 #define SIS_TYPE_66 1 107 #define SIS_TYPE_100OLD 2 108 #define SIS_TYPE_100NEW 3 109 #define SIS_TYPE_133OLD 4 110 #define SIS_TYPE_133NEW 5 111 #define SIS_TYPE_SOUTH 6 112 } sis_hostbr_type[] = { 113 /* Most infos here are from sos (at) freebsd.org */ 114 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 115 #if 0 116 /* 117 * controllers associated to a rev 0x2 530 Host to PCI Bridge 118 * have problems with UDMA (info provided by Christos) 119 */ 120 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 121 #endif 122 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 123 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 124 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 125 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 126 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 127 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 128 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 129 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 130 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 131 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 132 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 134 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 135 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 136 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 137 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 138 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 139 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 140 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 141 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 144 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 147 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 150 /* 151 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 152 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 153 */ 154 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 155 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 156 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 157 }; 158 159 static struct sis_hostbr_type *sis_hostbr_type_match; 160 161 static int 162 sis_hostbr_match(struct pci_attach_args *pa) 163 { 164 int i; 165 166 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 167 return 0; 168 sis_hostbr_type_match = NULL; 169 for (i = 0; 170 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 171 i++) { 172 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 173 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 174 sis_hostbr_type_match = &sis_hostbr_type[i]; 175 } 176 return (sis_hostbr_type_match != NULL); 177 } 178 179 static int 180 sis_south_match(struct pci_attach_args *pa) 181 { 182 183 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 184 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 185 PCI_REVISION(pa->pa_class) >= 0x10); 186 } 187 188 static void 189 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 190 { 191 struct pciide_channel *cp; 192 int channel; 193 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 194 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 195 pcireg_t rev = PCI_REVISION(pa->pa_class); 196 bus_size_t cmdsize, ctlsize; 197 198 if (pciide_chipen(sc, pa) == 0) 199 return; 200 201 aprint_normal("%s: Silicon Integrated Systems ", 202 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 203 pci_find_device(NULL, sis_hostbr_match); 204 if (sis_hostbr_type_match) { 205 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 206 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 207 pciide_pci_read(sc->sc_pc, sc->sc_tag, 208 SIS_REG_57) & 0x7f); 209 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 210 PCI_ID_REG)) == SIS_PRODUCT_5518) { 211 aprint_normal("96X UDMA%d", 212 sis_hostbr_type_match->udma_mode); 213 sc->sis_type = SIS_TYPE_133NEW; 214 sc->sc_wdcdev.sc_atac.atac_udma_cap = 215 sis_hostbr_type_match->udma_mode; 216 } else { 217 if (pci_find_device(NULL, sis_south_match)) { 218 sc->sis_type = SIS_TYPE_133OLD; 219 sc->sc_wdcdev.sc_atac.atac_udma_cap = 220 sis_hostbr_type_match->udma_mode; 221 } else { 222 sc->sis_type = SIS_TYPE_100NEW; 223 sc->sc_wdcdev.sc_atac.atac_udma_cap = 224 sis_hostbr_type_match->udma_mode; 225 } 226 } 227 } else { 228 sc->sis_type = sis_hostbr_type_match->type; 229 sc->sc_wdcdev.sc_atac.atac_udma_cap = 230 sis_hostbr_type_match->udma_mode; 231 } 232 aprint_normal(sis_hostbr_type_match->name); 233 } else { 234 aprint_normal("5597/5598"); 235 if (rev >= 0xd0) { 236 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 237 sc->sis_type = SIS_TYPE_66; 238 } else { 239 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 240 sc->sis_type = SIS_TYPE_NOUDMA; 241 } 242 } 243 aprint_normal(" IDE controller (rev. 0x%02x)\n", 244 PCI_REVISION(pa->pa_class)); 245 aprint_normal("%s: bus-master DMA support present", 246 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 247 pciide_mapreg_dma(sc, pa); 248 aprint_normal("\n"); 249 250 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 251 if (sc->sc_dma_ok) { 252 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 253 sc->sc_wdcdev.irqack = pciide_irqack; 254 if (sc->sis_type >= SIS_TYPE_66) 255 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 256 } 257 258 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 259 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 260 261 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 262 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 263 switch(sc->sis_type) { 264 case SIS_TYPE_NOUDMA: 265 case SIS_TYPE_66: 266 case SIS_TYPE_100OLD: 267 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 268 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 269 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 270 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 271 break; 272 case SIS_TYPE_100NEW: 273 case SIS_TYPE_133OLD: 274 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 275 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 276 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 277 break; 278 case SIS_TYPE_133NEW: 279 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 280 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 281 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 282 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 283 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 284 break; 285 } 286 287 wdc_allocate_regs(&sc->sc_wdcdev); 288 289 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 290 channel++) { 291 cp = &sc->pciide_channels[channel]; 292 if (pciide_chansetup(sc, channel, interface) == 0) 293 continue; 294 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 295 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 296 aprint_normal("%s: %s channel ignored (disabled)\n", 297 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 298 cp->ata_channel.ch_flags |= ATACH_DISABLED; 299 continue; 300 } 301 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 302 pciide_pci_intr); 303 } 304 } 305 306 static void 307 sis96x_setup_channel(struct ata_channel *chp) 308 { 309 struct ata_drive_datas *drvp; 310 int drive, s; 311 u_int32_t sis_tim; 312 u_int32_t idedma_ctl; 313 int regtim; 314 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 315 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 316 317 sis_tim = 0; 318 idedma_ctl = 0; 319 /* setup DMA if needed */ 320 pciide_channel_dma_setup(cp); 321 322 for (drive = 0; drive < 2; drive++) { 323 regtim = SIS_TIM133( 324 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 325 chp->ch_channel, drive); 326 drvp = &chp->ch_drive[drive]; 327 /* If no drive, skip */ 328 if ((drvp->drive_flags & DRIVE) == 0) 329 continue; 330 /* add timing values, setup DMA if needed */ 331 if (drvp->drive_flags & DRIVE_UDMA) { 332 /* use Ultra/DMA */ 333 s = splbio(); 334 drvp->drive_flags &= ~DRIVE_DMA; 335 splx(s); 336 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 337 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 338 if (drvp->UDMA_mode > 2) 339 drvp->UDMA_mode = 2; 340 } 341 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 342 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 343 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 344 } else if (drvp->drive_flags & DRIVE_DMA) { 345 /* 346 * use Multiword DMA 347 * Timings will be used for both PIO and DMA, 348 * so adjust DMA mode if needed 349 */ 350 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 351 drvp->PIO_mode = drvp->DMA_mode + 2; 352 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 353 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 354 drvp->PIO_mode - 2 : 0; 355 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 356 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 357 } else { 358 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 359 } 360 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 361 "channel %d drive %d: 0x%x (reg 0x%x)\n", 362 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 363 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 364 } 365 if (idedma_ctl != 0) { 366 /* Add software bits in status register */ 367 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 368 idedma_ctl); 369 } 370 } 371 372 static void 373 sis_setup_channel(struct ata_channel *chp) 374 { 375 struct ata_drive_datas *drvp; 376 int drive, s; 377 u_int32_t sis_tim; 378 u_int32_t idedma_ctl; 379 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 380 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 381 382 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 383 "channel %d 0x%x\n", chp->ch_channel, 384 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 385 DEBUG_PROBE); 386 sis_tim = 0; 387 idedma_ctl = 0; 388 /* setup DMA if needed */ 389 pciide_channel_dma_setup(cp); 390 391 for (drive = 0; drive < 2; drive++) { 392 drvp = &chp->ch_drive[drive]; 393 /* If no drive, skip */ 394 if ((drvp->drive_flags & DRIVE) == 0) 395 continue; 396 /* add timing values, setup DMA if needed */ 397 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 398 (drvp->drive_flags & DRIVE_UDMA) == 0) 399 goto pio; 400 401 if (drvp->drive_flags & DRIVE_UDMA) { 402 /* use Ultra/DMA */ 403 s = splbio(); 404 drvp->drive_flags &= ~DRIVE_DMA; 405 splx(s); 406 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 407 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 408 if (drvp->UDMA_mode > 2) 409 drvp->UDMA_mode = 2; 410 } 411 switch (sc->sis_type) { 412 case SIS_TYPE_66: 413 case SIS_TYPE_100OLD: 414 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 415 SIS_TIM66_UDMA_TIME_OFF(drive); 416 break; 417 case SIS_TYPE_100NEW: 418 sis_tim |= 419 sis_udma100new_tim[drvp->UDMA_mode] << 420 SIS_TIM100_UDMA_TIME_OFF(drive); 421 case SIS_TYPE_133OLD: 422 sis_tim |= 423 sis_udma133old_tim[drvp->UDMA_mode] << 424 SIS_TIM100_UDMA_TIME_OFF(drive); 425 break; 426 default: 427 aprint_error("unknown SiS IDE type %d\n", 428 sc->sis_type); 429 } 430 } else { 431 /* 432 * use Multiword DMA 433 * Timings will be used for both PIO and DMA, 434 * so adjust DMA mode if needed 435 */ 436 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 437 drvp->PIO_mode = drvp->DMA_mode + 2; 438 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 439 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 440 drvp->PIO_mode - 2 : 0; 441 if (drvp->DMA_mode == 0) 442 drvp->PIO_mode = 0; 443 } 444 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 445 pio: switch (sc->sis_type) { 446 case SIS_TYPE_NOUDMA: 447 case SIS_TYPE_66: 448 case SIS_TYPE_100OLD: 449 sis_tim |= sis_pio_act[drvp->PIO_mode] << 450 SIS_TIM66_ACT_OFF(drive); 451 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 452 SIS_TIM66_REC_OFF(drive); 453 break; 454 case SIS_TYPE_100NEW: 455 case SIS_TYPE_133OLD: 456 sis_tim |= sis_pio_act[drvp->PIO_mode] << 457 SIS_TIM100_ACT_OFF(drive); 458 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 459 SIS_TIM100_REC_OFF(drive); 460 break; 461 default: 462 aprint_error("unknown SiS IDE type %d\n", 463 sc->sis_type); 464 } 465 } 466 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 467 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 468 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 469 sis_tim); 470 if (idedma_ctl != 0) { 471 /* Add software bits in status register */ 472 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 473 idedma_ctl); 474 } 475 } 476 477 static void 478 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 479 { 480 struct pciide_channel *cp; 481 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 482 int channel; 483 bus_size_t cmdsize, ctlsize; 484 485 if (pciide_chipen(sc, pa) == 0) 486 return; 487 488 if (interface == 0) { 489 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 490 DEBUG_PROBE); 491 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 492 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 493 } 494 495 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 496 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 497 PCI_REVISION(pa->pa_class)); 498 499 aprint_normal("%s: bus-master DMA support present", 500 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 501 pciide_mapreg_dma(sc, pa); 502 aprint_normal("\n"); 503 504 if (sc->sc_dma_ok) { 505 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 506 sc->sc_wdcdev.irqack = pciide_irqack; 507 } 508 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 509 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 510 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 511 512 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 513 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 514 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 515 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 516 517 wdc_allocate_regs(&sc->sc_wdcdev); 518 519 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 520 channel++) { 521 cp = &sc->pciide_channels[channel]; 522 if (pciide_chansetup(sc, channel, interface) == 0) 523 continue; 524 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 525 pciide_pci_intr); 526 } 527 } 528
Indexes created Mon Sep 29 21:09:56 GMT 2025