siside.c revision 1.17
1 /* $NetBSD: siside.c,v 1.17 2005/06/16 19:30:02 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.17 2005/06/16 19:30:02 bouyer Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_sis_reg.h> 43 44 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 46 static void sis_setup_channel(struct ata_channel *); 47 static void sis96x_setup_channel(struct ata_channel *); 48 49 static int sis_hostbr_match(struct pci_attach_args *); 50 static int sis_south_match(struct pci_attach_args *); 51 52 static int siside_match(struct device *, struct cfdata *, void *); 53 static void siside_attach(struct device *, struct device *, void *); 54 55 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 56 siside_match, siside_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_sis_products[] = { 59 { PCI_PRODUCT_SIS_5597_IDE, 60 0, 61 NULL, 62 sis_chip_map, 63 }, 64 { PCI_PRODUCT_SIS_180_SATA, 65 0, 66 NULL, 67 sis_sata_chip_map, 68 }, 69 { 0, 70 0, 71 NULL, 72 NULL 73 } 74 }; 75 76 static int 77 siside_match(struct device *parent, struct cfdata *match, void *aux) 78 { 79 struct pci_attach_args *pa = aux; 80 81 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 82 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 83 return (2); 84 } 85 return (0); 86 } 87 88 static void 89 siside_attach(struct device *parent, struct device *self, void *aux) 90 { 91 struct pci_attach_args *pa = aux; 92 struct pciide_softc *sc = (struct pciide_softc *)self; 93 94 pciide_common_attach(sc, pa, 95 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 96 97 } 98 99 static struct sis_hostbr_type { 100 u_int16_t id; 101 u_int8_t rev; 102 u_int8_t udma_mode; 103 const char *name; 104 u_int8_t type; 105 #define SIS_TYPE_NOUDMA 0 106 #define SIS_TYPE_66 1 107 #define SIS_TYPE_100OLD 2 108 #define SIS_TYPE_100NEW 3 109 #define SIS_TYPE_133OLD 4 110 #define SIS_TYPE_133NEW 5 111 #define SIS_TYPE_SOUTH 6 112 } sis_hostbr_type[] = { 113 /* Most infos here are from sos (at) freebsd.org */ 114 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 115 #if 0 116 /* 117 * controllers associated to a rev 0x2 530 Host to PCI Bridge 118 * have problems with UDMA (info provided by Christos) 119 */ 120 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 121 #endif 122 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 123 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 124 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 125 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 126 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 127 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 128 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 129 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 130 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 131 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 132 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 134 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 135 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 136 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 137 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 138 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 139 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 140 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 141 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 144 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 147 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 150 /* 151 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 152 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 153 */ 154 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 155 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 156 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 157 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 158 }; 159 160 static struct sis_hostbr_type *sis_hostbr_type_match; 161 162 static int 163 sis_hostbr_match(struct pci_attach_args *pa) 164 { 165 int i; 166 pcireg_t id, reg; 167 168 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 169 return 0; 170 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503) { 171 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 172 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 173 reg | SIS96x_DETECT_MASQ); 174 id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 175 if (((PCI_PRODUCT(id) & 0xfff0) != 0x0960) 176 && (PCI_PRODUCT(id) != 0x0018)) { 177 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 178 reg); 179 } else { 180 pa->pa_id = id; 181 } 182 } 183 184 sis_hostbr_type_match = NULL; 185 for (i = 0; 186 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 187 i++) { 188 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 189 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 190 sis_hostbr_type_match = &sis_hostbr_type[i]; 191 } 192 return (sis_hostbr_type_match != NULL); 193 } 194 195 static int 196 sis_south_match(struct pci_attach_args *pa) 197 { 198 199 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 200 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 201 PCI_REVISION(pa->pa_class) >= 0x10); 202 } 203 204 static void 205 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 206 { 207 struct pciide_channel *cp; 208 int channel; 209 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 210 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 211 pcireg_t rev = PCI_REVISION(pa->pa_class); 212 bus_size_t cmdsize, ctlsize; 213 214 if (pciide_chipen(sc, pa) == 0) 215 return; 216 217 aprint_normal("%s: Silicon Integrated Systems ", 218 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 219 pci_find_device(NULL, sis_hostbr_match); 220 if (sis_hostbr_type_match) { 221 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 222 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 223 pciide_pci_read(sc->sc_pc, sc->sc_tag, 224 SIS_REG_57) & 0x7f); 225 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 226 PCI_ID_REG)) == SIS_PRODUCT_5518) { 227 aprint_normal("96X UDMA%d", 228 sis_hostbr_type_match->udma_mode); 229 sc->sis_type = SIS_TYPE_133NEW; 230 sc->sc_wdcdev.sc_atac.atac_udma_cap = 231 sis_hostbr_type_match->udma_mode; 232 } else { 233 if (pci_find_device(NULL, sis_south_match)) { 234 sc->sis_type = SIS_TYPE_133OLD; 235 sc->sc_wdcdev.sc_atac.atac_udma_cap = 236 sis_hostbr_type_match->udma_mode; 237 } else { 238 sc->sis_type = SIS_TYPE_100NEW; 239 sc->sc_wdcdev.sc_atac.atac_udma_cap = 240 sis_hostbr_type_match->udma_mode; 241 } 242 } 243 } else { 244 sc->sis_type = sis_hostbr_type_match->type; 245 sc->sc_wdcdev.sc_atac.atac_udma_cap = 246 sis_hostbr_type_match->udma_mode; 247 } 248 aprint_normal(sis_hostbr_type_match->name); 249 } else { 250 aprint_normal("5597/5598"); 251 if (rev >= 0xd0) { 252 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 253 sc->sis_type = SIS_TYPE_66; 254 } else { 255 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 256 sc->sis_type = SIS_TYPE_NOUDMA; 257 } 258 } 259 aprint_normal(" IDE controller (rev. 0x%02x)\n", 260 PCI_REVISION(pa->pa_class)); 261 aprint_normal("%s: bus-master DMA support present", 262 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 263 pciide_mapreg_dma(sc, pa); 264 aprint_normal("\n"); 265 266 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 267 if (sc->sc_dma_ok) { 268 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 269 sc->sc_wdcdev.irqack = pciide_irqack; 270 if (sc->sis_type >= SIS_TYPE_66) 271 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 272 } 273 274 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 275 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 276 277 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 278 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 279 switch(sc->sis_type) { 280 case SIS_TYPE_NOUDMA: 281 case SIS_TYPE_66: 282 case SIS_TYPE_100OLD: 283 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 284 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 285 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 286 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 287 break; 288 case SIS_TYPE_100NEW: 289 case SIS_TYPE_133OLD: 290 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 291 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 292 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 293 break; 294 case SIS_TYPE_133NEW: 295 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 296 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 297 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 298 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 299 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 300 break; 301 } 302 303 wdc_allocate_regs(&sc->sc_wdcdev); 304 305 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 306 channel++) { 307 cp = &sc->pciide_channels[channel]; 308 if (pciide_chansetup(sc, channel, interface) == 0) 309 continue; 310 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 311 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 312 aprint_normal("%s: %s channel ignored (disabled)\n", 313 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 314 cp->ata_channel.ch_flags |= ATACH_DISABLED; 315 continue; 316 } 317 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 318 pciide_pci_intr); 319 } 320 } 321 322 static void 323 sis96x_setup_channel(struct ata_channel *chp) 324 { 325 struct ata_drive_datas *drvp; 326 int drive, s; 327 u_int32_t sis_tim; 328 u_int32_t idedma_ctl; 329 int regtim; 330 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 331 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 332 333 sis_tim = 0; 334 idedma_ctl = 0; 335 /* setup DMA if needed */ 336 pciide_channel_dma_setup(cp); 337 338 for (drive = 0; drive < 2; drive++) { 339 regtim = SIS_TIM133( 340 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 341 chp->ch_channel, drive); 342 drvp = &chp->ch_drive[drive]; 343 /* If no drive, skip */ 344 if ((drvp->drive_flags & DRIVE) == 0) 345 continue; 346 /* add timing values, setup DMA if needed */ 347 if (drvp->drive_flags & DRIVE_UDMA) { 348 /* use Ultra/DMA */ 349 s = splbio(); 350 drvp->drive_flags &= ~DRIVE_DMA; 351 splx(s); 352 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 353 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 354 if (drvp->UDMA_mode > 2) 355 drvp->UDMA_mode = 2; 356 } 357 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 358 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 359 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 360 } else if (drvp->drive_flags & DRIVE_DMA) { 361 /* 362 * use Multiword DMA 363 * Timings will be used for both PIO and DMA, 364 * so adjust DMA mode if needed 365 */ 366 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 367 drvp->PIO_mode = drvp->DMA_mode + 2; 368 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 369 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 370 drvp->PIO_mode - 2 : 0; 371 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 372 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 373 } else { 374 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 375 } 376 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 377 "channel %d drive %d: 0x%x (reg 0x%x)\n", 378 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 379 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 380 } 381 if (idedma_ctl != 0) { 382 /* Add software bits in status register */ 383 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 384 idedma_ctl); 385 } 386 } 387 388 static void 389 sis_setup_channel(struct ata_channel *chp) 390 { 391 struct ata_drive_datas *drvp; 392 int drive, s; 393 u_int32_t sis_tim; 394 u_int32_t idedma_ctl; 395 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 396 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 397 398 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 399 "channel %d 0x%x\n", chp->ch_channel, 400 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 401 DEBUG_PROBE); 402 sis_tim = 0; 403 idedma_ctl = 0; 404 /* setup DMA if needed */ 405 pciide_channel_dma_setup(cp); 406 407 for (drive = 0; drive < 2; drive++) { 408 drvp = &chp->ch_drive[drive]; 409 /* If no drive, skip */ 410 if ((drvp->drive_flags & DRIVE) == 0) 411 continue; 412 /* add timing values, setup DMA if needed */ 413 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 414 (drvp->drive_flags & DRIVE_UDMA) == 0) 415 goto pio; 416 417 if (drvp->drive_flags & DRIVE_UDMA) { 418 /* use Ultra/DMA */ 419 s = splbio(); 420 drvp->drive_flags &= ~DRIVE_DMA; 421 splx(s); 422 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 423 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 424 if (drvp->UDMA_mode > 2) 425 drvp->UDMA_mode = 2; 426 } 427 switch (sc->sis_type) { 428 case SIS_TYPE_66: 429 case SIS_TYPE_100OLD: 430 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 431 SIS_TIM66_UDMA_TIME_OFF(drive); 432 break; 433 case SIS_TYPE_100NEW: 434 sis_tim |= 435 sis_udma100new_tim[drvp->UDMA_mode] << 436 SIS_TIM100_UDMA_TIME_OFF(drive); 437 case SIS_TYPE_133OLD: 438 sis_tim |= 439 sis_udma133old_tim[drvp->UDMA_mode] << 440 SIS_TIM100_UDMA_TIME_OFF(drive); 441 break; 442 default: 443 aprint_error("unknown SiS IDE type %d\n", 444 sc->sis_type); 445 } 446 } else { 447 /* 448 * use Multiword DMA 449 * Timings will be used for both PIO and DMA, 450 * so adjust DMA mode if needed 451 */ 452 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 453 drvp->PIO_mode = drvp->DMA_mode + 2; 454 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 455 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 456 drvp->PIO_mode - 2 : 0; 457 if (drvp->DMA_mode == 0) 458 drvp->PIO_mode = 0; 459 } 460 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 461 pio: switch (sc->sis_type) { 462 case SIS_TYPE_NOUDMA: 463 case SIS_TYPE_66: 464 case SIS_TYPE_100OLD: 465 sis_tim |= sis_pio_act[drvp->PIO_mode] << 466 SIS_TIM66_ACT_OFF(drive); 467 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 468 SIS_TIM66_REC_OFF(drive); 469 break; 470 case SIS_TYPE_100NEW: 471 case SIS_TYPE_133OLD: 472 sis_tim |= sis_pio_act[drvp->PIO_mode] << 473 SIS_TIM100_ACT_OFF(drive); 474 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 475 SIS_TIM100_REC_OFF(drive); 476 break; 477 default: 478 aprint_error("unknown SiS IDE type %d\n", 479 sc->sis_type); 480 } 481 } 482 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 483 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 484 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 485 sis_tim); 486 if (idedma_ctl != 0) { 487 /* Add software bits in status register */ 488 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 489 idedma_ctl); 490 } 491 } 492 493 static void 494 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 495 { 496 struct pciide_channel *cp; 497 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 498 int channel; 499 bus_size_t cmdsize, ctlsize; 500 501 if (pciide_chipen(sc, pa) == 0) 502 return; 503 504 if (interface == 0) { 505 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 506 DEBUG_PROBE); 507 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 508 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 509 } 510 511 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 512 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 513 PCI_REVISION(pa->pa_class)); 514 515 aprint_normal("%s: bus-master DMA support present", 516 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 517 pciide_mapreg_dma(sc, pa); 518 aprint_normal("\n"); 519 520 if (sc->sc_dma_ok) { 521 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 522 sc->sc_wdcdev.irqack = pciide_irqack; 523 } 524 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 525 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 526 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 527 528 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 529 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 530 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 531 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 532 533 wdc_allocate_regs(&sc->sc_wdcdev); 534 535 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 536 channel++) { 537 cp = &sc->pciide_channels[channel]; 538 if (pciide_chansetup(sc, channel, interface) == 0) 539 continue; 540 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 541 pciide_pci_intr); 542 } 543 } 544
Indexes created Tue Sep 30 07:10:03 GMT 2025