siside.c revision 1.19
1 /* $NetBSD: siside.c,v 1.19 2006/06/26 18:19:08 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.19 2006/06/26 18:19:08 xtraeme Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_sis_reg.h> 43 44 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 46 static void sis_setup_channel(struct ata_channel *); 47 static void sis96x_setup_channel(struct ata_channel *); 48 49 static int sis_hostbr_match(struct pci_attach_args *); 50 static int sis_south_match(struct pci_attach_args *); 51 52 static int siside_match(struct device *, struct cfdata *, void *); 53 static void siside_attach(struct device *, struct device *, void *); 54 55 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 56 siside_match, siside_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_sis_products[] = { 59 { PCI_PRODUCT_SIS_5597_IDE, 60 0, 61 NULL, 62 sis_chip_map, 63 }, 64 { PCI_PRODUCT_SIS_180_SATA, 65 0, 66 NULL, 67 sis_sata_chip_map, 68 }, 69 { PCI_PRODUCT_SIS_181_SATA, 70 0, 71 NULL, 72 sis_sata_chip_map, 73 }, 74 { PCI_PRODUCT_SIS_182_SATA, 75 0, 76 NULL, 77 sis_sata_chip_map, 78 }, 79 { 0, 80 0, 81 NULL, 82 NULL 83 } 84 }; 85 86 static int 87 siside_match(struct device *parent, struct cfdata *match, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 91 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 92 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 93 return (2); 94 } 95 return (0); 96 } 97 98 static void 99 siside_attach(struct device *parent, struct device *self, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 struct pciide_softc *sc = (struct pciide_softc *)self; 103 104 pciide_common_attach(sc, pa, 105 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 106 107 } 108 109 static struct sis_hostbr_type { 110 u_int16_t id; 111 u_int8_t rev; 112 u_int8_t udma_mode; 113 const char *name; 114 u_int8_t type; 115 #define SIS_TYPE_NOUDMA 0 116 #define SIS_TYPE_66 1 117 #define SIS_TYPE_100OLD 2 118 #define SIS_TYPE_100NEW 3 119 #define SIS_TYPE_133OLD 4 120 #define SIS_TYPE_133NEW 5 121 #define SIS_TYPE_SOUTH 6 122 } sis_hostbr_type[] = { 123 /* Most infos here are from sos (at) freebsd.org */ 124 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 125 #if 0 126 /* 127 * controllers associated to a rev 0x2 530 Host to PCI Bridge 128 * have problems with UDMA (info provided by Christos) 129 */ 130 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 131 #endif 132 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 133 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 134 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 135 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 136 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 137 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 138 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 139 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 140 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 141 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 144 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 147 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 150 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 151 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 152 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 153 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 154 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 155 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 156 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 157 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 158 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 159 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 160 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 161 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_133NEW}, 162 /* 163 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 164 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 165 */ 166 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 167 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 168 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 169 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 170 }; 171 172 static struct sis_hostbr_type *sis_hostbr_type_match; 173 174 static int 175 sis_hostbr_match(struct pci_attach_args *pa) 176 { 177 int i; 178 pcireg_t id, reg; 179 180 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 181 return 0; 182 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503) { 183 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 184 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 185 reg | SIS96x_DETECT_MASQ); 186 id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 187 if (((PCI_PRODUCT(id) & 0xfff0) != 0x0960) 188 && (PCI_PRODUCT(id) != 0x0018)) { 189 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 190 reg); 191 } else { 192 pa->pa_id = id; 193 } 194 } 195 196 sis_hostbr_type_match = NULL; 197 for (i = 0; 198 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 199 i++) { 200 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 201 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 202 sis_hostbr_type_match = &sis_hostbr_type[i]; 203 } 204 return (sis_hostbr_type_match != NULL); 205 } 206 207 static int 208 sis_south_match(struct pci_attach_args *pa) 209 { 210 211 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 212 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 213 PCI_REVISION(pa->pa_class) >= 0x10); 214 } 215 216 static void 217 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 218 { 219 struct pciide_channel *cp; 220 int channel; 221 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 222 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 223 pcireg_t rev = PCI_REVISION(pa->pa_class); 224 bus_size_t cmdsize, ctlsize; 225 226 if (pciide_chipen(sc, pa) == 0) 227 return; 228 229 aprint_normal("%s: Silicon Integrated Systems ", 230 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 231 pci_find_device(NULL, sis_hostbr_match); 232 if (sis_hostbr_type_match) { 233 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 234 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 235 pciide_pci_read(sc->sc_pc, sc->sc_tag, 236 SIS_REG_57) & 0x7f); 237 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 238 PCI_ID_REG)) == SIS_PRODUCT_5518) { 239 aprint_normal("96X UDMA%d", 240 sis_hostbr_type_match->udma_mode); 241 sc->sis_type = SIS_TYPE_133NEW; 242 sc->sc_wdcdev.sc_atac.atac_udma_cap = 243 sis_hostbr_type_match->udma_mode; 244 } else { 245 if (pci_find_device(NULL, sis_south_match)) { 246 sc->sis_type = SIS_TYPE_133OLD; 247 sc->sc_wdcdev.sc_atac.atac_udma_cap = 248 sis_hostbr_type_match->udma_mode; 249 } else { 250 sc->sis_type = SIS_TYPE_100NEW; 251 sc->sc_wdcdev.sc_atac.atac_udma_cap = 252 sis_hostbr_type_match->udma_mode; 253 } 254 } 255 } else { 256 sc->sis_type = sis_hostbr_type_match->type; 257 sc->sc_wdcdev.sc_atac.atac_udma_cap = 258 sis_hostbr_type_match->udma_mode; 259 } 260 aprint_normal(sis_hostbr_type_match->name); 261 } else { 262 aprint_normal("5597/5598"); 263 if (rev >= 0xd0) { 264 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 265 sc->sis_type = SIS_TYPE_66; 266 } else { 267 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 268 sc->sis_type = SIS_TYPE_NOUDMA; 269 } 270 } 271 aprint_normal(" IDE controller (rev. 0x%02x)\n", 272 PCI_REVISION(pa->pa_class)); 273 aprint_normal("%s: bus-master DMA support present", 274 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 275 pciide_mapreg_dma(sc, pa); 276 aprint_normal("\n"); 277 278 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 279 if (sc->sc_dma_ok) { 280 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 281 sc->sc_wdcdev.irqack = pciide_irqack; 282 if (sc->sis_type >= SIS_TYPE_66) 283 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 284 } 285 286 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 287 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 288 289 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 290 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 291 switch(sc->sis_type) { 292 case SIS_TYPE_NOUDMA: 293 case SIS_TYPE_66: 294 case SIS_TYPE_100OLD: 295 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 296 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 297 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 298 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 299 break; 300 case SIS_TYPE_100NEW: 301 case SIS_TYPE_133OLD: 302 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 303 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 304 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 305 break; 306 case SIS_TYPE_133NEW: 307 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 308 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 309 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 310 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 311 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 312 break; 313 } 314 315 wdc_allocate_regs(&sc->sc_wdcdev); 316 317 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 318 channel++) { 319 cp = &sc->pciide_channels[channel]; 320 if (pciide_chansetup(sc, channel, interface) == 0) 321 continue; 322 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 323 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 324 aprint_normal("%s: %s channel ignored (disabled)\n", 325 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 326 cp->ata_channel.ch_flags |= ATACH_DISABLED; 327 continue; 328 } 329 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 330 pciide_pci_intr); 331 } 332 } 333 334 static void 335 sis96x_setup_channel(struct ata_channel *chp) 336 { 337 struct ata_drive_datas *drvp; 338 int drive, s; 339 u_int32_t sis_tim; 340 u_int32_t idedma_ctl; 341 int regtim; 342 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 343 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 344 345 sis_tim = 0; 346 idedma_ctl = 0; 347 /* setup DMA if needed */ 348 pciide_channel_dma_setup(cp); 349 350 for (drive = 0; drive < 2; drive++) { 351 regtim = SIS_TIM133( 352 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 353 chp->ch_channel, drive); 354 drvp = &chp->ch_drive[drive]; 355 /* If no drive, skip */ 356 if ((drvp->drive_flags & DRIVE) == 0) 357 continue; 358 /* add timing values, setup DMA if needed */ 359 if (drvp->drive_flags & DRIVE_UDMA) { 360 /* use Ultra/DMA */ 361 s = splbio(); 362 drvp->drive_flags &= ~DRIVE_DMA; 363 splx(s); 364 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 365 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 366 if (drvp->UDMA_mode > 2) 367 drvp->UDMA_mode = 2; 368 } 369 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 370 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 371 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 372 } else if (drvp->drive_flags & DRIVE_DMA) { 373 /* 374 * use Multiword DMA 375 * Timings will be used for both PIO and DMA, 376 * so adjust DMA mode if needed 377 */ 378 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 379 drvp->PIO_mode = drvp->DMA_mode + 2; 380 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 381 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 382 drvp->PIO_mode - 2 : 0; 383 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 384 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 385 } else { 386 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 387 } 388 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 389 "channel %d drive %d: 0x%x (reg 0x%x)\n", 390 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 391 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 392 } 393 if (idedma_ctl != 0) { 394 /* Add software bits in status register */ 395 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 396 idedma_ctl); 397 } 398 } 399 400 static void 401 sis_setup_channel(struct ata_channel *chp) 402 { 403 struct ata_drive_datas *drvp; 404 int drive, s; 405 u_int32_t sis_tim; 406 u_int32_t idedma_ctl; 407 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 408 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 409 410 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 411 "channel %d 0x%x\n", chp->ch_channel, 412 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 413 DEBUG_PROBE); 414 sis_tim = 0; 415 idedma_ctl = 0; 416 /* setup DMA if needed */ 417 pciide_channel_dma_setup(cp); 418 419 for (drive = 0; drive < 2; drive++) { 420 drvp = &chp->ch_drive[drive]; 421 /* If no drive, skip */ 422 if ((drvp->drive_flags & DRIVE) == 0) 423 continue; 424 /* add timing values, setup DMA if needed */ 425 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 426 (drvp->drive_flags & DRIVE_UDMA) == 0) 427 goto pio; 428 429 if (drvp->drive_flags & DRIVE_UDMA) { 430 /* use Ultra/DMA */ 431 s = splbio(); 432 drvp->drive_flags &= ~DRIVE_DMA; 433 splx(s); 434 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 435 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 436 if (drvp->UDMA_mode > 2) 437 drvp->UDMA_mode = 2; 438 } 439 switch (sc->sis_type) { 440 case SIS_TYPE_66: 441 case SIS_TYPE_100OLD: 442 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 443 SIS_TIM66_UDMA_TIME_OFF(drive); 444 break; 445 case SIS_TYPE_100NEW: 446 sis_tim |= 447 sis_udma100new_tim[drvp->UDMA_mode] << 448 SIS_TIM100_UDMA_TIME_OFF(drive); 449 case SIS_TYPE_133OLD: 450 sis_tim |= 451 sis_udma133old_tim[drvp->UDMA_mode] << 452 SIS_TIM100_UDMA_TIME_OFF(drive); 453 break; 454 default: 455 aprint_error("unknown SiS IDE type %d\n", 456 sc->sis_type); 457 } 458 } else { 459 /* 460 * use Multiword DMA 461 * Timings will be used for both PIO and DMA, 462 * so adjust DMA mode if needed 463 */ 464 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 465 drvp->PIO_mode = drvp->DMA_mode + 2; 466 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 467 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 468 drvp->PIO_mode - 2 : 0; 469 if (drvp->DMA_mode == 0) 470 drvp->PIO_mode = 0; 471 } 472 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 473 pio: switch (sc->sis_type) { 474 case SIS_TYPE_NOUDMA: 475 case SIS_TYPE_66: 476 case SIS_TYPE_100OLD: 477 sis_tim |= sis_pio_act[drvp->PIO_mode] << 478 SIS_TIM66_ACT_OFF(drive); 479 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 480 SIS_TIM66_REC_OFF(drive); 481 break; 482 case SIS_TYPE_100NEW: 483 case SIS_TYPE_133OLD: 484 sis_tim |= sis_pio_act[drvp->PIO_mode] << 485 SIS_TIM100_ACT_OFF(drive); 486 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 487 SIS_TIM100_REC_OFF(drive); 488 break; 489 default: 490 aprint_error("unknown SiS IDE type %d\n", 491 sc->sis_type); 492 } 493 } 494 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 495 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 496 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 497 sis_tim); 498 if (idedma_ctl != 0) { 499 /* Add software bits in status register */ 500 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 501 idedma_ctl); 502 } 503 } 504 505 static void 506 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 507 { 508 struct pciide_channel *cp; 509 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 510 int channel; 511 bus_size_t cmdsize, ctlsize; 512 513 if (pciide_chipen(sc, pa) == 0) 514 return; 515 516 if (interface == 0) { 517 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 518 DEBUG_PROBE); 519 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 520 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 521 } 522 523 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 524 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 525 PCI_REVISION(pa->pa_class)); 526 527 aprint_normal("%s: bus-master DMA support present", 528 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 529 pciide_mapreg_dma(sc, pa); 530 aprint_normal("\n"); 531 532 if (sc->sc_dma_ok) { 533 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 534 sc->sc_wdcdev.irqack = pciide_irqack; 535 } 536 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 537 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 538 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 539 540 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 541 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 542 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 543 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 544 545 wdc_allocate_regs(&sc->sc_wdcdev); 546 547 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 548 channel++) { 549 cp = &sc->pciide_channels[channel]; 550 if (pciide_chansetup(sc, channel, interface) == 0) 551 continue; 552 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 553 pciide_pci_intr); 554 } 555 } 556
Indexes created Tue Sep 30 20:09:53 GMT 2025