siside.c revision 1.21
1 /* $NetBSD: siside.c,v 1.21 2006/11/16 01:33:10 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.21 2006/11/16 01:33:10 christos Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_sis_reg.h> 43 44 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 46 static void sis_setup_channel(struct ata_channel *); 47 static void sis96x_setup_channel(struct ata_channel *); 48 49 static int sis_hostbr_match(struct pci_attach_args *); 50 static int sis_south_match(struct pci_attach_args *); 51 52 static int siside_match(struct device *, struct cfdata *, void *); 53 static void siside_attach(struct device *, struct device *, void *); 54 55 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 56 siside_match, siside_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_sis_products[] = { 59 { PCI_PRODUCT_SIS_5597_IDE, 60 0, 61 NULL, 62 sis_chip_map, 63 }, 64 { PCI_PRODUCT_SIS_180_SATA, 65 0, 66 NULL, 67 sis_sata_chip_map, 68 }, 69 { PCI_PRODUCT_SIS_181_SATA, 70 0, 71 NULL, 72 sis_sata_chip_map, 73 }, 74 { PCI_PRODUCT_SIS_182_SATA, 75 0, 76 NULL, 77 sis_sata_chip_map, 78 }, 79 { 0, 80 0, 81 NULL, 82 NULL 83 } 84 }; 85 86 static int 87 siside_match(struct device *parent, struct cfdata *match, 88 void *aux) 89 { 90 struct pci_attach_args *pa = aux; 91 92 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 93 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 94 return (2); 95 } 96 return (0); 97 } 98 99 static void 100 siside_attach(struct device *parent, struct device *self, void *aux) 101 { 102 struct pci_attach_args *pa = aux; 103 struct pciide_softc *sc = (struct pciide_softc *)self; 104 105 pciide_common_attach(sc, pa, 106 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 107 108 } 109 110 static struct sis_hostbr_type { 111 u_int16_t id; 112 u_int8_t rev; 113 u_int8_t udma_mode; 114 const char *name; 115 u_int8_t type; 116 #define SIS_TYPE_NOUDMA 0 117 #define SIS_TYPE_66 1 118 #define SIS_TYPE_100OLD 2 119 #define SIS_TYPE_100NEW 3 120 #define SIS_TYPE_133OLD 4 121 #define SIS_TYPE_133NEW 5 122 #define SIS_TYPE_SOUTH 6 123 } sis_hostbr_type[] = { 124 /* Most infos here are from sos (at) freebsd.org */ 125 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 126 #if 0 127 /* 128 * controllers associated to a rev 0x2 530 Host to PCI Bridge 129 * have problems with UDMA (info provided by Christos) 130 */ 131 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 132 #endif 133 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 134 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 135 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 136 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 137 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 138 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 139 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 140 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 141 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 144 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 147 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 150 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 151 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 152 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 153 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 154 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 155 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 156 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 157 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 158 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 159 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 160 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 161 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 162 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_133NEW}, 163 /* 164 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 165 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 166 */ 167 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 168 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 169 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 170 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 171 }; 172 173 static struct sis_hostbr_type *sis_hostbr_type_match; 174 175 static int 176 sis_hostbr_match(struct pci_attach_args *pa) 177 { 178 int i; 179 pcireg_t id, reg; 180 181 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 182 return 0; 183 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503) { 184 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 185 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 186 reg | SIS96x_DETECT_MASQ); 187 id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 188 if (((PCI_PRODUCT(id) & 0xfff0) != 0x0960) 189 && (PCI_PRODUCT(id) != 0x0018)) { 190 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 191 reg); 192 } else { 193 pa->pa_id = id; 194 } 195 } 196 197 sis_hostbr_type_match = NULL; 198 for (i = 0; 199 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 200 i++) { 201 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 202 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 203 sis_hostbr_type_match = &sis_hostbr_type[i]; 204 } 205 return (sis_hostbr_type_match != NULL); 206 } 207 208 static int 209 sis_south_match(struct pci_attach_args *pa) 210 { 211 212 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 213 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 214 PCI_REVISION(pa->pa_class) >= 0x10); 215 } 216 217 static void 218 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 219 { 220 struct pciide_channel *cp; 221 int channel; 222 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 223 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 224 pcireg_t rev = PCI_REVISION(pa->pa_class); 225 bus_size_t cmdsize, ctlsize; 226 227 if (pciide_chipen(sc, pa) == 0) 228 return; 229 230 aprint_normal("%s: Silicon Integrated Systems ", 231 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 232 pci_find_device(NULL, sis_hostbr_match); 233 if (sis_hostbr_type_match) { 234 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 235 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 236 pciide_pci_read(sc->sc_pc, sc->sc_tag, 237 SIS_REG_57) & 0x7f); 238 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 239 PCI_ID_REG)) == SIS_PRODUCT_5518) { 240 aprint_normal("96X UDMA%d", 241 sis_hostbr_type_match->udma_mode); 242 sc->sis_type = SIS_TYPE_133NEW; 243 sc->sc_wdcdev.sc_atac.atac_udma_cap = 244 sis_hostbr_type_match->udma_mode; 245 } else { 246 if (pci_find_device(NULL, sis_south_match)) { 247 sc->sis_type = SIS_TYPE_133OLD; 248 sc->sc_wdcdev.sc_atac.atac_udma_cap = 249 sis_hostbr_type_match->udma_mode; 250 } else { 251 sc->sis_type = SIS_TYPE_100NEW; 252 sc->sc_wdcdev.sc_atac.atac_udma_cap = 253 sis_hostbr_type_match->udma_mode; 254 } 255 } 256 } else { 257 sc->sis_type = sis_hostbr_type_match->type; 258 sc->sc_wdcdev.sc_atac.atac_udma_cap = 259 sis_hostbr_type_match->udma_mode; 260 } 261 aprint_normal(sis_hostbr_type_match->name); 262 } else { 263 aprint_normal("5597/5598"); 264 if (rev >= 0xd0) { 265 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 266 sc->sis_type = SIS_TYPE_66; 267 } else { 268 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 269 sc->sis_type = SIS_TYPE_NOUDMA; 270 } 271 } 272 aprint_normal(" IDE controller (rev. 0x%02x)\n", 273 PCI_REVISION(pa->pa_class)); 274 aprint_normal("%s: bus-master DMA support present", 275 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 276 pciide_mapreg_dma(sc, pa); 277 aprint_normal("\n"); 278 279 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 280 if (sc->sc_dma_ok) { 281 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 282 sc->sc_wdcdev.irqack = pciide_irqack; 283 if (sc->sis_type >= SIS_TYPE_66) 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 285 } 286 287 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 288 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 289 290 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 291 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 292 switch(sc->sis_type) { 293 case SIS_TYPE_NOUDMA: 294 case SIS_TYPE_66: 295 case SIS_TYPE_100OLD: 296 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 297 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 298 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 299 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 300 break; 301 case SIS_TYPE_100NEW: 302 case SIS_TYPE_133OLD: 303 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 304 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 305 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 306 break; 307 case SIS_TYPE_133NEW: 308 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 309 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 310 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 311 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 312 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 313 break; 314 } 315 316 wdc_allocate_regs(&sc->sc_wdcdev); 317 318 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 319 channel++) { 320 cp = &sc->pciide_channels[channel]; 321 if (pciide_chansetup(sc, channel, interface) == 0) 322 continue; 323 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 324 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 325 aprint_normal("%s: %s channel ignored (disabled)\n", 326 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 327 cp->ata_channel.ch_flags |= ATACH_DISABLED; 328 continue; 329 } 330 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 331 pciide_pci_intr); 332 } 333 } 334 335 static void 336 sis96x_setup_channel(struct ata_channel *chp) 337 { 338 struct ata_drive_datas *drvp; 339 int drive, s; 340 u_int32_t sis_tim; 341 u_int32_t idedma_ctl; 342 int regtim; 343 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 344 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 345 346 sis_tim = 0; 347 idedma_ctl = 0; 348 /* setup DMA if needed */ 349 pciide_channel_dma_setup(cp); 350 351 for (drive = 0; drive < 2; drive++) { 352 regtim = SIS_TIM133( 353 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 354 chp->ch_channel, drive); 355 drvp = &chp->ch_drive[drive]; 356 /* If no drive, skip */ 357 if ((drvp->drive_flags & DRIVE) == 0) 358 continue; 359 /* add timing values, setup DMA if needed */ 360 if (drvp->drive_flags & DRIVE_UDMA) { 361 /* use Ultra/DMA */ 362 s = splbio(); 363 drvp->drive_flags &= ~DRIVE_DMA; 364 splx(s); 365 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 366 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 367 if (drvp->UDMA_mode > 2) 368 drvp->UDMA_mode = 2; 369 } 370 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 371 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 372 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 373 } else if (drvp->drive_flags & DRIVE_DMA) { 374 /* 375 * use Multiword DMA 376 * Timings will be used for both PIO and DMA, 377 * so adjust DMA mode if needed 378 */ 379 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 380 drvp->PIO_mode = drvp->DMA_mode + 2; 381 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 382 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 383 drvp->PIO_mode - 2 : 0; 384 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 385 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 386 } else { 387 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 388 } 389 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 390 "channel %d drive %d: 0x%x (reg 0x%x)\n", 391 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 392 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 393 } 394 if (idedma_ctl != 0) { 395 /* Add software bits in status register */ 396 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 397 idedma_ctl); 398 } 399 } 400 401 static void 402 sis_setup_channel(struct ata_channel *chp) 403 { 404 struct ata_drive_datas *drvp; 405 int drive, s; 406 u_int32_t sis_tim; 407 u_int32_t idedma_ctl; 408 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 409 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 410 411 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 412 "channel %d 0x%x\n", chp->ch_channel, 413 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 414 DEBUG_PROBE); 415 sis_tim = 0; 416 idedma_ctl = 0; 417 /* setup DMA if needed */ 418 pciide_channel_dma_setup(cp); 419 420 for (drive = 0; drive < 2; drive++) { 421 drvp = &chp->ch_drive[drive]; 422 /* If no drive, skip */ 423 if ((drvp->drive_flags & DRIVE) == 0) 424 continue; 425 /* add timing values, setup DMA if needed */ 426 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 427 (drvp->drive_flags & DRIVE_UDMA) == 0) 428 goto pio; 429 430 if (drvp->drive_flags & DRIVE_UDMA) { 431 /* use Ultra/DMA */ 432 s = splbio(); 433 drvp->drive_flags &= ~DRIVE_DMA; 434 splx(s); 435 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 436 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 437 if (drvp->UDMA_mode > 2) 438 drvp->UDMA_mode = 2; 439 } 440 switch (sc->sis_type) { 441 case SIS_TYPE_66: 442 case SIS_TYPE_100OLD: 443 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 444 SIS_TIM66_UDMA_TIME_OFF(drive); 445 break; 446 case SIS_TYPE_100NEW: 447 sis_tim |= 448 sis_udma100new_tim[drvp->UDMA_mode] << 449 SIS_TIM100_UDMA_TIME_OFF(drive); 450 case SIS_TYPE_133OLD: 451 sis_tim |= 452 sis_udma133old_tim[drvp->UDMA_mode] << 453 SIS_TIM100_UDMA_TIME_OFF(drive); 454 break; 455 default: 456 aprint_error("unknown SiS IDE type %d\n", 457 sc->sis_type); 458 } 459 } else { 460 /* 461 * use Multiword DMA 462 * Timings will be used for both PIO and DMA, 463 * so adjust DMA mode if needed 464 */ 465 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 466 drvp->PIO_mode = drvp->DMA_mode + 2; 467 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 468 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 469 drvp->PIO_mode - 2 : 0; 470 if (drvp->DMA_mode == 0) 471 drvp->PIO_mode = 0; 472 } 473 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 474 pio: switch (sc->sis_type) { 475 case SIS_TYPE_NOUDMA: 476 case SIS_TYPE_66: 477 case SIS_TYPE_100OLD: 478 sis_tim |= sis_pio_act[drvp->PIO_mode] << 479 SIS_TIM66_ACT_OFF(drive); 480 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 481 SIS_TIM66_REC_OFF(drive); 482 break; 483 case SIS_TYPE_100NEW: 484 case SIS_TYPE_133OLD: 485 sis_tim |= sis_pio_act[drvp->PIO_mode] << 486 SIS_TIM100_ACT_OFF(drive); 487 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 488 SIS_TIM100_REC_OFF(drive); 489 break; 490 default: 491 aprint_error("unknown SiS IDE type %d\n", 492 sc->sis_type); 493 } 494 } 495 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 496 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 497 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 498 sis_tim); 499 if (idedma_ctl != 0) { 500 /* Add software bits in status register */ 501 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 502 idedma_ctl); 503 } 504 } 505 506 static void 507 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 508 { 509 struct pciide_channel *cp; 510 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 511 int channel; 512 bus_size_t cmdsize, ctlsize; 513 514 if (pciide_chipen(sc, pa) == 0) 515 return; 516 517 if (interface == 0) { 518 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 519 DEBUG_PROBE); 520 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 521 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 522 } 523 524 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 525 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 526 PCI_REVISION(pa->pa_class)); 527 528 aprint_normal("%s: bus-master DMA support present", 529 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 530 pciide_mapreg_dma(sc, pa); 531 aprint_normal("\n"); 532 533 if (sc->sc_dma_ok) { 534 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 535 sc->sc_wdcdev.irqack = pciide_irqack; 536 } 537 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 538 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 539 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 540 541 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 542 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 543 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 544 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 545 546 wdc_allocate_regs(&sc->sc_wdcdev); 547 548 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 549 channel++) { 550 cp = &sc->pciide_channels[channel]; 551 if (pciide_chansetup(sc, channel, interface) == 0) 552 continue; 553 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 554 pciide_pci_intr); 555 } 556 } 557
Indexes created Mon Sep 29 21:09:56 GMT 2025