siside.c revision 1.23.4.1
1 /* $NetBSD: siside.c,v 1.23.4.1 2009/05/04 08:13:02 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.23.4.1 2009/05/04 08:13:02 yamt Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 #include <dev/pci/pciide_sis_reg.h> 43 44 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 45 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 46 static void sis_setup_channel(struct ata_channel *); 47 static void sis96x_setup_channel(struct ata_channel *); 48 49 static int sis_hostbr_match(struct pci_attach_args *); 50 static int sis_south_match(struct pci_attach_args *); 51 52 static int siside_match(device_t, cfdata_t, void *); 53 static void siside_attach(device_t, device_t, void *); 54 55 CFATTACH_DECL_NEW(siside, sizeof(struct pciide_softc), 56 siside_match, siside_attach, NULL, NULL); 57 58 static const struct pciide_product_desc pciide_sis_products[] = { 59 { PCI_PRODUCT_SIS_5597_IDE, 60 0, 61 NULL, 62 sis_chip_map, 63 }, 64 { PCI_PRODUCT_SIS_180_SATA, 65 0, 66 NULL, 67 sis_sata_chip_map, 68 }, 69 { PCI_PRODUCT_SIS_181_SATA, 70 0, 71 NULL, 72 sis_sata_chip_map, 73 }, 74 { PCI_PRODUCT_SIS_182_SATA, 75 0, 76 NULL, 77 sis_sata_chip_map, 78 }, 79 { 0, 80 0, 81 NULL, 82 NULL 83 } 84 }; 85 86 static int 87 siside_match(device_t parent, cfdata_t match, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 91 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 92 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 93 return (2); 94 } 95 return (0); 96 } 97 98 static void 99 siside_attach(device_t parent, device_t self, void *aux) 100 { 101 struct pci_attach_args *pa = aux; 102 struct pciide_softc *sc = device_private(self); 103 pci_chipset_tag_t pc = pa->pa_pc; 104 pcitag_t tag = pa->pa_tag; 105 pcireg_t csr; 106 107 sc->sc_wdcdev.sc_atac.atac_dev = self; 108 109 pciide_common_attach(sc, pa, 110 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 111 112 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 113 if (csr & PCI_COMMAND_INTERRUPT_DISABLE) { 114 csr &= ~PCI_COMMAND_INTERRUPT_DISABLE; 115 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 116 } 117 } 118 119 static struct sis_hostbr_type { 120 u_int16_t id; 121 u_int8_t rev; 122 u_int8_t udma_mode; 123 const char *name; 124 u_int8_t type; 125 #define SIS_TYPE_NOUDMA 0 126 #define SIS_TYPE_66 1 127 #define SIS_TYPE_100OLD 2 128 #define SIS_TYPE_100NEW 3 129 #define SIS_TYPE_133OLD 4 130 #define SIS_TYPE_133NEW 5 131 #define SIS_TYPE_SOUTH 6 132 } sis_hostbr_type[] = { 133 /* Most infos here are from sos (at) freebsd.org */ 134 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 135 #if 0 136 /* 137 * controllers associated to a rev 0x2 530 Host to PCI Bridge 138 * have problems with UDMA (info provided by Christos) 139 */ 140 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 141 #endif 142 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 143 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 144 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 145 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 146 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 147 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 148 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 149 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 150 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 151 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 152 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 153 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 154 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 155 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 156 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 157 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 158 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 159 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 160 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 161 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 162 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 163 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 164 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 165 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 166 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 167 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 168 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 169 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 170 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 171 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_133NEW}, 172 /* 173 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 174 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 175 */ 176 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 177 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 178 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 179 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 180 }; 181 182 static struct sis_hostbr_type *sis_hostbr_type_match; 183 184 static int 185 sis_hostbr_match(struct pci_attach_args *pa) 186 { 187 int i; 188 pcireg_t id, reg; 189 190 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 191 return 0; 192 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503) { 193 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 194 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 195 reg | SIS96x_DETECT_MASQ); 196 id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 197 if (((PCI_PRODUCT(id) & 0xfff0) != 0x0960) 198 && (PCI_PRODUCT(id) != 0x0018)) { 199 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 200 reg); 201 } else { 202 pa->pa_id = id; 203 } 204 } 205 206 sis_hostbr_type_match = NULL; 207 for (i = 0; 208 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 209 i++) { 210 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 211 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 212 sis_hostbr_type_match = &sis_hostbr_type[i]; 213 } 214 return (sis_hostbr_type_match != NULL); 215 } 216 217 static int 218 sis_south_match(struct pci_attach_args *pa) 219 { 220 221 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 222 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 223 PCI_REVISION(pa->pa_class) >= 0x10); 224 } 225 226 static void 227 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 228 { 229 struct pciide_channel *cp; 230 int channel; 231 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 232 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 233 pcireg_t rev = PCI_REVISION(pa->pa_class); 234 bus_size_t cmdsize, ctlsize; 235 236 if (pciide_chipen(sc, pa) == 0) 237 return; 238 239 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 240 "Silicon Integrated Systems "); 241 pci_find_device(NULL, sis_hostbr_match); 242 if (sis_hostbr_type_match) { 243 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 244 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 245 pciide_pci_read(sc->sc_pc, sc->sc_tag, 246 SIS_REG_57) & 0x7f); 247 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 248 PCI_ID_REG)) == SIS_PRODUCT_5518) { 249 aprint_normal("96X UDMA%d", 250 sis_hostbr_type_match->udma_mode); 251 sc->sis_type = SIS_TYPE_133NEW; 252 sc->sc_wdcdev.sc_atac.atac_udma_cap = 253 sis_hostbr_type_match->udma_mode; 254 } else { 255 if (pci_find_device(NULL, sis_south_match)) { 256 sc->sis_type = SIS_TYPE_133OLD; 257 sc->sc_wdcdev.sc_atac.atac_udma_cap = 258 sis_hostbr_type_match->udma_mode; 259 } else { 260 sc->sis_type = SIS_TYPE_100NEW; 261 sc->sc_wdcdev.sc_atac.atac_udma_cap = 262 sis_hostbr_type_match->udma_mode; 263 } 264 } 265 } else { 266 sc->sis_type = sis_hostbr_type_match->type; 267 sc->sc_wdcdev.sc_atac.atac_udma_cap = 268 sis_hostbr_type_match->udma_mode; 269 } 270 aprint_normal(sis_hostbr_type_match->name); 271 } else { 272 aprint_normal("5597/5598"); 273 if (rev >= 0xd0) { 274 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 275 sc->sis_type = SIS_TYPE_66; 276 } else { 277 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 278 sc->sis_type = SIS_TYPE_NOUDMA; 279 } 280 } 281 aprint_normal(" IDE controller (rev. 0x%02x)\n", 282 PCI_REVISION(pa->pa_class)); 283 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 284 "bus-master DMA support present"); 285 pciide_mapreg_dma(sc, pa); 286 aprint_verbose("\n"); 287 288 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 289 if (sc->sc_dma_ok) { 290 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 291 sc->sc_wdcdev.irqack = pciide_irqack; 292 if (sc->sis_type >= SIS_TYPE_66) 293 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 294 } 295 296 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 297 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 298 299 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 300 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 301 switch(sc->sis_type) { 302 case SIS_TYPE_NOUDMA: 303 case SIS_TYPE_66: 304 case SIS_TYPE_100OLD: 305 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 306 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 307 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 308 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 309 break; 310 case SIS_TYPE_100NEW: 311 case SIS_TYPE_133OLD: 312 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 313 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 314 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 315 break; 316 case SIS_TYPE_133NEW: 317 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 318 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 319 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 320 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 321 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 322 break; 323 } 324 325 wdc_allocate_regs(&sc->sc_wdcdev); 326 327 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 328 channel++) { 329 cp = &sc->pciide_channels[channel]; 330 if (pciide_chansetup(sc, channel, interface) == 0) 331 continue; 332 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 333 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 334 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 335 "%s channel ignored (disabled)\n", cp->name); 336 cp->ata_channel.ch_flags |= ATACH_DISABLED; 337 continue; 338 } 339 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 340 pciide_pci_intr); 341 } 342 } 343 344 static void 345 sis96x_setup_channel(struct ata_channel *chp) 346 { 347 struct ata_drive_datas *drvp; 348 int drive, s; 349 u_int32_t sis_tim; 350 u_int32_t idedma_ctl; 351 int regtim; 352 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 353 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 354 355 sis_tim = 0; 356 idedma_ctl = 0; 357 /* setup DMA if needed */ 358 pciide_channel_dma_setup(cp); 359 360 for (drive = 0; drive < 2; drive++) { 361 regtim = SIS_TIM133( 362 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 363 chp->ch_channel, drive); 364 drvp = &chp->ch_drive[drive]; 365 /* If no drive, skip */ 366 if ((drvp->drive_flags & DRIVE) == 0) 367 continue; 368 /* add timing values, setup DMA if needed */ 369 if (drvp->drive_flags & DRIVE_UDMA) { 370 /* use Ultra/DMA */ 371 s = splbio(); 372 drvp->drive_flags &= ~DRIVE_DMA; 373 splx(s); 374 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 375 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 376 if (drvp->UDMA_mode > 2) 377 drvp->UDMA_mode = 2; 378 } 379 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 380 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 381 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 382 } else if (drvp->drive_flags & DRIVE_DMA) { 383 /* 384 * use Multiword DMA 385 * Timings will be used for both PIO and DMA, 386 * so adjust DMA mode if needed 387 */ 388 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 389 drvp->PIO_mode = drvp->DMA_mode + 2; 390 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 391 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 392 drvp->PIO_mode - 2 : 0; 393 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 394 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 395 } else { 396 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 397 } 398 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 399 "channel %d drive %d: 0x%x (reg 0x%x)\n", 400 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 401 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 402 } 403 if (idedma_ctl != 0) { 404 /* Add software bits in status register */ 405 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 406 idedma_ctl); 407 } 408 } 409 410 static void 411 sis_setup_channel(struct ata_channel *chp) 412 { 413 struct ata_drive_datas *drvp; 414 int drive, s; 415 u_int32_t sis_tim; 416 u_int32_t idedma_ctl; 417 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 418 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 419 420 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 421 "channel %d 0x%x\n", chp->ch_channel, 422 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 423 DEBUG_PROBE); 424 sis_tim = 0; 425 idedma_ctl = 0; 426 /* setup DMA if needed */ 427 pciide_channel_dma_setup(cp); 428 429 for (drive = 0; drive < 2; drive++) { 430 drvp = &chp->ch_drive[drive]; 431 /* If no drive, skip */ 432 if ((drvp->drive_flags & DRIVE) == 0) 433 continue; 434 /* add timing values, setup DMA if needed */ 435 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 436 (drvp->drive_flags & DRIVE_UDMA) == 0) 437 goto pio; 438 439 if (drvp->drive_flags & DRIVE_UDMA) { 440 /* use Ultra/DMA */ 441 s = splbio(); 442 drvp->drive_flags &= ~DRIVE_DMA; 443 splx(s); 444 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 445 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 446 if (drvp->UDMA_mode > 2) 447 drvp->UDMA_mode = 2; 448 } 449 switch (sc->sis_type) { 450 case SIS_TYPE_66: 451 case SIS_TYPE_100OLD: 452 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 453 SIS_TIM66_UDMA_TIME_OFF(drive); 454 break; 455 case SIS_TYPE_100NEW: 456 sis_tim |= 457 sis_udma100new_tim[drvp->UDMA_mode] << 458 SIS_TIM100_UDMA_TIME_OFF(drive); 459 case SIS_TYPE_133OLD: 460 sis_tim |= 461 sis_udma133old_tim[drvp->UDMA_mode] << 462 SIS_TIM100_UDMA_TIME_OFF(drive); 463 break; 464 default: 465 aprint_error("unknown SiS IDE type %d\n", 466 sc->sis_type); 467 } 468 } else { 469 /* 470 * use Multiword DMA 471 * Timings will be used for both PIO and DMA, 472 * so adjust DMA mode if needed 473 */ 474 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 475 drvp->PIO_mode = drvp->DMA_mode + 2; 476 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 477 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 478 drvp->PIO_mode - 2 : 0; 479 if (drvp->DMA_mode == 0) 480 drvp->PIO_mode = 0; 481 } 482 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 483 pio: switch (sc->sis_type) { 484 case SIS_TYPE_NOUDMA: 485 case SIS_TYPE_66: 486 case SIS_TYPE_100OLD: 487 sis_tim |= sis_pio_act[drvp->PIO_mode] << 488 SIS_TIM66_ACT_OFF(drive); 489 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 490 SIS_TIM66_REC_OFF(drive); 491 break; 492 case SIS_TYPE_100NEW: 493 case SIS_TYPE_133OLD: 494 sis_tim |= sis_pio_act[drvp->PIO_mode] << 495 SIS_TIM100_ACT_OFF(drive); 496 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 497 SIS_TIM100_REC_OFF(drive); 498 break; 499 default: 500 aprint_error("unknown SiS IDE type %d\n", 501 sc->sis_type); 502 } 503 } 504 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 505 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 506 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 507 sis_tim); 508 if (idedma_ctl != 0) { 509 /* Add software bits in status register */ 510 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 511 idedma_ctl); 512 } 513 } 514 515 static void 516 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 517 { 518 struct pciide_channel *cp; 519 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 520 int channel; 521 bus_size_t cmdsize, ctlsize; 522 523 if (pciide_chipen(sc, pa) == 0) 524 return; 525 526 if (interface == 0) { 527 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 528 DEBUG_PROBE); 529 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 530 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 531 } 532 533 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 534 "Silicon Integrated Systems 180/96X SATA controller " 535 "(rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 536 537 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 538 "bus-master DMA support present"); 539 pciide_mapreg_dma(sc, pa); 540 aprint_verbose("\n"); 541 542 if (sc->sc_dma_ok) { 543 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 544 sc->sc_wdcdev.irqack = pciide_irqack; 545 } 546 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 547 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 548 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 549 550 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 551 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 552 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 553 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 554 555 wdc_allocate_regs(&sc->sc_wdcdev); 556 557 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 558 channel++) { 559 cp = &sc->pciide_channels[channel]; 560 if (pciide_chansetup(sc, channel, interface) == 0) 561 continue; 562 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 563 pciide_pci_intr); 564 } 565 } 566
Indexes created Sun Oct 19 02:09:48 GMT 2025