siside.c revision 1.26
1 /* $NetBSD: siside.c,v 1.26 2010/11/05 18:07:24 jakllsch Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.26 2010/11/05 18:07:24 jakllsch Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_sis_reg.h> 38 39 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 40 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 41 static void sis_setup_channel(struct ata_channel *); 42 static void sis96x_setup_channel(struct ata_channel *); 43 44 static int sis_hostbr_match(struct pci_attach_args *); 45 static int sis_south_match(struct pci_attach_args *); 46 47 static int siside_match(device_t, cfdata_t, void *); 48 static void siside_attach(device_t, device_t, void *); 49 50 CFATTACH_DECL_NEW(siside, sizeof(struct pciide_softc), 51 siside_match, siside_attach, NULL, NULL); 52 53 static const struct pciide_product_desc pciide_sis_products[] = { 54 { PCI_PRODUCT_SIS_5597_IDE, 55 0, 56 NULL, 57 sis_chip_map, 58 }, 59 { PCI_PRODUCT_SIS_180_SATA, 60 0, 61 NULL, 62 sis_sata_chip_map, 63 }, 64 { PCI_PRODUCT_SIS_181_SATA, 65 0, 66 NULL, 67 sis_sata_chip_map, 68 }, 69 { PCI_PRODUCT_SIS_182_SATA, 70 0, 71 NULL, 72 sis_sata_chip_map, 73 }, 74 { 0, 75 0, 76 NULL, 77 NULL 78 } 79 }; 80 81 static int 82 siside_match(device_t parent, cfdata_t match, void *aux) 83 { 84 struct pci_attach_args *pa = aux; 85 86 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 87 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 88 return (2); 89 } 90 return (0); 91 } 92 93 static void 94 siside_attach(device_t parent, device_t self, void *aux) 95 { 96 struct pci_attach_args *pa = aux; 97 struct pciide_softc *sc = device_private(self); 98 pci_chipset_tag_t pc = pa->pa_pc; 99 pcitag_t tag = pa->pa_tag; 100 pcireg_t csr; 101 102 sc->sc_wdcdev.sc_atac.atac_dev = self; 103 104 pciide_common_attach(sc, pa, 105 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 106 107 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 108 if (csr & PCI_COMMAND_INTERRUPT_DISABLE) { 109 csr &= ~PCI_COMMAND_INTERRUPT_DISABLE; 110 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 111 } 112 } 113 114 static struct sis_hostbr_type { 115 u_int16_t id; 116 u_int8_t rev; 117 u_int8_t udma_mode; 118 const char *name; 119 u_int8_t type; 120 #define SIS_TYPE_NOUDMA 0 121 #define SIS_TYPE_66 1 122 #define SIS_TYPE_100OLD 2 123 #define SIS_TYPE_100NEW 3 124 #define SIS_TYPE_133OLD 4 125 #define SIS_TYPE_133NEW 5 126 #define SIS_TYPE_SOUTH 6 127 } sis_hostbr_type[] = { 128 /* Most infos here are from sos (at) freebsd.org */ 129 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 130 #if 0 131 /* 132 * controllers associated to a rev 0x2 530 Host to PCI Bridge 133 * have problems with UDMA (info provided by Christos) 134 */ 135 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 136 #endif 137 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 138 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 139 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 140 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 141 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 142 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 143 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 144 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 146 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 147 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 150 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 151 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 152 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 153 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 154 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 155 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 156 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 157 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 158 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 159 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 160 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 161 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 162 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 163 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 164 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 165 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 166 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_133NEW}, 167 /* 168 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 169 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 170 */ 171 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 172 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 173 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 174 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 175 }; 176 177 static struct sis_hostbr_type *sis_hostbr_type_match; 178 179 static int 180 sis_hostbr_match(struct pci_attach_args *pa) 181 { 182 int i; 183 pcireg_t id, reg; 184 185 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 186 return 0; 187 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503) { 188 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 189 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 190 reg | SIS96x_DETECT_MASQ); 191 id = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 192 if (((PCI_PRODUCT(id) & 0xfff0) != 0x0960) 193 && (PCI_PRODUCT(id) != 0x0018)) { 194 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 195 reg); 196 } else { 197 pa->pa_id = id; 198 } 199 } 200 201 sis_hostbr_type_match = NULL; 202 for (i = 0; 203 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 204 i++) { 205 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 206 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 207 sis_hostbr_type_match = &sis_hostbr_type[i]; 208 } 209 return (sis_hostbr_type_match != NULL); 210 } 211 212 static int 213 sis_south_match(struct pci_attach_args *pa) 214 { 215 216 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 217 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 218 PCI_REVISION(pa->pa_class) >= 0x10); 219 } 220 221 static void 222 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 223 { 224 struct pciide_channel *cp; 225 int channel; 226 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 227 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 228 pcireg_t rev = PCI_REVISION(pa->pa_class); 229 230 if (pciide_chipen(sc, pa) == 0) 231 return; 232 233 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 234 "Silicon Integrated Systems "); 235 pci_find_device(NULL, sis_hostbr_match); 236 if (sis_hostbr_type_match) { 237 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 238 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 239 pciide_pci_read(sc->sc_pc, sc->sc_tag, 240 SIS_REG_57) & 0x7f); 241 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 242 PCI_ID_REG)) == SIS_PRODUCT_5518) { 243 aprint_normal("96X UDMA%d", 244 sis_hostbr_type_match->udma_mode); 245 sc->sis_type = SIS_TYPE_133NEW; 246 sc->sc_wdcdev.sc_atac.atac_udma_cap = 247 sis_hostbr_type_match->udma_mode; 248 } else { 249 if (pci_find_device(NULL, sis_south_match)) { 250 sc->sis_type = SIS_TYPE_133OLD; 251 sc->sc_wdcdev.sc_atac.atac_udma_cap = 252 sis_hostbr_type_match->udma_mode; 253 } else { 254 sc->sis_type = SIS_TYPE_100NEW; 255 sc->sc_wdcdev.sc_atac.atac_udma_cap = 256 sis_hostbr_type_match->udma_mode; 257 } 258 } 259 } else { 260 sc->sis_type = sis_hostbr_type_match->type; 261 sc->sc_wdcdev.sc_atac.atac_udma_cap = 262 sis_hostbr_type_match->udma_mode; 263 } 264 aprint_normal(sis_hostbr_type_match->name); 265 } else { 266 aprint_normal("5597/5598"); 267 if (rev >= 0xd0) { 268 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 269 sc->sis_type = SIS_TYPE_66; 270 } else { 271 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 272 sc->sis_type = SIS_TYPE_NOUDMA; 273 } 274 } 275 aprint_normal(" IDE controller (rev. 0x%02x)\n", 276 PCI_REVISION(pa->pa_class)); 277 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 278 "bus-master DMA support present"); 279 pciide_mapreg_dma(sc, pa); 280 aprint_verbose("\n"); 281 282 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 283 if (sc->sc_dma_ok) { 284 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 285 sc->sc_wdcdev.irqack = pciide_irqack; 286 if (sc->sis_type >= SIS_TYPE_66) 287 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 288 } 289 290 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 291 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 292 293 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 294 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 295 switch(sc->sis_type) { 296 case SIS_TYPE_NOUDMA: 297 case SIS_TYPE_66: 298 case SIS_TYPE_100OLD: 299 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 300 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 301 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 302 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 303 break; 304 case SIS_TYPE_100NEW: 305 case SIS_TYPE_133OLD: 306 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 307 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 308 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 309 break; 310 case SIS_TYPE_133NEW: 311 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 312 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 313 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 314 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 315 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 316 break; 317 } 318 319 wdc_allocate_regs(&sc->sc_wdcdev); 320 321 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 322 channel++) { 323 cp = &sc->pciide_channels[channel]; 324 if (pciide_chansetup(sc, channel, interface) == 0) 325 continue; 326 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 327 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 328 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 329 "%s channel ignored (disabled)\n", cp->name); 330 cp->ata_channel.ch_flags |= ATACH_DISABLED; 331 continue; 332 } 333 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 334 } 335 } 336 337 static void 338 sis96x_setup_channel(struct ata_channel *chp) 339 { 340 struct ata_drive_datas *drvp; 341 int drive, s; 342 u_int32_t sis_tim; 343 u_int32_t idedma_ctl; 344 int regtim; 345 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 346 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 347 348 sis_tim = 0; 349 idedma_ctl = 0; 350 /* setup DMA if needed */ 351 pciide_channel_dma_setup(cp); 352 353 for (drive = 0; drive < 2; drive++) { 354 regtim = SIS_TIM133( 355 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 356 chp->ch_channel, drive); 357 drvp = &chp->ch_drive[drive]; 358 /* If no drive, skip */ 359 if ((drvp->drive_flags & DRIVE) == 0) 360 continue; 361 /* add timing values, setup DMA if needed */ 362 if (drvp->drive_flags & DRIVE_UDMA) { 363 /* use Ultra/DMA */ 364 s = splbio(); 365 drvp->drive_flags &= ~DRIVE_DMA; 366 splx(s); 367 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 368 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 369 if (drvp->UDMA_mode > 2) 370 drvp->UDMA_mode = 2; 371 } 372 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 373 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 374 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 375 } else if (drvp->drive_flags & DRIVE_DMA) { 376 /* 377 * use Multiword DMA 378 * Timings will be used for both PIO and DMA, 379 * so adjust DMA mode if needed 380 */ 381 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 382 drvp->PIO_mode = drvp->DMA_mode + 2; 383 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 384 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 385 drvp->PIO_mode - 2 : 0; 386 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 387 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 388 } else { 389 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 390 } 391 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 392 "channel %d drive %d: 0x%x (reg 0x%x)\n", 393 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 394 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 395 } 396 if (idedma_ctl != 0) { 397 /* Add software bits in status register */ 398 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 399 idedma_ctl); 400 } 401 } 402 403 static void 404 sis_setup_channel(struct ata_channel *chp) 405 { 406 struct ata_drive_datas *drvp; 407 int drive, s; 408 u_int32_t sis_tim; 409 u_int32_t idedma_ctl; 410 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 411 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 412 413 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 414 "channel %d 0x%x\n", chp->ch_channel, 415 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 416 DEBUG_PROBE); 417 sis_tim = 0; 418 idedma_ctl = 0; 419 /* setup DMA if needed */ 420 pciide_channel_dma_setup(cp); 421 422 for (drive = 0; drive < 2; drive++) { 423 drvp = &chp->ch_drive[drive]; 424 /* If no drive, skip */ 425 if ((drvp->drive_flags & DRIVE) == 0) 426 continue; 427 /* add timing values, setup DMA if needed */ 428 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 429 (drvp->drive_flags & DRIVE_UDMA) == 0) 430 goto pio; 431 432 if (drvp->drive_flags & DRIVE_UDMA) { 433 /* use Ultra/DMA */ 434 s = splbio(); 435 drvp->drive_flags &= ~DRIVE_DMA; 436 splx(s); 437 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 438 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 439 if (drvp->UDMA_mode > 2) 440 drvp->UDMA_mode = 2; 441 } 442 switch (sc->sis_type) { 443 case SIS_TYPE_66: 444 case SIS_TYPE_100OLD: 445 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 446 SIS_TIM66_UDMA_TIME_OFF(drive); 447 break; 448 case SIS_TYPE_100NEW: 449 sis_tim |= 450 sis_udma100new_tim[drvp->UDMA_mode] << 451 SIS_TIM100_UDMA_TIME_OFF(drive); 452 case SIS_TYPE_133OLD: 453 sis_tim |= 454 sis_udma133old_tim[drvp->UDMA_mode] << 455 SIS_TIM100_UDMA_TIME_OFF(drive); 456 break; 457 default: 458 aprint_error("unknown SiS IDE type %d\n", 459 sc->sis_type); 460 } 461 } else { 462 /* 463 * use Multiword DMA 464 * Timings will be used for both PIO and DMA, 465 * so adjust DMA mode if needed 466 */ 467 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 468 drvp->PIO_mode = drvp->DMA_mode + 2; 469 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 470 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 471 drvp->PIO_mode - 2 : 0; 472 if (drvp->DMA_mode == 0) 473 drvp->PIO_mode = 0; 474 } 475 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 476 pio: switch (sc->sis_type) { 477 case SIS_TYPE_NOUDMA: 478 case SIS_TYPE_66: 479 case SIS_TYPE_100OLD: 480 sis_tim |= sis_pio_act[drvp->PIO_mode] << 481 SIS_TIM66_ACT_OFF(drive); 482 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 483 SIS_TIM66_REC_OFF(drive); 484 break; 485 case SIS_TYPE_100NEW: 486 case SIS_TYPE_133OLD: 487 sis_tim |= sis_pio_act[drvp->PIO_mode] << 488 SIS_TIM100_ACT_OFF(drive); 489 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 490 SIS_TIM100_REC_OFF(drive); 491 break; 492 default: 493 aprint_error("unknown SiS IDE type %d\n", 494 sc->sis_type); 495 } 496 } 497 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 498 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 499 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 500 sis_tim); 501 if (idedma_ctl != 0) { 502 /* Add software bits in status register */ 503 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 504 idedma_ctl); 505 } 506 } 507 508 static void 509 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 510 { 511 struct pciide_channel *cp; 512 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 513 int channel; 514 515 if (pciide_chipen(sc, pa) == 0) 516 return; 517 518 if (interface == 0) { 519 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 520 DEBUG_PROBE); 521 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 522 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 523 } 524 525 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 526 "Silicon Integrated Systems 180/96X SATA controller " 527 "(rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 528 529 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 530 "bus-master DMA support present"); 531 pciide_mapreg_dma(sc, pa); 532 aprint_verbose("\n"); 533 534 if (sc->sc_dma_ok) { 535 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 536 sc->sc_wdcdev.irqack = pciide_irqack; 537 } 538 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 539 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 540 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 541 542 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 543 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 544 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 545 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 546 547 wdc_allocate_regs(&sc->sc_wdcdev); 548 549 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 550 channel++) { 551 cp = &sc->pciide_channels[channel]; 552 if (pciide_chansetup(sc, channel, interface) == 0) 553 continue; 554 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 555 } 556 } 557
Indexes created Mon Sep 29 21:09:56 GMT 2025