siside.c revision 1.3
1 /* $NetBSD: siside.c,v 1.3 2003/11/27 23:02:40 fvdl Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_sis_reg.h> 40 41 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void sis_setup_channel(struct channel_softc *); 43 static void sis96x_setup_channel(struct channel_softc *); 44 45 static int sis_hostbr_match(struct pci_attach_args *); 46 static int sis_south_match(struct pci_attach_args *); 47 48 static int siside_match(struct device *, struct cfdata *, void *); 49 static void siside_attach(struct device *, struct device *, void *); 50 51 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 52 siside_match, siside_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_sis_products[] = { 55 { PCI_PRODUCT_SIS_5597_IDE, 56 0, 57 NULL, 58 sis_chip_map, 59 }, 60 { 0, 61 0, 62 NULL, 63 NULL 64 } 65 }; 66 67 static int 68 siside_match(struct device *parent, struct cfdata *match, void *aux) 69 { 70 struct pci_attach_args *pa = aux; 71 72 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 73 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 74 return (2); 75 } 76 return (0); 77 } 78 79 static void 80 siside_attach(struct device *parent, struct device *self, void *aux) 81 { 82 struct pci_attach_args *pa = aux; 83 struct pciide_softc *sc = (struct pciide_softc *)self; 84 85 pciide_common_attach(sc, pa, 86 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 87 88 } 89 90 static struct sis_hostbr_type { 91 u_int16_t id; 92 u_int8_t rev; 93 u_int8_t udma_mode; 94 char *name; 95 u_int8_t type; 96 #define SIS_TYPE_NOUDMA 0 97 #define SIS_TYPE_66 1 98 #define SIS_TYPE_100OLD 2 99 #define SIS_TYPE_100NEW 3 100 #define SIS_TYPE_133OLD 4 101 #define SIS_TYPE_133NEW 5 102 #define SIS_TYPE_SOUTH 6 103 } sis_hostbr_type[] = { 104 /* Most infos here are from sos (at) freebsd.org */ 105 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 106 #if 0 107 /* 108 * controllers associated to a rev 0x2 530 Host to PCI Bridge 109 * have problems with UDMA (info provided by Christos) 110 */ 111 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 112 #endif 113 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 114 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 115 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 116 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 117 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 118 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 119 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 120 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 121 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 122 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 123 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 124 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 125 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 126 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 127 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 128 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 129 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 130 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 131 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 132 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 134 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 135 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 136 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 137 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 138 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 139 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 140 /* 141 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 142 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 143 */ 144 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 145 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 146 }; 147 148 static struct sis_hostbr_type *sis_hostbr_type_match; 149 150 static int 151 sis_hostbr_match(struct pci_attach_args *pa) 152 { 153 int i; 154 155 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 156 return 0; 157 sis_hostbr_type_match = NULL; 158 for (i = 0; 159 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 160 i++) { 161 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 162 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 163 sis_hostbr_type_match = &sis_hostbr_type[i]; 164 } 165 return (sis_hostbr_type_match != NULL); 166 } 167 168 static int 169 sis_south_match(struct pci_attach_args *pa) 170 { 171 172 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 173 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 174 PCI_REVISION(pa->pa_class) >= 0x10); 175 } 176 177 static void 178 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 179 { 180 struct pciide_channel *cp; 181 int channel; 182 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 183 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 184 pcireg_t rev = PCI_REVISION(pa->pa_class); 185 bus_size_t cmdsize, ctlsize; 186 187 if (pciide_chipen(sc, pa) == 0) 188 return; 189 190 aprint_normal("%s: Silicon Integrated System ", 191 sc->sc_wdcdev.sc_dev.dv_xname); 192 pci_find_device(NULL, sis_hostbr_match); 193 if (sis_hostbr_type_match) { 194 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 195 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 196 pciide_pci_read(sc->sc_pc, sc->sc_tag, 197 SIS_REG_57) & 0x7f); 198 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 199 PCI_ID_REG)) == SIS_PRODUCT_5518) { 200 aprint_normal("96X UDMA%d", 201 sis_hostbr_type_match->udma_mode); 202 sc->sis_type = SIS_TYPE_133NEW; 203 sc->sc_wdcdev.UDMA_cap = 204 sis_hostbr_type_match->udma_mode; 205 } else { 206 if (pci_find_device(NULL, sis_south_match)) { 207 sc->sis_type = SIS_TYPE_133OLD; 208 sc->sc_wdcdev.UDMA_cap = 209 sis_hostbr_type_match->udma_mode; 210 } else { 211 sc->sis_type = SIS_TYPE_100NEW; 212 sc->sc_wdcdev.UDMA_cap = 213 sis_hostbr_type_match->udma_mode; 214 } 215 } 216 } else { 217 sc->sis_type = sis_hostbr_type_match->type; 218 sc->sc_wdcdev.UDMA_cap = 219 sis_hostbr_type_match->udma_mode; 220 } 221 aprint_normal(sis_hostbr_type_match->name); 222 } else { 223 aprint_normal("5597/5598"); 224 if (rev >= 0xd0) { 225 sc->sc_wdcdev.UDMA_cap = 2; 226 sc->sis_type = SIS_TYPE_66; 227 } else { 228 sc->sc_wdcdev.UDMA_cap = 0; 229 sc->sis_type = SIS_TYPE_NOUDMA; 230 } 231 } 232 aprint_normal(" IDE controller (rev. 0x%02x)\n", 233 PCI_REVISION(pa->pa_class)); 234 aprint_normal("%s: bus-master DMA support present", 235 sc->sc_wdcdev.sc_dev.dv_xname); 236 pciide_mapreg_dma(sc, pa); 237 aprint_normal("\n"); 238 239 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 240 WDC_CAPABILITY_MODE; 241 if (sc->sc_dma_ok) { 242 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 243 sc->sc_wdcdev.irqack = pciide_irqack; 244 if (sc->sis_type >= SIS_TYPE_66) 245 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 246 } 247 248 sc->sc_wdcdev.PIO_cap = 4; 249 sc->sc_wdcdev.DMA_cap = 2; 250 251 sc->sc_wdcdev.channels = sc->wdc_chanarray; 252 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 253 switch(sc->sis_type) { 254 case SIS_TYPE_NOUDMA: 255 case SIS_TYPE_66: 256 case SIS_TYPE_100OLD: 257 sc->sc_wdcdev.set_modes = sis_setup_channel; 258 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 259 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 260 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 261 break; 262 case SIS_TYPE_100NEW: 263 case SIS_TYPE_133OLD: 264 sc->sc_wdcdev.set_modes = sis_setup_channel; 265 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 266 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 267 break; 268 case SIS_TYPE_133NEW: 269 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 270 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 271 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 272 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 273 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 274 break; 275 } 276 277 278 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 279 cp = &sc->pciide_channels[channel]; 280 if (pciide_chansetup(sc, channel, interface) == 0) 281 continue; 282 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 283 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 284 aprint_normal("%s: %s channel ignored (disabled)\n", 285 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 286 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 287 continue; 288 } 289 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 290 pciide_pci_intr); 291 } 292 } 293 294 static void 295 sis96x_setup_channel(struct channel_softc *chp) 296 { 297 struct ata_drive_datas *drvp; 298 int drive; 299 u_int32_t sis_tim; 300 u_int32_t idedma_ctl; 301 int regtim; 302 struct pciide_channel *cp = (struct pciide_channel*)chp; 303 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 304 305 sis_tim = 0; 306 idedma_ctl = 0; 307 /* setup DMA if needed */ 308 pciide_channel_dma_setup(cp); 309 310 for (drive = 0; drive < 2; drive++) { 311 regtim = SIS_TIM133( 312 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 313 chp->channel, drive); 314 drvp = &chp->ch_drive[drive]; 315 /* If no drive, skip */ 316 if ((drvp->drive_flags & DRIVE) == 0) 317 continue; 318 /* add timing values, setup DMA if needed */ 319 if (drvp->drive_flags & DRIVE_UDMA) { 320 /* use Ultra/DMA */ 321 drvp->drive_flags &= ~DRIVE_DMA; 322 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 323 SIS96x_REG_CBL(chp->channel)) & SIS96x_REG_CBL_33) { 324 if (drvp->UDMA_mode > 2) 325 drvp->UDMA_mode = 2; 326 } 327 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 328 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 329 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 330 } else if (drvp->drive_flags & DRIVE_DMA) { 331 /* 332 * use Multiword DMA 333 * Timings will be used for both PIO and DMA, 334 * so adjust DMA mode if needed 335 */ 336 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 337 drvp->PIO_mode = drvp->DMA_mode + 2; 338 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 339 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 340 drvp->PIO_mode - 2 : 0; 341 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 342 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 343 } else { 344 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 345 } 346 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 347 "channel %d drive %d: 0x%x (reg 0x%x)\n", 348 chp->channel, drive, sis_tim, regtim), DEBUG_PROBE); 349 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 350 } 351 if (idedma_ctl != 0) { 352 /* Add software bits in status register */ 353 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 354 idedma_ctl); 355 } 356 } 357 358 static void 359 sis_setup_channel(struct channel_softc *chp) 360 { 361 struct ata_drive_datas *drvp; 362 int drive; 363 u_int32_t sis_tim; 364 u_int32_t idedma_ctl; 365 struct pciide_channel *cp = (struct pciide_channel*)chp; 366 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 367 368 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 369 "channel %d 0x%x\n", chp->channel, 370 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel))), 371 DEBUG_PROBE); 372 sis_tim = 0; 373 idedma_ctl = 0; 374 /* setup DMA if needed */ 375 pciide_channel_dma_setup(cp); 376 377 for (drive = 0; drive < 2; drive++) { 378 drvp = &chp->ch_drive[drive]; 379 /* If no drive, skip */ 380 if ((drvp->drive_flags & DRIVE) == 0) 381 continue; 382 /* add timing values, setup DMA if needed */ 383 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 384 (drvp->drive_flags & DRIVE_UDMA) == 0) 385 goto pio; 386 387 if (drvp->drive_flags & DRIVE_UDMA) { 388 /* use Ultra/DMA */ 389 drvp->drive_flags &= ~DRIVE_DMA; 390 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 391 SIS_REG_CBL) & SIS_REG_CBL_33(chp->channel)) { 392 if (drvp->UDMA_mode > 2) 393 drvp->UDMA_mode = 2; 394 } 395 switch (sc->sis_type) { 396 case SIS_TYPE_66: 397 case SIS_TYPE_100OLD: 398 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 399 SIS_TIM66_UDMA_TIME_OFF(drive); 400 break; 401 case SIS_TYPE_100NEW: 402 sis_tim |= 403 sis_udma100new_tim[drvp->UDMA_mode] << 404 SIS_TIM100_UDMA_TIME_OFF(drive); 405 case SIS_TYPE_133OLD: 406 sis_tim |= 407 sis_udma133old_tim[drvp->UDMA_mode] << 408 SIS_TIM100_UDMA_TIME_OFF(drive); 409 break; 410 default: 411 aprint_error("unknown SiS IDE type %d\n", 412 sc->sis_type); 413 } 414 } else { 415 /* 416 * use Multiword DMA 417 * Timings will be used for both PIO and DMA, 418 * so adjust DMA mode if needed 419 */ 420 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 421 drvp->PIO_mode = drvp->DMA_mode + 2; 422 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 423 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 424 drvp->PIO_mode - 2 : 0; 425 if (drvp->DMA_mode == 0) 426 drvp->PIO_mode = 0; 427 } 428 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 429 pio: switch (sc->sis_type) { 430 case SIS_TYPE_NOUDMA: 431 case SIS_TYPE_66: 432 case SIS_TYPE_100OLD: 433 sis_tim |= sis_pio_act[drvp->PIO_mode] << 434 SIS_TIM66_ACT_OFF(drive); 435 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 436 SIS_TIM66_REC_OFF(drive); 437 break; 438 case SIS_TYPE_100NEW: 439 case SIS_TYPE_133OLD: 440 sis_tim |= sis_pio_act[drvp->PIO_mode] << 441 SIS_TIM100_ACT_OFF(drive); 442 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 443 SIS_TIM100_REC_OFF(drive); 444 break; 445 default: 446 aprint_error("unknown SiS IDE type %d\n", 447 sc->sis_type); 448 } 449 } 450 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 451 "channel %d 0x%x\n", chp->channel, sis_tim), DEBUG_PROBE); 452 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->channel), sis_tim); 453 if (idedma_ctl != 0) { 454 /* Add software bits in status register */ 455 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 456 idedma_ctl); 457 } 458 } 459
Indexes created Mon Sep 29 21:09:56 GMT 2025