siside.c revision 1.33.2.1
1 /* $NetBSD: siside.c,v 1.33.2.1 2012/10/09 13:36:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __KERNEL_RCSID(0, "$NetBSD: siside.c,v 1.33.2.1 2012/10/09 13:36:06 bouyer Exp $"); 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 33 #include <dev/pci/pcivar.h> 34 #include <dev/pci/pcidevs.h> 35 #include <dev/pci/pciidereg.h> 36 #include <dev/pci/pciidevar.h> 37 #include <dev/pci/pciide_sis_reg.h> 38 39 static void sis_chip_map(struct pciide_softc *, const struct pci_attach_args *); 40 static void sis_sata_chip_map(struct pciide_softc *, 41 const struct pci_attach_args *); 42 static void sis_setup_channel(struct ata_channel *); 43 static void sis96x_setup_channel(struct ata_channel *); 44 45 static int sis_hostbr_match(const struct pci_attach_args *); 46 static int sis_south_match(const struct pci_attach_args *); 47 48 static int siside_match(device_t, cfdata_t, void *); 49 static void siside_attach(device_t, device_t, void *); 50 51 CFATTACH_DECL_NEW(siside, sizeof(struct pciide_softc), 52 siside_match, siside_attach, NULL, NULL); 53 54 static const struct pciide_product_desc pciide_sis_products[] = { 55 { PCI_PRODUCT_SIS_5597_IDE, 56 0, 57 NULL, 58 sis_chip_map, 59 }, 60 { PCI_PRODUCT_SIS_180_SATA, 61 0, 62 NULL, 63 sis_sata_chip_map, 64 }, 65 { PCI_PRODUCT_SIS_181_SATA, 66 0, 67 NULL, 68 sis_sata_chip_map, 69 }, 70 { PCI_PRODUCT_SIS_182_SATA, 71 0, 72 NULL, 73 sis_sata_chip_map, 74 }, 75 { 0, 76 0, 77 NULL, 78 NULL 79 } 80 }; 81 82 static int 83 siside_match(device_t parent, cfdata_t match, void *aux) 84 { 85 struct pci_attach_args *pa = aux; 86 87 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 88 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 89 return (2); 90 } 91 return (0); 92 } 93 94 static void 95 siside_attach(device_t parent, device_t self, void *aux) 96 { 97 struct pci_attach_args *pa = aux; 98 struct pciide_softc *sc = device_private(self); 99 pci_chipset_tag_t pc = pa->pa_pc; 100 pcitag_t tag = pa->pa_tag; 101 pcireg_t csr; 102 103 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 104 105 sc->sc_wdcdev.sc_atac.atac_dev = self; 106 107 pciide_common_attach(sc, pa, 108 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 109 110 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG); 111 if (csr & PCI_COMMAND_INTERRUPT_DISABLE) { 112 csr &= ~PCI_COMMAND_INTERRUPT_DISABLE; 113 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr); 114 } 115 } 116 117 static struct sis_hostbr_type { 118 u_int16_t id; 119 u_int8_t rev; 120 u_int8_t udma_mode; 121 const char *name; 122 u_int8_t type; 123 #define SIS_TYPE_NOUDMA 0 124 #define SIS_TYPE_66 1 125 #define SIS_TYPE_100OLD 2 126 #define SIS_TYPE_100NEW 3 127 #define SIS_TYPE_133OLD 4 128 #define SIS_TYPE_133NEW 5 129 #define SIS_TYPE_SOUTH 6 130 } sis_hostbr_type[] = { 131 /* Most infos here are from sos (at) freebsd.org */ 132 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 133 #if 0 134 /* 135 * controllers associated to a rev 0x2 530 Host to PCI Bridge 136 * have problems with UDMA (info provided by Christos) 137 */ 138 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 139 #endif 140 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 141 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 142 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 143 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 144 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 145 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 146 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 147 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 148 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 149 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 150 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 151 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 152 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 153 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 154 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 155 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 156 {PCI_PRODUCT_SIS_661, 0x00, 6, "661", SIS_TYPE_SOUTH}, 157 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 158 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 159 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 160 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 161 {PCI_PRODUCT_SIS_741, 0x00, 5, "741", SIS_TYPE_SOUTH}, 162 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 163 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 164 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 165 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 166 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 167 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 168 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 169 {PCI_PRODUCT_SIS_760, 0x00, 6, "760", SIS_TYPE_133NEW}, 170 /* 171 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 172 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 173 */ 174 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 175 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 176 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 177 {PCI_PRODUCT_SIS_965, 0x00, 6, "965", SIS_TYPE_133NEW}, 178 }; 179 180 static struct sis_hostbr_type *sis_hostbr_type_match; 181 182 static int 183 sis_hostbr_match(const struct pci_attach_args *pa) 184 { 185 int i; 186 pcireg_t id, masqid, reg; 187 188 id = pa->pa_id; 189 190 if (PCI_VENDOR(id) != PCI_VENDOR_SIS) 191 return 0; 192 if (PCI_PRODUCT(id) == PCI_PRODUCT_SIS_85C503) { 193 reg = pci_conf_read(pa->pa_pc, pa->pa_tag, SIS96x_DETECT); 194 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 195 reg | SIS96x_DETECT_MASQ); 196 masqid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_ID_REG); 197 if (((PCI_PRODUCT(masqid) & 0xfff0) != 0x0960) 198 && (PCI_PRODUCT(masqid) != 0x0018)) { 199 pci_conf_write(pa->pa_pc, pa->pa_tag, SIS96x_DETECT, 200 reg); 201 } else { 202 id = masqid; 203 } 204 } 205 206 sis_hostbr_type_match = NULL; 207 for (i = 0; i < __arraycount(sis_hostbr_type); i++) { 208 if (PCI_PRODUCT(id) == sis_hostbr_type[i].id && 209 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 210 sis_hostbr_type_match = &sis_hostbr_type[i]; 211 } 212 return (sis_hostbr_type_match != NULL); 213 } 214 215 static int 216 sis_south_match(const struct pci_attach_args *pa) 217 { 218 219 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 220 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 221 PCI_REVISION(pa->pa_class) >= 0x10); 222 } 223 224 static void 225 sis_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 226 { 227 struct pciide_channel *cp; 228 int channel; 229 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 230 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 231 pcireg_t rev = PCI_REVISION(pa->pa_class); 232 233 if (pciide_chipen(sc, pa) == 0) 234 return; 235 236 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 237 "Silicon Integrated Systems "); 238 pci_find_device(NULL, sis_hostbr_match); 239 if (sis_hostbr_type_match) { 240 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 241 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 242 pciide_pci_read(sc->sc_pc, sc->sc_tag, 243 SIS_REG_57) & 0x7f); 244 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 245 PCI_ID_REG)) == SIS_PRODUCT_5518) { 246 aprint_normal("96X UDMA%d", 247 sis_hostbr_type_match->udma_mode); 248 sc->sis_type = SIS_TYPE_133NEW; 249 sc->sc_wdcdev.sc_atac.atac_udma_cap = 250 sis_hostbr_type_match->udma_mode; 251 } else { 252 if (pci_find_device(NULL, sis_south_match)) { 253 sc->sis_type = SIS_TYPE_133OLD; 254 sc->sc_wdcdev.sc_atac.atac_udma_cap = 255 sis_hostbr_type_match->udma_mode; 256 } else { 257 sc->sis_type = SIS_TYPE_100NEW; 258 sc->sc_wdcdev.sc_atac.atac_udma_cap = 259 sis_hostbr_type_match->udma_mode; 260 } 261 } 262 } else { 263 sc->sis_type = sis_hostbr_type_match->type; 264 sc->sc_wdcdev.sc_atac.atac_udma_cap = 265 sis_hostbr_type_match->udma_mode; 266 } 267 aprint_normal("%s", sis_hostbr_type_match->name); 268 } else { 269 aprint_normal("5597/5598"); 270 if (rev >= 0xd0) { 271 sc->sc_wdcdev.sc_atac.atac_udma_cap = 2; 272 sc->sis_type = SIS_TYPE_66; 273 } else { 274 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 275 sc->sis_type = SIS_TYPE_NOUDMA; 276 } 277 } 278 aprint_normal(" IDE controller (rev. 0x%02x)\n", 279 PCI_REVISION(pa->pa_class)); 280 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 281 "bus-master DMA support present"); 282 pciide_mapreg_dma(sc, pa); 283 aprint_verbose("\n"); 284 285 sc->sc_wdcdev.sc_atac.atac_cap = ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 286 if (sc->sc_dma_ok) { 287 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 288 sc->sc_wdcdev.irqack = pciide_irqack; 289 if (sc->sis_type >= SIS_TYPE_66) 290 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA; 291 } 292 293 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 294 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 295 296 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 297 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 298 sc->sc_wdcdev.wdc_maxdrives = 2; 299 switch(sc->sis_type) { 300 case SIS_TYPE_NOUDMA: 301 case SIS_TYPE_66: 302 case SIS_TYPE_100OLD: 303 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 304 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 305 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 306 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 307 break; 308 case SIS_TYPE_100NEW: 309 case SIS_TYPE_133OLD: 310 sc->sc_wdcdev.sc_atac.atac_set_modes = sis_setup_channel; 311 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 312 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 313 break; 314 case SIS_TYPE_133NEW: 315 sc->sc_wdcdev.sc_atac.atac_set_modes = sis96x_setup_channel; 316 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 317 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 318 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 319 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 320 break; 321 } 322 323 wdc_allocate_regs(&sc->sc_wdcdev); 324 325 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 326 channel++) { 327 cp = &sc->pciide_channels[channel]; 328 if (pciide_chansetup(sc, channel, interface) == 0) 329 continue; 330 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 331 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 332 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 333 "%s channel ignored (disabled)\n", cp->name); 334 cp->ata_channel.ch_flags |= ATACH_DISABLED; 335 continue; 336 } 337 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 338 } 339 } 340 341 static void 342 sis96x_setup_channel(struct ata_channel *chp) 343 { 344 struct ata_drive_datas *drvp; 345 int drive, s; 346 u_int32_t sis_tim; 347 u_int32_t idedma_ctl; 348 int regtim; 349 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 350 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 351 352 sis_tim = 0; 353 idedma_ctl = 0; 354 /* setup DMA if needed */ 355 pciide_channel_dma_setup(cp); 356 357 for (drive = 0; drive < 2; drive++) { 358 regtim = SIS_TIM133( 359 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 360 chp->ch_channel, drive); 361 drvp = &chp->ch_drive[drive]; 362 /* If no drive, skip */ 363 if (drvp->drive_type == ATA_DRIVET_NONE) 364 continue; 365 /* add timing values, setup DMA if needed */ 366 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 367 /* use Ultra/DMA */ 368 s = splbio(); 369 drvp->drive_flags &= ~ATA_DRIVE_DMA; 370 splx(s); 371 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 372 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 373 if (drvp->UDMA_mode > 2) 374 drvp->UDMA_mode = 2; 375 } 376 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 377 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 378 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 379 } else if (drvp->drive_flags & ATA_DRIVE_DMA) { 380 /* 381 * use Multiword DMA 382 * Timings will be used for both PIO and DMA, 383 * so adjust DMA mode if needed 384 */ 385 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 386 drvp->PIO_mode = drvp->DMA_mode + 2; 387 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 388 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 389 drvp->PIO_mode - 2 : 0; 390 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 391 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 392 } else { 393 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 394 } 395 ATADEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 396 "channel %d drive %d: 0x%x (reg 0x%x)\n", 397 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 398 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 399 } 400 if (idedma_ctl != 0) { 401 /* Add software bits in status register */ 402 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 403 idedma_ctl); 404 } 405 } 406 407 static void 408 sis_setup_channel(struct ata_channel *chp) 409 { 410 struct ata_drive_datas *drvp; 411 int drive, s; 412 u_int32_t sis_tim; 413 u_int32_t idedma_ctl; 414 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 415 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 416 417 ATADEBUG_PRINT(("sis_setup_channel: old timings reg for " 418 "channel %d 0x%x\n", chp->ch_channel, 419 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 420 DEBUG_PROBE); 421 sis_tim = 0; 422 idedma_ctl = 0; 423 /* setup DMA if needed */ 424 pciide_channel_dma_setup(cp); 425 426 for (drive = 0; drive < 2; drive++) { 427 drvp = &chp->ch_drive[drive]; 428 /* If no drive, skip */ 429 if (drvp->drive_type == ATA_DRIVET_NONE) 430 continue; 431 /* add timing values, setup DMA if needed */ 432 if ((drvp->drive_flags & ATA_DRIVE_DMA) == 0 && 433 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) 434 goto pio; 435 436 if (drvp->drive_flags & ATA_DRIVE_UDMA) { 437 /* use Ultra/DMA */ 438 s = splbio(); 439 drvp->drive_flags &= ~ATA_DRIVE_DMA; 440 splx(s); 441 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 442 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 443 if (drvp->UDMA_mode > 2) 444 drvp->UDMA_mode = 2; 445 } 446 switch (sc->sis_type) { 447 case SIS_TYPE_66: 448 case SIS_TYPE_100OLD: 449 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 450 SIS_TIM66_UDMA_TIME_OFF(drive); 451 break; 452 case SIS_TYPE_100NEW: 453 sis_tim |= 454 sis_udma100new_tim[drvp->UDMA_mode] << 455 SIS_TIM100_UDMA_TIME_OFF(drive); 456 case SIS_TYPE_133OLD: 457 sis_tim |= 458 sis_udma133old_tim[drvp->UDMA_mode] << 459 SIS_TIM100_UDMA_TIME_OFF(drive); 460 break; 461 default: 462 aprint_error("unknown SiS IDE type %d\n", 463 sc->sis_type); 464 } 465 } else { 466 /* 467 * use Multiword DMA 468 * Timings will be used for both PIO and DMA, 469 * so adjust DMA mode if needed 470 */ 471 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 472 drvp->PIO_mode = drvp->DMA_mode + 2; 473 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 474 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 475 drvp->PIO_mode - 2 : 0; 476 if (drvp->DMA_mode == 0) 477 drvp->PIO_mode = 0; 478 } 479 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 480 pio: switch (sc->sis_type) { 481 case SIS_TYPE_NOUDMA: 482 case SIS_TYPE_66: 483 case SIS_TYPE_100OLD: 484 sis_tim |= sis_pio_act[drvp->PIO_mode] << 485 SIS_TIM66_ACT_OFF(drive); 486 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 487 SIS_TIM66_REC_OFF(drive); 488 break; 489 case SIS_TYPE_100NEW: 490 case SIS_TYPE_133OLD: 491 sis_tim |= sis_pio_act[drvp->PIO_mode] << 492 SIS_TIM100_ACT_OFF(drive); 493 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 494 SIS_TIM100_REC_OFF(drive); 495 break; 496 default: 497 aprint_error("unknown SiS IDE type %d\n", 498 sc->sis_type); 499 } 500 } 501 ATADEBUG_PRINT(("sis_setup_channel: new timings reg for " 502 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 503 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 504 sis_tim); 505 if (idedma_ctl != 0) { 506 /* Add software bits in status register */ 507 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 508 idedma_ctl); 509 } 510 } 511 512 static void 513 sis_sata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 514 { 515 struct pciide_channel *cp; 516 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 517 int channel; 518 519 if (pciide_chipen(sc, pa) == 0) 520 return; 521 522 if (interface == 0) { 523 ATADEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 524 DEBUG_PROBE); 525 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 526 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 527 } 528 529 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 530 "Silicon Integrated Systems 180/96X SATA controller " 531 "(rev. 0x%02x)\n", PCI_REVISION(pa->pa_class)); 532 533 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 534 "bus-master DMA support present"); 535 pciide_mapreg_dma(sc, pa); 536 aprint_verbose("\n"); 537 538 if (sc->sc_dma_ok) { 539 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_UDMA | ATAC_CAP_DMA; 540 sc->sc_wdcdev.irqack = pciide_irqack; 541 } 542 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 543 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 544 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 545 546 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 547 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 548 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 549 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 550 sc->sc_wdcdev.wdc_maxdrives = 2; 551 552 wdc_allocate_regs(&sc->sc_wdcdev); 553 554 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 555 channel++) { 556 cp = &sc->pciide_channels[channel]; 557 if (pciide_chansetup(sc, channel, interface) == 0) 558 continue; 559 pciide_mapchan(pa, cp, interface, pciide_pci_intr); 560 } 561 } 562
Indexes created Fri Oct 17 23:09:53 GMT 2025