siside.c revision 1.6
1 /* $NetBSD: siside.c,v 1.6 2004/04/22 11:30:04 skd Exp $ */ 2 3 /* 4 * Copyright (c) 1999, 2000, 2001 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 35 #include <dev/pci/pcivar.h> 36 #include <dev/pci/pcidevs.h> 37 #include <dev/pci/pciidereg.h> 38 #include <dev/pci/pciidevar.h> 39 #include <dev/pci/pciide_sis_reg.h> 40 41 static void sis_chip_map(struct pciide_softc *, struct pci_attach_args *); 42 static void sis_sata_chip_map(struct pciide_softc *, struct pci_attach_args *); 43 static void sis_setup_channel(struct wdc_channel *); 44 static void sis96x_setup_channel(struct wdc_channel *); 45 46 static int sis_hostbr_match(struct pci_attach_args *); 47 static int sis_south_match(struct pci_attach_args *); 48 49 static int siside_match(struct device *, struct cfdata *, void *); 50 static void siside_attach(struct device *, struct device *, void *); 51 52 CFATTACH_DECL(siside, sizeof(struct pciide_softc), 53 siside_match, siside_attach, NULL, NULL); 54 55 static const struct pciide_product_desc pciide_sis_products[] = { 56 { PCI_PRODUCT_SIS_5597_IDE, 57 0, 58 NULL, 59 sis_chip_map, 60 }, 61 { PCI_PRODUCT_SIS_180_SATA, 62 0, 63 NULL, 64 sis_sata_chip_map, 65 }, 66 { 0, 67 0, 68 NULL, 69 NULL 70 } 71 }; 72 73 static int 74 siside_match(struct device *parent, struct cfdata *match, void *aux) 75 { 76 struct pci_attach_args *pa = aux; 77 78 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS) { 79 if (pciide_lookup_product(pa->pa_id, pciide_sis_products)) 80 return (2); 81 } 82 return (0); 83 } 84 85 static void 86 siside_attach(struct device *parent, struct device *self, void *aux) 87 { 88 struct pci_attach_args *pa = aux; 89 struct pciide_softc *sc = (struct pciide_softc *)self; 90 91 pciide_common_attach(sc, pa, 92 pciide_lookup_product(pa->pa_id, pciide_sis_products)); 93 94 } 95 96 static struct sis_hostbr_type { 97 u_int16_t id; 98 u_int8_t rev; 99 u_int8_t udma_mode; 100 char *name; 101 u_int8_t type; 102 #define SIS_TYPE_NOUDMA 0 103 #define SIS_TYPE_66 1 104 #define SIS_TYPE_100OLD 2 105 #define SIS_TYPE_100NEW 3 106 #define SIS_TYPE_133OLD 4 107 #define SIS_TYPE_133NEW 5 108 #define SIS_TYPE_SOUTH 6 109 } sis_hostbr_type[] = { 110 /* Most infos here are from sos (at) freebsd.org */ 111 {PCI_PRODUCT_SIS_530HB, 0x00, 4, "530", SIS_TYPE_66}, 112 #if 0 113 /* 114 * controllers associated to a rev 0x2 530 Host to PCI Bridge 115 * have problems with UDMA (info provided by Christos) 116 */ 117 {PCI_PRODUCT_SIS_530HB, 0x02, 0, "530 (buggy)", SIS_TYPE_NOUDMA}, 118 #endif 119 {PCI_PRODUCT_SIS_540HB, 0x00, 4, "540", SIS_TYPE_66}, 120 {PCI_PRODUCT_SIS_550HB, 0x00, 4, "550", SIS_TYPE_66}, 121 {PCI_PRODUCT_SIS_620, 0x00, 4, "620", SIS_TYPE_66}, 122 {PCI_PRODUCT_SIS_630, 0x00, 4, "630", SIS_TYPE_66}, 123 {PCI_PRODUCT_SIS_630, 0x30, 5, "630S", SIS_TYPE_100NEW}, 124 {PCI_PRODUCT_SIS_633, 0x00, 5, "633", SIS_TYPE_100NEW}, 125 {PCI_PRODUCT_SIS_635, 0x00, 5, "635", SIS_TYPE_100NEW}, 126 {PCI_PRODUCT_SIS_640, 0x00, 4, "640", SIS_TYPE_SOUTH}, 127 {PCI_PRODUCT_SIS_645, 0x00, 6, "645", SIS_TYPE_SOUTH}, 128 {PCI_PRODUCT_SIS_646, 0x00, 6, "645DX", SIS_TYPE_SOUTH}, 129 {PCI_PRODUCT_SIS_648, 0x00, 6, "648", SIS_TYPE_SOUTH}, 130 {PCI_PRODUCT_SIS_650, 0x00, 6, "650", SIS_TYPE_SOUTH}, 131 {PCI_PRODUCT_SIS_651, 0x00, 6, "651", SIS_TYPE_SOUTH}, 132 {PCI_PRODUCT_SIS_652, 0x00, 6, "652", SIS_TYPE_SOUTH}, 133 {PCI_PRODUCT_SIS_655, 0x00, 6, "655", SIS_TYPE_SOUTH}, 134 {PCI_PRODUCT_SIS_658, 0x00, 6, "658", SIS_TYPE_SOUTH}, 135 {PCI_PRODUCT_SIS_730, 0x00, 5, "730", SIS_TYPE_100OLD}, 136 {PCI_PRODUCT_SIS_733, 0x00, 5, "733", SIS_TYPE_100NEW}, 137 {PCI_PRODUCT_SIS_735, 0x00, 5, "735", SIS_TYPE_100NEW}, 138 {PCI_PRODUCT_SIS_740, 0x00, 5, "740", SIS_TYPE_SOUTH}, 139 {PCI_PRODUCT_SIS_745, 0x00, 5, "745", SIS_TYPE_100NEW}, 140 {PCI_PRODUCT_SIS_746, 0x00, 6, "746", SIS_TYPE_SOUTH}, 141 {PCI_PRODUCT_SIS_748, 0x00, 6, "748", SIS_TYPE_SOUTH}, 142 {PCI_PRODUCT_SIS_750, 0x00, 6, "750", SIS_TYPE_SOUTH}, 143 {PCI_PRODUCT_SIS_751, 0x00, 6, "751", SIS_TYPE_SOUTH}, 144 {PCI_PRODUCT_SIS_752, 0x00, 6, "752", SIS_TYPE_SOUTH}, 145 {PCI_PRODUCT_SIS_755, 0x00, 6, "755", SIS_TYPE_SOUTH}, 146 /* 147 * From sos (at) freebsd.org: the 0x961 ID will never be found in real world 148 * {PCI_PRODUCT_SIS_961, 0x00, 6, "961", SIS_TYPE_133NEW}, 149 */ 150 {PCI_PRODUCT_SIS_962, 0x00, 6, "962", SIS_TYPE_133NEW}, 151 {PCI_PRODUCT_SIS_963, 0x00, 6, "963", SIS_TYPE_133NEW}, 152 {PCI_PRODUCT_SIS_964, 0x00, 6, "964", SIS_TYPE_133NEW}, 153 }; 154 155 static struct sis_hostbr_type *sis_hostbr_type_match; 156 157 static int 158 sis_hostbr_match(struct pci_attach_args *pa) 159 { 160 int i; 161 162 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_SIS) 163 return 0; 164 sis_hostbr_type_match = NULL; 165 for (i = 0; 166 i < sizeof(sis_hostbr_type) / sizeof(sis_hostbr_type[0]); 167 i++) { 168 if (PCI_PRODUCT(pa->pa_id) == sis_hostbr_type[i].id && 169 PCI_REVISION(pa->pa_class) >= sis_hostbr_type[i].rev) 170 sis_hostbr_type_match = &sis_hostbr_type[i]; 171 } 172 return (sis_hostbr_type_match != NULL); 173 } 174 175 static int 176 sis_south_match(struct pci_attach_args *pa) 177 { 178 179 return (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SIS && 180 PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_SIS_85C503 && 181 PCI_REVISION(pa->pa_class) >= 0x10); 182 } 183 184 static void 185 sis_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 186 { 187 struct pciide_channel *cp; 188 int channel; 189 u_int8_t sis_ctr0 = pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_CTRL0); 190 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 191 pcireg_t rev = PCI_REVISION(pa->pa_class); 192 bus_size_t cmdsize, ctlsize; 193 194 if (pciide_chipen(sc, pa) == 0) 195 return; 196 197 aprint_normal("%s: Silicon Integrated Systems ", 198 sc->sc_wdcdev.sc_dev.dv_xname); 199 pci_find_device(NULL, sis_hostbr_match); 200 if (sis_hostbr_type_match) { 201 if (sis_hostbr_type_match->type == SIS_TYPE_SOUTH) { 202 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_57, 203 pciide_pci_read(sc->sc_pc, sc->sc_tag, 204 SIS_REG_57) & 0x7f); 205 if (PCI_PRODUCT(pci_conf_read(sc->sc_pc, sc->sc_tag, 206 PCI_ID_REG)) == SIS_PRODUCT_5518) { 207 aprint_normal("96X UDMA%d", 208 sis_hostbr_type_match->udma_mode); 209 sc->sis_type = SIS_TYPE_133NEW; 210 sc->sc_wdcdev.UDMA_cap = 211 sis_hostbr_type_match->udma_mode; 212 } else { 213 if (pci_find_device(NULL, sis_south_match)) { 214 sc->sis_type = SIS_TYPE_133OLD; 215 sc->sc_wdcdev.UDMA_cap = 216 sis_hostbr_type_match->udma_mode; 217 } else { 218 sc->sis_type = SIS_TYPE_100NEW; 219 sc->sc_wdcdev.UDMA_cap = 220 sis_hostbr_type_match->udma_mode; 221 } 222 } 223 } else { 224 sc->sis_type = sis_hostbr_type_match->type; 225 sc->sc_wdcdev.UDMA_cap = 226 sis_hostbr_type_match->udma_mode; 227 } 228 aprint_normal(sis_hostbr_type_match->name); 229 } else { 230 aprint_normal("5597/5598"); 231 if (rev >= 0xd0) { 232 sc->sc_wdcdev.UDMA_cap = 2; 233 sc->sis_type = SIS_TYPE_66; 234 } else { 235 sc->sc_wdcdev.UDMA_cap = 0; 236 sc->sis_type = SIS_TYPE_NOUDMA; 237 } 238 } 239 aprint_normal(" IDE controller (rev. 0x%02x)\n", 240 PCI_REVISION(pa->pa_class)); 241 aprint_normal("%s: bus-master DMA support present", 242 sc->sc_wdcdev.sc_dev.dv_xname); 243 pciide_mapreg_dma(sc, pa); 244 aprint_normal("\n"); 245 246 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 247 WDC_CAPABILITY_MODE; 248 if (sc->sc_dma_ok) { 249 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 250 sc->sc_wdcdev.irqack = pciide_irqack; 251 if (sc->sis_type >= SIS_TYPE_66) 252 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA; 253 } 254 255 sc->sc_wdcdev.PIO_cap = 4; 256 sc->sc_wdcdev.DMA_cap = 2; 257 258 sc->sc_wdcdev.channels = sc->wdc_chanarray; 259 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 260 switch(sc->sis_type) { 261 case SIS_TYPE_NOUDMA: 262 case SIS_TYPE_66: 263 case SIS_TYPE_100OLD: 264 sc->sc_wdcdev.set_modes = sis_setup_channel; 265 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_MISC, 266 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_MISC) | 267 SIS_MISC_TIM_SEL | SIS_MISC_FIFO_SIZE | SIS_MISC_GTC); 268 break; 269 case SIS_TYPE_100NEW: 270 case SIS_TYPE_133OLD: 271 sc->sc_wdcdev.set_modes = sis_setup_channel; 272 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_49, 273 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_49) | 0x01); 274 break; 275 case SIS_TYPE_133NEW: 276 sc->sc_wdcdev.set_modes = sis96x_setup_channel; 277 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_50, 278 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_50) & 0xf7); 279 pciide_pci_write(sc->sc_pc, sc->sc_tag, SIS_REG_52, 280 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_52) & 0xf7); 281 break; 282 } 283 284 285 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 286 cp = &sc->pciide_channels[channel]; 287 if (pciide_chansetup(sc, channel, interface) == 0) 288 continue; 289 if ((channel == 0 && (sis_ctr0 & SIS_CTRL0_CHAN0_EN) == 0) || 290 (channel == 1 && (sis_ctr0 & SIS_CTRL0_CHAN1_EN) == 0)) { 291 aprint_normal("%s: %s channel ignored (disabled)\n", 292 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 293 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 294 continue; 295 } 296 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 297 pciide_pci_intr); 298 } 299 } 300 301 static void 302 sis96x_setup_channel(struct wdc_channel *chp) 303 { 304 struct ata_drive_datas *drvp; 305 int drive; 306 u_int32_t sis_tim; 307 u_int32_t idedma_ctl; 308 int regtim; 309 struct pciide_channel *cp = (struct pciide_channel*)chp; 310 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 311 312 sis_tim = 0; 313 idedma_ctl = 0; 314 /* setup DMA if needed */ 315 pciide_channel_dma_setup(cp); 316 317 for (drive = 0; drive < 2; drive++) { 318 regtim = SIS_TIM133( 319 pciide_pci_read(sc->sc_pc, sc->sc_tag, SIS_REG_57), 320 chp->ch_channel, drive); 321 drvp = &chp->ch_drive[drive]; 322 /* If no drive, skip */ 323 if ((drvp->drive_flags & DRIVE) == 0) 324 continue; 325 /* add timing values, setup DMA if needed */ 326 if (drvp->drive_flags & DRIVE_UDMA) { 327 /* use Ultra/DMA */ 328 drvp->drive_flags &= ~DRIVE_DMA; 329 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 330 SIS96x_REG_CBL(chp->ch_channel)) & SIS96x_REG_CBL_33) { 331 if (drvp->UDMA_mode > 2) 332 drvp->UDMA_mode = 2; 333 } 334 sis_tim |= sis_udma133new_tim[drvp->UDMA_mode]; 335 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 336 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 337 } else if (drvp->drive_flags & DRIVE_DMA) { 338 /* 339 * use Multiword DMA 340 * Timings will be used for both PIO and DMA, 341 * so adjust DMA mode if needed 342 */ 343 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 344 drvp->PIO_mode = drvp->DMA_mode + 2; 345 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 346 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 347 drvp->PIO_mode - 2 : 0; 348 sis_tim |= sis_dma133new_tim[drvp->DMA_mode]; 349 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 350 } else { 351 sis_tim |= sis_pio133new_tim[drvp->PIO_mode]; 352 } 353 WDCDEBUG_PRINT(("sis96x_setup_channel: new timings reg for " 354 "channel %d drive %d: 0x%x (reg 0x%x)\n", 355 chp->ch_channel, drive, sis_tim, regtim), DEBUG_PROBE); 356 pci_conf_write(sc->sc_pc, sc->sc_tag, regtim, sis_tim); 357 } 358 if (idedma_ctl != 0) { 359 /* Add software bits in status register */ 360 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 361 idedma_ctl); 362 } 363 } 364 365 static void 366 sis_setup_channel(struct wdc_channel *chp) 367 { 368 struct ata_drive_datas *drvp; 369 int drive; 370 u_int32_t sis_tim; 371 u_int32_t idedma_ctl; 372 struct pciide_channel *cp = (struct pciide_channel*)chp; 373 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.ch_wdc; 374 375 WDCDEBUG_PRINT(("sis_setup_channel: old timings reg for " 376 "channel %d 0x%x\n", chp->ch_channel, 377 pci_conf_read(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel))), 378 DEBUG_PROBE); 379 sis_tim = 0; 380 idedma_ctl = 0; 381 /* setup DMA if needed */ 382 pciide_channel_dma_setup(cp); 383 384 for (drive = 0; drive < 2; drive++) { 385 drvp = &chp->ch_drive[drive]; 386 /* If no drive, skip */ 387 if ((drvp->drive_flags & DRIVE) == 0) 388 continue; 389 /* add timing values, setup DMA if needed */ 390 if ((drvp->drive_flags & DRIVE_DMA) == 0 && 391 (drvp->drive_flags & DRIVE_UDMA) == 0) 392 goto pio; 393 394 if (drvp->drive_flags & DRIVE_UDMA) { 395 /* use Ultra/DMA */ 396 drvp->drive_flags &= ~DRIVE_DMA; 397 if (pciide_pci_read(sc->sc_pc, sc->sc_tag, 398 SIS_REG_CBL) & SIS_REG_CBL_33(chp->ch_channel)) { 399 if (drvp->UDMA_mode > 2) 400 drvp->UDMA_mode = 2; 401 } 402 switch (sc->sis_type) { 403 case SIS_TYPE_66: 404 case SIS_TYPE_100OLD: 405 sis_tim |= sis_udma66_tim[drvp->UDMA_mode] << 406 SIS_TIM66_UDMA_TIME_OFF(drive); 407 break; 408 case SIS_TYPE_100NEW: 409 sis_tim |= 410 sis_udma100new_tim[drvp->UDMA_mode] << 411 SIS_TIM100_UDMA_TIME_OFF(drive); 412 case SIS_TYPE_133OLD: 413 sis_tim |= 414 sis_udma133old_tim[drvp->UDMA_mode] << 415 SIS_TIM100_UDMA_TIME_OFF(drive); 416 break; 417 default: 418 aprint_error("unknown SiS IDE type %d\n", 419 sc->sis_type); 420 } 421 } else { 422 /* 423 * use Multiword DMA 424 * Timings will be used for both PIO and DMA, 425 * so adjust DMA mode if needed 426 */ 427 if (drvp->PIO_mode > (drvp->DMA_mode + 2)) 428 drvp->PIO_mode = drvp->DMA_mode + 2; 429 if (drvp->DMA_mode + 2 > (drvp->PIO_mode)) 430 drvp->DMA_mode = (drvp->PIO_mode > 2) ? 431 drvp->PIO_mode - 2 : 0; 432 if (drvp->DMA_mode == 0) 433 drvp->PIO_mode = 0; 434 } 435 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 436 pio: switch (sc->sis_type) { 437 case SIS_TYPE_NOUDMA: 438 case SIS_TYPE_66: 439 case SIS_TYPE_100OLD: 440 sis_tim |= sis_pio_act[drvp->PIO_mode] << 441 SIS_TIM66_ACT_OFF(drive); 442 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 443 SIS_TIM66_REC_OFF(drive); 444 break; 445 case SIS_TYPE_100NEW: 446 case SIS_TYPE_133OLD: 447 sis_tim |= sis_pio_act[drvp->PIO_mode] << 448 SIS_TIM100_ACT_OFF(drive); 449 sis_tim |= sis_pio_rec[drvp->PIO_mode] << 450 SIS_TIM100_REC_OFF(drive); 451 break; 452 default: 453 aprint_error("unknown SiS IDE type %d\n", 454 sc->sis_type); 455 } 456 } 457 WDCDEBUG_PRINT(("sis_setup_channel: new timings reg for " 458 "channel %d 0x%x\n", chp->ch_channel, sis_tim), DEBUG_PROBE); 459 pci_conf_write(sc->sc_pc, sc->sc_tag, SIS_TIM(chp->ch_channel), 460 sis_tim); 461 if (idedma_ctl != 0) { 462 /* Add software bits in status register */ 463 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 464 idedma_ctl); 465 } 466 } 467 468 static void 469 sis_sata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 470 { 471 struct pciide_channel *cp; 472 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 473 int channel; 474 bus_size_t cmdsize, ctlsize; 475 476 if (pciide_chipen(sc, pa) == 0) 477 return; 478 479 if (interface == 0) { 480 WDCDEBUG_PRINT(("sis_sata_chip_map interface == 0\n"), 481 DEBUG_PROBE); 482 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 483 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 484 } 485 486 aprint_normal("%s: Silicon Integrated Systems 180/96X SATA controller (rev. 0x%02x)\n", 487 sc->sc_wdcdev.sc_dev.dv_xname, 488 PCI_REVISION(pa->pa_class)); 489 490 aprint_normal("%s: bus-master DMA support present", 491 sc->sc_wdcdev.sc_dev.dv_xname); 492 pciide_mapreg_dma(sc, pa); 493 aprint_normal("\n"); 494 495 if (sc->sc_dma_ok) { 496 sc->sc_wdcdev.cap |= WDC_CAPABILITY_UDMA | WDC_CAPABILITY_DMA | 497 WDC_CAPABILITY_IRQACK; 498 sc->sc_wdcdev.irqack = pciide_irqack; 499 } 500 sc->sc_wdcdev.PIO_cap = 4; 501 sc->sc_wdcdev.DMA_cap = 2; 502 sc->sc_wdcdev.UDMA_cap = 6; 503 504 sc->sc_wdcdev.channels = sc->wdc_chanarray; 505 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 506 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32 | 507 WDC_CAPABILITY_MODE; 508 sc->sc_wdcdev.set_modes = sata_setup_channel; 509 510 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 511 cp = &sc->pciide_channels[channel]; 512 if (pciide_chansetup(sc, channel, interface) == 0) 513 continue; 514 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 515 pciide_pci_intr); 516 } 517 } 518
Indexes created Mon Sep 29 21:09:56 GMT 2025