slide.c revision 1.2
1 /* $NetBSD: slide.c,v 1.2 2003/10/11 17:40:15 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pciidereg.h> 45 #include <dev/pci/pciidevar.h> 46 #include <dev/pci/pciide_sl82c105_reg.h> 47 48 static void sl82c105_chip_map(struct pciide_softc*, struct pci_attach_args*); 49 static void sl82c105_setup_channel(struct channel_softc*); 50 51 static int slide_match(struct device *, struct cfdata *, void *); 52 static void slide_attach(struct device *, struct device *, void *); 53 54 CFATTACH_DECL(slide, sizeof(struct pciide_softc), 55 slide_match, slide_attach, NULL, NULL); 56 57 static const struct pciide_product_desc pciide_symphony_products[] = { 58 { PCI_PRODUCT_SYMPHONY_82C105, 59 0, 60 "Symphony Labs 82C105 IDE controller", 61 sl82c105_chip_map, 62 }, 63 { 0, 64 0, 65 NULL, 66 } 67 }; 68 69 static const struct pciide_product_desc pciide_winbond_products[] = { 70 { PCI_PRODUCT_WINBOND_W83C553F_1, 71 0, 72 "Winbond W83C553F IDE controller", 73 sl82c105_chip_map, 74 }, 75 { 0, 76 0, 77 NULL, 78 } 79 }; 80 81 static int 82 slide_match(struct device *parent, struct cfdata *match, void *aux) 83 { 84 struct pci_attach_args *pa = aux; 85 86 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SYMPHONY) { 87 if (pciide_lookup_product(pa->pa_id, pciide_symphony_products)) 88 return (2); 89 } 90 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) { 91 if (pciide_lookup_product(pa->pa_id, pciide_winbond_products)) 92 return (2); 93 } 94 return (0); 95 } 96 97 static void 98 slide_attach(struct device *parent, struct device *self, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 struct pciide_softc *sc = (struct pciide_softc *)self; 102 const struct pciide_product_desc *pp = NULL; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SYMPHONY) 105 pp = pciide_lookup_product(pa->pa_id, pciide_symphony_products); 106 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) 107 pp = pciide_lookup_product(pa->pa_id, pciide_winbond_products); 108 if (pp == NULL) 109 panic("slide_attach"); 110 pciide_common_attach(sc, pa, pp); 111 } 112 113 static int 114 sl82c105_bugchk(struct pci_attach_args *pa) 115 { 116 117 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 118 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 119 return (0); 120 121 if (PCI_REVISION(pa->pa_class) <= 0x05) 122 return (1); 123 124 return (0); 125 } 126 127 static void 128 sl82c105_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 129 { 130 struct pciide_channel *cp; 131 bus_size_t cmdsize, ctlsize; 132 pcireg_t interface, idecr; 133 int channel; 134 135 if (pciide_chipen(sc, pa) == 0) 136 return; 137 138 aprint_normal("%s: bus-master DMA support present", 139 sc->sc_wdcdev.sc_dev.dv_xname); 140 141 /* 142 * Check to see if we're part of the Winbond 83c553 Southbridge. 143 * If so, we need to disable DMA on rev. <= 5 of that chip. 144 */ 145 if (pci_find_device(pa, sl82c105_bugchk)) { 146 aprint_normal(" but disabled due to 83c553 rev. <= 0x05"); 147 sc->sc_dma_ok = 0; 148 } else 149 pciide_mapreg_dma(sc, pa); 150 aprint_normal("\n"); 151 152 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16 | 153 WDC_CAPABILITY_MODE; 154 sc->sc_wdcdev.PIO_cap = 4; 155 if (sc->sc_dma_ok) { 156 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA | WDC_CAPABILITY_IRQACK; 157 sc->sc_wdcdev.irqack = pciide_irqack; 158 sc->sc_wdcdev.DMA_cap = 2; 159 } 160 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 161 162 sc->sc_wdcdev.channels = sc->wdc_chanarray; 163 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 164 165 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 166 167 interface = PCI_INTERFACE(pa->pa_class); 168 169 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 170 cp = &sc->pciide_channels[channel]; 171 if (pciide_chansetup(sc, channel, interface) == 0) 172 continue; 173 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 174 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 175 aprint_normal("%s: %s channel ignored (disabled)\n", 176 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 177 cp->wdc_channel.ch_flags |= WDCF_DISABLED; 178 continue; 179 } 180 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 181 pciide_pci_intr); 182 } 183 } 184 185 static void 186 sl82c105_setup_channel(struct channel_softc *chp) 187 { 188 struct ata_drive_datas *drvp; 189 struct pciide_channel *cp = (struct pciide_channel*)chp; 190 struct pciide_softc *sc = (struct pciide_softc *)cp->wdc_channel.wdc; 191 int pxdx_reg, drive; 192 pcireg_t pxdx; 193 194 /* Set up DMA if needed. */ 195 pciide_channel_dma_setup(cp); 196 197 for (drive = 0; drive < 2; drive++) { 198 pxdx_reg = ((chp->channel == 0) ? SYMPH_P0D0CR 199 : SYMPH_P1D0CR) + (drive * 4); 200 201 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 202 203 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 204 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 205 206 drvp = &chp->ch_drive[drive]; 207 /* If no drive, skip. */ 208 if ((drvp->drive_flags & DRIVE) == 0) { 209 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 210 continue; 211 } 212 213 if (drvp->drive_flags & DRIVE_DMA) { 214 /* 215 * Timings will be used for both PIO and DMA, 216 * so adjust DMA mode if needed. 217 */ 218 if (drvp->PIO_mode >= 3) { 219 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 220 drvp->DMA_mode = drvp->PIO_mode - 2; 221 if (drvp->DMA_mode < 1) { 222 /* 223 * Can't mix both PIO and DMA. 224 * Disable DMA. 225 */ 226 drvp->drive_flags &= ~DRIVE_DMA; 227 } 228 } else { 229 /* 230 * Can't mix both PIO and DMA. Disable 231 * DMA. 232 */ 233 drvp->drive_flags &= ~DRIVE_DMA; 234 } 235 } 236 237 if (drvp->drive_flags & DRIVE_DMA) { 238 /* Use multi-word DMA. */ 239 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 240 PxDx_CMD_ON_SHIFT; 241 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 242 } else { 243 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 244 PxDx_CMD_ON_SHIFT; 245 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 246 } 247 248 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 249 250 /* ...and set the mode for this drive. */ 251 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 252 } 253 } 254
Indexes created Thu Oct 02 01:09:59 GMT 2025