slide.c revision 1.6
1 /* $NetBSD: slide.c,v 1.6 2004/08/14 15:08:06 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <dev/pci/pcidevs.h> 44 #include <dev/pci/pciidereg.h> 45 #include <dev/pci/pciidevar.h> 46 #include <dev/pci/pciide_sl82c105_reg.h> 47 48 static void sl82c105_chip_map(struct pciide_softc*, struct pci_attach_args*); 49 static void sl82c105_setup_channel(struct ata_channel*); 50 51 static int slide_match(struct device *, struct cfdata *, void *); 52 static void slide_attach(struct device *, struct device *, void *); 53 54 CFATTACH_DECL(slide, sizeof(struct pciide_softc), 55 slide_match, slide_attach, NULL, NULL); 56 57 static const struct pciide_product_desc pciide_symphony_products[] = { 58 { PCI_PRODUCT_SYMPHONY_82C105, 59 0, 60 "Symphony Labs 82C105 IDE controller", 61 sl82c105_chip_map, 62 }, 63 { 0, 64 0, 65 NULL, 66 } 67 }; 68 69 static const struct pciide_product_desc pciide_winbond_products[] = { 70 { PCI_PRODUCT_WINBOND_W83C553F_1, 71 0, 72 "Winbond W83C553F IDE controller", 73 sl82c105_chip_map, 74 }, 75 { 0, 76 0, 77 NULL, 78 } 79 }; 80 81 static int 82 slide_match(struct device *parent, struct cfdata *match, void *aux) 83 { 84 struct pci_attach_args *pa = aux; 85 86 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SYMPHONY) { 87 if (pciide_lookup_product(pa->pa_id, pciide_symphony_products)) 88 return (2); 89 } 90 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) { 91 if (pciide_lookup_product(pa->pa_id, pciide_winbond_products)) 92 return (2); 93 } 94 return (0); 95 } 96 97 static void 98 slide_attach(struct device *parent, struct device *self, void *aux) 99 { 100 struct pci_attach_args *pa = aux; 101 struct pciide_softc *sc = (struct pciide_softc *)self; 102 const struct pciide_product_desc *pp = NULL; 103 104 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SYMPHONY) 105 pp = pciide_lookup_product(pa->pa_id, pciide_symphony_products); 106 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_WINBOND) 107 pp = pciide_lookup_product(pa->pa_id, pciide_winbond_products); 108 if (pp == NULL) 109 panic("slide_attach"); 110 pciide_common_attach(sc, pa, pp); 111 } 112 113 static int 114 sl82c105_bugchk(struct pci_attach_args *pa) 115 { 116 117 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_WINBOND || 118 PCI_PRODUCT(pa->pa_id) != PCI_PRODUCT_WINBOND_W83C553F_0) 119 return (0); 120 121 if (PCI_REVISION(pa->pa_class) <= 0x05) 122 return (1); 123 124 return (0); 125 } 126 127 static void 128 sl82c105_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 129 { 130 struct pciide_channel *cp; 131 bus_size_t cmdsize, ctlsize; 132 pcireg_t interface, idecr; 133 int channel; 134 135 if (pciide_chipen(sc, pa) == 0) 136 return; 137 138 aprint_normal("%s: bus-master DMA support present", 139 sc->sc_wdcdev.sc_dev.dv_xname); 140 141 /* 142 * Check to see if we're part of the Winbond 83c553 Southbridge. 143 * If so, we need to disable DMA on rev. <= 5 of that chip. 144 */ 145 if (pci_find_device(pa, sl82c105_bugchk)) { 146 aprint_normal(" but disabled due to 83c553 rev. <= 0x05"); 147 sc->sc_dma_ok = 0; 148 } else 149 pciide_mapreg_dma(sc, pa); 150 aprint_normal("\n"); 151 152 sc->sc_wdcdev.cap = WDC_CAPABILITY_DATA32 | WDC_CAPABILITY_DATA16; 153 sc->sc_wdcdev.PIO_cap = 4; 154 if (sc->sc_dma_ok) { 155 sc->sc_wdcdev.cap |= WDC_CAPABILITY_DMA; 156 sc->sc_wdcdev.irqack = pciide_irqack; 157 sc->sc_wdcdev.DMA_cap = 2; 158 } 159 sc->sc_wdcdev.set_modes = sl82c105_setup_channel; 160 161 sc->sc_wdcdev.channels = sc->wdc_chanarray; 162 sc->sc_wdcdev.nchannels = PCIIDE_NUM_CHANNELS; 163 164 idecr = pci_conf_read(sc->sc_pc, sc->sc_tag, SYMPH_IDECSR); 165 166 interface = PCI_INTERFACE(pa->pa_class); 167 168 wdc_allocate_regs(&sc->sc_wdcdev); 169 170 for (channel = 0; channel < sc->sc_wdcdev.nchannels; channel++) { 171 cp = &sc->pciide_channels[channel]; 172 if (pciide_chansetup(sc, channel, interface) == 0) 173 continue; 174 if ((channel == 0 && (idecr & IDECR_P0EN) == 0) || 175 (channel == 1 && (idecr & IDECR_P1EN) == 0)) { 176 aprint_normal("%s: %s channel ignored (disabled)\n", 177 sc->sc_wdcdev.sc_dev.dv_xname, cp->name); 178 cp->ata_channel.ch_flags |= ATACH_DISABLED; 179 continue; 180 } 181 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 182 pciide_pci_intr); 183 } 184 } 185 186 static void 187 sl82c105_setup_channel(struct ata_channel *chp) 188 { 189 struct ata_drive_datas *drvp; 190 struct pciide_channel *cp = (struct pciide_channel*)chp; 191 struct pciide_softc *sc = (struct pciide_softc *)cp->ata_channel.ch_wdc; 192 int pxdx_reg, drive; 193 pcireg_t pxdx; 194 195 /* Set up DMA if needed. */ 196 pciide_channel_dma_setup(cp); 197 198 for (drive = 0; drive < 2; drive++) { 199 pxdx_reg = ((chp->ch_channel == 0) ? SYMPH_P0D0CR 200 : SYMPH_P1D0CR) + 201 (drive * 4); 202 203 pxdx = pci_conf_read(sc->sc_pc, sc->sc_tag, pxdx_reg); 204 205 pxdx &= ~(PxDx_CMD_ON_MASK|PxDx_CMD_OFF_MASK); 206 pxdx &= ~(PxDx_PWEN|PxDx_RDYEN|PxDx_RAEN); 207 208 drvp = &chp->ch_drive[drive]; 209 /* If no drive, skip. */ 210 if ((drvp->drive_flags & DRIVE) == 0) { 211 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 212 continue; 213 } 214 215 if (drvp->drive_flags & DRIVE_DMA) { 216 /* 217 * Timings will be used for both PIO and DMA, 218 * so adjust DMA mode if needed. 219 */ 220 if (drvp->PIO_mode >= 3) { 221 if ((drvp->DMA_mode + 2) > drvp->PIO_mode) 222 drvp->DMA_mode = drvp->PIO_mode - 2; 223 if (drvp->DMA_mode < 1) { 224 /* 225 * Can't mix both PIO and DMA. 226 * Disable DMA. 227 */ 228 drvp->drive_flags &= ~DRIVE_DMA; 229 } 230 } else { 231 /* 232 * Can't mix both PIO and DMA. Disable 233 * DMA. 234 */ 235 drvp->drive_flags &= ~DRIVE_DMA; 236 } 237 } 238 239 if (drvp->drive_flags & DRIVE_DMA) { 240 /* Use multi-word DMA. */ 241 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_on << 242 PxDx_CMD_ON_SHIFT; 243 pxdx |= symph_mw_dma_times[drvp->DMA_mode].cmd_off; 244 } else { 245 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_on << 246 PxDx_CMD_ON_SHIFT; 247 pxdx |= symph_pio_times[drvp->PIO_mode].cmd_off; 248 } 249 250 /* XXX PxDx_PWEN? PxDx_RDYEN? PxDx_RAEN? */ 251 252 /* ...and set the mode for this drive. */ 253 pci_conf_write(sc->sc_pc, sc->sc_tag, pxdx_reg, pxdx); 254 } 255 } 256
Indexes created Thu Oct 02 01:09:59 GMT 2025