sti_pci.c revision 1.2 1 1.2 msaitoh /* $NetBSD: sti_pci.c,v 1.2 2017/10/05 06:37:45 msaitoh Exp $ */
2 1.1 skrll
3 1.1 skrll /* $OpenBSD: sti_pci.c,v 1.7 2009/02/06 22:51:04 miod Exp $ */
4 1.1 skrll
5 1.1 skrll /*
6 1.1 skrll * Copyright (c) 2006, 2007 Miodrag Vallat.
7 1.1 skrll *
8 1.1 skrll * Permission to use, copy, modify, and distribute this software for any
9 1.1 skrll * purpose with or without fee is hereby granted, provided that the above
10 1.1 skrll * copyright notice, this permission notice, and the disclaimer below
11 1.1 skrll * appear in all copies.
12 1.1 skrll *
13 1.1 skrll * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 1.1 skrll * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 1.1 skrll * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 1.1 skrll * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 1.1 skrll * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 1.1 skrll * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 1.1 skrll * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 1.1 skrll */
21 1.1 skrll
22 1.1 skrll #include <sys/param.h>
23 1.1 skrll #include <sys/systm.h>
24 1.1 skrll #include <sys/device.h>
25 1.1 skrll
26 1.1 skrll #include <dev/pci/pcireg.h>
27 1.1 skrll #include <dev/pci/pcivar.h>
28 1.1 skrll #include <dev/pci/pcidevs.h>
29 1.1 skrll
30 1.1 skrll #include <dev/wscons/wsdisplayvar.h>
31 1.1 skrll
32 1.1 skrll #include <dev/ic/stireg.h>
33 1.1 skrll #include <dev/ic/stivar.h>
34 1.1 skrll
35 1.1 skrll #ifdef STIDEBUG
36 1.1 skrll #define DPRINTF(s) do { \
37 1.1 skrll if (stidebug) \
38 1.1 skrll printf s; \
39 1.1 skrll } while(0)
40 1.1 skrll
41 1.1 skrll extern int stidebug;
42 1.1 skrll #else
43 1.1 skrll #define DPRINTF(s) /* */
44 1.1 skrll #endif
45 1.1 skrll
46 1.1 skrll int sti_pci_match(device_t, cfdata_t, void *);
47 1.1 skrll void sti_pci_attach(device_t, device_t, void *);
48 1.1 skrll
49 1.1 skrll void sti_pci_end_attach(device_t dev);
50 1.1 skrll
51 1.1 skrll struct sti_pci_softc {
52 1.1 skrll device_t sc_dev;
53 1.1 skrll
54 1.1 skrll struct sti_softc sc_base;
55 1.1 skrll
56 1.1 skrll pci_chipset_tag_t sc_pc;
57 1.1 skrll pcitag_t sc_tag;
58 1.1 skrll
59 1.1 skrll bus_space_handle_t sc_romh;
60 1.1 skrll };
61 1.1 skrll
62 1.1 skrll CFATTACH_DECL_NEW(sti_pci, sizeof(struct sti_pci_softc),
63 1.1 skrll sti_pci_match, sti_pci_attach, NULL, NULL);
64 1.1 skrll
65 1.1 skrll int sti_readbar(struct sti_softc *, struct pci_attach_args *, u_int, int);
66 1.1 skrll int sti_check_rom(struct sti_pci_softc *, struct pci_attach_args *);
67 1.1 skrll void sti_pci_enable_rom(struct sti_softc *);
68 1.1 skrll void sti_pci_disable_rom(struct sti_softc *);
69 1.1 skrll void sti_pci_enable_rom_internal(struct sti_pci_softc *);
70 1.1 skrll void sti_pci_disable_rom_internal(struct sti_pci_softc *);
71 1.1 skrll
72 1.1 skrll int sti_pci_is_console(struct pci_attach_args *, bus_addr_t *);
73 1.1 skrll
74 1.1 skrll #define PCI_ROM_SIZE(mr) \
75 1.2 msaitoh (PCI_MAPREG_ROM_ADDR(mr) & -PCI_MAPREG_ROM_ADDR(mr))
76 1.1 skrll
77 1.1 skrll int
78 1.1 skrll sti_pci_match(device_t parent, cfdata_t cf, void *aux)
79 1.1 skrll {
80 1.1 skrll struct pci_attach_args *paa = aux;
81 1.1 skrll
82 1.1 skrll if (PCI_VENDOR(paa->pa_id) != PCI_VENDOR_HP)
83 1.1 skrll return 0;
84 1.1 skrll
85 1.1 skrll if (PCI_PRODUCT(paa->pa_id) == PCI_PRODUCT_HP_VISUALIZE_EG ||
86 1.1 skrll PCI_PRODUCT(paa->pa_id) == PCI_PRODUCT_HP_VISUALIZE_FX2 ||
87 1.1 skrll PCI_PRODUCT(paa->pa_id) == PCI_PRODUCT_HP_VISUALIZE_FX4 ||
88 1.1 skrll PCI_PRODUCT(paa->pa_id) == PCI_PRODUCT_HP_VISUALIZE_FX6 ||
89 1.1 skrll PCI_PRODUCT(paa->pa_id) == PCI_PRODUCT_HP_VISUALIZE_FXE)
90 1.1 skrll return 1;
91 1.1 skrll
92 1.1 skrll return 0;
93 1.1 skrll }
94 1.1 skrll
95 1.1 skrll void
96 1.1 skrll sti_pci_attach(device_t parent, device_t self, void *aux)
97 1.1 skrll {
98 1.1 skrll struct sti_pci_softc *spc = device_private(self);
99 1.1 skrll struct pci_attach_args *paa = aux;
100 1.1 skrll int ret;
101 1.1 skrll
102 1.1 skrll spc->sc_dev = self;
103 1.1 skrll
104 1.1 skrll spc->sc_pc = paa->pa_pc;
105 1.1 skrll spc->sc_tag = paa->pa_tag;
106 1.1 skrll spc->sc_base.sc_dev = self;
107 1.1 skrll spc->sc_base.sc_enable_rom = sti_pci_enable_rom;
108 1.1 skrll spc->sc_base.sc_disable_rom = sti_pci_disable_rom;
109 1.1 skrll
110 1.1 skrll aprint_normal("\n");
111 1.1 skrll
112 1.1 skrll if (sti_check_rom(spc, paa) != 0)
113 1.1 skrll return;
114 1.1 skrll
115 1.1 skrll aprint_normal("%s", device_xname(self));
116 1.1 skrll ret = sti_pci_is_console(paa, spc->sc_base. bases);
117 1.1 skrll if (ret != 0)
118 1.1 skrll spc->sc_base.sc_flags |= STI_CONSOLE;
119 1.1 skrll
120 1.1 skrll ret = sti_attach_common(&spc->sc_base, paa->pa_iot, paa->pa_memt,
121 1.1 skrll spc->sc_romh, STI_CODEBASE_MAIN);
122 1.1 skrll if (ret == 0)
123 1.1 skrll config_interrupts(self, sti_pci_end_attach);
124 1.1 skrll
125 1.1 skrll }
126 1.1 skrll
127 1.1 skrll void sti_pci_end_attach(device_t dev)
128 1.1 skrll {
129 1.1 skrll struct sti_pci_softc *spc = device_private(dev);
130 1.1 skrll struct sti_softc *sc = &spc->sc_base;
131 1.1 skrll
132 1.1 skrll sti_end_attach(sc);
133 1.1 skrll }
134 1.1 skrll
135 1.1 skrll
136 1.1 skrll /*
137 1.1 skrll * Grovel the STI ROM image.
138 1.1 skrll */
139 1.1 skrll int
140 1.1 skrll sti_check_rom(struct sti_pci_softc *spc, struct pci_attach_args *pa)
141 1.1 skrll {
142 1.1 skrll struct sti_softc *sc = &spc->sc_base;
143 1.1 skrll pcireg_t address, mask;
144 1.1 skrll bus_space_handle_t romh;
145 1.1 skrll bus_size_t romsize, subsize, stiromsize;
146 1.1 skrll bus_addr_t selected, offs, suboffs;
147 1.1 skrll uint32_t tmp;
148 1.1 skrll int i;
149 1.1 skrll int rc;
150 1.1 skrll
151 1.1 skrll /* sort of inline sti_pci_enable_rom(sc) */
152 1.1 skrll address = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM);
153 1.2 msaitoh pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM,
154 1.2 msaitoh ~PCI_MAPREG_ROM_ENABLE);
155 1.1 skrll mask = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM);
156 1.2 msaitoh address |= PCI_MAPREG_ROM_ENABLE;
157 1.1 skrll pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_MAPREG_ROM, address);
158 1.1 skrll sc->sc_flags |= STI_ROM_ENABLED;
159 1.1 skrll /*
160 1.1 skrll * Map the complete ROM for now.
161 1.1 skrll */
162 1.1 skrll
163 1.1 skrll romsize = PCI_ROM_SIZE(mask);
164 1.1 skrll DPRINTF(("%s: mapping rom @ %lx for %lx\n", __func__,
165 1.2 msaitoh (long)PCI_MAPREG_ROM_ADDR(address), (long)romsize));
166 1.1 skrll
167 1.2 msaitoh rc = bus_space_map(pa->pa_memt, PCI_MAPREG_ROM_ADDR(address), romsize,
168 1.1 skrll 0, &romh);
169 1.1 skrll if (rc != 0) {
170 1.1 skrll aprint_error_dev(sc->sc_dev, "can't map PCI ROM (%d)\n", rc);
171 1.1 skrll goto fail2;
172 1.1 skrll }
173 1.1 skrll
174 1.1 skrll sti_pci_disable_rom_internal(spc);
175 1.1 skrll /*
176 1.1 skrll * Iterate over the ROM images, pick the best candidate.
177 1.1 skrll */
178 1.1 skrll
179 1.1 skrll selected = (bus_addr_t)-1;
180 1.1 skrll for (offs = 0; offs < romsize; offs += subsize) {
181 1.1 skrll sti_pci_enable_rom_internal(spc);
182 1.1 skrll /*
183 1.1 skrll * Check for a valid ROM header.
184 1.1 skrll */
185 1.1 skrll tmp = bus_space_read_4(pa->pa_memt, romh, offs + 0);
186 1.1 skrll tmp = le32toh(tmp);
187 1.1 skrll if (tmp != 0x55aa0000) {
188 1.1 skrll sti_pci_disable_rom_internal(spc);
189 1.1 skrll if (offs == 0) {
190 1.1 skrll aprint_error_dev(sc->sc_dev,
191 1.1 skrll "invalid PCI ROM header signature (%08x)\n",
192 1.1 skrll tmp);
193 1.1 skrll rc = EINVAL;
194 1.1 skrll }
195 1.1 skrll break;
196 1.1 skrll }
197 1.1 skrll
198 1.1 skrll /*
199 1.1 skrll * Check ROM type.
200 1.1 skrll */
201 1.1 skrll tmp = bus_space_read_4(pa->pa_memt, romh, offs + 4);
202 1.1 skrll tmp = le32toh(tmp);
203 1.1 skrll if (tmp != 0x00000001) { /* 1 == STI ROM */
204 1.1 skrll sti_pci_disable_rom_internal(spc);
205 1.1 skrll if (offs == 0) {
206 1.1 skrll aprint_error_dev(sc->sc_dev,
207 1.1 skrll "invalid PCI ROM type (%08x)\n", tmp);
208 1.1 skrll rc = EINVAL;
209 1.1 skrll }
210 1.1 skrll break;
211 1.1 skrll }
212 1.1 skrll
213 1.1 skrll subsize = (bus_addr_t)bus_space_read_2(pa->pa_memt, romh,
214 1.1 skrll offs + 0x0c);
215 1.1 skrll subsize <<= 9;
216 1.1 skrll
217 1.1 skrll #ifdef STIDEBUG
218 1.1 skrll sti_pci_disable_rom_internal(spc);
219 1.1 skrll DPRINTF(("ROM offset %08x size %08x type %08x",
220 1.1 skrll (u_int)offs, (u_int)subsize, tmp));
221 1.1 skrll sti_pci_enable_rom_internal(spc);
222 1.1 skrll #endif
223 1.1 skrll
224 1.1 skrll /*
225 1.1 skrll * Check for a valid ROM data structure.
226 1.1 skrll * We do not need it except to know what architecture the ROM
227 1.1 skrll * code is for.
228 1.1 skrll */
229 1.1 skrll
230 1.1 skrll suboffs = offs +(bus_addr_t)bus_space_read_2(pa->pa_memt, romh,
231 1.1 skrll offs + 0x18);
232 1.1 skrll tmp = bus_space_read_4(pa->pa_memt, romh, suboffs + 0);
233 1.1 skrll tmp = le32toh(tmp);
234 1.1 skrll if (tmp != 0x50434952) { /* PCIR */
235 1.1 skrll sti_pci_disable_rom_internal(spc);
236 1.1 skrll if (offs == 0) {
237 1.1 skrll aprint_error_dev(sc->sc_dev, "invalid PCI data"
238 1.1 skrll " signature (%08x)\n", tmp);
239 1.1 skrll rc = EINVAL;
240 1.1 skrll } else {
241 1.1 skrll DPRINTF((" invalid PCI data signature %08x\n",
242 1.1 skrll tmp));
243 1.1 skrll continue;
244 1.1 skrll }
245 1.1 skrll }
246 1.1 skrll
247 1.1 skrll tmp = bus_space_read_1(pa->pa_memt, romh, suboffs + 0x14);
248 1.1 skrll sti_pci_disable_rom_internal(spc);
249 1.1 skrll DPRINTF((" code %02x", tmp));
250 1.1 skrll
251 1.1 skrll switch (tmp) {
252 1.1 skrll #ifdef __hppa__
253 1.1 skrll case 0x10:
254 1.1 skrll if (selected == (bus_addr_t)-1)
255 1.1 skrll selected = offs;
256 1.1 skrll break;
257 1.1 skrll #endif
258 1.1 skrll #ifdef __i386__
259 1.1 skrll case 0x00:
260 1.1 skrll if (selected == (bus_addr_t)-1)
261 1.1 skrll selected = offs;
262 1.1 skrll break;
263 1.1 skrll #endif
264 1.1 skrll default:
265 1.1 skrll #ifdef STIDEBUG
266 1.1 skrll DPRINTF((" (wrong architecture)"));
267 1.1 skrll #endif
268 1.1 skrll break;
269 1.1 skrll }
270 1.1 skrll DPRINTF(("%s\n", selected == offs ? " -> SELECTED" : ""));
271 1.1 skrll }
272 1.1 skrll
273 1.1 skrll if (selected == (bus_addr_t)-1) {
274 1.1 skrll if (rc == 0) {
275 1.1 skrll aprint_error_dev(sc->sc_dev, "found no ROM with "
276 1.1 skrll "correct microcode architecture\n");
277 1.1 skrll rc = ENOEXEC;
278 1.1 skrll }
279 1.1 skrll goto fail;
280 1.1 skrll }
281 1.1 skrll
282 1.1 skrll /*
283 1.1 skrll * Read the STI region BAR assignments.
284 1.1 skrll */
285 1.1 skrll
286 1.1 skrll sti_pci_enable_rom_internal(spc);
287 1.1 skrll offs = selected +
288 1.1 skrll (bus_addr_t)bus_space_read_2(pa->pa_memt, romh, selected + 0x0e);
289 1.1 skrll for (i = 0; i < STI_REGION_MAX; i++) {
290 1.1 skrll rc = sti_readbar(sc, pa, i,
291 1.1 skrll bus_space_read_1(pa->pa_memt, romh, offs + i));
292 1.1 skrll if (rc != 0)
293 1.1 skrll goto fail;
294 1.1 skrll }
295 1.1 skrll
296 1.1 skrll /*
297 1.1 skrll * Find out where the STI ROM itself lies, and its size.
298 1.1 skrll */
299 1.1 skrll
300 1.1 skrll offs = selected +
301 1.1 skrll (bus_addr_t)bus_space_read_4(pa->pa_memt, romh, selected + 0x08);
302 1.1 skrll stiromsize = (bus_addr_t)bus_space_read_4(pa->pa_memt, romh,
303 1.1 skrll offs + 0x18);
304 1.1 skrll stiromsize = le32toh(stiromsize);
305 1.1 skrll sti_pci_disable_rom_internal(spc);
306 1.1 skrll
307 1.1 skrll /*
308 1.1 skrll * Replace our mapping with a smaller mapping of only the area
309 1.1 skrll * we are interested in.
310 1.1 skrll */
311 1.1 skrll
312 1.1 skrll DPRINTF(("remapping rom @ %lx for %lx\n",
313 1.2 msaitoh (long)(PCI_MAPREG_ROM_ADDR(address) + offs), (long)stiromsize));
314 1.1 skrll bus_space_unmap(pa->pa_memt, romh, romsize);
315 1.2 msaitoh rc = bus_space_map(pa->pa_memt, PCI_MAPREG_ROM_ADDR(address) + offs,
316 1.1 skrll stiromsize, 0, &spc->sc_romh);
317 1.1 skrll if (rc != 0) {
318 1.1 skrll aprint_error_dev(sc->sc_dev, "can't map STI ROM (%d)\n",
319 1.1 skrll rc);
320 1.1 skrll goto fail2;
321 1.1 skrll }
322 1.1 skrll sti_pci_disable_rom_internal(spc);
323 1.1 skrll sc->sc_flags &= ~STI_ROM_ENABLED;
324 1.1 skrll
325 1.1 skrll return 0;
326 1.1 skrll
327 1.1 skrll fail:
328 1.1 skrll bus_space_unmap(pa->pa_memt, romh, romsize);
329 1.1 skrll fail2:
330 1.1 skrll sti_pci_disable_rom_internal(spc);
331 1.1 skrll
332 1.1 skrll return rc;
333 1.1 skrll }
334 1.1 skrll
335 1.1 skrll /*
336 1.1 skrll * Decode a BAR register.
337 1.1 skrll */
338 1.1 skrll int
339 1.1 skrll sti_readbar(struct sti_softc *sc, struct pci_attach_args *pa, u_int region,
340 1.1 skrll int bar)
341 1.1 skrll {
342 1.1 skrll bus_addr_t addr;
343 1.1 skrll bus_size_t size;
344 1.1 skrll uint32_t cf;
345 1.1 skrll int rc;
346 1.1 skrll
347 1.1 skrll if (bar == 0) {
348 1.1 skrll sc->bases[region] = 0;
349 1.1 skrll return (0);
350 1.1 skrll }
351 1.1 skrll
352 1.1 skrll #ifdef DIAGNOSTIC
353 1.1 skrll if (bar < PCI_MAPREG_START || bar > PCI_MAPREG_PPB_END) {
354 1.1 skrll sti_pci_disable_rom(sc);
355 1.1 skrll printf("%s: unexpected bar %02x for region %d\n",
356 1.1 skrll device_xname(sc->sc_dev), bar, region);
357 1.1 skrll sti_pci_enable_rom(sc);
358 1.1 skrll }
359 1.1 skrll #endif
360 1.1 skrll
361 1.1 skrll cf = pci_conf_read(pa->pa_pc, pa->pa_tag, bar);
362 1.1 skrll
363 1.1 skrll rc = pci_mapreg_info(pa->pa_pc, pa->pa_tag, bar, PCI_MAPREG_TYPE(cf),
364 1.1 skrll &addr, &size, NULL);
365 1.1 skrll
366 1.1 skrll if (rc != 0) {
367 1.1 skrll sti_pci_disable_rom(sc);
368 1.1 skrll aprint_error_dev(sc->sc_dev, "invalid bar %02x for region %d\n",
369 1.1 skrll bar, region);
370 1.1 skrll sti_pci_enable_rom(sc);
371 1.1 skrll return (rc);
372 1.1 skrll }
373 1.1 skrll
374 1.1 skrll sc->bases[region] = addr;
375 1.1 skrll return (0);
376 1.1 skrll }
377 1.1 skrll
378 1.1 skrll /*
379 1.1 skrll * Enable PCI ROM.
380 1.1 skrll */
381 1.1 skrll void
382 1.1 skrll sti_pci_enable_rom_internal(struct sti_pci_softc *spc)
383 1.1 skrll {
384 1.1 skrll pcireg_t address;
385 1.1 skrll
386 1.1 skrll KASSERT(spc != NULL);
387 1.1 skrll
388 1.1 skrll address = pci_conf_read(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM);
389 1.2 msaitoh address |= PCI_MAPREG_ROM_ENABLE;
390 1.1 skrll pci_conf_write(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM, address);
391 1.1 skrll }
392 1.1 skrll
393 1.1 skrll void
394 1.1 skrll sti_pci_enable_rom(struct sti_softc *sc)
395 1.1 skrll {
396 1.1 skrll struct sti_pci_softc *spc = device_private(sc->sc_dev);
397 1.1 skrll
398 1.1 skrll if (!ISSET(sc->sc_flags, STI_ROM_ENABLED)) {
399 1.1 skrll sti_pci_enable_rom_internal(spc);
400 1.1 skrll }
401 1.1 skrll SET(sc->sc_flags, STI_ROM_ENABLED);
402 1.1 skrll }
403 1.1 skrll
404 1.1 skrll /*
405 1.1 skrll * Disable PCI ROM.
406 1.1 skrll */
407 1.1 skrll void
408 1.1 skrll sti_pci_disable_rom_internal(struct sti_pci_softc *spc)
409 1.1 skrll {
410 1.1 skrll pcireg_t address;
411 1.1 skrll
412 1.1 skrll KASSERT(spc != NULL);
413 1.1 skrll
414 1.1 skrll address = pci_conf_read(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM);
415 1.2 msaitoh address &= ~PCI_MAPREG_ROM_ENABLE;
416 1.1 skrll pci_conf_write(spc->sc_pc, spc->sc_tag, PCI_MAPREG_ROM, address);
417 1.1 skrll }
418 1.1 skrll
419 1.1 skrll void
420 1.1 skrll sti_pci_disable_rom(struct sti_softc *sc)
421 1.1 skrll {
422 1.1 skrll struct sti_pci_softc *spc = device_private(sc->sc_dev);
423 1.1 skrll
424 1.1 skrll if (ISSET(sc->sc_flags, STI_ROM_ENABLED)) {
425 1.1 skrll sti_pci_disable_rom_internal(spc);
426 1.1 skrll }
427 1.1 skrll CLR(sc->sc_flags, STI_ROM_ENABLED);
428 1.1 skrll }
429