stpcide.c revision 1.17
1 /* $NetBSD: stpcide.c,v 1.17 2007/02/09 21:55:27 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Tohru Nishimura 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Tohru Nishimura. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: stpcide.c,v 1.17 2007/02/09 21:55:27 ad Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <dev/pci/pcivar.h> 39 #include <dev/pci/pcidevs.h> 40 #include <dev/pci/pciidereg.h> 41 #include <dev/pci/pciidevar.h> 42 43 static void stpc_chip_map(struct pciide_softc *, struct pci_attach_args *); 44 static void stpc_setup_channel(struct ata_channel *); 45 46 static int stpcide_match(struct device *, struct cfdata *, void *); 47 static void stpcide_attach(struct device *, struct device *, void *); 48 49 const struct pciide_product_desc pciide_stpc_products[] = { 50 { 0x0228, 51 0, 52 "STMicroelectronics STPC IDE Controller", 53 stpc_chip_map, 54 }, 55 { 0, 0, NULL, NULL }, 56 }; 57 58 CFATTACH_DECL(stpcide, sizeof(struct pciide_softc), 59 stpcide_match, stpcide_attach, NULL, NULL); 60 61 static int 62 stpcide_match(struct device *parent, struct cfdata *match, 63 void *aux) 64 { 65 struct pci_attach_args *pa = aux; 66 67 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SGSTHOMSON) { 68 if (pciide_lookup_product(pa->pa_id, pciide_stpc_products)) 69 return (2); 70 } 71 return (0); 72 } 73 74 static void 75 stpcide_attach(struct device *parent, struct device *self, void *aux) 76 { 77 struct pci_attach_args *pa = aux; 78 struct pciide_softc *sc = (struct pciide_softc *)self; 79 80 pciide_common_attach(sc, pa, 81 pciide_lookup_product(pa->pa_id, pciide_stpc_products)); 82 83 } 84 85 static void 86 stpc_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 87 { 88 struct pciide_channel *cp; 89 int channel; 90 pcireg_t interface = PCI_INTERFACE(pa->pa_class); 91 bus_size_t cmdsize, ctlsize; 92 93 if (pciide_chipen(sc, pa) == 0) 94 return; 95 96 aprint_verbose("%s: bus-master DMA support present", 97 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 98 pciide_mapreg_dma(sc, pa); 99 aprint_verbose("\n"); 100 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 101 if (sc->sc_dma_ok) { 102 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA; 103 sc->sc_wdcdev.irqack = pciide_irqack; 104 } 105 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 106 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 107 sc->sc_wdcdev.sc_atac.atac_udma_cap = 0; 108 sc->sc_wdcdev.sc_atac.atac_set_modes = stpc_setup_channel; 109 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 110 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS; 111 112 wdc_allocate_regs(&sc->sc_wdcdev); 113 114 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 115 channel++) { 116 cp = &sc->pciide_channels[channel]; 117 if (pciide_chansetup(sc, channel, interface) == 0) 118 continue; 119 pciide_mapchan(pa, cp, interface, &cmdsize, &ctlsize, 120 pciide_pci_intr); 121 } 122 } 123 124 /* 125 * IDE timing register (0x40, 0x42, 0x44, and 0x46) assignment. 126 * 33MHz PCI system will have; 127 * DMA0 01-11-11 128 * DMA1 00-01-10 129 * DMA2 00-00-10 130 * PIO0 111-100 131 * PIO1 100-011 132 * PIO2 011-010 133 * PIO3 010-001 134 * PIO4 000-001 135 * MISC XYZW 136 */ 137 static const u_int16_t dmatbl[] = { 0x7C00, 0x1800, 0x0800 }; 138 static const u_int16_t piotbl[] = { 0x03C0, 0x0230, 0x01A0, 0x0110, 0x0010 }; 139 140 static void 141 stpc_setup_channel(struct ata_channel *chp) 142 { 143 struct atac_softc *atac = chp->ch_atac; 144 struct pciide_channel *cp = CHAN_TO_PCHAN(chp); 145 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp); 146 int channel = chp->ch_channel; 147 struct ata_drive_datas *drvp; 148 u_int32_t idedma_ctl, idetim; 149 int drive, bits[2], s; 150 151 /* setup DMA if needed */ 152 pciide_channel_dma_setup(cp); 153 154 idedma_ctl = 0; 155 bits[0] = bits[1] = 0x7F60; /* assume PIO2/DMA0 */ 156 157 /* Per drive settings */ 158 for (drive = 0; drive < 2; drive++) { 159 drvp = &chp->ch_drive[drive]; 160 /* If no drive, skip */ 161 if ((drvp->drive_flags & DRIVE) == 0) 162 continue; 163 /* add timing values, setup DMA if needed */ 164 if ((atac->atac_cap & ATAC_CAP_DMA) && 165 (drvp->drive_flags & DRIVE_DMA)) { 166 /* use Multiword DMA */ 167 s = splbio(); 168 drvp->drive_flags &= ~DRIVE_UDMA; 169 splx(s); 170 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive); 171 bits[drive] = 0xe; /* IOCHRDY,wr/post,rd/prefetch */ 172 } 173 else { 174 /* PIO only */ 175 s = splbio(); 176 drvp->drive_flags &= ~(DRIVE_UDMA | DRIVE_DMA); 177 splx(s); 178 bits[drive] = 0x8; /* IOCHRDY */ 179 } 180 bits[drive] |= dmatbl[drvp->DMA_mode] | piotbl[drvp->PIO_mode]; 181 } 182 #if 0 183 idetim = pci_conf_read(sc->sc_pc, sc->sc_tag, 184 (channel == 0) ? 0x40 : 0x44); 185 aprint_normal("wdc%d: IDETIM %08x -> %08x\n", 186 channel, idetim, (bits[1] << 16) | bits[0]); 187 #endif 188 idetim = (bits[1] << 16) | bits[0]; 189 pci_conf_write(sc->sc_pc, sc->sc_tag, 190 (channel == 0) ? 0x40 : 0x44, idetim); 191 192 if (idedma_ctl != 0) { 193 /* Add software bits in status register */ 194 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0, 195 idedma_ctl); 196 } 197 } 198
Indexes created Fri Oct 03 02:09:57 GMT 2025