svwsata.c revision 1.16.2.1
1 /* $NetBSD: svwsata.c,v 1.16.2.1 2012/10/09 13:36:06 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Mark Kettenis 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.16.2.1 2012/10/09 13:36:06 bouyer Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 25 #include <dev/ata/atareg.h> 26 #include <dev/ata/satareg.h> 27 #include <dev/ata/satavar.h> 28 #include <dev/pci/pcivar.h> 29 #include <dev/pci/pcidevs.h> 30 #include <dev/pci/pciidereg.h> 31 #include <dev/pci/pciidevar.h> 32 #include <dev/pci/pciide_svwsata_reg.h> 33 34 static int svwsata_match(device_t, cfdata_t, void *); 35 static void svwsata_attach(device_t, device_t, void *); 36 37 static void svwsata_chip_map(struct pciide_softc *, 38 const struct pci_attach_args *); 39 static void svwsata_mapreg_dma(struct pciide_softc *, 40 const struct pci_attach_args *); 41 static void svwsata_mapchan(struct pciide_channel *); 42 43 CFATTACH_DECL_NEW(svwsata, sizeof(struct pciide_softc), 44 svwsata_match, svwsata_attach, NULL, NULL); 45 46 static const struct pciide_product_desc pciide_svwsata_products[] = { 47 { PCI_PRODUCT_SERVERWORKS_K2_SATA, 48 0, 49 "ServerWorks K2 SATA Controller", 50 svwsata_chip_map 51 }, 52 { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA, 53 0, 54 "ServerWorks Frodo4 SATA Controller", 55 svwsata_chip_map 56 }, 57 { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA, 58 0, 59 "ServerWorks Frodo8 SATA Controller", 60 svwsata_chip_map 61 }, 62 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_1, 63 0, 64 "ServerWorks HT-1000 SATA Controller", 65 svwsata_chip_map 66 }, 67 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_2, 68 0, 69 "ServerWorks HT-1000 SATA Controller", 70 svwsata_chip_map 71 }, 72 { 0, 73 0, 74 NULL, 75 NULL, 76 } 77 }; 78 79 static int 80 svwsata_match(device_t parent, cfdata_t match, void *aux) 81 { 82 struct pci_attach_args *pa = aux; 83 84 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 85 if (pciide_lookup_product(pa->pa_id, 86 pciide_svwsata_products)) 87 return (2); 88 } 89 return (0); 90 } 91 92 static void 93 svwsata_attach(device_t parent, device_t self, void *aux) 94 { 95 struct pci_attach_args *pa = aux; 96 struct pciide_softc *sc = device_private(self); 97 98 self->dv_maxphys = MIN(parent->dv_maxphys, MACHINE_MAXPHYS); 99 100 sc->sc_wdcdev.sc_atac.atac_dev = self; 101 102 pciide_common_attach(sc, pa, 103 pciide_lookup_product(pa->pa_id, pciide_svwsata_products)); 104 } 105 106 static void 107 svwsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 108 { 109 struct pciide_channel *cp; 110 pci_intr_handle_t intrhandle; 111 pcireg_t interface; 112 const char *intrstr; 113 int channel; 114 115 if (pciide_chipen(sc, pa) == 0) 116 return; 117 118 /* The 4-port version has a dummy second function. */ 119 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 120 PCI_MAPREG_START + 0x14) == 0) { 121 aprint_normal("\n"); 122 return; 123 } 124 125 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 126 PCI_MAPREG_TYPE_MEM | 127 PCI_MAPREG_MEM_TYPE_32BIT, 0, 128 &sc->sc_ba5_st, &sc->sc_ba5_sh, 129 NULL, &sc->sc_ba5_ss) != 0) { 130 aprint_error(": unable to map BA5 register space\n"); 131 return; 132 } 133 134 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 135 "bus-master DMA support present"); 136 svwsata_mapreg_dma(sc, pa); 137 aprint_verbose("\n"); 138 139 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 140 141 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 142 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 143 if (sc->sc_dma_ok) { 144 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 145 sc->sc_wdcdev.irqack = pciide_irqack; 146 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 147 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 148 } 149 150 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 151 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 152 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 153 154 /* We can use SControl and SStatus to probe for drives. */ 155 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 156 sc->sc_wdcdev.wdc_maxdrives = 1; 157 158 wdc_allocate_regs(&sc->sc_wdcdev); 159 160 /* Map and establish the interrupt handler. */ 161 if(pci_intr_map(pa, &intrhandle) != 0) { 162 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 163 "couldn't map native-PCI interrupt\n"); 164 return; 165 } 166 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 167 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 168 pciide_pci_intr, sc); 169 if (sc->sc_pci_ih != NULL) { 170 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 171 "using %s for native-PCI interrupt\n", 172 intrstr ? intrstr : "unknown interrupt"); 173 } else { 174 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 175 "couldn't establish native-PCI interrupt"); 176 if (intrstr != NULL) 177 aprint_error(" at %s", intrstr); 178 aprint_error("\n"); 179 return; 180 } 181 182 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 183 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 184 185 186 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 187 channel++) { 188 cp = &sc->pciide_channels[channel]; 189 190 if (pciide_chansetup(sc, channel, interface) == 0) 191 continue; 192 svwsata_mapchan(cp); 193 } 194 } 195 196 static void 197 svwsata_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 198 { 199 struct pciide_channel *pc; 200 int chan, reg; 201 bus_size_t size; 202 203 sc->sc_wdcdev.dma_arg = sc; 204 sc->sc_wdcdev.dma_init = pciide_dma_init; 205 sc->sc_wdcdev.dma_start = pciide_dma_start; 206 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 207 208 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 209 PCIIDE_OPTIONS_NODMA) { 210 aprint_normal( 211 ", but unused (forced off by config file)"); 212 sc->sc_dma_ok = 0; 213 return; 214 } 215 216 /* 217 * Slice off a subregion of BA5 for each of the channel's DMA 218 * registers. 219 */ 220 221 sc->sc_dma_iot = sc->sc_ba5_st; 222 for (chan = 0; chan < 4; chan++) { 223 pc = &sc->pciide_channels[chan]; 224 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 225 size = 4; 226 if (size > (IDEDMA_SCH_OFFSET - reg)) 227 size = IDEDMA_SCH_OFFSET - reg; 228 if (bus_space_subregion(sc->sc_ba5_st, 229 sc->sc_ba5_sh, 230 (chan << 8) + SVWSATA_DMA + reg, 231 size, &pc->dma_iohs[reg]) != 0) { 232 sc->sc_dma_ok = 0; 233 aprint_normal(", but can't subregion offset " 234 "%lu size %lu", 235 (u_long) (chan << 8) + SVWSATA_DMA + reg, 236 (u_long) size); 237 return; 238 } 239 } 240 } 241 242 /* DMA registers all set up! */ 243 sc->sc_dmat = pa->pa_dmat; 244 sc->sc_dma_ok = 1; 245 } 246 247 static void 248 svwsata_mapchan(struct pciide_channel *cp) 249 { 250 struct ata_channel *wdc_cp = &cp->ata_channel; 251 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 252 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 253 int i; 254 255 cp->compat = 0; 256 cp->ih = sc->sc_pci_ih; 257 258 wdr->cmd_iot = sc->sc_ba5_st; 259 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 260 (wdc_cp->ch_channel << 8) + SVWSATA_TF0, 261 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) { 262 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 263 "couldn't map %s cmd regs\n", cp->name); 264 goto bad; 265 } 266 267 wdr->ctl_iot = sc->sc_ba5_st; 268 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 269 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4, 270 &cp->ctl_baseioh) != 0) { 271 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 272 "couldn't map %s ctl regs\n", cp->name); 273 goto bad; 274 } 275 wdr->ctl_ioh = cp->ctl_baseioh; 276 277 for (i = 0; i < WDC_NREG; i++) { 278 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 279 i << 2, i == 0 ? 4 : 1, 280 &wdr->cmd_iohs[i]) != 0) { 281 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 282 "couldn't subregion %s channel cmd regs\n", 283 cp->name); 284 goto bad; 285 } 286 } 287 wdc_init_shadow_regs(wdc_cp); 288 wdr->data32iot = wdr->cmd_iot; 289 wdr->data32ioh = wdr->cmd_iohs[0]; 290 291 292 wdr->sata_iot = sc->sc_ba5_st; 293 wdr->sata_baseioh = sc->sc_ba5_sh; 294 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 295 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1, 296 &wdr->sata_status) != 0) { 297 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 298 "couldn't map channel %d sata_status regs\n", 299 wdc_cp->ch_channel); 300 goto bad; 301 } 302 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 303 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1, 304 &wdr->sata_error) != 0) { 305 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 306 "couldn't map channel %d sata_error regs\n", 307 wdc_cp->ch_channel); 308 goto bad; 309 } 310 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 311 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1, 312 &wdr->sata_control) != 0) { 313 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 314 "couldn't map channel %d sata_control regs\n", 315 wdc_cp->ch_channel); 316 goto bad; 317 } 318 319 wdcattach(wdc_cp); 320 return; 321 322 bad: 323 cp->ata_channel.ch_flags |= ATACH_DISABLED; 324 } 325
Indexes created Sun Oct 12 09:09:55 GMT 2025