svwsata.c revision 1.22
1 /* $NetBSD: svwsata.c,v 1.22 2018/06/01 18:14:33 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Mark Kettenis 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.22 2018/06/01 18:14:33 macallan Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 25 #include <dev/ata/atareg.h> 26 #include <dev/ata/satareg.h> 27 #include <dev/ata/satavar.h> 28 #include <dev/pci/pcivar.h> 29 #include <dev/pci/pcidevs.h> 30 #include <dev/pci/pciidereg.h> 31 #include <dev/pci/pciidevar.h> 32 #include <dev/pci/pciide_svwsata_reg.h> 33 34 static int svwsata_match(device_t, cfdata_t, void *); 35 static void svwsata_attach(device_t, device_t, void *); 36 37 static void svwsata_chip_map(struct pciide_softc *, 38 const struct pci_attach_args *); 39 static void svwsata_mapreg_dma(struct pciide_softc *, 40 const struct pci_attach_args *); 41 static void svwsata_mapchan(struct pciide_channel *); 42 int svwsata_intr(void *); 43 44 CFATTACH_DECL_NEW(svwsata, sizeof(struct pciide_softc), 45 svwsata_match, svwsata_attach, pciide_detach, NULL); 46 47 static const struct pciide_product_desc pciide_svwsata_products[] = { 48 { PCI_PRODUCT_SERVERWORKS_K2_SATA, 49 0, 50 "ServerWorks K2 SATA Controller", 51 svwsata_chip_map 52 }, 53 { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA, 54 0, 55 "ServerWorks Frodo4 SATA Controller", 56 svwsata_chip_map 57 }, 58 { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA, 59 0, 60 "ServerWorks Frodo8 SATA Controller", 61 svwsata_chip_map 62 }, 63 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_1, 64 0, 65 "ServerWorks HT-1000 SATA Controller", 66 svwsata_chip_map 67 }, 68 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA_2, 69 0, 70 "ServerWorks HT-1000 SATA Controller", 71 svwsata_chip_map 72 }, 73 { 0, 74 0, 75 NULL, 76 NULL, 77 } 78 }; 79 80 static int 81 svwsata_match(device_t parent, cfdata_t match, void *aux) 82 { 83 struct pci_attach_args *pa = aux; 84 85 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 86 if (pciide_lookup_product(pa->pa_id, 87 pciide_svwsata_products)) 88 return (2); 89 } 90 return (0); 91 } 92 93 static void 94 svwsata_attach(device_t parent, device_t self, void *aux) 95 { 96 struct pci_attach_args *pa = aux; 97 struct pciide_softc *sc = device_private(self); 98 99 sc->sc_wdcdev.sc_atac.atac_dev = self; 100 101 pciide_common_attach(sc, pa, 102 pciide_lookup_product(pa->pa_id, pciide_svwsata_products)); 103 } 104 105 static void 106 svwsata_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa) 107 { 108 struct pciide_channel *cp; 109 pci_intr_handle_t intrhandle; 110 pcireg_t interface; 111 const char *intrstr; 112 int channel; 113 char intrbuf[PCI_INTRSTR_LEN]; 114 115 /* The 4-port version has a dummy second function. */ 116 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 117 PCI_MAPREG_START + 0x14) == 0) { 118 aprint_normal("\n"); 119 return; 120 } 121 122 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 123 PCI_MAPREG_TYPE_MEM | 124 PCI_MAPREG_MEM_TYPE_32BIT, 0, 125 &sc->sc_ba5_st, &sc->sc_ba5_sh, 126 NULL, &sc->sc_ba5_ss) != 0) { 127 aprint_error(": unable to map BA5 register space\n"); 128 return; 129 } 130 131 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev, 132 "bus-master DMA support present"); 133 svwsata_mapreg_dma(sc, pa); 134 aprint_verbose("\n"); 135 136 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS; 137 138 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 139 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 140 if (sc->sc_dma_ok) { 141 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 142 sc->sc_wdcdev.irqack = pciide_irqack; 143 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 144 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 145 } 146 147 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 148 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 149 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 150 151 /* We can use SControl and SStatus to probe for drives. */ 152 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 153 sc->sc_wdcdev.wdc_maxdrives = 1; 154 155 wdc_allocate_regs(&sc->sc_wdcdev); 156 157 /* Map and establish the interrupt handler. */ 158 if(pci_intr_map(pa, &intrhandle) != 0) { 159 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 160 "couldn't map native-PCI interrupt\n"); 161 return; 162 } 163 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf)); 164 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 165 svwsata_intr, sc); 166 if (sc->sc_pci_ih != NULL) { 167 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev, 168 "using %s for native-PCI interrupt\n", 169 intrstr ? intrstr : "unknown interrupt"); 170 } else { 171 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 172 "couldn't establish native-PCI interrupt"); 173 if (intrstr != NULL) 174 aprint_error(" at %s", intrstr); 175 aprint_error("\n"); 176 return; 177 } 178 179 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 180 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 181 182 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 183 channel++) { 184 cp = &sc->pciide_channels[channel]; 185 186 if (pciide_chansetup(sc, channel, interface) == 0) 187 continue; 188 svwsata_mapchan(cp); 189 } 190 } 191 192 static void 193 svwsata_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa) 194 { 195 struct pciide_channel *pc; 196 int chan, reg; 197 bus_size_t size; 198 199 sc->sc_wdcdev.dma_arg = sc; 200 sc->sc_wdcdev.dma_init = pciide_dma_init; 201 sc->sc_wdcdev.dma_start = pciide_dma_start; 202 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 203 204 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 205 PCIIDE_OPTIONS_NODMA) { 206 aprint_normal( 207 ", but unused (forced off by config file)"); 208 sc->sc_dma_ok = 0; 209 return; 210 } 211 212 /* 213 * Slice off a subregion of BA5 for each of the channel's DMA 214 * registers. 215 */ 216 217 sc->sc_dma_iot = sc->sc_ba5_st; 218 for (chan = 0; chan < 4; chan++) { 219 pc = &sc->pciide_channels[chan]; 220 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 221 size = 4; 222 if (size > (IDEDMA_SCH_OFFSET - reg)) 223 size = IDEDMA_SCH_OFFSET - reg; 224 if (bus_space_subregion(sc->sc_ba5_st, 225 sc->sc_ba5_sh, 226 (chan << 8) + SVWSATA_DMA + reg, 227 size, &pc->dma_iohs[reg]) != 0) { 228 sc->sc_dma_ok = 0; 229 aprint_normal(", but can't subregion offset " 230 "%lu size %lu", 231 (u_long) (chan << 8) + SVWSATA_DMA + reg, 232 (u_long) size); 233 return; 234 } 235 } 236 } 237 238 /* DMA registers all set up! */ 239 sc->sc_dmat = pa->pa_dmat; 240 sc->sc_dma_ok = 1; 241 } 242 243 static void 244 svwsata_mapchan(struct pciide_channel *cp) 245 { 246 struct ata_channel *wdc_cp = &cp->ata_channel; 247 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 248 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 249 int i; 250 251 cp->compat = 0; 252 cp->ih = sc->sc_pci_ih; 253 254 wdr->cmd_iot = sc->sc_ba5_st; 255 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 256 (wdc_cp->ch_channel << 8) + SVWSATA_TF0, 257 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) { 258 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 259 "couldn't map %s cmd regs\n", cp->name); 260 goto bad; 261 } 262 263 wdr->ctl_iot = sc->sc_ba5_st; 264 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 265 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4, 266 &cp->ctl_baseioh) != 0) { 267 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 268 "couldn't map %s ctl regs\n", cp->name); 269 goto bad; 270 } 271 wdr->ctl_ioh = cp->ctl_baseioh; 272 273 for (i = 0; i < WDC_NREG; i++) { 274 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 275 i << 2, i == 0 ? 4 : 1, 276 &wdr->cmd_iohs[i]) != 0) { 277 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 278 "couldn't subregion %s channel cmd regs\n", 279 cp->name); 280 goto bad; 281 } 282 } 283 wdc_init_shadow_regs(wdr); 284 wdr->data32iot = wdr->cmd_iot; 285 wdr->data32ioh = wdr->cmd_iohs[0]; 286 287 288 wdr->sata_iot = sc->sc_ba5_st; 289 wdr->sata_baseioh = sc->sc_ba5_sh; 290 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 291 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1, 292 &wdr->sata_status) != 0) { 293 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 294 "couldn't map channel %d sata_status regs\n", 295 wdc_cp->ch_channel); 296 goto bad; 297 } 298 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 299 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1, 300 &wdr->sata_error) != 0) { 301 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 302 "couldn't map channel %d sata_error regs\n", 303 wdc_cp->ch_channel); 304 goto bad; 305 } 306 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 307 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1, 308 &wdr->sata_control) != 0) { 309 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev, 310 "couldn't map channel %d sata_control regs\n", 311 wdc_cp->ch_channel); 312 goto bad; 313 } 314 315 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 316 (wdc_cp->ch_channel << 8) + SVWSATA_SICR1, 317 bus_space_read_4(sc->sc_ba5_st, sc->sc_ba5_sh, 318 (wdc_cp->ch_channel << 8) + SVWSATA_SICR1) 319 & ~0x00040000); 320 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 321 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 0xffffffff); 322 bus_space_write_4(sc->sc_ba5_st, sc->sc_ba5_sh, 323 (wdc_cp->ch_channel << 8) + SVWSATA_SIM, 0); 324 325 cp->ata_channel.ch_flags |= ATACH_DMA_BEFORE_CMD; 326 327 wdcattach(wdc_cp); 328 return; 329 330 bad: 331 cp->ata_channel.ch_flags |= ATACH_DISABLED; 332 } 333 334 int 335 svwsata_intr(void *arg) 336 { 337 struct pciide_softc *sc = arg; 338 struct pciide_channel *cp; 339 struct ata_channel *wdc_cp; 340 struct wdc_regs *wdr; 341 int i, rv, crv; 342 uint8_t dmastat; 343 344 rv = 0; 345 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) { 346 volatile uint32_t status; 347 cp = &sc->pciide_channels[i]; 348 wdc_cp = &cp->ata_channel; 349 wdr = CHAN_TO_WDC_REGS(wdc_cp); 350 351 /* 352 * from FreeBSD's ata-serverworks.c: 353 * We need to do a 4-byte read on the status reg before the 354 * values will report correctly 355 */ 356 bus_space_read_4(wdr->cmd_iot, 357 wdr->cmd_iohs[wd_status], 0); 358 __USE(status); 359 360 dmastat = bus_space_read_1(sc->sc_dma_iot, 361 cp->dma_iohs[IDEDMA_CTL], 0); 362 363 /* If a compat channel skip. */ 364 if (cp->compat) 365 continue; 366 367 /* if this channel not waiting for intr, skip */ 368 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0) { 369 continue; 370 } 371 crv = wdcintr(wdc_cp); 372 if ((crv == 0)) { 373 bus_space_write_1(sc->sc_dma_iot, 374 cp->dma_iohs[IDEDMA_CTL], 0, dmastat); 375 } 376 else if (crv == 1) 377 rv = 1; /* claim the intr */ 378 else if (rv == 0) /* crv should be -1 in this case */ 379 rv = crv; /* if we've done no better, take it */ 380 } 381 return (rv); 382 } 383
Indexes created Fri Sep 26 20:09:58 GMT 2025