svwsata.c revision 1.5
1 /* $NetBSD: svwsata.c,v 1.5 2006/10/25 17:34:49 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2005 Mark Kettenis 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #include <sys/cdefs.h> 20 __KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.5 2006/10/25 17:34:49 bouyer Exp $"); 21 22 #include <sys/param.h> 23 #include <sys/systm.h> 24 25 #include <dev/ata/atareg.h> 26 #include <dev/ata/satareg.h> 27 #include <dev/ata/satavar.h> 28 #include <dev/pci/pcivar.h> 29 #include <dev/pci/pcidevs.h> 30 #include <dev/pci/pciidereg.h> 31 #include <dev/pci/pciidevar.h> 32 #include <dev/pci/pciide_svwsata_reg.h> 33 34 static int svwsata_match(struct device *, struct cfdata *, void *); 35 static void svwsata_attach(struct device *, struct device *, void *); 36 37 static void svwsata_chip_map(struct pciide_softc *, struct pci_attach_args *) __unused; 38 static void svwsata_mapreg_dma(struct pciide_softc *, struct pci_attach_args *); 39 static void svwsata_mapchan(struct pciide_channel *); 40 41 CFATTACH_DECL(svwsata, sizeof(struct pciide_softc), 42 svwsata_match, svwsata_attach, NULL, NULL); 43 44 static const struct pciide_product_desc pciide_svwsata_products[] = { 45 { PCI_PRODUCT_SERVERWORKS_K2_SATA, 46 0, 47 "ServerWorks K2 SATA Controller", 48 svwsata_chip_map 49 }, 50 { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA, 51 0, 52 "ServerWorks Frodo4 SATA Controller", 53 svwsata_chip_map 54 }, 55 { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA, 56 0, 57 "ServerWorks Frodo8 SATA Controller", 58 svwsata_chip_map 59 }, 60 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA, 61 0, 62 "ServerWorks HT-1000 SATA Controller", 63 svwsata_chip_map 64 }, 65 { 0, 66 0, 67 NULL, 68 NULL, 69 } 70 }; 71 72 static int 73 svwsata_match(struct device *parent __unused, struct cfdata *match __unused, 74 void *aux) 75 { 76 struct pci_attach_args *pa = aux; 77 78 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) { 79 if (pciide_lookup_product(pa->pa_id, 80 pciide_svwsata_products)) 81 return (2); 82 } 83 return (0); 84 } 85 86 static void 87 svwsata_attach(struct device *parent __unused, struct device *self, void *aux) 88 { 89 struct pci_attach_args *pa = aux; 90 struct pciide_softc *sc = (void *)self; 91 92 pciide_common_attach(sc, pa, 93 pciide_lookup_product(pa->pa_id, pciide_svwsata_products)); 94 } 95 96 static void 97 svwsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa) 98 { 99 struct pciide_channel *cp; 100 pci_intr_handle_t intrhandle; 101 pcireg_t interface; 102 const char *intrstr; 103 int channel; 104 105 if (pciide_chipen(sc, pa) == 0) 106 return; 107 108 /* The 4-port version has a dummy second function. */ 109 if (pci_conf_read(sc->sc_pc, sc->sc_tag, 110 PCI_MAPREG_START + 0x14) == 0) { 111 aprint_normal("\n"); 112 return; 113 } 114 115 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14, 116 PCI_MAPREG_TYPE_MEM | 117 PCI_MAPREG_MEM_TYPE_32BIT, 0, 118 &sc->sc_ba5_st, &sc->sc_ba5_sh, 119 NULL, NULL) != 0) { 120 aprint_error(": unable to map BA5 register space\n"); 121 return; 122 } 123 124 aprint_normal(": DMA"); 125 svwsata_mapreg_dma(sc, pa); 126 aprint_normal("\n"); 127 128 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32; 129 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4; 130 if (sc->sc_dma_ok) { 131 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA; 132 sc->sc_wdcdev.irqack = pciide_irqack; 133 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2; 134 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6; 135 } 136 137 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray; 138 sc->sc_wdcdev.sc_atac.atac_nchannels = 4; 139 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel; 140 141 /* We can use SControl and SStatus to probe for drives. */ 142 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe; 143 144 wdc_allocate_regs(&sc->sc_wdcdev); 145 146 /* Map and establish the interrupt handler. */ 147 if(pci_intr_map(pa, &intrhandle) != 0) { 148 aprint_error("%s: couldn't map native-PCI interrupt\n", 149 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 150 return; 151 } 152 intrstr = pci_intr_string(pa->pa_pc, intrhandle); 153 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO, 154 pciide_pci_intr, sc); 155 if (sc->sc_pci_ih != NULL) { 156 aprint_normal("%s: using %s for native-PCI interrupt\n", 157 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 158 intrstr ? intrstr : "unknown interrupt"); 159 } else { 160 aprint_error("%s: couldn't establish native-PCI interrupt", 161 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname); 162 if (intrstr != NULL) 163 aprint_normal(" at %s", intrstr); 164 aprint_normal("\n"); 165 return; 166 } 167 168 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA | 169 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1); 170 171 172 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels; 173 channel++) { 174 cp = &sc->pciide_channels[channel]; 175 176 if (pciide_chansetup(sc, channel, interface) == 0) 177 continue; 178 svwsata_mapchan(cp); 179 } 180 } 181 182 static void 183 svwsata_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa) 184 { 185 struct pciide_channel *pc; 186 int chan, reg; 187 bus_size_t size; 188 189 sc->sc_wdcdev.dma_arg = sc; 190 sc->sc_wdcdev.dma_init = pciide_dma_init; 191 sc->sc_wdcdev.dma_start = pciide_dma_start; 192 sc->sc_wdcdev.dma_finish = pciide_dma_finish; 193 194 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags & 195 PCIIDE_OPTIONS_NODMA) { 196 aprint_normal( 197 ", but unused (forced off by config file)"); 198 sc->sc_dma_ok = 0; 199 return; 200 } 201 202 /* 203 * Slice off a subregion of BA5 for each of the channel's DMA 204 * registers. 205 */ 206 207 sc->sc_dma_iot = sc->sc_ba5_st; 208 for (chan = 0; chan < 4; chan++) { 209 pc = &sc->pciide_channels[chan]; 210 for (reg = 0; reg < IDEDMA_NREGS; reg++) { 211 size = 4; 212 if (size > (IDEDMA_SCH_OFFSET - reg)) 213 size = IDEDMA_SCH_OFFSET - reg; 214 if (bus_space_subregion(sc->sc_ba5_st, 215 sc->sc_ba5_sh, 216 (chan << 8) + SVWSATA_DMA + reg, 217 size, &pc->dma_iohs[reg]) != 0) { 218 sc->sc_dma_ok = 0; 219 aprint_normal(", but can't subregion offset " 220 "%lu size %lu", 221 (u_long) (chan << 8) + SVWSATA_DMA + reg, 222 (u_long) size); 223 return; 224 } 225 } 226 } 227 228 /* DMA registers all set up! */ 229 sc->sc_dmat = pa->pa_dmat; 230 sc->sc_dma_ok = 1; 231 } 232 233 static void 234 svwsata_mapchan(struct pciide_channel *cp) 235 { 236 struct ata_channel *wdc_cp = &cp->ata_channel; 237 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp); 238 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp); 239 int i; 240 241 cp->compat = 0; 242 cp->ih = sc->sc_pci_ih; 243 244 wdr->cmd_iot = sc->sc_ba5_st; 245 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 246 (wdc_cp->ch_channel << 8) + SVWSATA_TF0, 247 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) { 248 aprint_error("%s: couldn't map %s cmd regs\n", 249 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 250 goto bad; 251 } 252 253 wdr->ctl_iot = sc->sc_ba5_st; 254 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh, 255 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4, 256 &cp->ctl_baseioh) != 0) { 257 aprint_error("%s: couldn't map %s ctl regs\n", 258 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 259 goto bad; 260 } 261 wdr->ctl_ioh = cp->ctl_baseioh; 262 263 for (i = 0; i < WDC_NREG; i++) { 264 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, 265 i << 2, i == 0 ? 4 : 1, 266 &wdr->cmd_iohs[i]) != 0) { 267 aprint_error("%s: couldn't subregion %s channel " 268 "cmd regs\n", 269 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name); 270 goto bad; 271 } 272 } 273 wdc_init_shadow_regs(wdc_cp); 274 wdr->data32iot = wdr->cmd_iot; 275 wdr->data32ioh = wdr->cmd_iohs[0]; 276 277 278 wdr->sata_iot = sc->sc_ba5_st; 279 wdr->sata_baseioh = sc->sc_ba5_sh; 280 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 281 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1, 282 &wdr->sata_status) != 0) { 283 aprint_error("%s: couldn't map channel %d " 284 "sata_status regs\n", 285 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 286 wdc_cp->ch_channel); 287 goto bad; 288 } 289 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 290 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1, 291 &wdr->sata_error) != 0) { 292 aprint_error("%s: couldn't map channel %d " 293 "sata_error regs\n", 294 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 295 wdc_cp->ch_channel); 296 goto bad; 297 } 298 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh, 299 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1, 300 &wdr->sata_control) != 0) { 301 aprint_error("%s: couldn't map channel %d " 302 "sata_control regs\n", 303 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, 304 wdc_cp->ch_channel); 305 goto bad; 306 } 307 308 wdcattach(wdc_cp); 309 return; 310 311 bad: 312 cp->ata_channel.ch_flags |= ATACH_DISABLED; 313 } 314
Indexes created Fri Sep 26 20:09:58 GMT 2025