svwsata.c revision 1.7 1 /* $NetBSD: svwsata.c,v 1.7 2006/11/30 19:32:37 hannken Exp $ */
2
3 /*
4 * Copyright (c) 2005 Mark Kettenis
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19 #include <sys/cdefs.h>
20 __KERNEL_RCSID(0, "$NetBSD: svwsata.c,v 1.7 2006/11/30 19:32:37 hannken Exp $");
21
22 #include <sys/param.h>
23 #include <sys/systm.h>
24
25 #include <dev/ata/atareg.h>
26 #include <dev/ata/satareg.h>
27 #include <dev/ata/satavar.h>
28 #include <dev/pci/pcivar.h>
29 #include <dev/pci/pcidevs.h>
30 #include <dev/pci/pciidereg.h>
31 #include <dev/pci/pciidevar.h>
32 #include <dev/pci/pciide_svwsata_reg.h>
33
34 static int svwsata_match(struct device *, struct cfdata *, void *);
35 static void svwsata_attach(struct device *, struct device *, void *);
36
37 static void svwsata_chip_map(struct pciide_softc *, struct pci_attach_args *);
38 static void svwsata_mapreg_dma(struct pciide_softc *, struct pci_attach_args *);
39 static void svwsata_mapchan(struct pciide_channel *);
40
41 CFATTACH_DECL(svwsata, sizeof(struct pciide_softc),
42 svwsata_match, svwsata_attach, NULL, NULL);
43
44 static const struct pciide_product_desc pciide_svwsata_products[] = {
45 { PCI_PRODUCT_SERVERWORKS_K2_SATA,
46 0,
47 "ServerWorks K2 SATA Controller",
48 svwsata_chip_map
49 },
50 { PCI_PRODUCT_SERVERWORKS_FRODO4_SATA,
51 0,
52 "ServerWorks Frodo4 SATA Controller",
53 svwsata_chip_map
54 },
55 { PCI_PRODUCT_SERVERWORKS_FRODO8_SATA,
56 0,
57 "ServerWorks Frodo8 SATA Controller",
58 svwsata_chip_map
59 },
60 { PCI_PRODUCT_SERVERWORKS_HT1000_SATA,
61 0,
62 "ServerWorks HT-1000 SATA Controller",
63 svwsata_chip_map
64 },
65 { 0,
66 0,
67 NULL,
68 NULL,
69 }
70 };
71
72 static int
73 svwsata_match(struct device *parent, struct cfdata *match,
74 void *aux)
75 {
76 struct pci_attach_args *pa = aux;
77
78 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_SERVERWORKS) {
79 if (pciide_lookup_product(pa->pa_id,
80 pciide_svwsata_products))
81 return (2);
82 }
83 return (0);
84 }
85
86 static void
87 svwsata_attach(struct device *parent, struct device *self, void *aux)
88 {
89 struct pci_attach_args *pa = aux;
90 struct pciide_softc *sc = (void *)self;
91
92 pciide_common_attach(sc, pa,
93 pciide_lookup_product(pa->pa_id, pciide_svwsata_products));
94 }
95
96 static void
97 svwsata_chip_map(struct pciide_softc *sc, struct pci_attach_args *pa)
98 {
99 struct pciide_channel *cp;
100 pci_intr_handle_t intrhandle;
101 pcireg_t interface;
102 const char *intrstr;
103 int channel;
104
105 if (pciide_chipen(sc, pa) == 0)
106 return;
107
108 /* The 4-port version has a dummy second function. */
109 if (pci_conf_read(sc->sc_pc, sc->sc_tag,
110 PCI_MAPREG_START + 0x14) == 0) {
111 aprint_normal("\n");
112 return;
113 }
114
115 if (pci_mapreg_map(pa, PCI_MAPREG_START + 0x14,
116 PCI_MAPREG_TYPE_MEM |
117 PCI_MAPREG_MEM_TYPE_32BIT, 0,
118 &sc->sc_ba5_st, &sc->sc_ba5_sh,
119 NULL, NULL) != 0) {
120 aprint_error(": unable to map BA5 register space\n");
121 return;
122 }
123
124 aprint_normal(": DMA");
125 svwsata_mapreg_dma(sc, pa);
126 aprint_normal("\n");
127
128 sc->sc_wdcdev.cap = WDC_CAPABILITY_WIDEREGS;
129
130 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16 | ATAC_CAP_DATA32;
131 sc->sc_wdcdev.sc_atac.atac_pio_cap = 4;
132 if (sc->sc_dma_ok) {
133 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA | ATAC_CAP_UDMA;
134 sc->sc_wdcdev.irqack = pciide_irqack;
135 sc->sc_wdcdev.sc_atac.atac_dma_cap = 2;
136 sc->sc_wdcdev.sc_atac.atac_udma_cap = 6;
137 }
138
139 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
140 sc->sc_wdcdev.sc_atac.atac_nchannels = 4;
141 sc->sc_wdcdev.sc_atac.atac_set_modes = sata_setup_channel;
142
143 /* We can use SControl and SStatus to probe for drives. */
144 sc->sc_wdcdev.sc_atac.atac_probe = wdc_sataprobe;
145
146 wdc_allocate_regs(&sc->sc_wdcdev);
147
148 /* Map and establish the interrupt handler. */
149 if(pci_intr_map(pa, &intrhandle) != 0) {
150 aprint_error("%s: couldn't map native-PCI interrupt\n",
151 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
152 return;
153 }
154 intrstr = pci_intr_string(pa->pa_pc, intrhandle);
155 sc->sc_pci_ih = pci_intr_establish(pa->pa_pc, intrhandle, IPL_BIO,
156 pciide_pci_intr, sc);
157 if (sc->sc_pci_ih != NULL) {
158 aprint_normal("%s: using %s for native-PCI interrupt\n",
159 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
160 intrstr ? intrstr : "unknown interrupt");
161 } else {
162 aprint_error("%s: couldn't establish native-PCI interrupt",
163 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname);
164 if (intrstr != NULL)
165 aprint_normal(" at %s", intrstr);
166 aprint_normal("\n");
167 return;
168 }
169
170 interface = PCIIDE_INTERFACE_BUS_MASTER_DMA |
171 PCIIDE_INTERFACE_PCI(0) | PCIIDE_INTERFACE_PCI(1);
172
173
174 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
175 channel++) {
176 cp = &sc->pciide_channels[channel];
177
178 if (pciide_chansetup(sc, channel, interface) == 0)
179 continue;
180 svwsata_mapchan(cp);
181 }
182 }
183
184 static void
185 svwsata_mapreg_dma(struct pciide_softc *sc, struct pci_attach_args *pa)
186 {
187 struct pciide_channel *pc;
188 int chan, reg;
189 bus_size_t size;
190
191 sc->sc_wdcdev.dma_arg = sc;
192 sc->sc_wdcdev.dma_init = pciide_dma_init;
193 sc->sc_wdcdev.dma_start = pciide_dma_start;
194 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
195
196 if (device_cfdata(&sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
197 PCIIDE_OPTIONS_NODMA) {
198 aprint_normal(
199 ", but unused (forced off by config file)");
200 sc->sc_dma_ok = 0;
201 return;
202 }
203
204 /*
205 * Slice off a subregion of BA5 for each of the channel's DMA
206 * registers.
207 */
208
209 sc->sc_dma_iot = sc->sc_ba5_st;
210 for (chan = 0; chan < 4; chan++) {
211 pc = &sc->pciide_channels[chan];
212 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
213 size = 4;
214 if (size > (IDEDMA_SCH_OFFSET - reg))
215 size = IDEDMA_SCH_OFFSET - reg;
216 if (bus_space_subregion(sc->sc_ba5_st,
217 sc->sc_ba5_sh,
218 (chan << 8) + SVWSATA_DMA + reg,
219 size, &pc->dma_iohs[reg]) != 0) {
220 sc->sc_dma_ok = 0;
221 aprint_normal(", but can't subregion offset "
222 "%lu size %lu",
223 (u_long) (chan << 8) + SVWSATA_DMA + reg,
224 (u_long) size);
225 return;
226 }
227 }
228 }
229
230 /* DMA registers all set up! */
231 sc->sc_dmat = pa->pa_dmat;
232 sc->sc_dma_ok = 1;
233 }
234
235 static void
236 svwsata_mapchan(struct pciide_channel *cp)
237 {
238 struct ata_channel *wdc_cp = &cp->ata_channel;
239 struct pciide_softc *sc = CHAN_TO_PCIIDE(wdc_cp);
240 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
241 int i;
242
243 cp->compat = 0;
244 cp->ih = sc->sc_pci_ih;
245
246 wdr->cmd_iot = sc->sc_ba5_st;
247 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
248 (wdc_cp->ch_channel << 8) + SVWSATA_TF0,
249 SVWSATA_TF8 - SVWSATA_TF0, &wdr->cmd_baseioh) != 0) {
250 aprint_error("%s: couldn't map %s cmd regs\n",
251 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
252 goto bad;
253 }
254
255 wdr->ctl_iot = sc->sc_ba5_st;
256 if (bus_space_subregion(sc->sc_ba5_st, sc->sc_ba5_sh,
257 (wdc_cp->ch_channel << 8) + SVWSATA_TF8, 4,
258 &cp->ctl_baseioh) != 0) {
259 aprint_error("%s: couldn't map %s ctl regs\n",
260 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
261 goto bad;
262 }
263 wdr->ctl_ioh = cp->ctl_baseioh;
264
265 for (i = 0; i < WDC_NREG; i++) {
266 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh,
267 i << 2, i == 0 ? 4 : 1,
268 &wdr->cmd_iohs[i]) != 0) {
269 aprint_error("%s: couldn't subregion %s channel "
270 "cmd regs\n",
271 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname, cp->name);
272 goto bad;
273 }
274 }
275 wdc_init_shadow_regs(wdc_cp);
276 wdr->data32iot = wdr->cmd_iot;
277 wdr->data32ioh = wdr->cmd_iohs[0];
278
279
280 wdr->sata_iot = sc->sc_ba5_st;
281 wdr->sata_baseioh = sc->sc_ba5_sh;
282 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
283 (wdc_cp->ch_channel << 8) + SVWSATA_SSTATUS, 1,
284 &wdr->sata_status) != 0) {
285 aprint_error("%s: couldn't map channel %d "
286 "sata_status regs\n",
287 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
288 wdc_cp->ch_channel);
289 goto bad;
290 }
291 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
292 (wdc_cp->ch_channel << 8) + SVWSATA_SERROR, 1,
293 &wdr->sata_error) != 0) {
294 aprint_error("%s: couldn't map channel %d "
295 "sata_error regs\n",
296 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
297 wdc_cp->ch_channel);
298 goto bad;
299 }
300 if (bus_space_subregion(wdr->sata_iot, wdr->sata_baseioh,
301 (wdc_cp->ch_channel << 8) + SVWSATA_SCONTROL, 1,
302 &wdr->sata_control) != 0) {
303 aprint_error("%s: couldn't map channel %d "
304 "sata_control regs\n",
305 sc->sc_wdcdev.sc_atac.atac_dev.dv_xname,
306 wdc_cp->ch_channel);
307 goto bad;
308 }
309
310 wdcattach(wdc_cp);
311 return;
312
313 bad:
314 cp->ata_channel.ch_flags |= ATACH_DISABLED;
315 }
316