tdvfb.c revision 1.2
1 /* $NetBSD: tdvfb.c,v 1.2 2012/07/20 12:03:32 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * A console driver for 3Dfx Voodoo2 (CVG) and 3Dfx Voodoo Graphics (SST-1). 33 * 34 * 3Dfx Glide 2.x source code, Linux driver by Ghozlane Toumi, and 35 * "Voodoo2 Graphics Engine for 3D Game Acceleration" document were used as 36 * reference. wscons attachment code based mostly on genfb by Michael 37 * Lorenz. 38 * 39 * This driver currently only support boards with ICS GENDAC (which seems to 40 * be most popular, however at least two different DACs were used with CVG). 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: tdvfb.c,v 1.2 2012/07/20 12:03:32 rkujawa Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/endian.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 #include <dev/pci/pciio.h> 56 57 #include <dev/pci/tdvfbreg.h> 58 #include <dev/pci/tdvfbvar.h> 59 60 #include <dev/videomode/videomode.h> 61 62 #include "opt_wsemul.h" 63 #include "opt_tdvfb.h" 64 65 #define MAXLOOP 4096 66 67 static int tdvfb_match(device_t, cfdata_t, void *); 68 static void tdvfb_attach(device_t, device_t, void *); 69 70 static uint32_t tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg); 71 static void tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, 72 uint32_t val); 73 static void tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, 74 uint32_t bits); 75 static void tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, 76 uint32_t bits); 77 static uint8_t tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg); 78 void tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, 79 uint32_t val); 80 static void tdvfb_wait(struct tdvfb_softc *sc); 81 82 static bool tdvfb_init(struct tdvfb_softc *sc); 83 static void tdvfb_fbiinit_defaults(struct tdvfb_softc *sc); 84 static size_t tdvfb_mem_size(struct tdvfb_softc *sc); 85 86 static bool tdvfb_videomode_set(struct tdvfb_softc *sc); 87 static void tdvfb_videomode_dac(struct tdvfb_softc *sc); 88 89 static bool tdvfb_gendac_detect(struct tdvfb_softc *sc); 90 static struct tdvfb_dac_timing tdvfb_gendac_calc_pll(int freq); 91 static void tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 92 struct tdvfb_dac_timing *timing); 93 static void tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 94 struct tdvfb_dac_timing *timing); 95 96 static void tdvfb_init_screen(void *cookie, struct vcons_screen *scr, 97 int existing, long *defattr); 98 static void tdvfb_init_palette(struct tdvfb_softc *sc); 99 100 CFATTACH_DECL_NEW(tdvfb, sizeof(struct tdvfb_softc), 101 tdvfb_match, tdvfb_attach, NULL, NULL); 102 103 static int 104 tdvfb_match(device_t parent, cfdata_t match, void *aux) 105 { 106 const struct pci_attach_args *pa = (const struct pci_attach_args *)aux; 107 108 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 109 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2)) 110 return 100; 111 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 112 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO)) 113 return 100; 114 115 return 0; 116 } 117 118 static void 119 tdvfb_attach(device_t parent, device_t self, void *aux) 120 { 121 struct tdvfb_softc *sc = device_private(self); 122 struct wsemuldisplaydev_attach_args ws_aa; 123 struct rasops_info *ri; 124 const struct pci_attach_args *pa = aux; 125 pcireg_t screg; 126 bool console; 127 long defattr; 128 129 #ifdef TDVFB_CONSOLE 130 console = true; 131 #else 132 console = false; 133 #endif 134 135 sc->sc_pc = pa->pa_pc; 136 sc->sc_pcitag = pa->pa_tag; 137 sc->sc_dev = self; 138 139 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2) 140 sc->sc_voodootype = TDV_VOODOO_2; 141 else 142 sc->sc_voodootype = TDV_VOODOO_1; 143 144 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 145 PCI_COMMAND_STATUS_REG); 146 screg |= PCI_COMMAND_MEM_ENABLE; 147 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 148 screg); 149 150 pci_aprint_devinfo(pa, NULL); 151 152 /* map the BAR */ 153 if (pci_mapreg_map(pa, TDV_MM_BAR, PCI_MAPREG_TYPE_MEM, 0, 154 &sc->sc_cvgt, &sc->sc_cvgh, &sc->sc_cvg_pa, 0) != 0 ) { 155 aprint_error_dev(sc->sc_dev, "unable to map CVG BAR"); 156 return; 157 } 158 159 /* Map the framebuffer. */ 160 if (bus_space_subregion(sc->sc_cvgt, sc->sc_cvgh, TDV_OFF_FB, 161 TDV_FB_SIZE, &sc->sc_fbh)) { 162 aprint_error_dev(sc->sc_dev, "unable to map the framebuffer"); 163 } 164 165 aprint_normal_dev(sc->sc_dev, "registers at 0x%08x, fb at 0x%08x\n", 166 sc->sc_cvg_pa, sc->sc_cvg_pa + TDV_OFF_FB); 167 168 /* Do the low level setup. */ 169 if (!tdvfb_init(sc)) { 170 aprint_error_dev(sc->sc_dev, "could not initialize CVG\n"); 171 return; 172 } 173 174 /* 175 * The card is alive now, let's check how much framebuffer memory 176 * do we have. 177 */ 178 sc->sc_memsize = tdvfb_mem_size(sc); 179 180 /* Select video mode, 800x600 32bpp 60Hz by default... */ 181 sc->sc_width = 800; 182 sc->sc_height = 600; 183 sc->sc_bpp = 32; 184 sc->sc_linebytes = 1024 * (sc->sc_bpp / 8); 185 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, sc->sc_height, 60); 186 187 tdvfb_videomode_set(sc); 188 189 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 190 "default", 191 0, 0, 192 NULL, 193 8, 16, 194 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 195 NULL 196 }; 197 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 198 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 199 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 200 201 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 202 &sc->sc_accessops); 203 sc->vd.init_screen = tdvfb_init_screen; 204 205 ri = &sc->sc_console_screen.scr_ri; 206 207 tdvfb_init_palette(sc); 208 209 if (console) { 210 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 211 &defattr); 212 213 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC | 214 VCONS_DONT_READ; 215 vcons_redraw_screen(&sc->sc_console_screen); 216 217 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 218 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 219 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 220 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 221 222 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 223 defattr); 224 vcons_replay_msgbuf(&sc->sc_console_screen); 225 } else if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 226 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 227 &defattr); 228 } 229 230 ws_aa.console = console; 231 ws_aa.scrdata = &sc->sc_screenlist; 232 ws_aa.accessops = &sc->sc_accessops; 233 ws_aa.accesscookie = &sc->vd; 234 235 config_found(sc->sc_dev, &ws_aa, wsemuldisplaydevprint); 236 } 237 238 static void 239 tdvfb_init_palette(struct tdvfb_softc *sc) 240 { 241 int i, j; 242 243 j = 0; 244 for (i = 0; i < 256; i++) { 245 sc->sc_cmap_red[i] = rasops_cmap[j]; 246 sc->sc_cmap_green[i] = rasops_cmap[j + 1]; 247 sc->sc_cmap_blue[i] = rasops_cmap[j + 2]; 248 j += 3; 249 } 250 } 251 252 static void 253 tdvfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 254 long *defattr) 255 { 256 struct tdvfb_softc *sc = cookie; 257 struct rasops_info *ri = &scr->scr_ri; 258 259 wsfont_init(); 260 261 ri->ri_depth = sc->sc_bpp; 262 ri->ri_width = sc->sc_width; 263 ri->ri_height = sc->sc_height; 264 ri->ri_stride = sc->sc_linebytes; 265 ri->ri_flg = RI_CENTER; 266 ri->ri_bits = (char *) bus_space_vaddr(sc->sc_cvgt, sc->sc_fbh); 267 268 scr->scr_flags |= VCONS_DONT_READ; 269 270 rasops_init(ri, 0, 0); 271 ri->ri_caps = WSSCREEN_WSCOLORS; 272 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 273 sc->sc_width / ri->ri_font->fontwidth); 274 275 ri->ri_hw = scr; 276 } 277 278 static bool 279 tdvfb_videomode_set(struct tdvfb_softc *sc) 280 { 281 uint32_t fbiinit1, fbiinit5, fbiinit6, lfbmode; 282 uint16_t vbackporch, vsyncon, vsyncoff; 283 uint16_t hbackporch, hsyncon, hsyncoff; 284 uint16_t yheight, xwidth; 285 286 yheight = sc->sc_videomode->vdisplay; 287 xwidth = sc->sc_videomode->hdisplay; 288 289 vbackporch = sc->sc_videomode->vtotal - sc->sc_videomode->vsync_end; 290 hbackporch = sc->sc_videomode->htotal - sc->sc_videomode->hsync_end; 291 292 vsyncon = sc->sc_videomode->vsync_end - sc->sc_videomode->vsync_start; 293 hsyncon = sc->sc_videomode->hsync_end - sc->sc_videomode->hsync_start; 294 295 vsyncoff = sc->sc_videomode->vtotal - vsyncon; 296 hsyncoff = sc->sc_videomode->htotal - hsyncon; 297 #ifdef TDVFB_DEBUG 298 aprint_normal_dev(sc->sc_dev, 299 "xy %d %d hbp %d vbp %d, hson %d, hsoff %d, vson %d, vsoff %d\n", 300 xwidth, yheight, hbackporch, vbackporch, hsyncon, hsyncoff, 301 vsyncon, vsyncoff); 302 #endif /* TDVFB_DEBUG */ 303 304 sc->vid_timing = tdvfb_gendac_calc_pll(sc->sc_videomode->dot_clock); 305 306 if(sc->sc_voodootype == TDV_VOODOO_2) 307 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64 * 2; 308 else 309 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64; 310 311 tdvfb_cvg_write(sc, TDV_OFF_NOPCMD, 0); 312 tdvfb_wait(sc); 313 314 /* enable writing to fbiinit regs, reset, disable DRAM refresh */ 315 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 316 TDV_INITENABLE_EN_INIT); 317 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 318 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 319 TDV_FBIINIT0_FIFO_RST); 320 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 321 tdvfb_wait(sc); 322 323 /* program video timings into CVG/SST-1*/ 324 tdvfb_cvg_write(sc, TDV_OFF_VDIMENSIONS, yheight << 16 | (xwidth - 1)); 325 tdvfb_cvg_write(sc, TDV_OFF_BACKPORCH, vbackporch << 16 | 326 (hbackporch - 2)); 327 tdvfb_cvg_write(sc, TDV_OFF_HSYNC, hsyncoff << 16 | (hsyncon - 1)); 328 tdvfb_cvg_write(sc, TDV_OFF_VSYNC, vsyncoff << 16 | vsyncon); 329 330 tdvfb_videomode_dac(sc); 331 332 fbiinit1 = ((tdvfb_cvg_read(sc, TDV_OFF_FBIINIT1) & 333 TDV_FBIINIT1_VIDMASK) | 334 TDV_FBIINIT1_DR_DATA | 335 TDV_FBIINIT1_DR_BLANKING | 336 TDV_FBIINIT1_DR_HVSYNC | 337 TDV_FBIINIT1_DR_DCLK | 338 TDV_FBIINIT1_IN_VCLK_2X ); 339 340 if (sc->sc_voodootype == TDV_VOODOO_2) { 341 fbiinit1 |= ((sc->sc_x_tiles & 0x20) >> 5) 342 << TDV_FBIINIT1_TILES_X_MSB | ((sc->sc_x_tiles & 0x1e) >> 1) 343 << TDV_FBIINIT1_TILES_X; 344 fbiinit6 = (sc->sc_x_tiles & 0x1) << TDV_FBIINIT6_TILES_X_LSB; 345 } else 346 fbiinit1 |= sc->sc_x_tiles << TDV_FBIINIT1_TILES_X; 347 348 fbiinit1 |= TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC; 349 350 if (sc->sc_voodootype == TDV_VOODOO_2) { 351 fbiinit5 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT5) 352 & TDV_FBIINIT5_VIDMASK; 353 if (sc->sc_videomode->flags & VID_PHSYNC) 354 fbiinit5 |= TDV_FBIINIT5_PHSYNC; 355 if (sc->sc_videomode->flags & VID_PVSYNC) 356 fbiinit5 |= TDV_FBIINIT5_PVSYNC; 357 } 358 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 359 if (sc->sc_voodootype == TDV_VOODOO_2) { 360 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 361 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT5, fbiinit5); 362 } 363 tdvfb_wait(sc); 364 365 /* unreset, enable DRAM refresh */ 366 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 367 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 368 TDV_FBIINIT0_FIFO_RST); 369 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 370 /* diable access to FBIINIT regs */ 371 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 372 TDV_INITENABLE_EN_FIFO); 373 tdvfb_wait(sc); 374 375 lfbmode = TDV_LFBMODE_8888; 376 377 #if BYTE_ORDER == BIG_ENDIAN 378 lfbmode |= TDV_LFBMODE_BSW_WR | TDV_LFBMODE_BSW_RD; 379 #endif 380 381 tdvfb_cvg_write(sc, TDV_OFF_LFBMODE, lfbmode); 382 383 return true; 384 } 385 386 /* 387 * Update DAC parameters for selected video mode. 388 */ 389 static void 390 tdvfb_videomode_dac(struct tdvfb_softc *sc) 391 { 392 uint32_t fbiinit2, fbiinit3; 393 394 /* remember current FBIINIT settings */ 395 fbiinit2 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); 396 fbiinit3 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT3); 397 398 /* remap DAC */ 399 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 400 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 401 402 tdvfb_cvg_dac_write(sc, TDV_GENDAC_CMD, TDV_GENDAC_CMD_16BITS); 403 404 tdvfb_gendac_set_vid_timing(sc, &(sc->vid_timing)); 405 406 /* disable remapping */ 407 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 408 TDV_INITENABLE_EN_INIT); 409 /* restore */ 410 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 411 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit3); 412 } 413 414 /* 415 * Check how much memory do we have. Actually, Voodoo1/2 has separate 416 * framebuffer and texture memory. This function only checks for framebuffer 417 * memory. Texture memory ramains unused. 418 */ 419 static size_t 420 tdvfb_mem_size(struct tdvfb_softc *sc) 421 { 422 size_t mem_size; 423 uint32_t vram_test4, vram_test2; 424 425 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0, 0x11aabbaa); 426 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x100000, 0x22aabbaa); 427 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x200000, 0x44aabbaa); 428 429 vram_test4 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x400000); 430 vram_test2 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x200000); 431 432 if (vram_test4 == 0x44aabbaa) 433 mem_size = 4*1024*1024; 434 else if (vram_test2 == 0x22aabbaa) { 435 mem_size = 2*1024*1024; 436 } else 437 mem_size = 1*1024*1024; 438 439 return mem_size; 440 } 441 442 /* do the low level init of Voodoo board */ 443 static bool 444 tdvfb_init(struct tdvfb_softc *sc) 445 { 446 /* undocumented - found in glide code */ 447 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_DISABLE_REG, 0); 448 /* allow write to hardware initialization registers */ 449 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 450 TDV_INITENABLE_EN_INIT); 451 452 /* reset the board */ 453 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 454 tdvfb_wait(sc); 455 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 456 TDV_FBIINIT0_FIFO_RST); 457 tdvfb_wait(sc); 458 459 /* disable video RAM refresh */ 460 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 461 tdvfb_wait(sc); 462 463 /* on voodoo1 I had to read FBIINIT2 before remapping, 464 * otherwise weird things were happening, on v2 it works just fine */ 465 /* tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); */ 466 467 /* remap DAC */ 468 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 469 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 470 471 /* detect supported DAC, TODO: we really should support other DACs */ 472 if(!tdvfb_gendac_detect(sc)) { 473 aprint_error_dev(sc->sc_dev, "could not detect ICS GENDAC\n"); 474 return false; 475 } 476 477 /* calculate PLL used to drive the chips (graphics clock) */ 478 if(sc->sc_voodootype == TDV_VOODOO_2) 479 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_CVG_CLK); 480 else 481 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_SST_CLK); 482 483 /* set PLL for gfx clock */ 484 tdvfb_gendac_set_cvg_timing(sc, &(sc->cvg_timing)); 485 486 /* don't remap the DAC anymore */ 487 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 488 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_EN_FIFO); 489 490 /* set FBIINIT registers to some default values that make sense */ 491 tdvfb_fbiinit_defaults(sc); 492 493 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 494 TDV_INITENABLE_EN_FIFO); 495 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_ENABLE_REG, 0); 496 497 return true; 498 } 499 500 static void 501 tdvfb_fbiinit_defaults(struct tdvfb_softc *sc) 502 { 503 uint32_t fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6; 504 505 fbiinit0 = TDV_FBIINIT0_VGA_PASS; /* disable VGA passthrough */ 506 fbiinit1 = /*TDV_FBIINIT1_PCIWAIT |*/ /* one wait state for PCI write */ 507 TDV_FBIINIT1_LFB_EN | /* enable lfb reads */ 508 TDV_FBIINIT1_VIDEO_RST | /* video timing reset */ 509 10 << TDV_FBIINIT1_TILES_X | /* tiles x/horizontal */ 510 TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC ; 511 512 fbiinit2 = TDV_FBIINIT2_SWB_ALG |/* swap buffer use DAC sync */ 513 TDV_FBIINIT2_FAST_RAS | /* fast RAS read */ 514 TDV_FBIINIT2_DRAM_OE | /* enable DRAM OE */ 515 TDV_FBIINIT2_DRAM_REFR | /* enable DRAM refresh */ 516 TDV_FBIINIT2_FIFO_RDA | /* FIFO read ahead */ 517 TDV_FBIINIT2_DRAM_REF16 << TDV_FBIINIT2_DRAM_REFLD; /* 16 ms */ 518 519 fbiinit3 = TDV_FBIINIT3_TREX_DIS; /* disable texture mapping */ 520 521 fbiinit4 = /*TDV_FBIINIT4_PCIWAIT|*/ /* one wait state for PCI write */ 522 TDV_FBIINIT4_LFB_RDA; /* lfb read ahead */ 523 524 fbiinit6 = 0; 525 #ifdef TDVFB_DEBUG 526 aprint_normal("fbiinit: 0 %x, 1 %x, 2 %x, 3 %x, 4 %x, 6 %x\n", 527 fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6); 528 #endif /* TDVFB_DEBUG */ 529 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT0, fbiinit0); 530 tdvfb_wait(sc); 531 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 532 tdvfb_wait(sc); 533 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 534 tdvfb_wait(sc); 535 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT3, fbiinit3); 536 tdvfb_wait(sc); 537 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT4, fbiinit4); 538 tdvfb_wait(sc); 539 if (sc->sc_voodootype == TDV_VOODOO_2) { 540 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 541 tdvfb_wait(sc); 542 } 543 } 544 545 static void 546 tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 547 struct tdvfb_dac_timing *timing) 548 { 549 uint8_t pllreg; 550 551 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 552 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 553 554 /* write the timing for gfx clock into "slot" 0 */ 555 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0); 556 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 557 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 558 /* select "slot" 0 for output */ 559 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 560 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 561 (pllreg & TDV_GENDAC_VIDPLLMASK) | TDV_GENDAC_PLL_VIDCLK | 562 TDV_GENDAC_PLL_VIDCLK0); 563 tdvfb_wait(sc); 564 tdvfb_wait(sc); 565 #ifdef TDVFB_DEBUG 566 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_0); 567 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 568 aprint_normal("vid read again: %d\n", pllreg); 569 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 570 aprint_normal("vid read again: %d\n", pllreg); 571 #endif /* TDVFB_DEBUG */ 572 } 573 574 static void 575 tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 576 struct tdvfb_dac_timing *timing) 577 { 578 uint8_t pllreg; 579 580 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 581 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 582 583 /* write the timing for gfx clock into "slot" A */ 584 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_A); 585 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 586 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 587 /* select "slot" A for output */ 588 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 589 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 590 (pllreg & TDV_GENDAC_CVGPLLMASK) | TDV_GENDAC_PLL_CVGCLKA); 591 #ifdef TDVFB_DEBUG 592 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_A); 593 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 594 aprint_normal("read again: %d\n", pllreg); 595 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 596 aprint_normal("read again: %d\n", pllreg); 597 #endif /* TDVFB_DEBUG */ 598 tdvfb_wait(sc); 599 } 600 601 static struct tdvfb_dac_timing 602 tdvfb_gendac_calc_pll(int freq) 603 { 604 int n1, n2; 605 int m, mdbl; 606 int best_m, best_n1, best_error; 607 int fout; 608 struct tdvfb_dac_timing timing; 609 610 best_m = -1; best_n1 = -1; 611 612 /* select highest possible n2, check n2 * fCLK < TDV_GENDAC_MAXVCO */ 613 for (n2 = TDV_GENDAC_MAX_N2; n2 >= TDV_GENDAC_MIN_N2; n2--) { 614 if ((freq * (1 << n2)) < TDV_GENDAC_MAXVCO) 615 break; 616 } 617 618 best_error = freq; 619 620 /* 621 * m+2 2^n2 * fOUT 622 * ---- = ----------- 623 * n1+2 fREF 624 */ 625 for (n1 = TDV_GENDAC_MIN_N1; n1 <= TDV_GENDAC_MAX_N1; n1++) { 626 /* loop mostly inspired by Linux driver */ 627 mdbl = (2 * freq * (1 << n2)*(n1 + 2)) / TDV_GENDAC_REFFREQ - 4; 628 if (mdbl % 2) 629 m = mdbl/2+1; 630 else 631 m = mdbl/2; 632 633 if(m > TDV_GENDAC_MAX_M) 634 break; 635 636 fout = (TDV_GENDAC_REFFREQ * (m + 2)) / ((1 << n2) * (n1 + 2)); 637 if ((abs(fout - freq) < best_error) && (m > 0)) { 638 best_n1 = n1; 639 best_m = m; 640 best_error = abs(fout - freq); 641 if (200*best_error < freq) break; 642 } 643 644 } 645 646 fout = (TDV_GENDAC_REFFREQ * (best_m + 2)) / ((1 << n2) * (best_n1 + 2)); 647 timing.m = best_m; 648 timing.n = (n2 << 5) | best_n1; 649 timing.fout = fout; 650 651 #ifdef TDVFB_DEBUG 652 aprint_normal("tdvfb_gendac_calc_pll ret: m %d, n %d, fout %d kHz\n", 653 timing.m, timing.n, timing.fout); 654 #endif /* TDVFB_DEBUG */ 655 656 return timing; 657 } 658 659 static bool 660 tdvfb_gendac_detect(struct tdvfb_softc *sc) 661 { 662 uint8_t m_f1, m_f7, m_fb; 663 uint8_t n_f1, n_f7, n_fb; 664 665 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x1); 666 m_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 667 n_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 668 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x7); 669 m_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 670 n_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 671 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0xB); 672 m_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 673 n_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 674 675 if( (m_f1 == TDV_GENDAC_DFLT_F1_M) && 676 (n_f1 == TDV_GENDAC_DFLT_F1_N) && 677 (m_f7 == TDV_GENDAC_DFLT_F7_M) && 678 (n_f7 == TDV_GENDAC_DFLT_F7_N) && 679 (n_fb == TDV_GENDAC_DFLT_FB_N) && 680 (n_fb == TDV_GENDAC_DFLT_FB_N) ) { 681 aprint_normal_dev(sc->sc_dev, "ICS 5342 GENDAC\n"); 682 return true; 683 } 684 685 return false; 686 } 687 688 static void 689 tdvfb_wait(struct tdvfb_softc *sc) 690 { 691 uint32_t x, cnt; 692 cnt = 0; 693 for (x = 0; x < MAXLOOP; x++) { 694 if (tdvfb_cvg_read(sc, TDV_OFF_STATUS) & TDV_STATUS_FBI_BUSY) 695 cnt = 0; 696 else 697 cnt++; 698 699 if (cnt >= 5) /* Voodoo2 specs suggest at least 3 */ 700 break; 701 } 702 703 if (x == MAXLOOP) 704 /* 705 * The console probably isn't working now anyway, so maybe 706 * let's panic... At least it will drop into ddb if some other 707 * device a console. 708 */ 709 panic("tdvfb is stuck!\n"); 710 } 711 712 static uint32_t 713 tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg) 714 { 715 uint32_t rv; 716 rv = bus_space_read_4(sc->sc_cvgt, sc->sc_cvgh, reg); 717 #ifdef TDVFB_DEBUG 718 aprint_normal("cvg_read val %x from reg %x\n", rv, reg); 719 #endif /* TDVFB_DEBUG */ 720 return rv; 721 } 722 723 static void 724 tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 725 { 726 #ifdef TDVFB_DEBUG 727 aprint_normal("cvg_write val %x to reg %x\n", val, reg); 728 #endif /* TDVFB_DEBUG */ 729 bus_space_write_4(sc->sc_cvgt, sc->sc_cvgh, reg, val); 730 } 731 732 static void 733 tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 734 { 735 uint32_t v; 736 v = tdvfb_cvg_read(sc, reg) | bits; 737 tdvfb_cvg_write(sc, reg, v); 738 } 739 740 static void 741 tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 742 { 743 uint32_t v; 744 v = tdvfb_cvg_read(sc, reg) & ~bits; 745 tdvfb_cvg_write(sc, reg, v); 746 } 747 748 static uint8_t 749 tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg) 750 { 751 uint32_t rv; 752 753 tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ); 754 755 rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ); 756 #ifdef TDVFB_DEBUG 757 aprint_normal("cvg_dac_read val %x from reg %x\n", rv, reg); 758 #endif /* TDVFB_DEBUG */ 759 return rv & 0xFF; 760 } 761 762 void 763 tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 764 { 765 uint32_t wreg; 766 767 wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val; 768 769 #ifdef TDVFB_DEBUG 770 aprint_normal("cvg_dac_write val %x to reg %x (%x)\n", val, reg, 771 wreg); 772 #endif /* TDVFB_DEBUG */ 773 774 tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg); 775 tdvfb_wait(sc); 776 } 777 778
Indexes created Tue Sep 30 20:09:53 GMT 2025