tdvfb.c revision 1.3
1 /* $NetBSD: tdvfb.c,v 1.3 2012/07/20 21:31:28 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * A console driver for 3Dfx Voodoo2 (CVG) and 3Dfx Voodoo Graphics (SST-1). 33 * 34 * 3Dfx Glide 2.x source code, Linux driver by Ghozlane Toumi, and 35 * "Voodoo2 Graphics Engine for 3D Game Acceleration" document were used as 36 * reference. wscons attachment code based mostly on genfb by Michael 37 * Lorenz. 38 * 39 * This driver currently only support boards with ICS GENDAC (which seems to 40 * be most popular, however at least two different DACs were used with CVG). 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: tdvfb.c,v 1.3 2012/07/20 21:31:28 rkujawa Exp $"); 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/kernel.h> 49 #include <sys/device.h> 50 #include <sys/endian.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <dev/pci/pcireg.h> 54 #include <dev/pci/pcidevs.h> 55 #include <dev/pci/pciio.h> 56 57 #include <dev/pci/tdvfbreg.h> 58 #include <dev/pci/tdvfbvar.h> 59 60 #include <dev/videomode/videomode.h> 61 62 #include "opt_wsemul.h" 63 #include "opt_tdvfb.h" 64 65 #define MAXLOOP 4096 66 67 static int tdvfb_match(device_t, cfdata_t, void *); 68 static void tdvfb_attach(device_t, device_t, void *); 69 70 static uint32_t tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg); 71 static void tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, 72 uint32_t val); 73 static void tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, 74 uint32_t bits); 75 static void tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, 76 uint32_t bits); 77 static uint8_t tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg); 78 static void tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, 79 uint32_t val); 80 static void tdvfb_wait(struct tdvfb_softc *sc); 81 82 static bool tdvfb_init(struct tdvfb_softc *sc); 83 static void tdvfb_fbiinit_defaults(struct tdvfb_softc *sc); 84 static size_t tdvfb_mem_size(struct tdvfb_softc *sc); 85 86 static bool tdvfb_videomode_set(struct tdvfb_softc *sc); 87 static void tdvfb_videomode_dac(struct tdvfb_softc *sc); 88 89 static bool tdvfb_gendac_detect(struct tdvfb_softc *sc); 90 static struct tdvfb_dac_timing tdvfb_gendac_calc_pll(int freq); 91 static void tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 92 struct tdvfb_dac_timing *timing); 93 static void tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 94 struct tdvfb_dac_timing *timing); 95 96 static void tdvfb_init_screen(void *cookie, struct vcons_screen *scr, 97 int existing, long *defattr); 98 static void tdvfb_init_palette(struct tdvfb_softc *sc); 99 /* blitter support */ 100 static void tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, 101 int he, uint32_t color); 102 static void tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, 103 int yd, int wi, int he); 104 /* accelerated raster ops */ 105 static void tdvfb_eraserows(void *cookie, int row, int nrows, 106 long fillattr); 107 static void tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows); 108 109 CFATTACH_DECL_NEW(tdvfb, sizeof(struct tdvfb_softc), 110 tdvfb_match, tdvfb_attach, NULL, NULL); 111 112 static int 113 tdvfb_match(device_t parent, cfdata_t match, void *aux) 114 { 115 const struct pci_attach_args *pa = (const struct pci_attach_args *)aux; 116 117 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 118 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2)) 119 return 100; 120 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 121 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO)) 122 return 100; 123 124 return 0; 125 } 126 127 static void 128 tdvfb_attach(device_t parent, device_t self, void *aux) 129 { 130 struct tdvfb_softc *sc = device_private(self); 131 struct wsemuldisplaydev_attach_args ws_aa; 132 struct rasops_info *ri; 133 const struct pci_attach_args *pa = aux; 134 pcireg_t screg; 135 bool console; 136 long defattr; 137 138 #ifdef TDVFB_CONSOLE 139 console = true; 140 #else 141 console = false; 142 #endif 143 144 sc->sc_pc = pa->pa_pc; 145 sc->sc_pcitag = pa->pa_tag; 146 sc->sc_dev = self; 147 148 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2) 149 sc->sc_voodootype = TDV_VOODOO_2; 150 else 151 sc->sc_voodootype = TDV_VOODOO_1; 152 153 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 154 PCI_COMMAND_STATUS_REG); 155 screg |= PCI_COMMAND_MEM_ENABLE; 156 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 157 screg); 158 159 pci_aprint_devinfo(pa, NULL); 160 161 /* map the BAR */ 162 if (pci_mapreg_map(pa, TDV_MM_BAR, PCI_MAPREG_TYPE_MEM, 0, 163 &sc->sc_cvgt, &sc->sc_cvgh, &sc->sc_cvg_pa, 0) != 0 ) { 164 aprint_error_dev(sc->sc_dev, "unable to map CVG BAR"); 165 return; 166 } 167 168 /* Map the framebuffer. */ 169 if (bus_space_subregion(sc->sc_cvgt, sc->sc_cvgh, TDV_OFF_FB, 170 TDV_FB_SIZE, &sc->sc_fbh)) { 171 aprint_error_dev(sc->sc_dev, "unable to map the framebuffer"); 172 } 173 174 aprint_normal_dev(sc->sc_dev, "registers at 0x%08x, fb at 0x%08x\n", 175 sc->sc_cvg_pa, sc->sc_cvg_pa + TDV_OFF_FB); 176 177 /* Do the low level setup. */ 178 if (!tdvfb_init(sc)) { 179 aprint_error_dev(sc->sc_dev, "could not initialize CVG\n"); 180 return; 181 } 182 183 /* 184 * The card is alive now, let's check how much framebuffer memory 185 * do we have. 186 */ 187 sc->sc_memsize = tdvfb_mem_size(sc); 188 189 /* Select video mode, 800x600 32bpp 60Hz by default... */ 190 sc->sc_width = 800; 191 sc->sc_height = 600; 192 sc->sc_bpp = 32; /* XXX: 16 would allow blitter use. */ 193 sc->sc_linebytes = 1024 * (sc->sc_bpp / 8); 194 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, sc->sc_height, 60); 195 196 tdvfb_videomode_set(sc); 197 198 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 199 "default", 200 0, 0, 201 NULL, 202 8, 16, 203 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 204 NULL 205 }; 206 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 207 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 208 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 209 210 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 211 &sc->sc_accessops); 212 sc->vd.init_screen = tdvfb_init_screen; 213 214 ri = &sc->sc_console_screen.scr_ri; 215 216 tdvfb_init_palette(sc); 217 218 if (console) { 219 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 220 &defattr); 221 222 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC | 223 VCONS_DONT_READ; 224 vcons_redraw_screen(&sc->sc_console_screen); 225 226 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 227 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 228 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 229 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 230 231 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 232 defattr); 233 vcons_replay_msgbuf(&sc->sc_console_screen); 234 } else if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 235 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 236 &defattr); 237 } 238 239 ws_aa.console = console; 240 ws_aa.scrdata = &sc->sc_screenlist; 241 ws_aa.accessops = &sc->sc_accessops; 242 ws_aa.accesscookie = &sc->vd; 243 244 config_found(sc->sc_dev, &ws_aa, wsemuldisplaydevprint); 245 } 246 247 static void 248 tdvfb_init_palette(struct tdvfb_softc *sc) 249 { 250 int i, j; 251 252 j = 0; 253 for (i = 0; i < 256; i++) { 254 sc->sc_cmap_red[i] = rasops_cmap[j]; 255 sc->sc_cmap_green[i] = rasops_cmap[j + 1]; 256 sc->sc_cmap_blue[i] = rasops_cmap[j + 2]; 257 j += 3; 258 } 259 } 260 261 static void 262 tdvfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 263 long *defattr) 264 { 265 struct tdvfb_softc *sc = cookie; 266 struct rasops_info *ri = &scr->scr_ri; 267 268 wsfont_init(); 269 270 ri->ri_depth = sc->sc_bpp; 271 ri->ri_width = sc->sc_width; 272 ri->ri_height = sc->sc_height; 273 ri->ri_stride = sc->sc_linebytes; 274 ri->ri_flg = RI_CENTER; 275 276 #if BYTE_ORDER == BIG_ENDIAN 277 #if 0 /* XXX: not yet :( */ 278 if (sc->sc_bpp == 16) 279 ri->ri_flg |= RI_BITSWAP; 280 #endif 281 #endif 282 283 ri->ri_bits = (char *) bus_space_vaddr(sc->sc_cvgt, sc->sc_fbh); 284 285 scr->scr_flags |= VCONS_DONT_READ; 286 287 rasops_init(ri, 0, 0); 288 ri->ri_caps = WSSCREEN_WSCOLORS; 289 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 290 sc->sc_width / ri->ri_font->fontwidth); 291 292 ri->ri_hw = scr; 293 294 /* If we are a Voodoo2 and running in 16 bits try to use blitter. */ 295 if ((sc->sc_voodootype == TDV_VOODOO_2) && (sc->sc_bpp == 16)) { 296 aprint_normal_dev(sc->sc_dev, "using CVG blitter\n"); 297 ri->ri_ops.eraserows = tdvfb_eraserows; 298 ri->ri_ops.copyrows = tdvfb_copyrows; 299 } 300 } 301 302 static bool 303 tdvfb_videomode_set(struct tdvfb_softc *sc) 304 { 305 uint32_t fbiinit1, fbiinit5, fbiinit6, lfbmode; 306 uint16_t vbackporch, vsyncon, vsyncoff; 307 uint16_t hbackporch, hsyncon, hsyncoff; 308 uint16_t yheight, xwidth; 309 310 yheight = sc->sc_videomode->vdisplay; 311 xwidth = sc->sc_videomode->hdisplay; 312 313 vbackporch = sc->sc_videomode->vtotal - sc->sc_videomode->vsync_end; 314 hbackporch = sc->sc_videomode->htotal - sc->sc_videomode->hsync_end; 315 316 vsyncon = sc->sc_videomode->vsync_end - sc->sc_videomode->vsync_start; 317 hsyncon = sc->sc_videomode->hsync_end - sc->sc_videomode->hsync_start; 318 319 vsyncoff = sc->sc_videomode->vtotal - vsyncon; 320 hsyncoff = sc->sc_videomode->htotal - hsyncon; 321 #ifdef TDVFB_DEBUG 322 aprint_normal_dev(sc->sc_dev, 323 "xy %d %d hbp %d vbp %d, hson %d, hsoff %d, vson %d, vsoff %d\n", 324 xwidth, yheight, hbackporch, vbackporch, hsyncon, hsyncoff, 325 vsyncon, vsyncoff); 326 #endif /* TDVFB_DEBUG */ 327 328 sc->vid_timing = tdvfb_gendac_calc_pll(sc->sc_videomode->dot_clock); 329 330 if(sc->sc_voodootype == TDV_VOODOO_2) 331 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64 * 2; 332 else 333 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64; 334 335 tdvfb_cvg_write(sc, TDV_OFF_NOPCMD, 0); 336 tdvfb_wait(sc); 337 338 /* enable writing to fbiinit regs, reset, disable DRAM refresh */ 339 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 340 TDV_INITENABLE_EN_INIT); 341 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 342 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 343 TDV_FBIINIT0_FIFO_RST); 344 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 345 tdvfb_wait(sc); 346 347 /* program video timings into CVG/SST-1*/ 348 tdvfb_cvg_write(sc, TDV_OFF_VDIMENSIONS, yheight << 16 | (xwidth - 1)); 349 tdvfb_cvg_write(sc, TDV_OFF_BACKPORCH, vbackporch << 16 | 350 (hbackporch - 2)); 351 tdvfb_cvg_write(sc, TDV_OFF_HSYNC, hsyncoff << 16 | (hsyncon - 1)); 352 tdvfb_cvg_write(sc, TDV_OFF_VSYNC, vsyncoff << 16 | vsyncon); 353 354 tdvfb_videomode_dac(sc); 355 356 fbiinit1 = ((tdvfb_cvg_read(sc, TDV_OFF_FBIINIT1) & 357 TDV_FBIINIT1_VIDMASK) | 358 TDV_FBIINIT1_DR_DATA | 359 TDV_FBIINIT1_DR_BLANKING | 360 TDV_FBIINIT1_DR_HVSYNC | 361 TDV_FBIINIT1_DR_DCLK | 362 TDV_FBIINIT1_IN_VCLK_2X ); 363 364 if (sc->sc_voodootype == TDV_VOODOO_2) { 365 fbiinit1 |= ((sc->sc_x_tiles & 0x20) >> 5) 366 << TDV_FBIINIT1_TILES_X_MSB | ((sc->sc_x_tiles & 0x1e) >> 1) 367 << TDV_FBIINIT1_TILES_X; 368 fbiinit6 = (sc->sc_x_tiles & 0x1) << TDV_FBIINIT6_TILES_X_LSB; 369 } else 370 fbiinit1 |= sc->sc_x_tiles << TDV_FBIINIT1_TILES_X; 371 372 fbiinit1 |= TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC; 373 374 if (sc->sc_voodootype == TDV_VOODOO_2) { 375 fbiinit5 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT5) 376 & TDV_FBIINIT5_VIDMASK; 377 if (sc->sc_videomode->flags & VID_PHSYNC) 378 fbiinit5 |= TDV_FBIINIT5_PHSYNC; 379 if (sc->sc_videomode->flags & VID_PVSYNC) 380 fbiinit5 |= TDV_FBIINIT5_PVSYNC; 381 } 382 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 383 if (sc->sc_voodootype == TDV_VOODOO_2) { 384 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 385 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT5, fbiinit5); 386 } 387 tdvfb_wait(sc); 388 389 /* unreset, enable DRAM refresh */ 390 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 391 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 392 TDV_FBIINIT0_FIFO_RST); 393 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 394 /* diable access to FBIINIT regs */ 395 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 396 TDV_INITENABLE_EN_FIFO); 397 tdvfb_wait(sc); 398 399 if (sc->sc_bpp == 16) 400 lfbmode = TDV_LFBMODE_565; 401 else if (sc->sc_bpp == 32) 402 lfbmode = TDV_LFBMODE_8888; 403 else 404 return false; 405 406 #if BYTE_ORDER == BIG_ENDIAN 407 lfbmode |= TDV_LFBMODE_BSW_WR | TDV_LFBMODE_BSW_RD; 408 #endif 409 410 tdvfb_cvg_write(sc, TDV_OFF_LFBMODE, lfbmode); 411 412 return true; 413 } 414 415 /* 416 * Update DAC parameters for selected video mode. 417 */ 418 static void 419 tdvfb_videomode_dac(struct tdvfb_softc *sc) 420 { 421 uint32_t fbiinit2, fbiinit3; 422 423 /* remember current FBIINIT settings */ 424 fbiinit2 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); 425 fbiinit3 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT3); 426 427 /* remap DAC */ 428 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 429 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 430 431 tdvfb_cvg_dac_write(sc, TDV_GENDAC_CMD, TDV_GENDAC_CMD_16BITS); 432 433 tdvfb_gendac_set_vid_timing(sc, &(sc->vid_timing)); 434 435 /* disable remapping */ 436 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 437 TDV_INITENABLE_EN_INIT); 438 /* restore */ 439 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 440 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit3); 441 } 442 443 /* 444 * Check how much memory do we have. Actually, Voodoo1/2 has separate 445 * framebuffer and texture memory. This function only checks for framebuffer 446 * memory. Texture memory ramains unused. 447 */ 448 static size_t 449 tdvfb_mem_size(struct tdvfb_softc *sc) 450 { 451 size_t mem_size; 452 uint32_t vram_test4, vram_test2; 453 454 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0, 0x11aabbaa); 455 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x100000, 0x22aabbaa); 456 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x200000, 0x44aabbaa); 457 458 vram_test4 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x400000); 459 vram_test2 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x200000); 460 461 if (vram_test4 == 0x44aabbaa) 462 mem_size = 4*1024*1024; 463 else if (vram_test2 == 0x22aabbaa) { 464 mem_size = 2*1024*1024; 465 } else 466 mem_size = 1*1024*1024; 467 468 return mem_size; 469 } 470 471 /* do the low level init of Voodoo board */ 472 static bool 473 tdvfb_init(struct tdvfb_softc *sc) 474 { 475 /* undocumented - found in glide code */ 476 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_DISABLE_REG, 0); 477 /* allow write to hardware initialization registers */ 478 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 479 TDV_INITENABLE_EN_INIT); 480 481 /* reset the board */ 482 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 483 tdvfb_wait(sc); 484 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 485 TDV_FBIINIT0_FIFO_RST); 486 tdvfb_wait(sc); 487 488 /* disable video RAM refresh */ 489 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 490 tdvfb_wait(sc); 491 492 /* on voodoo1 I had to read FBIINIT2 before remapping, 493 * otherwise weird things were happening, on v2 it works just fine */ 494 /* tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); */ 495 496 /* remap DAC */ 497 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 498 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 499 500 /* detect supported DAC, TODO: we really should support other DACs */ 501 if(!tdvfb_gendac_detect(sc)) { 502 aprint_error_dev(sc->sc_dev, "could not detect ICS GENDAC\n"); 503 return false; 504 } 505 506 /* calculate PLL used to drive the chips (graphics clock) */ 507 if(sc->sc_voodootype == TDV_VOODOO_2) 508 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_CVG_CLK); 509 else 510 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_SST_CLK); 511 512 /* set PLL for gfx clock */ 513 tdvfb_gendac_set_cvg_timing(sc, &(sc->cvg_timing)); 514 515 /* don't remap the DAC anymore */ 516 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 517 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_EN_FIFO); 518 519 /* set FBIINIT registers to some default values that make sense */ 520 tdvfb_fbiinit_defaults(sc); 521 522 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 523 TDV_INITENABLE_EN_FIFO); 524 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_ENABLE_REG, 0); 525 526 return true; 527 } 528 529 static void 530 tdvfb_fbiinit_defaults(struct tdvfb_softc *sc) 531 { 532 uint32_t fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6; 533 534 fbiinit0 = TDV_FBIINIT0_VGA_PASS; /* disable VGA passthrough */ 535 fbiinit1 = /*TDV_FBIINIT1_PCIWAIT |*/ /* one wait state for PCI write */ 536 TDV_FBIINIT1_LFB_EN | /* enable lfb reads */ 537 TDV_FBIINIT1_VIDEO_RST | /* video timing reset */ 538 10 << TDV_FBIINIT1_TILES_X | /* tiles x/horizontal */ 539 TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC ; 540 541 fbiinit2 = TDV_FBIINIT2_SWB_ALG |/* swap buffer use DAC sync */ 542 TDV_FBIINIT2_FAST_RAS | /* fast RAS read */ 543 TDV_FBIINIT2_DRAM_OE | /* enable DRAM OE */ 544 TDV_FBIINIT2_DRAM_REFR | /* enable DRAM refresh */ 545 TDV_FBIINIT2_FIFO_RDA | /* FIFO read ahead */ 546 TDV_FBIINIT2_DRAM_REF16 << TDV_FBIINIT2_DRAM_REFLD; /* 16 ms */ 547 548 fbiinit3 = TDV_FBIINIT3_TREX_DIS; /* disable texture mapping */ 549 550 fbiinit4 = /*TDV_FBIINIT4_PCIWAIT|*/ /* one wait state for PCI write */ 551 TDV_FBIINIT4_LFB_RDA; /* lfb read ahead */ 552 553 fbiinit6 = 0; 554 #ifdef TDVFB_DEBUG 555 aprint_normal("fbiinit: 0 %x, 1 %x, 2 %x, 3 %x, 4 %x, 6 %x\n", 556 fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6); 557 #endif /* TDVFB_DEBUG */ 558 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT0, fbiinit0); 559 tdvfb_wait(sc); 560 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 561 tdvfb_wait(sc); 562 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 563 tdvfb_wait(sc); 564 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT3, fbiinit3); 565 tdvfb_wait(sc); 566 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT4, fbiinit4); 567 tdvfb_wait(sc); 568 if (sc->sc_voodootype == TDV_VOODOO_2) { 569 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 570 tdvfb_wait(sc); 571 } 572 } 573 574 static void 575 tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 576 struct tdvfb_dac_timing *timing) 577 { 578 uint8_t pllreg; 579 580 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 581 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 582 583 /* write the timing for gfx clock into "slot" 0 */ 584 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0); 585 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 586 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 587 /* select "slot" 0 for output */ 588 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 589 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 590 (pllreg & TDV_GENDAC_VIDPLLMASK) | TDV_GENDAC_PLL_VIDCLK | 591 TDV_GENDAC_PLL_VIDCLK0); 592 tdvfb_wait(sc); 593 tdvfb_wait(sc); 594 #ifdef TDVFB_DEBUG 595 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_0); 596 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 597 aprint_normal("vid read again: %d\n", pllreg); 598 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 599 aprint_normal("vid read again: %d\n", pllreg); 600 #endif /* TDVFB_DEBUG */ 601 } 602 603 static void 604 tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 605 struct tdvfb_dac_timing *timing) 606 { 607 uint8_t pllreg; 608 609 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 610 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 611 612 /* write the timing for gfx clock into "slot" A */ 613 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_A); 614 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 615 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 616 /* select "slot" A for output */ 617 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 618 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 619 (pllreg & TDV_GENDAC_CVGPLLMASK) | TDV_GENDAC_PLL_CVGCLKA); 620 #ifdef TDVFB_DEBUG 621 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_A); 622 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 623 aprint_normal("read again: %d\n", pllreg); 624 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 625 aprint_normal("read again: %d\n", pllreg); 626 #endif /* TDVFB_DEBUG */ 627 tdvfb_wait(sc); 628 } 629 630 static struct tdvfb_dac_timing 631 tdvfb_gendac_calc_pll(int freq) 632 { 633 int n1, n2; 634 int m, mdbl; 635 int best_m, best_n1, best_error; 636 int fout; 637 struct tdvfb_dac_timing timing; 638 639 best_m = -1; best_n1 = -1; 640 641 /* select highest possible n2, check n2 * fCLK < TDV_GENDAC_MAXVCO */ 642 for (n2 = TDV_GENDAC_MAX_N2; n2 >= TDV_GENDAC_MIN_N2; n2--) { 643 if ((freq * (1 << n2)) < TDV_GENDAC_MAXVCO) 644 break; 645 } 646 647 best_error = freq; 648 649 /* 650 * m+2 2^n2 * fOUT 651 * ---- = ----------- 652 * n1+2 fREF 653 */ 654 for (n1 = TDV_GENDAC_MIN_N1; n1 <= TDV_GENDAC_MAX_N1; n1++) { 655 /* loop mostly inspired by Linux driver */ 656 mdbl = (2 * freq * (1 << n2)*(n1 + 2)) / TDV_GENDAC_REFFREQ - 4; 657 if (mdbl % 2) 658 m = mdbl/2+1; 659 else 660 m = mdbl/2; 661 662 if(m > TDV_GENDAC_MAX_M) 663 break; 664 665 fout = (TDV_GENDAC_REFFREQ * (m + 2)) / ((1 << n2) * (n1 + 2)); 666 if ((abs(fout - freq) < best_error) && (m > 0)) { 667 best_n1 = n1; 668 best_m = m; 669 best_error = abs(fout - freq); 670 if (200*best_error < freq) break; 671 } 672 673 } 674 675 fout = (TDV_GENDAC_REFFREQ * (best_m + 2)) / ((1 << n2) * (best_n1 + 2)); 676 timing.m = best_m; 677 timing.n = (n2 << 5) | best_n1; 678 timing.fout = fout; 679 680 #ifdef TDVFB_DEBUG 681 aprint_normal("tdvfb_gendac_calc_pll ret: m %d, n %d, fout %d kHz\n", 682 timing.m, timing.n, timing.fout); 683 #endif /* TDVFB_DEBUG */ 684 685 return timing; 686 } 687 688 static bool 689 tdvfb_gendac_detect(struct tdvfb_softc *sc) 690 { 691 uint8_t m_f1, m_f7, m_fb; 692 uint8_t n_f1, n_f7, n_fb; 693 694 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x1); 695 m_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 696 n_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 697 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x7); 698 m_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 699 n_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 700 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0xB); 701 m_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 702 n_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 703 704 if( (m_f1 == TDV_GENDAC_DFLT_F1_M) && 705 (n_f1 == TDV_GENDAC_DFLT_F1_N) && 706 (m_f7 == TDV_GENDAC_DFLT_F7_M) && 707 (n_f7 == TDV_GENDAC_DFLT_F7_N) && 708 (n_fb == TDV_GENDAC_DFLT_FB_N) && 709 (n_fb == TDV_GENDAC_DFLT_FB_N) ) { 710 aprint_normal_dev(sc->sc_dev, "ICS 5342 GENDAC\n"); 711 return true; 712 } 713 714 return false; 715 } 716 717 static void 718 tdvfb_wait(struct tdvfb_softc *sc) 719 { 720 uint32_t x, cnt; 721 cnt = 0; 722 for (x = 0; x < MAXLOOP; x++) { 723 if (tdvfb_cvg_read(sc, TDV_OFF_STATUS) & TDV_STATUS_FBI_BUSY) 724 cnt = 0; 725 else 726 cnt++; 727 728 if (cnt >= 5) /* Voodoo2 specs suggest at least 3 */ 729 break; 730 } 731 732 if (x == MAXLOOP) 733 /* 734 * The console probably isn't working now anyway, so maybe 735 * let's panic... At least it will drop into ddb if some other 736 * device a console. 737 */ 738 panic("tdvfb is stuck!\n"); 739 } 740 741 static uint32_t 742 tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg) 743 { 744 uint32_t rv; 745 rv = bus_space_read_4(sc->sc_cvgt, sc->sc_cvgh, reg); 746 #ifdef TDVFB_DEBUG 747 aprint_normal("cvg_read val %x from reg %x\n", rv, reg); 748 #endif /* TDVFB_DEBUG */ 749 return rv; 750 } 751 752 static void 753 tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 754 { 755 #ifdef TDVFB_DEBUG 756 aprint_normal("cvg_write val %x to reg %x\n", val, reg); 757 #endif /* TDVFB_DEBUG */ 758 bus_space_write_4(sc->sc_cvgt, sc->sc_cvgh, reg, val); 759 } 760 761 static void 762 tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 763 { 764 uint32_t v; 765 v = tdvfb_cvg_read(sc, reg) | bits; 766 tdvfb_cvg_write(sc, reg, v); 767 } 768 769 static void 770 tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 771 { 772 uint32_t v; 773 v = tdvfb_cvg_read(sc, reg) & ~bits; 774 tdvfb_cvg_write(sc, reg, v); 775 } 776 777 static uint8_t 778 tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg) 779 { 780 uint32_t rv; 781 782 tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ); 783 784 rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ); 785 #ifdef TDVFB_DEBUG 786 aprint_normal("cvg_dac_read val %x from reg %x\n", rv, reg); 787 #endif /* TDVFB_DEBUG */ 788 return rv & 0xFF; 789 } 790 791 static void 792 tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 793 { 794 uint32_t wreg; 795 796 wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val; 797 798 #ifdef TDVFB_DEBUG 799 aprint_normal("cvg_dac_write val %x to reg %x (%x)\n", val, reg, 800 wreg); 801 #endif /* TDVFB_DEBUG */ 802 803 tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg); 804 tdvfb_wait(sc); 805 } 806 807 static void 808 tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, int he, 809 uint32_t color) 810 { 811 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 812 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 813 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 814 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 815 sc->sc_linebytes | (sc->sc_linebytes << 16)); 816 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, x | (y << 16)); 817 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 818 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_RECTFILL | 819 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3 | TDV_BLTCMD_DSTTILED | 820 TDV_BLTCMD_CLIPRECT ); 821 tdvfb_wait(sc); 822 } 823 824 static void 825 tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, int yd, int wi, 826 int he) 827 { 828 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 829 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 830 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 831 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 832 sc->sc_linebytes | (sc->sc_linebytes << 16)); 833 tdvfb_cvg_write(sc, TDV_OFF_BLTSRCXY, xs | (ys << 16)); 834 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, xd | (yd << 16)); 835 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 836 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_SCR2SCR | 837 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3); 838 839 tdvfb_wait(sc); 840 } 841 842 static void 843 tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 844 { 845 struct tdvfb_softc *sc; 846 struct rasops_info *ri; 847 struct vcons_screen *scr; 848 int x, ys, yd, wi, he; 849 850 ri = cookie; 851 scr = ri->ri_hw; 852 sc = scr->scr_cookie; 853 854 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 855 x = ri->ri_xorigin; 856 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 857 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 858 wi = ri->ri_emuwidth; 859 he = ri->ri_font->fontheight * nrows; 860 tdvfb_bitblt(sc, x, ys, x, yd, wi, he); 861 } 862 } 863 864 static void 865 tdvfb_eraserows(void *cookie, int row, int nrows, long fillattr) 866 { 867 868 struct tdvfb_softc *sc; 869 struct rasops_info *ri; 870 struct vcons_screen *scr; 871 int x, y, wi, he, fg, bg, ul; 872 873 ri = cookie; 874 scr = ri->ri_hw; 875 sc = scr->scr_cookie; 876 877 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 878 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 879 if ((row == 0) && (nrows == ri->ri_rows)) 880 tdvfb_rectfill(sc, 0, 0, ri->ri_width, 881 ri->ri_height, ri->ri_devcmap[bg]); 882 else { 883 x = ri->ri_xorigin; 884 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 885 wi = ri->ri_emuwidth; 886 he = ri->ri_font->fontheight * nrows; 887 tdvfb_rectfill(sc, x, y, wi, he, ri->ri_devcmap[bg]); 888 } 889 } 890 } 891 892
Indexes created Tue Sep 30 20:09:53 GMT 2025