tdvfb.c revision 1.4
1 /* $NetBSD: tdvfb.c,v 1.4 2012/07/29 20:31:53 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * A console driver for 3Dfx Voodoo2 (CVG) and 3Dfx Voodoo Graphics (SST-1). 33 * 34 * 3Dfx Glide 2.x source code, Linux driver by Ghozlane Toumi, and 35 * "Voodoo2 Graphics Engine for 3D Game Acceleration" document were used as 36 * reference. wscons attachment code based mostly on genfb by Michael 37 * Lorenz. 38 * 39 * This driver currently only support boards with ICS GENDAC (which seems to 40 * be most popular, however at least two different DACs were used with CVG). 41 * 42 * TODO (in no particular order): 43 * - Finally fix 16-bit depth handling on big-endian machines. 44 * - Expose card to userspace through /dev/3dfx compatible device file 45 * (for Glide). 46 * - Allow mmap'ing of registers through wscons access op. 47 * - Complete wscons emul ops acceleration support. 48 * - Add support for others DACs (need hardware). 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: tdvfb.c,v 1.4 2012/07/29 20:31:53 rkujawa Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/endian.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 #include <dev/pci/pciio.h> 64 65 #include <dev/pci/tdvfbreg.h> 66 #include <dev/pci/tdvfbvar.h> 67 68 #include <dev/videomode/videomode.h> 69 #include <dev/pci/wsdisplay_pci.h> 70 71 #include "opt_wsemul.h" 72 #include "opt_tdvfb.h" 73 74 #define MAXLOOP 4096 75 76 static int tdvfb_match(device_t, cfdata_t, void *); 77 static void tdvfb_attach(device_t, device_t, void *); 78 79 static uint32_t tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg); 80 static void tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, 81 uint32_t val); 82 static void tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, 83 uint32_t bits); 84 static void tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, 85 uint32_t bits); 86 static uint8_t tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg); 87 static void tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, 88 uint32_t val); 89 static void tdvfb_wait(struct tdvfb_softc *sc); 90 91 static bool tdvfb_init(struct tdvfb_softc *sc); 92 static void tdvfb_fbiinit_defaults(struct tdvfb_softc *sc); 93 static size_t tdvfb_mem_size(struct tdvfb_softc *sc); 94 95 static bool tdvfb_videomode_set(struct tdvfb_softc *sc); 96 static void tdvfb_videomode_dac(struct tdvfb_softc *sc); 97 98 static bool tdvfb_gendac_detect(struct tdvfb_softc *sc); 99 static struct tdvfb_dac_timing tdvfb_gendac_calc_pll(int freq); 100 static void tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 101 struct tdvfb_dac_timing *timing); 102 static void tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 103 struct tdvfb_dac_timing *timing); 104 105 static paddr_t tdvfb_mmap(void *v, void *vs, off_t offset, int prot); 106 static int tdvfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 107 struct lwp *l); 108 static void tdvfb_init_screen(void *cookie, struct vcons_screen *scr, 109 int existing, long *defattr); 110 static void tdvfb_init_palette(struct tdvfb_softc *sc); 111 /* blitter support */ 112 static void tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, 113 int he, uint32_t color); 114 static void tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, 115 int yd, int wi, int he); 116 /* accelerated raster ops */ 117 static void tdvfb_eraserows(void *cookie, int row, int nrows, 118 long fillattr); 119 static void tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows); 120 121 CFATTACH_DECL_NEW(tdvfb, sizeof(struct tdvfb_softc), 122 tdvfb_match, tdvfb_attach, NULL, NULL); 123 124 struct wsdisplay_accessops tdvfb_accessops = { 125 tdvfb_ioctl, 126 tdvfb_mmap, 127 NULL, /* alloc_screen */ 128 NULL, /* free_screen */ 129 NULL, /* show_screen */ 130 NULL, /* load_font */ 131 NULL, /* pollc */ 132 NULL /* scroll */ 133 }; 134 135 static int 136 tdvfb_match(device_t parent, cfdata_t match, void *aux) 137 { 138 const struct pci_attach_args *pa = (const struct pci_attach_args *)aux; 139 140 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 141 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2)) 142 return 100; 143 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 144 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO)) 145 return 100; 146 147 return 0; 148 } 149 150 static void 151 tdvfb_attach(device_t parent, device_t self, void *aux) 152 { 153 struct tdvfb_softc *sc = device_private(self); 154 struct wsemuldisplaydev_attach_args ws_aa; 155 struct rasops_info *ri; 156 const struct pci_attach_args *pa = aux; 157 pcireg_t screg; 158 bool console; 159 long defattr; 160 161 #ifdef TDVFB_CONSOLE 162 console = true; 163 #else 164 console = false; 165 #endif 166 167 sc->sc_pc = pa->pa_pc; 168 sc->sc_pcitag = pa->pa_tag; 169 sc->sc_dev = self; 170 171 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2) 172 sc->sc_voodootype = TDV_VOODOO_2; 173 else 174 sc->sc_voodootype = TDV_VOODOO_1; 175 176 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 177 PCI_COMMAND_STATUS_REG); 178 screg |= PCI_COMMAND_MEM_ENABLE; 179 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 180 screg); 181 182 pci_aprint_devinfo(pa, NULL); 183 184 /* map the BAR */ 185 if (pci_mapreg_map(pa, TDV_MM_BAR, PCI_MAPREG_TYPE_MEM, 0, 186 &sc->sc_cvgt, &sc->sc_cvgh, &sc->sc_cvg_pa, 0) != 0 ) { 187 aprint_error_dev(sc->sc_dev, "unable to map CVG BAR"); 188 return; 189 } 190 191 /* Map the framebuffer. */ 192 if (bus_space_subregion(sc->sc_cvgt, sc->sc_cvgh, TDV_OFF_FB, 193 TDV_FB_SIZE, &sc->sc_fbh)) { 194 aprint_error_dev(sc->sc_dev, "unable to map the framebuffer"); 195 } 196 197 aprint_normal_dev(sc->sc_dev, "registers at 0x%08x, fb at 0x%08x\n", 198 (uint32_t) sc->sc_cvg_pa, (uint32_t) sc->sc_cvg_pa + TDV_OFF_FB); 199 200 /* Do the low level setup. */ 201 if (!tdvfb_init(sc)) { 202 aprint_error_dev(sc->sc_dev, "could not initialize CVG\n"); 203 return; 204 } 205 206 /* 207 * The card is alive now, let's check how much framebuffer memory 208 * do we have. 209 */ 210 sc->sc_memsize = tdvfb_mem_size(sc); 211 212 aprint_normal_dev(sc->sc_dev, "%d MB framebuffer memory present\n", 213 sc->sc_memsize / 1024 / 1024); 214 215 /* Select video mode, 800x600 32bpp 60Hz by default... */ 216 sc->sc_width = 800; 217 sc->sc_height = 600; 218 #if BYTE_ORDER == BIG_ENDIAN 219 sc->sc_bpp = 32; /* XXX: 16 would allow blitter use. */ 220 #else 221 sc->sc_bpp = 16; 222 #endif 223 sc->sc_linebytes = 1024 * (sc->sc_bpp / 8); 224 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, sc->sc_height, 60); 225 226 aprint_normal_dev(sc->sc_dev, "setting %dx%d %d bpp resolution\n", 227 sc->sc_width, sc->sc_height, sc->sc_bpp); 228 229 tdvfb_videomode_set(sc); 230 231 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 232 "default", 233 0, 0, 234 NULL, 235 8, 16, 236 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 237 NULL 238 }; 239 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 240 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 241 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 242 243 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 244 &tdvfb_accessops); 245 sc->vd.init_screen = tdvfb_init_screen; 246 247 ri = &sc->sc_console_screen.scr_ri; 248 249 tdvfb_init_palette(sc); 250 251 if (console) { 252 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 253 &defattr); 254 255 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC | 256 VCONS_DONT_READ; 257 vcons_redraw_screen(&sc->sc_console_screen); 258 259 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 260 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 261 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 262 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 263 264 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 265 defattr); 266 vcons_replay_msgbuf(&sc->sc_console_screen); 267 } else if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 268 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 269 &defattr); 270 } 271 272 ws_aa.console = console; 273 ws_aa.scrdata = &sc->sc_screenlist; 274 ws_aa.accessops = &tdvfb_accessops; 275 ws_aa.accesscookie = &sc->vd; 276 277 config_found(sc->sc_dev, &ws_aa, wsemuldisplaydevprint); 278 } 279 280 static void 281 tdvfb_init_palette(struct tdvfb_softc *sc) 282 { 283 int i, j; 284 285 j = 0; 286 for (i = 0; i < 256; i++) { 287 sc->sc_cmap_red[i] = rasops_cmap[j]; 288 sc->sc_cmap_green[i] = rasops_cmap[j + 1]; 289 sc->sc_cmap_blue[i] = rasops_cmap[j + 2]; 290 j += 3; 291 } 292 } 293 294 static void 295 tdvfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 296 long *defattr) 297 { 298 struct tdvfb_softc *sc = cookie; 299 struct rasops_info *ri = &scr->scr_ri; 300 301 wsfont_init(); 302 303 ri->ri_depth = sc->sc_bpp; 304 ri->ri_width = sc->sc_width; 305 ri->ri_height = sc->sc_height; 306 ri->ri_stride = sc->sc_linebytes; 307 ri->ri_flg = RI_CENTER; 308 309 #if BYTE_ORDER == BIG_ENDIAN 310 #if 0 /* XXX: not yet :( */ 311 if (sc->sc_bpp == 16) 312 ri->ri_flg |= RI_BITSWAP; 313 #endif 314 #endif 315 316 ri->ri_bits = (char *) bus_space_vaddr(sc->sc_cvgt, sc->sc_fbh); 317 318 scr->scr_flags |= VCONS_DONT_READ; 319 320 rasops_init(ri, 0, 0); 321 ri->ri_caps = WSSCREEN_WSCOLORS; 322 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 323 sc->sc_width / ri->ri_font->fontwidth); 324 325 ri->ri_hw = scr; 326 327 /* If we are a Voodoo2 and running in 16 bits try to use blitter. */ 328 if ((sc->sc_voodootype == TDV_VOODOO_2) && (sc->sc_bpp == 16)) { 329 aprint_normal_dev(sc->sc_dev, "using CVG blitter\n"); 330 ri->ri_ops.eraserows = tdvfb_eraserows; 331 ri->ri_ops.copyrows = tdvfb_copyrows; 332 } 333 } 334 335 static bool 336 tdvfb_videomode_set(struct tdvfb_softc *sc) 337 { 338 uint32_t fbiinit1, fbiinit5, fbiinit6, lfbmode; 339 uint16_t vbackporch, vsyncon, vsyncoff; 340 uint16_t hbackporch, hsyncon, hsyncoff; 341 uint16_t yheight, xwidth; 342 343 yheight = sc->sc_videomode->vdisplay; 344 xwidth = sc->sc_videomode->hdisplay; 345 346 vbackporch = sc->sc_videomode->vtotal - sc->sc_videomode->vsync_end; 347 hbackporch = sc->sc_videomode->htotal - sc->sc_videomode->hsync_end; 348 349 vsyncon = sc->sc_videomode->vsync_end - sc->sc_videomode->vsync_start; 350 hsyncon = sc->sc_videomode->hsync_end - sc->sc_videomode->hsync_start; 351 352 vsyncoff = sc->sc_videomode->vtotal - vsyncon; 353 hsyncoff = sc->sc_videomode->htotal - hsyncon; 354 #ifdef TDVFB_DEBUG 355 aprint_normal_dev(sc->sc_dev, 356 "xy %d %d hbp %d vbp %d, hson %d, hsoff %d, vson %d, vsoff %d\n", 357 xwidth, yheight, hbackporch, vbackporch, hsyncon, hsyncoff, 358 vsyncon, vsyncoff); 359 #endif /* TDVFB_DEBUG */ 360 361 sc->vid_timing = tdvfb_gendac_calc_pll(sc->sc_videomode->dot_clock); 362 363 if(sc->sc_voodootype == TDV_VOODOO_2) 364 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64 * 2; 365 else 366 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64; 367 368 tdvfb_cvg_write(sc, TDV_OFF_NOPCMD, 0); 369 tdvfb_wait(sc); 370 371 /* enable writing to fbiinit regs, reset, disable DRAM refresh */ 372 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 373 TDV_INITENABLE_EN_INIT); 374 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 375 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 376 TDV_FBIINIT0_FIFO_RST); 377 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 378 tdvfb_wait(sc); 379 380 /* program video timings into CVG/SST-1*/ 381 tdvfb_cvg_write(sc, TDV_OFF_VDIMENSIONS, yheight << 16 | (xwidth - 1)); 382 tdvfb_cvg_write(sc, TDV_OFF_BACKPORCH, vbackporch << 16 | 383 (hbackporch - 2)); 384 tdvfb_cvg_write(sc, TDV_OFF_HSYNC, hsyncoff << 16 | (hsyncon - 1)); 385 tdvfb_cvg_write(sc, TDV_OFF_VSYNC, vsyncoff << 16 | vsyncon); 386 387 tdvfb_videomode_dac(sc); 388 389 fbiinit1 = ((tdvfb_cvg_read(sc, TDV_OFF_FBIINIT1) & 390 TDV_FBIINIT1_VIDMASK) | 391 TDV_FBIINIT1_DR_DATA | 392 TDV_FBIINIT1_DR_BLANKING | 393 TDV_FBIINIT1_DR_HVSYNC | 394 TDV_FBIINIT1_DR_DCLK | 395 TDV_FBIINIT1_IN_VCLK_2X ); 396 397 if (sc->sc_voodootype == TDV_VOODOO_2) { 398 fbiinit1 |= ((sc->sc_x_tiles & 0x20) >> 5) 399 << TDV_FBIINIT1_TILES_X_MSB | ((sc->sc_x_tiles & 0x1e) >> 1) 400 << TDV_FBIINIT1_TILES_X; 401 fbiinit6 = (sc->sc_x_tiles & 0x1) << TDV_FBIINIT6_TILES_X_LSB; 402 } else 403 fbiinit1 |= sc->sc_x_tiles << TDV_FBIINIT1_TILES_X; 404 405 fbiinit1 |= TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC; 406 407 if (sc->sc_voodootype == TDV_VOODOO_2) { 408 fbiinit5 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT5) 409 & TDV_FBIINIT5_VIDMASK; 410 if (sc->sc_videomode->flags & VID_PHSYNC) 411 fbiinit5 |= TDV_FBIINIT5_PHSYNC; 412 if (sc->sc_videomode->flags & VID_PVSYNC) 413 fbiinit5 |= TDV_FBIINIT5_PVSYNC; 414 } 415 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 416 if (sc->sc_voodootype == TDV_VOODOO_2) { 417 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 418 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT5, fbiinit5); 419 } 420 tdvfb_wait(sc); 421 422 /* unreset, enable DRAM refresh */ 423 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 424 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 425 TDV_FBIINIT0_FIFO_RST); 426 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 427 /* diable access to FBIINIT regs */ 428 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 429 TDV_INITENABLE_EN_FIFO); 430 tdvfb_wait(sc); 431 432 if (sc->sc_bpp == 16) 433 lfbmode = TDV_LFBMODE_565; 434 else if (sc->sc_bpp == 32) 435 lfbmode = TDV_LFBMODE_8888; 436 else 437 return false; 438 439 #if BYTE_ORDER == BIG_ENDIAN 440 lfbmode |= TDV_LFBMODE_BSW_WR | TDV_LFBMODE_BSW_RD; 441 #endif 442 443 tdvfb_cvg_write(sc, TDV_OFF_LFBMODE, lfbmode); 444 445 return true; 446 } 447 448 /* 449 * Update DAC parameters for selected video mode. 450 */ 451 static void 452 tdvfb_videomode_dac(struct tdvfb_softc *sc) 453 { 454 uint32_t fbiinit2, fbiinit3; 455 456 /* remember current FBIINIT settings */ 457 fbiinit2 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); 458 fbiinit3 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT3); 459 460 /* remap DAC */ 461 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 462 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 463 464 tdvfb_cvg_dac_write(sc, TDV_GENDAC_CMD, TDV_GENDAC_CMD_16BITS); 465 466 tdvfb_gendac_set_vid_timing(sc, &(sc->vid_timing)); 467 468 /* disable remapping */ 469 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 470 TDV_INITENABLE_EN_INIT); 471 /* restore */ 472 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 473 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit3); 474 } 475 476 /* 477 * Check how much memory do we have. Actually, Voodoo1/2 has separate 478 * framebuffer and texture memory. This function only checks for framebuffer 479 * memory. Texture memory ramains unused. 480 */ 481 static size_t 482 tdvfb_mem_size(struct tdvfb_softc *sc) 483 { 484 size_t mem_size; 485 uint32_t vram_test4, vram_test2; 486 487 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0, 0x11aabbaa); 488 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x100000, 0x22aabbaa); 489 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x200000, 0x44aabbaa); 490 491 vram_test4 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x400000); 492 vram_test2 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x200000); 493 494 if (vram_test4 == 0x44aabbaa) 495 mem_size = 4*1024*1024; 496 else if (vram_test2 == 0x22aabbaa) { 497 mem_size = 2*1024*1024; 498 } else 499 mem_size = 1*1024*1024; 500 501 return mem_size; 502 } 503 504 /* do the low level init of Voodoo board */ 505 static bool 506 tdvfb_init(struct tdvfb_softc *sc) 507 { 508 /* undocumented - found in glide code */ 509 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_DISABLE_REG, 0); 510 /* allow write to hardware initialization registers */ 511 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 512 TDV_INITENABLE_EN_INIT); 513 514 /* reset the board */ 515 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 516 tdvfb_wait(sc); 517 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 518 TDV_FBIINIT0_FIFO_RST); 519 tdvfb_wait(sc); 520 521 /* disable video RAM refresh */ 522 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 523 tdvfb_wait(sc); 524 525 /* on voodoo1 I had to read FBIINIT2 before remapping, 526 * otherwise weird things were happening, on v2 it works just fine */ 527 /* tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); */ 528 529 /* remap DAC */ 530 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 531 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 532 533 /* detect supported DAC, TODO: we really should support other DACs */ 534 if(!tdvfb_gendac_detect(sc)) { 535 aprint_error_dev(sc->sc_dev, "could not detect ICS GENDAC\n"); 536 return false; 537 } 538 539 /* calculate PLL used to drive the chips (graphics clock) */ 540 if(sc->sc_voodootype == TDV_VOODOO_2) 541 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_CVG_CLK); 542 else 543 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_SST_CLK); 544 545 /* set PLL for gfx clock */ 546 tdvfb_gendac_set_cvg_timing(sc, &(sc->cvg_timing)); 547 548 /* don't remap the DAC anymore */ 549 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 550 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_EN_FIFO); 551 552 /* set FBIINIT registers to some default values that make sense */ 553 tdvfb_fbiinit_defaults(sc); 554 555 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 556 TDV_INITENABLE_EN_FIFO); 557 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_ENABLE_REG, 0); 558 559 return true; 560 } 561 562 static void 563 tdvfb_fbiinit_defaults(struct tdvfb_softc *sc) 564 { 565 uint32_t fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6; 566 567 fbiinit0 = TDV_FBIINIT0_VGA_PASS; /* disable VGA passthrough */ 568 fbiinit1 = /*TDV_FBIINIT1_PCIWAIT |*/ /* one wait state for PCI write */ 569 TDV_FBIINIT1_LFB_EN | /* enable lfb reads */ 570 TDV_FBIINIT1_VIDEO_RST | /* video timing reset */ 571 10 << TDV_FBIINIT1_TILES_X | /* tiles x/horizontal */ 572 TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC ; 573 574 fbiinit2 = TDV_FBIINIT2_SWB_ALG |/* swap buffer use DAC sync */ 575 TDV_FBIINIT2_FAST_RAS | /* fast RAS read */ 576 TDV_FBIINIT2_DRAM_OE | /* enable DRAM OE */ 577 TDV_FBIINIT2_DRAM_REFR | /* enable DRAM refresh */ 578 TDV_FBIINIT2_FIFO_RDA | /* FIFO read ahead */ 579 TDV_FBIINIT2_DRAM_REF16 << TDV_FBIINIT2_DRAM_REFLD; /* 16 ms */ 580 581 fbiinit3 = TDV_FBIINIT3_TREX_DIS; /* disable texture mapping */ 582 583 fbiinit4 = /*TDV_FBIINIT4_PCIWAIT|*/ /* one wait state for PCI write */ 584 TDV_FBIINIT4_LFB_RDA; /* lfb read ahead */ 585 586 fbiinit6 = 0; 587 #ifdef TDVFB_DEBUG 588 aprint_normal("fbiinit: 0 %x, 1 %x, 2 %x, 3 %x, 4 %x, 6 %x\n", 589 fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6); 590 #endif /* TDVFB_DEBUG */ 591 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT0, fbiinit0); 592 tdvfb_wait(sc); 593 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 594 tdvfb_wait(sc); 595 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 596 tdvfb_wait(sc); 597 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT3, fbiinit3); 598 tdvfb_wait(sc); 599 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT4, fbiinit4); 600 tdvfb_wait(sc); 601 if (sc->sc_voodootype == TDV_VOODOO_2) { 602 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 603 tdvfb_wait(sc); 604 } 605 } 606 607 static void 608 tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 609 struct tdvfb_dac_timing *timing) 610 { 611 uint8_t pllreg; 612 613 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 614 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 615 616 /* write the timing for gfx clock into "slot" 0 */ 617 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0); 618 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 619 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 620 /* select "slot" 0 for output */ 621 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 622 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 623 (pllreg & TDV_GENDAC_VIDPLLMASK) | TDV_GENDAC_PLL_VIDCLK | 624 TDV_GENDAC_PLL_VIDCLK0); 625 tdvfb_wait(sc); 626 tdvfb_wait(sc); 627 #ifdef TDVFB_DEBUG 628 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_0); 629 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 630 aprint_normal("vid read again: %d\n", pllreg); 631 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 632 aprint_normal("vid read again: %d\n", pllreg); 633 #endif /* TDVFB_DEBUG */ 634 } 635 636 static void 637 tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 638 struct tdvfb_dac_timing *timing) 639 { 640 uint8_t pllreg; 641 642 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 643 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 644 645 /* write the timing for gfx clock into "slot" A */ 646 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_A); 647 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 648 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 649 /* select "slot" A for output */ 650 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 651 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 652 (pllreg & TDV_GENDAC_CVGPLLMASK) | TDV_GENDAC_PLL_CVGCLKA); 653 #ifdef TDVFB_DEBUG 654 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_A); 655 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 656 aprint_normal("read again: %d\n", pllreg); 657 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 658 aprint_normal("read again: %d\n", pllreg); 659 #endif /* TDVFB_DEBUG */ 660 tdvfb_wait(sc); 661 } 662 663 static struct tdvfb_dac_timing 664 tdvfb_gendac_calc_pll(int freq) 665 { 666 int n1, n2; 667 int m, mdbl; 668 int best_m, best_n1, best_error; 669 int fout; 670 struct tdvfb_dac_timing timing; 671 672 best_m = -1; best_n1 = -1; 673 674 /* select highest possible n2, check n2 * fCLK < TDV_GENDAC_MAXVCO */ 675 for (n2 = TDV_GENDAC_MAX_N2; n2 >= TDV_GENDAC_MIN_N2; n2--) { 676 if ((freq * (1 << n2)) < TDV_GENDAC_MAXVCO) 677 break; 678 } 679 680 best_error = freq; 681 682 /* 683 * m+2 2^n2 * fOUT 684 * ---- = ----------- 685 * n1+2 fREF 686 */ 687 for (n1 = TDV_GENDAC_MIN_N1; n1 <= TDV_GENDAC_MAX_N1; n1++) { 688 /* loop mostly inspired by Linux driver */ 689 mdbl = (2 * freq * (1 << n2)*(n1 + 2)) / TDV_GENDAC_REFFREQ - 4; 690 if (mdbl % 2) 691 m = mdbl/2+1; 692 else 693 m = mdbl/2; 694 695 if(m > TDV_GENDAC_MAX_M) 696 break; 697 698 fout = (TDV_GENDAC_REFFREQ * (m + 2)) / ((1 << n2) * (n1 + 2)); 699 if ((abs(fout - freq) < best_error) && (m > 0)) { 700 best_n1 = n1; 701 best_m = m; 702 best_error = abs(fout - freq); 703 if (200*best_error < freq) break; 704 } 705 706 } 707 708 fout = (TDV_GENDAC_REFFREQ * (best_m + 2)) / ((1 << n2) * (best_n1 + 2)); 709 timing.m = best_m; 710 timing.n = (n2 << 5) | best_n1; 711 timing.fout = fout; 712 713 #ifdef TDVFB_DEBUG 714 aprint_normal("tdvfb_gendac_calc_pll ret: m %d, n %d, fout %d kHz\n", 715 timing.m, timing.n, timing.fout); 716 #endif /* TDVFB_DEBUG */ 717 718 return timing; 719 } 720 721 static bool 722 tdvfb_gendac_detect(struct tdvfb_softc *sc) 723 { 724 uint8_t m_f1, m_f7, m_fb; 725 uint8_t n_f1, n_f7, n_fb; 726 727 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x1); 728 m_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 729 n_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 730 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x7); 731 m_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 732 n_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 733 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0xB); 734 m_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 735 n_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 736 737 if( (m_f1 == TDV_GENDAC_DFLT_F1_M) && 738 (n_f1 == TDV_GENDAC_DFLT_F1_N) && 739 (m_f7 == TDV_GENDAC_DFLT_F7_M) && 740 (n_f7 == TDV_GENDAC_DFLT_F7_N) && 741 (n_fb == TDV_GENDAC_DFLT_FB_N) && 742 (n_fb == TDV_GENDAC_DFLT_FB_N) ) { 743 aprint_normal_dev(sc->sc_dev, "ICS 5342 GENDAC\n"); 744 return true; 745 } 746 747 return false; 748 } 749 750 static void 751 tdvfb_wait(struct tdvfb_softc *sc) 752 { 753 uint32_t x, cnt; 754 cnt = 0; 755 for (x = 0; x < MAXLOOP; x++) { 756 if (tdvfb_cvg_read(sc, TDV_OFF_STATUS) & TDV_STATUS_FBI_BUSY) 757 cnt = 0; 758 else 759 cnt++; 760 761 if (cnt >= 5) /* Voodoo2 specs suggest at least 3 */ 762 break; 763 } 764 765 if (x == MAXLOOP) 766 /* 767 * The console probably isn't working now anyway, so maybe 768 * let's panic... At least it will drop into ddb if some other 769 * device a console. 770 */ 771 panic("tdvfb is stuck!\n"); 772 } 773 774 static uint32_t 775 tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg) 776 { 777 uint32_t rv; 778 rv = bus_space_read_4(sc->sc_cvgt, sc->sc_cvgh, reg); 779 #ifdef TDVFB_DEBUG 780 aprint_normal("cvg_read val %x from reg %x\n", rv, reg); 781 #endif /* TDVFB_DEBUG */ 782 return rv; 783 } 784 785 static void 786 tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 787 { 788 #ifdef TDVFB_DEBUG 789 aprint_normal("cvg_write val %x to reg %x\n", val, reg); 790 #endif /* TDVFB_DEBUG */ 791 bus_space_write_4(sc->sc_cvgt, sc->sc_cvgh, reg, val); 792 } 793 794 static void 795 tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 796 { 797 uint32_t v; 798 v = tdvfb_cvg_read(sc, reg) | bits; 799 tdvfb_cvg_write(sc, reg, v); 800 } 801 802 static void 803 tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 804 { 805 uint32_t v; 806 v = tdvfb_cvg_read(sc, reg) & ~bits; 807 tdvfb_cvg_write(sc, reg, v); 808 } 809 810 static uint8_t 811 tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg) 812 { 813 uint32_t rv; 814 815 tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ); 816 817 rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ); 818 #ifdef TDVFB_DEBUG 819 aprint_normal("cvg_dac_read val %x from reg %x\n", rv, reg); 820 #endif /* TDVFB_DEBUG */ 821 return rv & 0xFF; 822 } 823 824 static void 825 tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 826 { 827 uint32_t wreg; 828 829 wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val; 830 831 #ifdef TDVFB_DEBUG 832 aprint_normal("cvg_dac_write val %x to reg %x (%x)\n", val, reg, 833 wreg); 834 #endif /* TDVFB_DEBUG */ 835 836 tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg); 837 tdvfb_wait(sc); 838 } 839 840 static void 841 tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, int he, 842 uint32_t color) 843 { 844 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 845 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 846 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 847 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 848 sc->sc_linebytes | (sc->sc_linebytes << 16)); 849 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, x | (y << 16)); 850 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 851 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_RECTFILL | 852 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3 | TDV_BLTCMD_DSTTILED | 853 TDV_BLTCMD_CLIPRECT ); 854 tdvfb_wait(sc); 855 } 856 857 static void 858 tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, int yd, int wi, 859 int he) 860 { 861 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 862 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 863 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 864 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 865 sc->sc_linebytes | (sc->sc_linebytes << 16)); 866 tdvfb_cvg_write(sc, TDV_OFF_BLTSRCXY, xs | (ys << 16)); 867 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, xd | (yd << 16)); 868 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 869 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_SCR2SCR | 870 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3); 871 872 tdvfb_wait(sc); 873 } 874 875 static void 876 tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 877 { 878 struct tdvfb_softc *sc; 879 struct rasops_info *ri; 880 struct vcons_screen *scr; 881 int x, ys, yd, wi, he; 882 883 ri = cookie; 884 scr = ri->ri_hw; 885 sc = scr->scr_cookie; 886 887 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 888 x = ri->ri_xorigin; 889 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 890 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 891 wi = ri->ri_emuwidth; 892 he = ri->ri_font->fontheight * nrows; 893 tdvfb_bitblt(sc, x, ys, x, yd, wi, he); 894 } 895 } 896 897 static void 898 tdvfb_eraserows(void *cookie, int row, int nrows, long fillattr) 899 { 900 901 struct tdvfb_softc *sc; 902 struct rasops_info *ri; 903 struct vcons_screen *scr; 904 int x, y, wi, he, fg, bg, ul; 905 906 ri = cookie; 907 scr = ri->ri_hw; 908 sc = scr->scr_cookie; 909 910 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 911 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 912 if ((row == 0) && (nrows == ri->ri_rows)) 913 tdvfb_rectfill(sc, 0, 0, ri->ri_width, 914 ri->ri_height, ri->ri_devcmap[bg]); 915 else { 916 x = ri->ri_xorigin; 917 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 918 wi = ri->ri_emuwidth; 919 he = ri->ri_font->fontheight * nrows; 920 tdvfb_rectfill(sc, x, y, wi, he, ri->ri_devcmap[bg]); 921 } 922 } 923 } 924 925 static int 926 tdvfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 927 { 928 struct vcons_data *vd; 929 struct tdvfb_softc *sc; 930 struct wsdisplay_fbinfo *wsfbi; 931 struct vcons_screen *ms; 932 933 vd = v; 934 sc = vd->cookie; 935 ms = vd->active; 936 937 switch (cmd) { 938 case WSDISPLAYIO_GTYPE: 939 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 940 return 0; 941 942 case PCI_IOC_CFGREAD: 943 case PCI_IOC_CFGWRITE: 944 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 945 cmd, data, flag, l); 946 947 case WSDISPLAYIO_GET_BUSID: 948 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 949 sc->sc_pcitag, data); 950 951 case WSDISPLAYIO_GINFO: 952 if (ms == NULL) 953 return ENODEV; 954 955 wsfbi = (void*) data; 956 wsfbi->height = ms->scr_ri.ri_height; 957 wsfbi->width = ms->scr_ri.ri_width; 958 wsfbi->depth = ms->scr_ri.ri_depth; 959 wsfbi->cmsize = 256; 960 return 0; 961 962 case WSDISPLAYIO_LINEBYTES: 963 *(u_int*)data = sc->sc_linebytes; 964 return 0; 965 966 case WSDISPLAYIO_SMODE: 967 { 968 int new_mode = *(int*)data; 969 if (new_mode != sc->sc_mode) { 970 sc->sc_mode = new_mode; 971 if(new_mode == WSDISPLAYIO_MODE_EMUL) 972 vcons_redraw_screen(ms); 973 } 974 return 0; 975 } 976 } 977 return EPASSTHROUGH; 978 } 979 980 static paddr_t 981 tdvfb_mmap(void *v, void *vs, off_t offset, int prot) 982 { 983 struct vcons_data *vd; 984 struct tdvfb_softc *sc; 985 paddr_t pa; 986 987 vd = v; 988 sc = vd->cookie; 989 990 if (offset < sc->sc_memsize) { 991 pa = bus_space_mmap(sc->sc_cvgt, sc->sc_fbh + offset, 0, prot, 992 BUS_SPACE_MAP_LINEAR); 993 return pa; 994 } 995 996 return -1; 997 } 998 999
Indexes created Tue Sep 30 20:09:53 GMT 2025