tdvfb.c revision 1.5
1 /* $NetBSD: tdvfb.c,v 1.5 2013/01/31 11:57:07 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * A console driver for 3Dfx Voodoo2 (CVG) and 3Dfx Voodoo Graphics (SST-1). 33 * 34 * 3Dfx Glide 2.x source code, Linux driver by Ghozlane Toumi, and 35 * "Voodoo2 Graphics Engine for 3D Game Acceleration" document were used as 36 * reference. wscons attachment code based mostly on genfb by Michael 37 * Lorenz. 38 * 39 * This driver currently only support boards with ICS GENDAC (which seems to 40 * be most popular, however at least two different DACs were used with CVG). 41 * 42 * TODO (in no particular order): 43 * - Finally fix 16-bit depth handling on big-endian machines. 44 * - Expose card to userspace through /dev/3dfx compatible device file 45 * (for Glide). 46 * - Allow mmap'ing of registers through wscons access op. 47 * - Complete wscons emul ops acceleration support. 48 * - Add support for others DACs (need hardware). 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: tdvfb.c,v 1.5 2013/01/31 11:57:07 rkujawa Exp $"); 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/kernel.h> 57 #include <sys/device.h> 58 #include <sys/endian.h> 59 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pcireg.h> 62 #include <dev/pci/pcidevs.h> 63 #include <dev/pci/pciio.h> 64 65 #include <dev/pci/tdvfbreg.h> 66 #include <dev/pci/tdvfbvar.h> 67 68 #include <dev/videomode/videomode.h> 69 #include <dev/pci/wsdisplay_pci.h> 70 71 #include "opt_wsemul.h" 72 #include "opt_tdvfb.h" 73 74 #define MAXLOOP 4096 75 /* #define TDVFB_DEBUG 1 */ 76 77 static int tdvfb_match(device_t, cfdata_t, void *); 78 static void tdvfb_attach(device_t, device_t, void *); 79 80 static uint32_t tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg); 81 static void tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, 82 uint32_t val); 83 static void tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, 84 uint32_t bits); 85 static void tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, 86 uint32_t bits); 87 static uint8_t tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg); 88 static void tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, 89 uint32_t val); 90 static void tdvfb_wait(struct tdvfb_softc *sc); 91 92 static bool tdvfb_init(struct tdvfb_softc *sc); 93 static void tdvfb_fbiinit_defaults(struct tdvfb_softc *sc); 94 static size_t tdvfb_mem_size(struct tdvfb_softc *sc); 95 96 static bool tdvfb_videomode_set(struct tdvfb_softc *sc); 97 static void tdvfb_videomode_dac(struct tdvfb_softc *sc); 98 99 static bool tdvfb_gendac_detect(struct tdvfb_softc *sc); 100 static struct tdvfb_dac_timing tdvfb_gendac_calc_pll(int freq); 101 static void tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 102 struct tdvfb_dac_timing *timing); 103 static void tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 104 struct tdvfb_dac_timing *timing); 105 106 static paddr_t tdvfb_mmap(void *v, void *vs, off_t offset, int prot); 107 static int tdvfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, 108 struct lwp *l); 109 static void tdvfb_init_screen(void *cookie, struct vcons_screen *scr, 110 int existing, long *defattr); 111 static void tdvfb_init_palette(struct tdvfb_softc *sc); 112 /* blitter support */ 113 static void tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, 114 int he, uint32_t color); 115 static void tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, 116 int yd, int wi, int he); 117 /* accelerated raster ops */ 118 static void tdvfb_eraserows(void *cookie, int row, int nrows, 119 long fillattr); 120 static void tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows); 121 122 CFATTACH_DECL_NEW(tdvfb, sizeof(struct tdvfb_softc), 123 tdvfb_match, tdvfb_attach, NULL, NULL); 124 125 struct wsdisplay_accessops tdvfb_accessops = { 126 tdvfb_ioctl, 127 tdvfb_mmap, 128 NULL, /* alloc_screen */ 129 NULL, /* free_screen */ 130 NULL, /* show_screen */ 131 NULL, /* load_font */ 132 NULL, /* pollc */ 133 NULL /* scroll */ 134 }; 135 136 static int 137 tdvfb_match(device_t parent, cfdata_t match, void *aux) 138 { 139 const struct pci_attach_args *pa = (const struct pci_attach_args *)aux; 140 141 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 142 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2)) 143 return 100; 144 if ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) && 145 (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO)) 146 return 100; 147 148 return 0; 149 } 150 151 static void 152 tdvfb_attach(device_t parent, device_t self, void *aux) 153 { 154 struct tdvfb_softc *sc = device_private(self); 155 struct wsemuldisplaydev_attach_args ws_aa; 156 struct rasops_info *ri; 157 const struct pci_attach_args *pa = aux; 158 pcireg_t screg; 159 bool console; 160 long defattr; 161 162 #ifdef TDVFB_CONSOLE 163 console = true; 164 #else 165 console = false; 166 #endif 167 168 sc->sc_pc = pa->pa_pc; 169 sc->sc_pcitag = pa->pa_tag; 170 sc->sc_dev = self; 171 172 if (PCI_PRODUCT(pa->pa_id) == PCI_PRODUCT_3DFX_VOODOO2) 173 sc->sc_voodootype = TDV_VOODOO_2; 174 else 175 sc->sc_voodootype = TDV_VOODOO_1; 176 177 screg = pci_conf_read(sc->sc_pc, sc->sc_pcitag, 178 PCI_COMMAND_STATUS_REG); 179 screg |= PCI_COMMAND_MEM_ENABLE; 180 pci_conf_write(sc->sc_pc, sc->sc_pcitag, PCI_COMMAND_STATUS_REG, 181 screg); 182 183 pci_aprint_devinfo(pa, NULL); 184 185 /* map the BAR */ 186 if (pci_mapreg_map(pa, TDV_MM_BAR, PCI_MAPREG_TYPE_MEM, 187 BUS_SPACE_MAP_LINEAR, &sc->sc_cvgt, &sc->sc_cvgh, 188 &sc->sc_cvg_pa, 0) != 0 ) { 189 aprint_error_dev(sc->sc_dev, "unable to map CVG BAR"); 190 return; 191 } 192 193 /* Map the framebuffer. */ 194 if (bus_space_subregion(sc->sc_cvgt, sc->sc_cvgh, TDV_OFF_FB, 195 TDV_FB_SIZE, &sc->sc_fbh)) { 196 aprint_error_dev(sc->sc_dev, "unable to map the framebuffer"); 197 } 198 199 aprint_normal_dev(sc->sc_dev, "registers at 0x%08x, fb at 0x%08x\n", 200 (uint32_t) sc->sc_cvg_pa, (uint32_t) sc->sc_cvg_pa + TDV_OFF_FB); 201 202 /* Do the low level setup. */ 203 if (!tdvfb_init(sc)) { 204 aprint_error_dev(sc->sc_dev, "could not initialize CVG\n"); 205 return; 206 } 207 208 /* 209 * The card is alive now, let's check how much framebuffer memory 210 * do we have. 211 */ 212 sc->sc_memsize = tdvfb_mem_size(sc); 213 214 aprint_normal_dev(sc->sc_dev, "%d MB framebuffer memory present\n", 215 sc->sc_memsize / 1024 / 1024); 216 217 /* Select video mode, 800x600 32bpp 60Hz by default... */ 218 sc->sc_width = 800; 219 sc->sc_height = 600; 220 #if BYTE_ORDER == BIG_ENDIAN 221 sc->sc_bpp = 32; /* XXX: 16 would allow blitter use. */ 222 #else 223 sc->sc_bpp = 16; 224 #endif 225 sc->sc_linebytes = 1024 * (sc->sc_bpp / 8); 226 sc->sc_videomode = pick_mode_by_ref(sc->sc_width, sc->sc_height, 60); 227 228 aprint_normal_dev(sc->sc_dev, "setting %dx%d %d bpp resolution\n", 229 sc->sc_width, sc->sc_height, sc->sc_bpp); 230 231 tdvfb_videomode_set(sc); 232 233 sc->sc_defaultscreen_descr = (struct wsscreen_descr){ 234 "default", 235 0, 0, 236 NULL, 237 8, 16, 238 WSSCREEN_WSCOLORS | WSSCREEN_HILIT, 239 NULL 240 }; 241 sc->sc_screens[0] = &sc->sc_defaultscreen_descr; 242 sc->sc_screenlist = (struct wsscreen_list){1, sc->sc_screens}; 243 sc->sc_mode = WSDISPLAYIO_MODE_EMUL; 244 245 vcons_init(&sc->vd, sc, &sc->sc_defaultscreen_descr, 246 &tdvfb_accessops); 247 sc->vd.init_screen = tdvfb_init_screen; 248 249 ri = &sc->sc_console_screen.scr_ri; 250 251 tdvfb_init_palette(sc); 252 253 if (console) { 254 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 255 &defattr); 256 257 sc->sc_console_screen.scr_flags |= VCONS_SCREEN_IS_STATIC | 258 VCONS_DONT_READ; 259 vcons_redraw_screen(&sc->sc_console_screen); 260 261 sc->sc_defaultscreen_descr.textops = &ri->ri_ops; 262 sc->sc_defaultscreen_descr.capabilities = ri->ri_caps; 263 sc->sc_defaultscreen_descr.nrows = ri->ri_rows; 264 sc->sc_defaultscreen_descr.ncols = ri->ri_cols; 265 266 wsdisplay_cnattach(&sc->sc_defaultscreen_descr, ri, 0, 0, 267 defattr); 268 vcons_replay_msgbuf(&sc->sc_console_screen); 269 } else if (sc->sc_console_screen.scr_ri.ri_rows == 0) { 270 vcons_init_screen(&sc->vd, &sc->sc_console_screen, 1, 271 &defattr); 272 } 273 274 ws_aa.console = console; 275 ws_aa.scrdata = &sc->sc_screenlist; 276 ws_aa.accessops = &tdvfb_accessops; 277 ws_aa.accesscookie = &sc->vd; 278 279 config_found(sc->sc_dev, &ws_aa, wsemuldisplaydevprint); 280 } 281 282 static void 283 tdvfb_init_palette(struct tdvfb_softc *sc) 284 { 285 int i, j; 286 287 j = 0; 288 for (i = 0; i < 256; i++) { 289 sc->sc_cmap_red[i] = rasops_cmap[j]; 290 sc->sc_cmap_green[i] = rasops_cmap[j + 1]; 291 sc->sc_cmap_blue[i] = rasops_cmap[j + 2]; 292 j += 3; 293 } 294 } 295 296 static void 297 tdvfb_init_screen(void *cookie, struct vcons_screen *scr, int existing, 298 long *defattr) 299 { 300 struct tdvfb_softc *sc = cookie; 301 struct rasops_info *ri = &scr->scr_ri; 302 303 wsfont_init(); 304 305 ri->ri_depth = sc->sc_bpp; 306 ri->ri_width = sc->sc_width; 307 ri->ri_height = sc->sc_height; 308 ri->ri_stride = sc->sc_linebytes; 309 ri->ri_flg = RI_CENTER; 310 311 #if BYTE_ORDER == BIG_ENDIAN 312 #if 0 /* XXX: not yet :( */ 313 if (sc->sc_bpp == 16) 314 ri->ri_flg |= RI_BITSWAP; 315 #endif 316 #endif 317 318 ri->ri_bits = (char *) bus_space_vaddr(sc->sc_cvgt, sc->sc_fbh); 319 #ifdef TDVFB_DEBUG 320 aprint_normal_dev(sc->sc_dev, "fb handle: %lx, ri_bits: %p\n", sc->sc_fbh, ri->ri_bits); 321 #endif /* TDVFB_DEBUG */ 322 323 scr->scr_flags |= VCONS_DONT_READ; 324 325 rasops_init(ri, 0, 0); 326 ri->ri_caps = WSSCREEN_WSCOLORS; 327 rasops_reconfig(ri, sc->sc_height / ri->ri_font->fontheight, 328 sc->sc_width / ri->ri_font->fontwidth); 329 330 ri->ri_hw = scr; 331 332 /* If we are a Voodoo2 and running in 16 bits try to use blitter. */ 333 if ((sc->sc_voodootype == TDV_VOODOO_2) && (sc->sc_bpp == 16)) { 334 aprint_normal_dev(sc->sc_dev, "using CVG blitter\n"); 335 ri->ri_ops.eraserows = tdvfb_eraserows; 336 ri->ri_ops.copyrows = tdvfb_copyrows; 337 } 338 } 339 340 static bool 341 tdvfb_videomode_set(struct tdvfb_softc *sc) 342 { 343 uint32_t fbiinit1, fbiinit5, fbiinit6, lfbmode; 344 uint16_t vbackporch, vsyncon, vsyncoff; 345 uint16_t hbackporch, hsyncon, hsyncoff; 346 uint16_t yheight, xwidth; 347 348 yheight = sc->sc_videomode->vdisplay; 349 xwidth = sc->sc_videomode->hdisplay; 350 351 vbackporch = sc->sc_videomode->vtotal - sc->sc_videomode->vsync_end; 352 hbackporch = sc->sc_videomode->htotal - sc->sc_videomode->hsync_end; 353 354 vsyncon = sc->sc_videomode->vsync_end - sc->sc_videomode->vsync_start; 355 hsyncon = sc->sc_videomode->hsync_end - sc->sc_videomode->hsync_start; 356 357 vsyncoff = sc->sc_videomode->vtotal - vsyncon; 358 hsyncoff = sc->sc_videomode->htotal - hsyncon; 359 #ifdef TDVFB_DEBUG 360 aprint_normal_dev(sc->sc_dev, 361 "xy %d %d hbp %d vbp %d, hson %d, hsoff %d, vson %d, vsoff %d\n", 362 xwidth, yheight, hbackporch, vbackporch, hsyncon, hsyncoff, 363 vsyncon, vsyncoff); 364 #endif /* TDVFB_DEBUG */ 365 366 sc->vid_timing = tdvfb_gendac_calc_pll(sc->sc_videomode->dot_clock); 367 368 if(sc->sc_voodootype == TDV_VOODOO_2) 369 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64 * 2; 370 else 371 sc->sc_x_tiles = (sc->sc_videomode->hdisplay + 63 ) / 64; 372 373 tdvfb_cvg_write(sc, TDV_OFF_NOPCMD, 0); 374 tdvfb_wait(sc); 375 376 /* enable writing to fbiinit regs, reset, disable DRAM refresh */ 377 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 378 TDV_INITENABLE_EN_INIT); 379 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 380 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 381 TDV_FBIINIT0_FIFO_RST); 382 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 383 tdvfb_wait(sc); 384 385 /* program video timings into CVG/SST-1*/ 386 tdvfb_cvg_write(sc, TDV_OFF_VDIMENSIONS, yheight << 16 | (xwidth - 1)); 387 tdvfb_cvg_write(sc, TDV_OFF_BACKPORCH, vbackporch << 16 | 388 (hbackporch - 2)); 389 tdvfb_cvg_write(sc, TDV_OFF_HSYNC, hsyncoff << 16 | (hsyncon - 1)); 390 tdvfb_cvg_write(sc, TDV_OFF_VSYNC, vsyncoff << 16 | vsyncon); 391 392 tdvfb_videomode_dac(sc); 393 394 fbiinit1 = ((tdvfb_cvg_read(sc, TDV_OFF_FBIINIT1) & 395 TDV_FBIINIT1_VIDMASK) | 396 TDV_FBIINIT1_DR_DATA | 397 TDV_FBIINIT1_DR_BLANKING | 398 TDV_FBIINIT1_DR_HVSYNC | 399 TDV_FBIINIT1_DR_DCLK | 400 TDV_FBIINIT1_IN_VCLK_2X ); 401 402 if (sc->sc_voodootype == TDV_VOODOO_2) { 403 fbiinit1 |= ((sc->sc_x_tiles & 0x20) >> 5) 404 << TDV_FBIINIT1_TILES_X_MSB | ((sc->sc_x_tiles & 0x1e) >> 1) 405 << TDV_FBIINIT1_TILES_X; 406 fbiinit6 = (sc->sc_x_tiles & 0x1) << TDV_FBIINIT6_TILES_X_LSB; 407 } else 408 fbiinit1 |= sc->sc_x_tiles << TDV_FBIINIT1_TILES_X; 409 410 fbiinit1 |= TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC; 411 412 if (sc->sc_voodootype == TDV_VOODOO_2) { 413 fbiinit5 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT5) 414 & TDV_FBIINIT5_VIDMASK; 415 if (sc->sc_videomode->flags & VID_PHSYNC) 416 fbiinit5 |= TDV_FBIINIT5_PHSYNC; 417 if (sc->sc_videomode->flags & VID_PVSYNC) 418 fbiinit5 |= TDV_FBIINIT5_PVSYNC; 419 } 420 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 421 if (sc->sc_voodootype == TDV_VOODOO_2) { 422 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 423 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT5, fbiinit5); 424 } 425 tdvfb_wait(sc); 426 427 /* unreset, enable DRAM refresh */ 428 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 429 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 430 TDV_FBIINIT0_FIFO_RST); 431 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 432 /* diable access to FBIINIT regs */ 433 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 434 TDV_INITENABLE_EN_FIFO); 435 tdvfb_wait(sc); 436 437 if (sc->sc_bpp == 16) 438 lfbmode = TDV_LFBMODE_565; 439 else if (sc->sc_bpp == 32) 440 lfbmode = TDV_LFBMODE_8888; 441 else 442 return false; 443 444 #if BYTE_ORDER == BIG_ENDIAN 445 lfbmode |= TDV_LFBMODE_BSW_WR | TDV_LFBMODE_BSW_RD; 446 #endif 447 448 tdvfb_cvg_write(sc, TDV_OFF_LFBMODE, lfbmode); 449 450 return true; 451 } 452 453 /* 454 * Update DAC parameters for selected video mode. 455 */ 456 static void 457 tdvfb_videomode_dac(struct tdvfb_softc *sc) 458 { 459 uint32_t fbiinit2, fbiinit3; 460 461 /* remember current FBIINIT settings */ 462 fbiinit2 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); 463 fbiinit3 = tdvfb_cvg_read(sc, TDV_OFF_FBIINIT3); 464 465 /* remap DAC */ 466 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 467 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 468 469 tdvfb_cvg_dac_write(sc, TDV_GENDAC_CMD, TDV_GENDAC_CMD_16BITS); 470 471 tdvfb_gendac_set_vid_timing(sc, &(sc->vid_timing)); 472 473 /* disable remapping */ 474 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 475 TDV_INITENABLE_EN_INIT); 476 /* restore */ 477 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 478 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit3); 479 } 480 481 /* 482 * Check how much memory do we have. Actually, Voodoo1/2 has separate 483 * framebuffer and texture memory. This function only checks for framebuffer 484 * memory. Texture memory ramains unused. 485 */ 486 static size_t 487 tdvfb_mem_size(struct tdvfb_softc *sc) 488 { 489 size_t mem_size; 490 uint32_t vram_test4, vram_test2; 491 492 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0, 0x11aabbaa); 493 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x100000, 0x22aabbaa); 494 bus_space_write_4(sc->sc_cvgt, sc->sc_fbh, 0x200000, 0x44aabbaa); 495 496 vram_test4 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x400000); 497 vram_test2 = bus_space_read_4(sc->sc_cvgt, sc->sc_fbh, 0x200000); 498 499 if (vram_test4 == 0x44aabbaa) 500 mem_size = 4*1024*1024; 501 else if (vram_test2 == 0x22aabbaa) { 502 mem_size = 2*1024*1024; 503 } else 504 mem_size = 1*1024*1024; 505 506 return mem_size; 507 } 508 509 /* do the low level init of Voodoo board */ 510 static bool 511 tdvfb_init(struct tdvfb_softc *sc) 512 { 513 /* undocumented - found in glide code */ 514 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_DISABLE_REG, 0); 515 /* allow write to hardware initialization registers */ 516 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 517 TDV_INITENABLE_EN_INIT); 518 519 /* reset the board */ 520 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT1, TDV_FBIINIT1_VIDEO_RST); 521 tdvfb_wait(sc); 522 tdvfb_cvg_set(sc, TDV_OFF_FBIINIT0, TDV_FBIINIT0_FBI_RST | 523 TDV_FBIINIT0_FIFO_RST); 524 tdvfb_wait(sc); 525 526 /* disable video RAM refresh */ 527 tdvfb_cvg_unset(sc, TDV_OFF_FBIINIT2, TDV_FBIINIT2_DRAM_REFR); 528 tdvfb_wait(sc); 529 530 /* on voodoo1 I had to read FBIINIT2 before remapping, 531 * otherwise weird things were happening, on v2 it works just fine */ 532 /* tdvfb_cvg_read(sc, TDV_OFF_FBIINIT2); */ 533 534 /* remap DAC */ 535 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 536 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_REMAPDAC); 537 538 /* detect supported DAC, TODO: we really should support other DACs */ 539 if(!tdvfb_gendac_detect(sc)) { 540 aprint_error_dev(sc->sc_dev, "could not detect ICS GENDAC\n"); 541 return false; 542 } 543 544 /* calculate PLL used to drive the chips (graphics clock) */ 545 if(sc->sc_voodootype == TDV_VOODOO_2) 546 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_CVG_CLK); 547 else 548 sc->cvg_timing = tdvfb_gendac_calc_pll(TDV_SST_CLK); 549 550 /* set PLL for gfx clock */ 551 tdvfb_gendac_set_cvg_timing(sc, &(sc->cvg_timing)); 552 553 /* don't remap the DAC anymore */ 554 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 555 TDV_INITENABLE_EN_INIT | TDV_INITENABLE_EN_FIFO); 556 557 /* set FBIINIT registers to some default values that make sense */ 558 tdvfb_fbiinit_defaults(sc); 559 560 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_INITENABLE_REG, 561 TDV_INITENABLE_EN_FIFO); 562 pci_conf_write(sc->sc_pc, sc->sc_pcitag, TDV_VCLK_ENABLE_REG, 0); 563 564 return true; 565 } 566 567 static void 568 tdvfb_fbiinit_defaults(struct tdvfb_softc *sc) 569 { 570 uint32_t fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6; 571 572 fbiinit0 = TDV_FBIINIT0_VGA_PASS; /* disable VGA passthrough */ 573 fbiinit1 = /*TDV_FBIINIT1_PCIWAIT |*/ /* one wait state for PCI write */ 574 TDV_FBIINIT1_LFB_EN | /* enable lfb reads */ 575 TDV_FBIINIT1_VIDEO_RST | /* video timing reset */ 576 10 << TDV_FBIINIT1_TILES_X | /* tiles x/horizontal */ 577 TDV_FBIINIT1_VCLK_2X << TDV_FBIINIT1_VCLK_SRC ; 578 579 fbiinit2 = TDV_FBIINIT2_SWB_ALG |/* swap buffer use DAC sync */ 580 TDV_FBIINIT2_FAST_RAS | /* fast RAS read */ 581 TDV_FBIINIT2_DRAM_OE | /* enable DRAM OE */ 582 TDV_FBIINIT2_DRAM_REFR | /* enable DRAM refresh */ 583 TDV_FBIINIT2_FIFO_RDA | /* FIFO read ahead */ 584 TDV_FBIINIT2_DRAM_REF16 << TDV_FBIINIT2_DRAM_REFLD; /* 16 ms */ 585 586 fbiinit3 = TDV_FBIINIT3_TREX_DIS; /* disable texture mapping */ 587 588 fbiinit4 = /*TDV_FBIINIT4_PCIWAIT|*/ /* one wait state for PCI write */ 589 TDV_FBIINIT4_LFB_RDA; /* lfb read ahead */ 590 591 fbiinit6 = 0; 592 #ifdef TDVFB_DEBUG 593 aprint_normal("fbiinit: 0 %x, 1 %x, 2 %x, 3 %x, 4 %x, 6 %x\n", 594 fbiinit0, fbiinit1, fbiinit2, fbiinit3, fbiinit4, fbiinit6); 595 #endif /* TDVFB_DEBUG */ 596 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT0, fbiinit0); 597 tdvfb_wait(sc); 598 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT1, fbiinit1); 599 tdvfb_wait(sc); 600 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT2, fbiinit2); 601 tdvfb_wait(sc); 602 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT3, fbiinit3); 603 tdvfb_wait(sc); 604 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT4, fbiinit4); 605 tdvfb_wait(sc); 606 if (sc->sc_voodootype == TDV_VOODOO_2) { 607 tdvfb_cvg_write(sc, TDV_OFF_FBIINIT6, fbiinit6); 608 tdvfb_wait(sc); 609 } 610 } 611 612 static void 613 tdvfb_gendac_set_vid_timing(struct tdvfb_softc *sc, 614 struct tdvfb_dac_timing *timing) 615 { 616 uint8_t pllreg; 617 618 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 619 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 620 621 /* write the timing for gfx clock into "slot" 0 */ 622 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_0); 623 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 624 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 625 /* select "slot" 0 for output */ 626 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 627 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 628 (pllreg & TDV_GENDAC_VIDPLLMASK) | TDV_GENDAC_PLL_VIDCLK | 629 TDV_GENDAC_PLL_VIDCLK0); 630 tdvfb_wait(sc); 631 tdvfb_wait(sc); 632 #ifdef TDVFB_DEBUG 633 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_0); 634 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 635 aprint_normal("vid read again: %d\n", pllreg); 636 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 637 aprint_normal("vid read again: %d\n", pllreg); 638 #endif /* TDVFB_DEBUG */ 639 } 640 641 static void 642 tdvfb_gendac_set_cvg_timing(struct tdvfb_softc *sc, 643 struct tdvfb_dac_timing *timing) 644 { 645 uint8_t pllreg; 646 647 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_CTRL); 648 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 649 650 /* write the timing for gfx clock into "slot" A */ 651 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_A); 652 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->m); 653 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, timing->n); 654 /* select "slot" A for output */ 655 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLWR, TDV_GENDAC_PLL_CTRL); 656 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLDATA, 657 (pllreg & TDV_GENDAC_CVGPLLMASK) | TDV_GENDAC_PLL_CVGCLKA); 658 #ifdef TDVFB_DEBUG 659 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, TDV_GENDAC_PLL_A); 660 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 661 aprint_normal("read again: %d\n", pllreg); 662 pllreg = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 663 aprint_normal("read again: %d\n", pllreg); 664 #endif /* TDVFB_DEBUG */ 665 tdvfb_wait(sc); 666 } 667 668 static struct tdvfb_dac_timing 669 tdvfb_gendac_calc_pll(int freq) 670 { 671 int n1, n2; 672 int m, mdbl; 673 int best_m, best_n1, best_error; 674 int fout; 675 struct tdvfb_dac_timing timing; 676 677 best_m = -1; best_n1 = -1; 678 679 /* select highest possible n2, check n2 * fCLK < TDV_GENDAC_MAXVCO */ 680 for (n2 = TDV_GENDAC_MAX_N2; n2 >= TDV_GENDAC_MIN_N2; n2--) { 681 if ((freq * (1 << n2)) < TDV_GENDAC_MAXVCO) 682 break; 683 } 684 685 best_error = freq; 686 687 /* 688 * m+2 2^n2 * fOUT 689 * ---- = ----------- 690 * n1+2 fREF 691 */ 692 for (n1 = TDV_GENDAC_MIN_N1; n1 <= TDV_GENDAC_MAX_N1; n1++) { 693 /* loop mostly inspired by Linux driver */ 694 mdbl = (2 * freq * (1 << n2)*(n1 + 2)) / TDV_GENDAC_REFFREQ - 4; 695 if (mdbl % 2) 696 m = mdbl/2+1; 697 else 698 m = mdbl/2; 699 700 if(m > TDV_GENDAC_MAX_M) 701 break; 702 703 fout = (TDV_GENDAC_REFFREQ * (m + 2)) / ((1 << n2) * (n1 + 2)); 704 if ((abs(fout - freq) < best_error) && (m > 0)) { 705 best_n1 = n1; 706 best_m = m; 707 best_error = abs(fout - freq); 708 if (200*best_error < freq) break; 709 } 710 711 } 712 713 fout = (TDV_GENDAC_REFFREQ * (best_m + 2)) / ((1 << n2) * (best_n1 + 2)); 714 timing.m = best_m; 715 timing.n = (n2 << 5) | best_n1; 716 timing.fout = fout; 717 718 #ifdef TDVFB_DEBUG 719 aprint_normal("tdvfb_gendac_calc_pll ret: m %d, n %d, fout %d kHz\n", 720 timing.m, timing.n, timing.fout); 721 #endif /* TDVFB_DEBUG */ 722 723 return timing; 724 } 725 726 static bool 727 tdvfb_gendac_detect(struct tdvfb_softc *sc) 728 { 729 uint8_t m_f1, m_f7, m_fb; 730 uint8_t n_f1, n_f7, n_fb; 731 732 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x1); 733 m_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 734 n_f1 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 735 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0x7); 736 m_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 737 n_f7 = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 738 tdvfb_cvg_dac_write(sc, TDV_GENDAC_PLLRD, 0xB); 739 m_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 740 n_fb = tdvfb_cvg_dac_read(sc, TDV_GENDAC_PLLDATA); 741 742 if( (m_f1 == TDV_GENDAC_DFLT_F1_M) && 743 (n_f1 == TDV_GENDAC_DFLT_F1_N) && 744 (m_f7 == TDV_GENDAC_DFLT_F7_M) && 745 (n_f7 == TDV_GENDAC_DFLT_F7_N) && 746 (n_fb == TDV_GENDAC_DFLT_FB_N) && 747 (n_fb == TDV_GENDAC_DFLT_FB_N) ) { 748 aprint_normal_dev(sc->sc_dev, "ICS 5342 GENDAC\n"); 749 return true; 750 } 751 752 return false; 753 } 754 755 static void 756 tdvfb_wait(struct tdvfb_softc *sc) 757 { 758 uint32_t x, cnt; 759 cnt = 0; 760 for (x = 0; x < MAXLOOP; x++) { 761 if (tdvfb_cvg_read(sc, TDV_OFF_STATUS) & TDV_STATUS_FBI_BUSY) 762 cnt = 0; 763 else 764 cnt++; 765 766 if (cnt >= 5) /* Voodoo2 specs suggest at least 3 */ 767 break; 768 } 769 770 if (x == MAXLOOP) 771 /* 772 * The console probably isn't working now anyway, so maybe 773 * let's panic... At least it will drop into ddb if some other 774 * device a console. 775 */ 776 panic("tdvfb is stuck!\n"); 777 } 778 779 static uint32_t 780 tdvfb_cvg_read(struct tdvfb_softc *sc, uint32_t reg) 781 { 782 uint32_t rv; 783 rv = bus_space_read_4(sc->sc_cvgt, sc->sc_cvgh, reg); 784 #ifdef TDVFB_DEBUG_REGS 785 aprint_normal("cvg_read val %x from reg %x\n", rv, reg); 786 #endif /* TDVFB_DEBUG_REGS */ 787 return rv; 788 } 789 790 static void 791 tdvfb_cvg_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 792 { 793 #ifdef TDVFB_DEBUG_REGS 794 aprint_normal("cvg_write val %x to reg %x\n", val, reg); 795 #endif /* TDVFB_DEBUG_REGS */ 796 bus_space_write_4(sc->sc_cvgt, sc->sc_cvgh, reg, val); 797 } 798 799 static void 800 tdvfb_cvg_set(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 801 { 802 uint32_t v; 803 v = tdvfb_cvg_read(sc, reg) | bits; 804 tdvfb_cvg_write(sc, reg, v); 805 } 806 807 static void 808 tdvfb_cvg_unset(struct tdvfb_softc *sc, uint32_t reg, uint32_t bits) 809 { 810 uint32_t v; 811 v = tdvfb_cvg_read(sc, reg) & ~bits; 812 tdvfb_cvg_write(sc, reg, v); 813 } 814 815 static uint8_t 816 tdvfb_cvg_dac_read(struct tdvfb_softc *sc, uint32_t reg) 817 { 818 uint32_t rv; 819 820 tdvfb_cvg_dac_write(sc, reg, TDV_DAC_DATA_READ); 821 822 rv = tdvfb_cvg_read(sc, TDV_OFF_DAC_READ); 823 #ifdef TDVFB_DEBUG_REGS 824 aprint_normal("cvg_dac_read val %x from reg %x\n", rv, reg); 825 #endif /* TDVFB_DEBUG_REGS */ 826 return rv & 0xFF; 827 } 828 829 static void 830 tdvfb_cvg_dac_write(struct tdvfb_softc *sc, uint32_t reg, uint32_t val) 831 { 832 uint32_t wreg; 833 834 wreg = ((reg & TDV_GENDAC_ADDRMASK) << 8) | val; 835 836 #ifdef TDVFB_DEBUG_REGS 837 aprint_normal("cvg_dac_write val %x to reg %x (%x)\n", val, reg, 838 wreg); 839 #endif /* TDVFB_DEBUG_REGS */ 840 841 tdvfb_cvg_write(sc, TDV_OFF_DAC_DATA, wreg); 842 tdvfb_wait(sc); 843 } 844 845 static void 846 tdvfb_rectfill(struct tdvfb_softc *sc, int x, int y, int wi, int he, 847 uint32_t color) 848 { 849 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 850 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 851 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 852 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 853 sc->sc_linebytes | (sc->sc_linebytes << 16)); 854 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, x | (y << 16)); 855 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 856 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_RECTFILL | 857 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3 | TDV_BLTCMD_DSTTILED | 858 TDV_BLTCMD_CLIPRECT ); 859 tdvfb_wait(sc); 860 } 861 862 static void 863 tdvfb_bitblt(struct tdvfb_softc *sc, int xs, int ys, int xd, int yd, int wi, 864 int he) 865 { 866 tdvfb_cvg_write(sc, TDV_OFF_BLTSRC, 0); 867 tdvfb_cvg_write(sc, TDV_OFF_BLTDST, 0); 868 tdvfb_cvg_write(sc, TDV_OFF_BLTROP, TDV_BLTROP_COPY); 869 tdvfb_cvg_write(sc, TDV_OFF_BLTXYSTRIDE, 870 sc->sc_linebytes | (sc->sc_linebytes << 16)); 871 tdvfb_cvg_write(sc, TDV_OFF_BLTSRCXY, xs | (ys << 16)); 872 tdvfb_cvg_write(sc, TDV_OFF_BLTDSTXY, xd | (yd << 16)); 873 tdvfb_cvg_write(sc, TDV_OFF_BLTSIZE, wi | (he << 16)); 874 tdvfb_cvg_write(sc, TDV_OFF_BLTCMD, TDV_BLTCMD_SCR2SCR | 875 TDV_BLTCMD_LAUNCH | TDV_BLTCMD_FMT_565 << 3); 876 877 tdvfb_wait(sc); 878 } 879 880 static void 881 tdvfb_copyrows(void *cookie, int srcrow, int dstrow, int nrows) 882 { 883 struct tdvfb_softc *sc; 884 struct rasops_info *ri; 885 struct vcons_screen *scr; 886 int x, ys, yd, wi, he; 887 888 ri = cookie; 889 scr = ri->ri_hw; 890 sc = scr->scr_cookie; 891 892 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 893 x = ri->ri_xorigin; 894 ys = ri->ri_yorigin + ri->ri_font->fontheight * srcrow; 895 yd = ri->ri_yorigin + ri->ri_font->fontheight * dstrow; 896 wi = ri->ri_emuwidth; 897 he = ri->ri_font->fontheight * nrows; 898 tdvfb_bitblt(sc, x, ys, x, yd, wi, he); 899 } 900 } 901 902 static void 903 tdvfb_eraserows(void *cookie, int row, int nrows, long fillattr) 904 { 905 906 struct tdvfb_softc *sc; 907 struct rasops_info *ri; 908 struct vcons_screen *scr; 909 int x, y, wi, he, fg, bg, ul; 910 911 ri = cookie; 912 scr = ri->ri_hw; 913 sc = scr->scr_cookie; 914 915 if (sc->sc_mode == WSDISPLAYIO_MODE_EMUL) { 916 rasops_unpack_attr(fillattr, &fg, &bg, &ul); 917 if ((row == 0) && (nrows == ri->ri_rows)) 918 tdvfb_rectfill(sc, 0, 0, ri->ri_width, 919 ri->ri_height, ri->ri_devcmap[bg]); 920 else { 921 x = ri->ri_xorigin; 922 y = ri->ri_yorigin + ri->ri_font->fontheight * row; 923 wi = ri->ri_emuwidth; 924 he = ri->ri_font->fontheight * nrows; 925 tdvfb_rectfill(sc, x, y, wi, he, ri->ri_devcmap[bg]); 926 } 927 } 928 } 929 930 static int 931 tdvfb_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 932 { 933 struct vcons_data *vd; 934 struct tdvfb_softc *sc; 935 struct wsdisplay_fbinfo *wsfbi; 936 struct vcons_screen *ms; 937 938 vd = v; 939 sc = vd->cookie; 940 ms = vd->active; 941 942 switch (cmd) { 943 case WSDISPLAYIO_GTYPE: 944 *(u_int *)data = WSDISPLAY_TYPE_PCIMISC; 945 return 0; 946 947 case PCI_IOC_CFGREAD: 948 case PCI_IOC_CFGWRITE: 949 return pci_devioctl(sc->sc_pc, sc->sc_pcitag, 950 cmd, data, flag, l); 951 952 case WSDISPLAYIO_GET_BUSID: 953 return wsdisplayio_busid_pci(sc->sc_dev, sc->sc_pc, 954 sc->sc_pcitag, data); 955 956 case WSDISPLAYIO_GINFO: 957 if (ms == NULL) 958 return ENODEV; 959 960 wsfbi = (void*) data; 961 wsfbi->height = ms->scr_ri.ri_height; 962 wsfbi->width = ms->scr_ri.ri_width; 963 wsfbi->depth = ms->scr_ri.ri_depth; 964 wsfbi->cmsize = 256; 965 return 0; 966 967 case WSDISPLAYIO_LINEBYTES: 968 *(u_int*)data = sc->sc_linebytes; 969 return 0; 970 971 case WSDISPLAYIO_SMODE: 972 { 973 int new_mode = *(int*)data; 974 if (new_mode != sc->sc_mode) { 975 sc->sc_mode = new_mode; 976 if(new_mode == WSDISPLAYIO_MODE_EMUL) 977 vcons_redraw_screen(ms); 978 } 979 return 0; 980 } 981 case WSDISPLAYIO_GET_FBINFO: 982 { 983 struct wsdisplayio_fbinfo *fbi = data; 984 struct rasops_info *ri; 985 int ret; 986 987 ri = &sc->vd.active->scr_ri; 988 ret = wsdisplayio_get_fbinfo(ri, fbi); 989 return ret; 990 } 991 } 992 return EPASSTHROUGH; 993 } 994 995 static paddr_t 996 tdvfb_mmap(void *v, void *vs, off_t offset, int prot) 997 { 998 struct vcons_data *vd; 999 struct tdvfb_softc *sc; 1000 paddr_t pa; 1001 1002 vd = v; 1003 sc = vd->cookie; 1004 1005 if (offset < sc->sc_memsize) { 1006 pa = bus_space_mmap(sc->sc_cvgt, sc->sc_fbh + offset, 0, prot, 1007 BUS_SPACE_MAP_LINEAR); 1008 return pa; 1009 } 1010 1011 return -1; 1012 } 1013 1014
Indexes created Tue Sep 30 20:09:53 GMT 2025