tga.c revision 1.23
1 /* $NetBSD: tga.c,v 1.23 2000/04/20 05:25:20 nathanw Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/ioctl.h> 38 39 #include <vm/vm.h> 40 41 #include <machine/bus.h> 42 #include <machine/intr.h> 43 44 #include <dev/pci/pcireg.h> 45 #include <dev/pci/pcivar.h> 46 #include <dev/pci/pcidevs.h> 47 #include <dev/pci/tgareg.h> 48 #include <dev/pci/tgavar.h> 49 #include <dev/ic/bt485reg.h> 50 #include <dev/ic/bt485var.h> 51 #include <dev/ic/bt463reg.h> 52 #include <dev/ic/bt463var.h> 53 54 #include <dev/wscons/wsconsio.h> 55 #include <dev/wscons/wscons_raster.h> 56 #include <dev/rasops/rasops.h> 57 #include <dev/wsfont/wsfont.h> 58 59 #ifdef __alpha__ 60 #include <machine/pte.h> 61 #endif 62 63 int tgamatch __P((struct device *, struct cfdata *, void *)); 64 void tgaattach __P((struct device *, struct device *, void *)); 65 int tgaprint __P((void *, const char *)); 66 67 struct cfattach tga_ca = { 68 sizeof(struct tga_softc), tgamatch, tgaattach, 69 }; 70 71 int tga_identify __P((struct tga_devconfig *)); 72 const struct tga_conf *tga_getconf __P((int)); 73 static void tga_getdevconfig __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 74 pcitag_t tag, struct tga_devconfig *dc)); 75 76 struct tga_devconfig tga_console_dc; 77 78 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 79 int tga_mmap __P((void *, off_t, int)); 80 static void tga_copyrows __P((void *, int, int, int)); 81 static void tga_copycols __P((void *, int, int, int, int)); 82 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 83 void **, int *, int *, long *)); 84 static void tga_free_screen __P((void *, void *)); 85 static int tga_show_screen __P((void *, void *, int, 86 void (*) (void *, int, int), void *)); 87 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 88 struct rasops_info *, int, int)); 89 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 90 int, struct rasops_info *, int, int )); 91 static void tga_putchar __P((void *c, int row, int col, 92 u_int uc, long attr)); 93 static void tga_eraserows __P((void *, int, int, long)); 94 static void tga_erasecols __P((void *, int, int, int, long)); 95 void tga2_init __P((struct tga_devconfig *, int)); 96 97 static void tga_config_interrupts __P((struct device *)); 98 99 /* RAMDAC interface functions */ 100 static int tga_sched_update __P((void *, void (*)(void *))); 101 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 102 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 103 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 104 static u_int8_t tga_bt463_rd __P((void *, u_int)); 105 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 106 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 107 108 /* Interrupt handler */ 109 static int tga_intr __P((void *)); 110 111 /* The NULL entries will get filled in by rasops_init(). 112 * XXX and the non-NULL ones will be overwritten; reset after calling it. 113 */ 114 struct wsdisplay_emulops tga_emulops = { 115 NULL, 116 NULL, 117 tga_putchar, 118 tga_copycols, 119 tga_erasecols, 120 tga_copyrows, 121 tga_eraserows, 122 NULL, 123 }; 124 125 struct wsscreen_descr tga_stdscreen = { 126 "std", 127 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 128 &tga_emulops, 129 0, 0, 130 WSSCREEN_REVERSE 131 }; 132 133 const struct wsscreen_descr *_tga_scrlist[] = { 134 &tga_stdscreen, 135 /* XXX other formats, graphics screen? */ 136 }; 137 138 struct wsscreen_list tga_screenlist = { 139 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 140 }; 141 142 struct wsdisplay_accessops tga_accessops = { 143 tga_ioctl, 144 tga_mmap, 145 tga_alloc_screen, 146 tga_free_screen, 147 tga_show_screen, 148 0 /* load_font */ 149 }; 150 151 static void tga_blank __P((struct tga_devconfig *)); 152 static void tga_unblank __P((struct tga_devconfig *)); 153 154 int 155 tgamatch(parent, match, aux) 156 struct device *parent; 157 struct cfdata *match; 158 void *aux; 159 { 160 struct pci_attach_args *pa = aux; 161 162 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 163 return (0); 164 165 switch (PCI_PRODUCT(pa->pa_id)) { 166 case PCI_PRODUCT_DEC_21030: 167 case PCI_PRODUCT_DEC_PBXGB: 168 return 10; 169 default: 170 return 0; 171 } 172 return (0); 173 } 174 175 static void 176 tga_getdevconfig(memt, pc, tag, dc) 177 bus_space_tag_t memt; 178 pci_chipset_tag_t pc; 179 pcitag_t tag; 180 struct tga_devconfig *dc; 181 { 182 const struct tga_conf *tgac; 183 struct rasops_info *rip; 184 int cookie; 185 bus_size_t pcisize; 186 int i, flags; 187 188 dc->dc_memt = memt; 189 190 dc->dc_pcitag = tag; 191 192 /* XXX magic number */ 193 if (pci_mapreg_info(pc, tag, 0x10, 194 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 195 &dc->dc_pcipaddr, &pcisize, &flags)) 196 return; 197 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 198 panic("tga memory not prefetchable"); 199 200 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 201 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 202 return; 203 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 204 #ifdef __alpha__ 205 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 206 #endif 207 208 bus_space_subregion(dc->dc_memt, dc->dc_memh, 209 TGA_MEM_CREGS, TGA_CREGS_SIZE, 210 &dc->dc_regs); 211 dc->dc_tga_type = tga_identify(dc); 212 213 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 214 if (tgac == NULL) 215 return; 216 217 #if 0 218 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 219 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 220 panic("tga_getdevconfig: memory size mismatch?"); 221 #endif 222 223 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 224 case 0x01: 225 case 0x02: 226 case 0x03: 227 case 0x04: 228 dc->dc_tga2 = 0; 229 break; 230 case 0x20: 231 case 0x21: 232 case 0x22: 233 dc->dc_tga2 = 1; 234 break; 235 default: 236 panic("tga_getdevconfig: TGA Revision not recognized"); 237 } 238 239 if (dc->dc_tga2) { 240 int monitor; 241 242 monitor = (~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f; 243 tga2_init(dc, monitor); 244 } 245 246 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 247 case 0: 248 dc->dc_wid = 8192; 249 break; 250 251 case 1: 252 dc->dc_wid = 8196; 253 break; 254 255 default: 256 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 257 break; 258 } 259 260 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 261 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 262 263 /* XXX this seems to be what DEC does */ 264 TGAWREG(dc, TGA_REG_CCBR, 0); 265 TGAWREG(dc, TGA_REG_VVBR, 1); 266 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 267 1 * tgac->tgac_vvbr_units; 268 dc->dc_blanked = 1; 269 tga_unblank(dc); 270 271 /* 272 * Set all bits in the pixel mask, to enable writes to all pixels. 273 * It seems that the console firmware clears some of them 274 * under some circumstances, which causes cute vertical stripes. 275 */ 276 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 277 278 /* clear the screen */ 279 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 280 *(u_int32_t *)(dc->dc_videobase + i) = 0; 281 282 /* Initialize rasops descriptor */ 283 rip = &dc->dc_rinfo; 284 rip->ri_flg = RI_CENTER; 285 rip->ri_depth = tgac->tgac_phys_depth; 286 rip->ri_bits = (void *)dc->dc_videobase; 287 rip->ri_width = dc->dc_wid; 288 rip->ri_height = dc->dc_ht; 289 rip->ri_stride = dc->dc_rowbytes; 290 rip->ri_hw = dc; 291 292 if (tgac->tgac_phys_depth == 32) { 293 rip->ri_rnum = 8; 294 rip->ri_gnum = 8; 295 rip->ri_bnum = 8; 296 rip->ri_rpos = 16; 297 rip->ri_gpos = 8; 298 rip->ri_bpos = 0; 299 } 300 301 wsfont_init(); 302 /* prefer 8 pixel wide font */ 303 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0) 304 cookie = wsfont_find(NULL, 0, 0, 0); 305 if (cookie <= 0) { 306 printf("tga: no appropriate fonts.\n"); 307 return; 308 } 309 310 /* the accelerated tga_putchar() needs LSbit left */ 311 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font, 312 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 313 printf("tga: couldn't lock font\n"); 314 return; 315 } 316 dc->dc_rinfo.ri_wsfcookie = cookie; 317 318 rasops_init(rip, 34, 80); 319 320 /* add our accelerated functions */ 321 /* XXX shouldn't have to do this; rasops should leave non-NULL 322 * XXX entries alone. 323 */ 324 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 325 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 326 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 327 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 328 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 329 330 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 331 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 332 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 333 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 334 335 336 dc->dc_intrenabled = 0; 337 } 338 339 void 340 tgaattach(parent, self, aux) 341 struct device *parent, *self; 342 void *aux; 343 { 344 struct pci_attach_args *pa = aux; 345 struct tga_softc *sc = (struct tga_softc *)self; 346 struct wsemuldisplaydev_attach_args aa; 347 pci_intr_handle_t intrh; 348 const char *intrstr; 349 u_int8_t rev; 350 int console; 351 352 #ifdef __alpha__ 353 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 354 #else 355 console = 0; 356 #endif 357 if (console) { 358 sc->sc_dc = &tga_console_dc; 359 sc->nscreens = 1; 360 } else { 361 sc->sc_dc = (struct tga_devconfig *) 362 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK); 363 bzero(sc->sc_dc, sizeof(struct tga_devconfig)); 364 tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, 365 sc->sc_dc); 366 } 367 if (sc->sc_dc->dc_vaddr == NULL) { 368 printf(": couldn't map memory space; punt!\n"); 369 return; 370 } 371 372 /* XXX say what's going on. */ 373 intrstr = NULL; 374 if (pci_intr_map(pa->pa_pc, pa->pa_intrtag, pa->pa_intrpin, 375 pa->pa_intrline, &intrh)) { 376 printf(": couldn't map interrupt"); 377 return; 378 } 379 intrstr = pci_intr_string(pa->pa_pc, intrh); 380 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 381 sc->sc_dc); 382 if (sc->sc_intr == NULL) { 383 printf(": couldn't establish interrupt"); 384 if (intrstr != NULL) 385 printf("at %s", intrstr); 386 printf("\n"); 387 return; 388 } 389 390 rev = PCI_REVISION(pa->pa_class); 391 switch (rev) { 392 case 0x1: 393 case 0x2: 394 case 0x3: 395 printf(": DC21030 step %c", 'A' + rev - 1); 396 break; 397 case 0x20: 398 printf(": TGA2 abstract software model"); 399 break; 400 case 0x21: 401 case 0x22: 402 printf(": TGA2 pass %d", rev - 0x20); 403 break; 404 405 default: 406 printf("unknown stepping (0x%x)", rev); 407 break; 408 } 409 printf(", "); 410 411 /* 412 * Get RAMDAC function vectors and call the RAMDAC functions 413 * to allocate its private storage and pass that back to us. 414 */ 415 416 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 417 if (!sc->sc_dc->dc_tga2) { 418 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 419 sc->sc_dc->dc_ramdac_cookie = 420 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 421 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 422 else 423 sc->sc_dc->dc_ramdac_cookie = 424 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 425 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 426 } else { 427 sc->sc_dc->dc_ramdac_cookie = 428 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 429 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 430 } 431 432 /* 433 * Initialize the RAMDAC. Initialization includes disabling 434 * cursor, setting a sane colormap, etc. 435 */ 436 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 437 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 438 439 if (sc->sc_dc->dc_tgaconf == NULL) { 440 printf("unknown board configuration\n"); 441 return; 442 } 443 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 444 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 445 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 446 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 447 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 448 449 if (intrstr != NULL) 450 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 451 intrstr); 452 453 aa.console = console; 454 aa.scrdata = &tga_screenlist; 455 aa.accessops = &tga_accessops; 456 aa.accesscookie = sc; 457 458 config_found(self, &aa, wsemuldisplaydevprint); 459 460 config_interrupts(self, tga_config_interrupts); 461 } 462 463 static void 464 tga_config_interrupts (d) 465 struct device *d; 466 { 467 struct tga_softc *sc = (struct tga_softc *)d; 468 sc->sc_dc->dc_intrenabled = 1; 469 } 470 471 472 int 473 tga_ioctl(v, cmd, data, flag, p) 474 void *v; 475 u_long cmd; 476 caddr_t data; 477 int flag; 478 struct proc *p; 479 { 480 struct tga_softc *sc = v; 481 struct tga_devconfig *dc = sc->sc_dc; 482 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 483 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 484 485 switch (cmd) { 486 case WSDISPLAYIO_GTYPE: 487 *(u_int *)data = WSDISPLAY_TYPE_TGA; 488 return (0); 489 490 case WSDISPLAYIO_GINFO: 491 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 492 wsd_fbip->height = sc->sc_dc->dc_ht; 493 wsd_fbip->width = sc->sc_dc->dc_wid; 494 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 495 wsd_fbip->cmsize = 256; /* XXX ??? */ 496 #undef wsd_fbip 497 return (0); 498 499 case WSDISPLAYIO_GETCMAP: 500 return (*dcrf->ramdac_get_cmap)(dcrc, 501 (struct wsdisplay_cmap *)data); 502 503 case WSDISPLAYIO_PUTCMAP: 504 return (*dcrf->ramdac_set_cmap)(dcrc, 505 (struct wsdisplay_cmap *)data); 506 507 case WSDISPLAYIO_SVIDEO: 508 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 509 tga_blank(sc->sc_dc); 510 else 511 tga_unblank(sc->sc_dc); 512 return (0); 513 514 case WSDISPLAYIO_GVIDEO: 515 *(u_int *)data = dc->dc_blanked ? 516 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 517 return (0); 518 519 case WSDISPLAYIO_GCURPOS: 520 return (*dcrf->ramdac_get_curpos)(dcrc, 521 (struct wsdisplay_curpos *)data); 522 523 case WSDISPLAYIO_SCURPOS: 524 return (*dcrf->ramdac_set_curpos)(dcrc, 525 (struct wsdisplay_curpos *)data); 526 527 case WSDISPLAYIO_GCURMAX: 528 return (*dcrf->ramdac_get_curmax)(dcrc, 529 (struct wsdisplay_curpos *)data); 530 531 case WSDISPLAYIO_GCURSOR: 532 return (*dcrf->ramdac_get_cursor)(dcrc, 533 (struct wsdisplay_cursor *)data); 534 535 case WSDISPLAYIO_SCURSOR: 536 return (*dcrf->ramdac_set_cursor)(dcrc, 537 (struct wsdisplay_cursor *)data); 538 } 539 return (-1); 540 } 541 542 static int 543 tga_sched_update(v, f) 544 void *v; 545 void (*f) __P((void *)); 546 { 547 struct tga_devconfig *dc = v; 548 549 if (dc->dc_intrenabled) { 550 /* Arrange for f to be called at the next end-of-frame interrupt */ 551 dc->dc_ramdac_intr = f; 552 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 553 } else { 554 /* Spin until the end-of-frame, then call f */ 555 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 556 TGAREGWB(dc, TGA_REG_SISR, 1); 557 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 558 ; 559 f(dc->dc_ramdac_cookie); 560 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 561 TGAREGWB(dc, TGA_REG_SISR, 1); 562 } 563 564 return 0; 565 } 566 567 static int 568 tga_intr(v) 569 void *v; 570 { 571 struct tga_devconfig *dc = v; 572 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 573 574 u_int32_t reg; 575 576 reg = TGARREG(dc, TGA_REG_SISR); 577 if (( reg & 0x00010001) != 0x00010001) { 578 /* Odd. We never set any of the other interrupt enables. */ 579 if ((reg & 0x1f) != 0) { 580 /* Clear the mysterious pending interrupts. */ 581 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 582 TGAREGWB(dc, TGA_REG_SISR, 1); 583 /* This was our interrupt, even if we're puzzled as to why 584 * we got it. Don't make the interrupt handler think it 585 * was a stray. 586 */ 587 return -1; 588 } else { 589 return 0; 590 } 591 } 592 dc->dc_ramdac_intr(dcrc); 593 dc->dc_ramdac_intr = NULL; 594 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 595 TGAREGWB(dc, TGA_REG_SISR, 1); 596 return (1); 597 } 598 599 int 600 tga_mmap(v, offset, prot) 601 void *v; 602 off_t offset; 603 int prot; 604 { 605 606 /* XXX NEW MAPPING CODE... */ 607 608 #ifdef __alpha__ 609 struct tga_softc *sc = v; 610 611 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 612 return -1; 613 return alpha_btop(sc->sc_dc->dc_paddr + offset); 614 #else 615 return (-1); 616 #endif 617 } 618 619 static int 620 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 621 void *v; 622 const struct wsscreen_descr *type; 623 void **cookiep; 624 int *curxp, *curyp; 625 long *attrp; 626 { 627 struct tga_softc *sc = v; 628 long defattr; 629 630 if (sc->nscreens > 0) 631 return (ENOMEM); 632 633 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 634 *curxp = 0; 635 *curyp = 0; 636 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 637 0, 0, 0, &defattr); 638 *attrp = defattr; 639 sc->nscreens++; 640 return (0); 641 } 642 643 static void 644 tga_free_screen(v, cookie) 645 void *v; 646 void *cookie; 647 { 648 struct tga_softc *sc = v; 649 650 if (sc->sc_dc == &tga_console_dc) 651 panic("tga_free_screen: console"); 652 653 sc->nscreens--; 654 } 655 656 static int 657 tga_show_screen(v, cookie, waitok, cb, cbarg) 658 void *v; 659 void *cookie; 660 int waitok; 661 void (*cb) __P((void *, int, int)); 662 void *cbarg; 663 { 664 665 return (0); 666 } 667 668 int 669 tga_cnattach(iot, memt, pc, bus, device, function) 670 bus_space_tag_t iot, memt; 671 pci_chipset_tag_t pc; 672 int bus, device, function; 673 { 674 struct tga_devconfig *dcp = &tga_console_dc; 675 long defattr; 676 677 tga_getdevconfig(memt, pc, 678 pci_make_tag(pc, bus, device, function), dcp); 679 680 /* sanity checks */ 681 if (dcp->dc_vaddr == NULL) 682 panic("tga_console(%d, %d): couldn't map memory space", 683 device, function); 684 if (dcp->dc_tgaconf == NULL) 685 panic("tga_console(%d, %d): unknown board configuration", 686 device, function); 687 688 /* 689 * Initialize the RAMDAC but DO NOT allocate any private storage. 690 * Initialization includes disabling cursor, setting a sane 691 * colormap, etc. It will be reinitialized in tgaattach(). 692 */ 693 if (dcp->dc_tga2) 694 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 695 tga2_ramdac_rd); 696 else { 697 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 698 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 699 tga_ramdac_rd); 700 else { 701 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 702 tga_bt463_rd); 703 } 704 } 705 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 706 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 707 708 return(0); 709 } 710 711 /* 712 * Functions to blank and unblank the display. 713 */ 714 static void 715 tga_blank(dc) 716 struct tga_devconfig *dc; 717 { 718 719 if (!dc->dc_blanked) { 720 dc->dc_blanked = 1; 721 /* XXX */ 722 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 723 } 724 } 725 726 static void 727 tga_unblank(dc) 728 struct tga_devconfig *dc; 729 { 730 731 if (dc->dc_blanked) { 732 dc->dc_blanked = 0; 733 /* XXX */ 734 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 735 } 736 } 737 738 /* 739 * Functions to manipulate the built-in cursor handing hardware. 740 */ 741 int 742 tga_builtin_set_cursor(dc, cursorp) 743 struct tga_devconfig *dc; 744 struct wsdisplay_cursor *cursorp; 745 { 746 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 747 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 748 int count, error, v; 749 750 v = cursorp->which; 751 if (v & WSDISPLAY_CURSOR_DOCMAP) { 752 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 753 if (error) 754 return (error); 755 } 756 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 757 if ((u_int)cursorp->size.x != 64 || 758 (u_int)cursorp->size.y > 64) 759 return (EINVAL); 760 /* The cursor is 2 bits deep, and there is no mask */ 761 count = (cursorp->size.y * 64 * 2) / NBBY; 762 if (!uvm_useracc(cursorp->image, count, B_READ)) 763 return (EFAULT); 764 } 765 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 766 return EINVAL; 767 768 /* parameters are OK; do it */ 769 if (v & WSDISPLAY_CURSOR_DOCUR) { 770 if (cursorp->enable) 771 /* XXX */ 772 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 773 else 774 /* XXX */ 775 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 776 } 777 if (v & WSDISPLAY_CURSOR_DOPOS) { 778 TGAWREG(dc, TGA_REG_CXYR, 779 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 780 } 781 if (v & WSDISPLAY_CURSOR_DOCMAP) { 782 /* can't fail. */ 783 dcrf->ramdac_set_curcmap(dcrc, cursorp); 784 } 785 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 786 count = ((64 * 2) / NBBY) * cursorp->size.y; 787 TGAWREG(dc, TGA_REG_CCBR, 788 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 789 copyin(cursorp->image, (char *)(dc->dc_vaddr + 790 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 791 count); /* can't fail. */ 792 } 793 return (0); 794 } 795 796 int 797 tga_builtin_get_cursor(dc, cursorp) 798 struct tga_devconfig *dc; 799 struct wsdisplay_cursor *cursorp; 800 { 801 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 802 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 803 int count, error; 804 805 cursorp->which = WSDISPLAY_CURSOR_DOALL & 806 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 807 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 808 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 809 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 810 cursorp->size.x = 64; 811 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 812 813 if (cursorp->image != NULL) { 814 count = (cursorp->size.y * 64 * 2) / NBBY; 815 error = copyout((char *)(dc->dc_vaddr + 816 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 817 cursorp->image, count); 818 if (error) 819 return (error); 820 /* No mask */ 821 } 822 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 823 return (error); 824 } 825 826 int 827 tga_builtin_set_curpos(dc, curposp) 828 struct tga_devconfig *dc; 829 struct wsdisplay_curpos *curposp; 830 { 831 832 TGAWREG(dc, TGA_REG_CXYR, 833 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 834 return (0); 835 } 836 837 int 838 tga_builtin_get_curpos(dc, curposp) 839 struct tga_devconfig *dc; 840 struct wsdisplay_curpos *curposp; 841 { 842 843 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 844 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 845 return (0); 846 } 847 848 int 849 tga_builtin_get_curmax(dc, curposp) 850 struct tga_devconfig *dc; 851 struct wsdisplay_curpos *curposp; 852 { 853 854 curposp->x = curposp->y = 64; 855 return (0); 856 } 857 858 /* 859 * Copy columns (characters) in a row (line). 860 */ 861 static void 862 tga_copycols(id, row, srccol, dstcol, ncols) 863 void *id; 864 int row, srccol, dstcol, ncols; 865 { 866 struct rasops_info *ri = id; 867 int y, srcx, dstx, nx; 868 869 y = ri->ri_font->fontheight * row; 870 srcx = ri->ri_font->fontwidth * srccol; 871 dstx = ri->ri_font->fontwidth * dstcol; 872 nx = ri->ri_font->fontwidth * ncols; 873 874 tga_rop(ri, dstx, y, 875 nx, ri->ri_font->fontheight, RAS_SRC, 876 ri, srcx, y); 877 } 878 879 /* 880 * Copy rows (lines). 881 */ 882 static void 883 tga_copyrows(id, srcrow, dstrow, nrows) 884 void *id; 885 int srcrow, dstrow, nrows; 886 { 887 struct rasops_info *ri = id; 888 int srcy, dsty, ny; 889 890 srcy = ri->ri_font->fontheight * srcrow; 891 dsty = ri->ri_font->fontheight * dstrow; 892 ny = ri->ri_font->fontheight * nrows; 893 894 tga_rop(ri, 0, dsty, 895 ri->ri_emuwidth, ny, RAS_SRC, 896 ri, 0, srcy); 897 } 898 899 /* Do we need the src? */ 900 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 901 902 /* A mapping between our API and the TGA card */ 903 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 904 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 905 }; 906 907 /* 908 * Generic TGA raster op. 909 * This covers all possible raster ops, and 910 * clips the sizes and all of that. 911 */ 912 static int 913 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 914 struct rasops_info *dst; 915 int dx, dy, w, h, rop; 916 struct rasops_info *src; 917 int sx, sy; 918 { 919 if (!dst) 920 return -1; 921 if (needsrc[RAS_GETOP(rop)]) { 922 if (src == NULL) 923 return -1; /* We want a src */ 924 /* Clip against src */ 925 if (sx < 0) { 926 w += sx; 927 sx = 0; 928 } 929 if (sy < 0) { 930 h += sy; 931 sy = 0; 932 } 933 if (sx + w > src->ri_emuwidth) 934 w = src->ri_emuwidth - sx; 935 if (sy + h > src->ri_emuheight) 936 h = src->ri_emuheight - sy; 937 } else { 938 if (src != NULL) 939 return -1; /* We need no src */ 940 } 941 /* Clip against dst. We modify src regardless of using it, 942 * since it really doesn't matter. 943 */ 944 if (dx < 0) { 945 w += dx; 946 sx -= dx; 947 dx = 0; 948 } 949 if (dy < 0) { 950 h += dy; 951 sy -= dy; 952 dy = 0; 953 } 954 if (dx + w > dst->ri_emuwidth) 955 w = dst->ri_emuwidth - dx; 956 if (dy + h > dst->ri_emuheight) 957 h = dst->ri_emuheight - dy; 958 if (w <= 0 || h <= 0) 959 return 0; /* Vacuously true; */ 960 if (!src) { 961 /* XXX Punt! */ 962 return -1; 963 } 964 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 965 } 966 967 968 969 /* 970 * Video to Video raster ops. 971 * This function deals with all raster ops that have a src and dst 972 * that are on the card. 973 */ 974 static int 975 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 976 struct rasops_info *dst; 977 int dx, dy, w, h, rop; 978 struct rasops_info *src; 979 int sx, sy; 980 { 981 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 982 int srcb, dstb; 983 int x, y; 984 int xstart, xend, xdir, xinc; 985 int ystart, yend, ydir, yinc; 986 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 987 988 /* 989 * I don't yet want to deal with unaligned guys, really. And we don't 990 * deal with copies from one card to another. 991 */ 992 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 993 /* XXX Punt! */ 994 /* XXX should never happen, since it's only being used to 995 * XXX copy 8-pixel-wide characters. 996 */ 997 return -1; 998 } 999 1000 if (sy >= dy) { 1001 ystart = 0; 1002 yend = h; 1003 ydir = 1; 1004 } else { 1005 ystart = h; 1006 yend = 0; 1007 ydir = -1; 1008 } 1009 if (sx >= dx) { 1010 xstart = 0; 1011 xend = w * (dst->ri_depth / 8); 1012 xdir = 1; 1013 } else { 1014 xstart = w * (dst->ri_depth / 8); 1015 xend = 0; 1016 xdir = -1; 1017 } 1018 xinc = xdir * 4 * 64; 1019 yinc = ydir * dst->ri_stride; 1020 ystart *= dst->ri_stride; 1021 yend *= dst->ri_stride; 1022 srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1023 (sx + src->ri_xorigin) * (src->ri_depth/8); 1024 dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1025 (dx + dst->ri_xorigin ) * (dst->ri_depth/8); 1026 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1027 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1028 for (y = ystart; (ydir * y) < (ydir * yend); y += yinc) { 1029 for (x = xstart; (xdir * x) < (xdir * xend); x += xinc) { 1030 /* XXX XXX Eight writes to different addresses should fill 1031 * XXX XXX up the write buffers on 21064 and 21164 chips, 1032 * XXX XXX but later CPUs might have larger write buffers which 1033 * XXX XXX require further unrolling of this loop, or the 1034 * XXX XXX insertion of memory barriers. 1035 */ 1036 TGAWALREG(dc, TGA_REG_GCSR, 0, srcb + y + x + 3 * 64); 1037 TGAWALREG(dc, TGA_REG_GCDR, 0, dstb + y + x + 3 * 64); 1038 TGAWALREG(dc, TGA_REG_GCSR, 1, srcb + y + x + 2 * 64); 1039 TGAWALREG(dc, TGA_REG_GCDR, 1, dstb + y + x + 2 * 64); 1040 TGAWALREG(dc, TGA_REG_GCSR, 2, srcb + y + x + 1 * 64); 1041 TGAWALREG(dc, TGA_REG_GCDR, 2, dstb + y + x + 1 * 64); 1042 TGAWALREG(dc, TGA_REG_GCSR, 3, srcb + y + x + 0 * 64); 1043 TGAWALREG(dc, TGA_REG_GCDR, 3, dstb + y + x + 0 * 64); 1044 } 1045 } 1046 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1047 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1048 return 0; 1049 } 1050 1051 1052 void tga_putchar (c, row, col, uc, attr) 1053 void *c; 1054 int row, col; 1055 u_int uc; 1056 long attr; 1057 { 1058 struct rasops_info *ri = c; 1059 struct tga_devconfig *dc = ri->ri_hw; 1060 int fs, height, width; 1061 u_char *fr; 1062 int32_t *rp; 1063 1064 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1065 1066 height = ri->ri_font->fontheight; 1067 width = ri->ri_font->fontwidth; 1068 1069 uc -= ri->ri_font->firstchar; 1070 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1071 fs = ri->ri_font->stride; 1072 1073 /* Set foreground and background color. XXX memoize this somehow? 1074 * The rasops code has already expanded the color entry to 32 bits 1075 * for us, even for 8-bit displays, so we don't have to do anything. 1076 */ 1077 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1078 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1079 1080 /* Set raster operation to "copy"... */ 1081 if (ri->ri_depth == 8) 1082 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1083 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1084 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1085 1086 /* Set which pixels we're drawing (of a possible 32). */ 1087 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1088 1089 /* Set drawing mode to opaque stipple. */ 1090 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1091 1092 /* Insert write barrier before actually sending data */ 1093 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1094 TGAREGWB(dc, TGA_REG_GMOR, 1); 1095 1096 while(height--) { 1097 /* The actual stipple write */ 1098 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1099 1100 fr += fs; 1101 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1102 } 1103 1104 /* Do underline */ 1105 if ((attr & 1) != 0) { 1106 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1107 *rp = 0xffffffff; 1108 } 1109 1110 /* Set grapics mode back to normal. */ 1111 TGAWREG(dc, TGA_REG_GMOR, 0); 1112 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1113 1114 } 1115 1116 static void 1117 tga_eraserows(c, row, num, attr) 1118 void *c; 1119 int row, num; 1120 long attr; 1121 { 1122 struct rasops_info *ri = c; 1123 struct tga_devconfig *dc = ri->ri_hw; 1124 int32_t color, lines, pixels; 1125 int32_t *rp; 1126 1127 color = ri->ri_devcmap[(attr >> 16) & 15]; 1128 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1129 lines = num * ri->ri_font->fontheight; 1130 pixels = ri->ri_emuwidth - 1; 1131 1132 /* Set fill color in block-color registers */ 1133 TGAWREG(dc, TGA_REG_GBCR0, color); 1134 TGAWREG(dc, TGA_REG_GBCR1, color); 1135 if (ri->ri_depth != 8) { 1136 TGAWREG(dc, TGA_REG_GBCR2, color); 1137 TGAWREG(dc, TGA_REG_GBCR3, color); 1138 TGAWREG(dc, TGA_REG_GBCR4, color); 1139 TGAWREG(dc, TGA_REG_GBCR5, color); 1140 TGAWREG(dc, TGA_REG_GBCR6, color); 1141 TGAWREG(dc, TGA_REG_GBCR7, color); 1142 } 1143 1144 /* Set raster operation to "copy"... */ 1145 if (ri->ri_depth == 8) 1146 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1147 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1148 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1149 1150 /* Set which pixels we're drawing (of a possible 32). */ 1151 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1152 1153 /* Set drawing mode to block fill. */ 1154 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1155 1156 /* Insert write barrier before actually sending data */ 1157 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1158 TGAREGWB(dc, TGA_REG_GMOR, 1); 1159 1160 while (lines--) { 1161 *rp = pixels; 1162 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1163 } 1164 1165 /* Set grapics mode back to normal. */ 1166 TGAWREG(dc, TGA_REG_GMOR, 0); 1167 1168 } 1169 1170 static void 1171 tga_erasecols (c, row, col, num, attr) 1172 void *c; 1173 int row, col, num; 1174 long attr; 1175 { 1176 struct rasops_info *ri = c; 1177 struct tga_devconfig *dc = ri->ri_hw; 1178 int32_t color, lines, pixels; 1179 int32_t *rp; 1180 1181 color = ri->ri_devcmap[(attr >> 16) & 15]; 1182 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1183 lines = ri->ri_font->fontheight; 1184 pixels = (num * ri->ri_font->fontwidth) - 1; 1185 1186 /* Set fill color in block-color registers */ 1187 TGAWREG(dc, TGA_REG_GBCR0, color); 1188 TGAWREG(dc, TGA_REG_GBCR1, color); 1189 if (ri->ri_depth != 8) { 1190 TGAWREG(dc, TGA_REG_GBCR2, color); 1191 TGAWREG(dc, TGA_REG_GBCR3, color); 1192 TGAWREG(dc, TGA_REG_GBCR4, color); 1193 TGAWREG(dc, TGA_REG_GBCR5, color); 1194 TGAWREG(dc, TGA_REG_GBCR6, color); 1195 TGAWREG(dc, TGA_REG_GBCR7, color); 1196 } 1197 1198 /* Set raster operation to "copy"... */ 1199 if (ri->ri_depth == 8) 1200 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1201 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1202 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1203 1204 /* Set which pixels we're drawing (of a possible 32). */ 1205 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1206 1207 /* Set drawing mode to block fill. */ 1208 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1209 1210 /* Insert write barrier before actually sending data */ 1211 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1212 TGAREGWB(dc, TGA_REG_GMOR, 1); 1213 1214 while (lines--) { 1215 *rp = pixels; 1216 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1217 } 1218 1219 /* Set grapics mode back to normal. */ 1220 TGAWREG(dc, TGA_REG_GMOR, 0); 1221 } 1222 1223 1224 static void 1225 tga_ramdac_wr(v, btreg, val) 1226 void *v; 1227 u_int btreg; 1228 u_int8_t val; 1229 { 1230 struct tga_devconfig *dc = v; 1231 1232 if (btreg > BT485_REG_MAX) 1233 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1234 1235 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1236 TGAREGWB(dc, TGA_REG_EPDR, 1); 1237 } 1238 1239 static void 1240 tga2_ramdac_wr(v, btreg, val) 1241 void *v; 1242 u_int btreg; 1243 u_int8_t val; 1244 { 1245 struct tga_devconfig *dc = v; 1246 bus_space_handle_t ramdac; 1247 1248 if (btreg > BT485_REG_MAX) 1249 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1250 1251 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1252 (0xe << 12) + (btreg << 8), 4, &ramdac); 1253 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1254 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1255 } 1256 1257 static u_int8_t 1258 tga_bt463_rd(v, btreg) 1259 void *v; 1260 u_int btreg; 1261 { 1262 struct tga_devconfig *dc = v; 1263 tga_reg_t rdval; 1264 1265 /* 1266 * Strobe CE# (high->low->high) since status and data are latched on 1267 * the falling and rising edges (repsectively) of this active-low signal. 1268 */ 1269 1270 TGAREGWB(dc, TGA_REG_EPSR, 1); 1271 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1272 TGAREGWB(dc, TGA_REG_EPSR, 1); 1273 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1274 1275 TGAREGRB(dc, TGA_REG_EPSR, 1); 1276 1277 rdval = TGARREG(dc, TGA_REG_EPDR); 1278 TGAREGWB(dc, TGA_REG_EPSR, 1); 1279 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1280 1281 return (rdval >> 16) & 0xff; 1282 } 1283 1284 static void 1285 tga_bt463_wr(v, btreg, val) 1286 void *v; 1287 u_int btreg; 1288 u_int8_t val; 1289 { 1290 struct tga_devconfig *dc = v; 1291 1292 /* 1293 * In spite of the 21030 documentation, to set the MPU bus bits for 1294 * a write, you set them in the upper bits of EPDR, not EPSR. 1295 */ 1296 1297 /* 1298 * Strobe CE# (high->low->high) since status and data are latched on 1299 * the falling and rising edges of this active-low signal. 1300 */ 1301 1302 TGAREGWB(dc, TGA_REG_EPDR, 1); 1303 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1304 TGAREGWB(dc, TGA_REG_EPDR, 1); 1305 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1306 TGAREGWB(dc, TGA_REG_EPDR, 1); 1307 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1308 1309 } 1310 1311 static u_int8_t 1312 tga_ramdac_rd(v, btreg) 1313 void *v; 1314 u_int btreg; 1315 { 1316 struct tga_devconfig *dc = v; 1317 tga_reg_t rdval; 1318 1319 if (btreg > BT485_REG_MAX) 1320 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1321 1322 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1323 TGAREGWB(dc, TGA_REG_EPSR, 1); 1324 1325 rdval = TGARREG(dc, TGA_REG_EPDR); 1326 return (rdval >> 16) & 0xff; /* XXX */ 1327 } 1328 1329 static u_int8_t 1330 tga2_ramdac_rd(v, btreg) 1331 void *v; 1332 u_int btreg; 1333 { 1334 struct tga_devconfig *dc = v; 1335 bus_space_handle_t ramdac; 1336 u_int8_t retval; 1337 1338 if (btreg > BT485_REG_MAX) 1339 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1340 1341 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1342 (0xe << 12) + (btreg << 8), 4, &ramdac); 1343 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1344 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1345 return retval; 1346 } 1347 1348 #include <dev/ic/decmonitors.c> 1349 void tga2_ics9110_wr __P(( 1350 struct tga_devconfig *dc, 1351 int dotclock 1352 )); 1353 1354 void 1355 tga2_init(dc, m) 1356 struct tga_devconfig *dc; 1357 int m; 1358 { 1359 1360 tga2_ics9110_wr(dc, decmonitors[m].dotclock); 1361 #if 0 1362 TGAWREG(dc, TGA_REG_VHCR, 1363 ((decmonitors[m].hbp / 4) << 21) | 1364 ((decmonitors[m].hsync / 4) << 14) | 1365 (((decmonitors[m].hfp - 4) / 4) << 9) | 1366 ((decmonitors[m].cols + 4) / 4)); 1367 #else 1368 TGAWREG(dc, TGA_REG_VHCR, 1369 ((decmonitors[m].hbp / 4) << 21) | 1370 ((decmonitors[m].hsync / 4) << 14) | 1371 (((decmonitors[m].hfp) / 4) << 9) | 1372 ((decmonitors[m].cols) / 4)); 1373 #endif 1374 TGAWREG(dc, TGA_REG_VVCR, 1375 (decmonitors[m].vbp << 22) | 1376 (decmonitors[m].vsync << 16) | 1377 (decmonitors[m].vfp << 11) | 1378 (decmonitors[m].rows)); 1379 TGAWREG(dc, TGA_REG_VVBR, 1); 1380 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1381 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1382 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1383 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1384 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1385 } 1386 1387 void 1388 tga2_ics9110_wr(dc, dotclock) 1389 struct tga_devconfig *dc; 1390 int dotclock; 1391 { 1392 bus_space_handle_t clock; 1393 u_int32_t valU; 1394 int N, M, R, V, X; 1395 int i; 1396 1397 switch (dotclock) { 1398 case 130808000: 1399 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1400 case 119840000: 1401 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1402 case 108180000: 1403 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1404 case 103994000: 1405 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1406 case 175000000: 1407 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1408 case 75000000: 1409 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1410 case 74000000: 1411 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1412 case 69000000: 1413 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1414 case 65000000: 1415 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1416 case 50000000: 1417 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1418 case 40000000: 1419 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1420 case 31500000: 1421 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1422 case 25175000: 1423 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1424 case 135000000: 1425 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1426 case 110000000: 1427 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1428 case 202500000: 1429 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1430 default: 1431 panic("unrecognized clock rate %d\n", dotclock); 1432 } 1433 1434 /* XXX -- hard coded, bad */ 1435 valU = N | ( M << 7 ) | (V << 14); 1436 valU |= (X << 15) | (R << 17); 1437 valU |= 0x17 << 19; 1438 1439 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1440 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1441 1442 for (i=24; i>0; i--) { 1443 u_int32_t writeval; 1444 1445 writeval = valU & 0x1; 1446 if (i == 1) 1447 writeval |= 0x2; 1448 valU >>= 1; 1449 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1450 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1451 } 1452 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1453 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1454 &clock); /* XXX */ 1455 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1456 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1457 } 1458
Indexes created Thu Sep 25 06:09:39 GMT 2025