tga.c revision 1.30
1 /* $NetBSD: tga.c,v 1.30 2000/12/28 22:59:15 sommerfeld Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/param.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/device.h> 34 #include <sys/conf.h> 35 #include <sys/malloc.h> 36 #include <sys/buf.h> 37 #include <sys/ioctl.h> 38 39 #include <machine/bus.h> 40 #include <machine/intr.h> 41 42 #include <dev/pci/pcireg.h> 43 #include <dev/pci/pcivar.h> 44 #include <dev/pci/pcidevs.h> 45 #include <dev/pci/tgareg.h> 46 #include <dev/pci/tgavar.h> 47 #include <dev/ic/bt485reg.h> 48 #include <dev/ic/bt485var.h> 49 #include <dev/ic/bt463reg.h> 50 #include <dev/ic/bt463var.h> 51 52 #include <dev/wscons/wsconsio.h> 53 #include <dev/wscons/wscons_raster.h> 54 #include <dev/rasops/rasops.h> 55 #include <dev/wsfont/wsfont.h> 56 #include <uvm/uvm_extern.h> 57 58 #ifdef __alpha__ 59 #include <machine/pte.h> 60 #endif 61 #ifdef __mips__ 62 #include <mips/pte.h> 63 #endif 64 65 int tgamatch __P((struct device *, struct cfdata *, void *)); 66 void tgaattach __P((struct device *, struct device *, void *)); 67 int tgaprint __P((void *, const char *)); 68 69 struct cfattach tga_ca = { 70 sizeof(struct tga_softc), tgamatch, tgaattach, 71 }; 72 73 int tga_identify __P((struct tga_devconfig *)); 74 const struct tga_conf *tga_getconf __P((int)); 75 static void tga_getdevconfig __P((bus_space_tag_t memt, pci_chipset_tag_t pc, 76 pcitag_t tag, struct tga_devconfig *dc)); 77 78 struct tga_devconfig tga_console_dc; 79 80 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *)); 81 paddr_t tga_mmap __P((void *, off_t, int)); 82 static void tga_copyrows __P((void *, int, int, int)); 83 static void tga_copycols __P((void *, int, int, int, int)); 84 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *, 85 void **, int *, int *, long *)); 86 static void tga_free_screen __P((void *, void *)); 87 static int tga_show_screen __P((void *, void *, int, 88 void (*) (void *, int, int), void *)); 89 static int tga_rop __P((struct rasops_info *, int, int, int, int, int, 90 struct rasops_info *, int, int)); 91 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int, 92 int, struct rasops_info *, int, int )); 93 static void tga_putchar __P((void *c, int row, int col, 94 u_int uc, long attr)); 95 static void tga_eraserows __P((void *, int, int, long)); 96 static void tga_erasecols __P((void *, int, int, int, long)); 97 void tga2_init __P((struct tga_devconfig *, int)); 98 99 static void tga_config_interrupts __P((struct device *)); 100 101 /* RAMDAC interface functions */ 102 static int tga_sched_update __P((void *, void (*)(void *))); 103 static void tga_ramdac_wr __P((void *, u_int, u_int8_t)); 104 static u_int8_t tga_ramdac_rd __P((void *, u_int)); 105 static void tga_bt463_wr __P((void *, u_int, u_int8_t)); 106 static u_int8_t tga_bt463_rd __P((void *, u_int)); 107 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t)); 108 static u_int8_t tga2_ramdac_rd __P((void *, u_int)); 109 110 /* Interrupt handler */ 111 static int tga_intr __P((void *)); 112 113 /* The NULL entries will get filled in by rasops_init(). 114 * XXX and the non-NULL ones will be overwritten; reset after calling it. 115 */ 116 struct wsdisplay_emulops tga_emulops = { 117 NULL, 118 NULL, 119 tga_putchar, 120 tga_copycols, 121 tga_erasecols, 122 tga_copyrows, 123 tga_eraserows, 124 NULL, 125 }; 126 127 struct wsscreen_descr tga_stdscreen = { 128 "std", 129 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 130 &tga_emulops, 131 0, 0, 132 WSSCREEN_REVERSE 133 }; 134 135 const struct wsscreen_descr *_tga_scrlist[] = { 136 &tga_stdscreen, 137 /* XXX other formats, graphics screen? */ 138 }; 139 140 struct wsscreen_list tga_screenlist = { 141 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 142 }; 143 144 struct wsdisplay_accessops tga_accessops = { 145 tga_ioctl, 146 tga_mmap, 147 tga_alloc_screen, 148 tga_free_screen, 149 tga_show_screen, 150 0 /* load_font */ 151 }; 152 153 static void tga_blank __P((struct tga_devconfig *)); 154 static void tga_unblank __P((struct tga_devconfig *)); 155 156 int 157 tgamatch(parent, match, aux) 158 struct device *parent; 159 struct cfdata *match; 160 void *aux; 161 { 162 struct pci_attach_args *pa = aux; 163 164 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 165 return (0); 166 167 switch (PCI_PRODUCT(pa->pa_id)) { 168 case PCI_PRODUCT_DEC_21030: 169 case PCI_PRODUCT_DEC_PBXGB: 170 return 10; 171 default: 172 return 0; 173 } 174 return (0); 175 } 176 177 static void 178 tga_getdevconfig(memt, pc, tag, dc) 179 bus_space_tag_t memt; 180 pci_chipset_tag_t pc; 181 pcitag_t tag; 182 struct tga_devconfig *dc; 183 { 184 const struct tga_conf *tgac; 185 struct rasops_info *rip; 186 int cookie; 187 bus_size_t pcisize; 188 int i, flags; 189 190 dc->dc_memt = memt; 191 192 dc->dc_pcitag = tag; 193 194 /* XXX magic number */ 195 if (pci_mapreg_info(pc, tag, 0x10, 196 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 197 &dc->dc_pcipaddr, &pcisize, &flags)) 198 return; 199 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 200 panic("tga memory not prefetchable"); 201 202 if (bus_space_map(memt, dc->dc_pcipaddr, pcisize, 203 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 204 return; 205 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh); 206 #ifdef __alpha__ 207 dc->dc_paddr = ALPHA_K0SEG_TO_PHYS(dc->dc_vaddr); /* XXX */ 208 #endif 209 #ifdef arc 210 bus_space_paddr(memt, dc->dc_memh, &dc->dc_paddr); 211 #endif 212 213 bus_space_subregion(dc->dc_memt, dc->dc_memh, 214 TGA_MEM_CREGS, TGA_CREGS_SIZE, 215 &dc->dc_regs); 216 dc->dc_tga_type = tga_identify(dc); 217 218 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 219 if (tgac == NULL) 220 return; 221 222 #if 0 223 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 224 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 225 panic("tga_getdevconfig: memory size mismatch?"); 226 #endif 227 228 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 229 case 0x01: 230 case 0x02: 231 case 0x03: 232 case 0x04: 233 dc->dc_tga2 = 0; 234 break; 235 case 0x20: 236 case 0x21: 237 case 0x22: 238 dc->dc_tga2 = 1; 239 break; 240 default: 241 panic("tga_getdevconfig: TGA Revision not recognized"); 242 } 243 244 if (dc->dc_tga2) { 245 int monitor; 246 247 monitor = (~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f; 248 tga2_init(dc, monitor); 249 } 250 251 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 252 case 0: 253 dc->dc_wid = 8192; 254 break; 255 256 case 1: 257 dc->dc_wid = 8196; 258 break; 259 260 default: 261 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 262 break; 263 } 264 265 /* 266 * XXX XXX Turning off "odd" shouldn't be necessary, 267 * XXX XXX but I can't make X work with the weird size. 268 */ 269 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 270 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 271 TGAWREG(dc, TGA_REG_VHCR, 272 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 273 dc->dc_wid -= 4; 274 } 275 276 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 277 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 278 279 /* XXX this seems to be what DEC does */ 280 TGAWREG(dc, TGA_REG_CCBR, 0); 281 TGAWREG(dc, TGA_REG_VVBR, 1); 282 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 283 1 * tgac->tgac_vvbr_units; 284 dc->dc_blanked = 1; 285 tga_unblank(dc); 286 287 /* 288 * Set all bits in the pixel mask, to enable writes to all pixels. 289 * It seems that the console firmware clears some of them 290 * under some circumstances, which causes cute vertical stripes. 291 */ 292 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 293 294 /* clear the screen */ 295 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t)) 296 *(u_int32_t *)(dc->dc_videobase + i) = 0; 297 298 /* Initialize rasops descriptor */ 299 rip = &dc->dc_rinfo; 300 rip->ri_flg = RI_CENTER; 301 rip->ri_depth = tgac->tgac_phys_depth; 302 rip->ri_bits = (void *)dc->dc_videobase; 303 rip->ri_width = dc->dc_wid; 304 rip->ri_height = dc->dc_ht; 305 rip->ri_stride = dc->dc_rowbytes; 306 rip->ri_hw = dc; 307 308 if (tgac->tgac_phys_depth == 32) { 309 rip->ri_rnum = 8; 310 rip->ri_gnum = 8; 311 rip->ri_bnum = 8; 312 rip->ri_rpos = 16; 313 rip->ri_gpos = 8; 314 rip->ri_bpos = 0; 315 } 316 317 wsfont_init(); 318 /* prefer 8 pixel wide font */ 319 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0) 320 cookie = wsfont_find(NULL, 0, 0, 0); 321 if (cookie <= 0) { 322 printf("tga: no appropriate fonts.\n"); 323 return; 324 } 325 326 /* the accelerated tga_putchar() needs LSbit left */ 327 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font, 328 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) { 329 printf("tga: couldn't lock font\n"); 330 return; 331 } 332 dc->dc_rinfo.ri_wsfcookie = cookie; 333 334 rasops_init(rip, 34, 80); 335 336 /* add our accelerated functions */ 337 /* XXX shouldn't have to do this; rasops should leave non-NULL 338 * XXX entries alone. 339 */ 340 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 341 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 342 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 343 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 344 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 345 346 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 347 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 348 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 349 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 350 351 352 dc->dc_intrenabled = 0; 353 } 354 355 void 356 tgaattach(parent, self, aux) 357 struct device *parent, *self; 358 void *aux; 359 { 360 struct pci_attach_args *pa = aux; 361 struct tga_softc *sc = (struct tga_softc *)self; 362 struct wsemuldisplaydev_attach_args aa; 363 pci_intr_handle_t intrh; 364 const char *intrstr; 365 u_int8_t rev; 366 int console; 367 368 #if defined(__alpha__) || defined(arc) 369 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 370 #else 371 console = 0; 372 #endif 373 if (console) { 374 sc->sc_dc = &tga_console_dc; 375 sc->nscreens = 1; 376 } else { 377 sc->sc_dc = (struct tga_devconfig *) 378 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK); 379 bzero(sc->sc_dc, sizeof(struct tga_devconfig)); 380 tga_getdevconfig(pa->pa_memt, pa->pa_pc, pa->pa_tag, 381 sc->sc_dc); 382 } 383 if (sc->sc_dc->dc_vaddr == NULL) { 384 printf(": couldn't map memory space; punt!\n"); 385 return; 386 } 387 388 /* XXX say what's going on. */ 389 intrstr = NULL; 390 if (pci_intr_map(pa, &intrh)) { 391 printf(": couldn't map interrupt"); 392 return; 393 } 394 intrstr = pci_intr_string(pa->pa_pc, intrh); 395 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 396 sc->sc_dc); 397 if (sc->sc_intr == NULL) { 398 printf(": couldn't establish interrupt"); 399 if (intrstr != NULL) 400 printf("at %s", intrstr); 401 printf("\n"); 402 return; 403 } 404 405 rev = PCI_REVISION(pa->pa_class); 406 switch (rev) { 407 case 0x1: 408 case 0x2: 409 case 0x3: 410 printf(": DC21030 step %c", 'A' + rev - 1); 411 break; 412 case 0x20: 413 printf(": TGA2 abstract software model"); 414 break; 415 case 0x21: 416 case 0x22: 417 printf(": TGA2 pass %d", rev - 0x20); 418 break; 419 420 default: 421 printf("unknown stepping (0x%x)", rev); 422 break; 423 } 424 printf(", "); 425 426 /* 427 * Get RAMDAC function vectors and call the RAMDAC functions 428 * to allocate its private storage and pass that back to us. 429 */ 430 431 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs(); 432 if (!sc->sc_dc->dc_tga2) { 433 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 434 sc->sc_dc->dc_ramdac_cookie = 435 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 436 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 437 else 438 sc->sc_dc->dc_ramdac_cookie = 439 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 440 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 441 } else { 442 sc->sc_dc->dc_ramdac_cookie = 443 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc, 444 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 445 } 446 447 /* 448 * Initialize the RAMDAC. Initialization includes disabling 449 * cursor, setting a sane colormap, etc. 450 */ 451 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie); 452 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */ 453 454 if (sc->sc_dc->dc_tgaconf == NULL) { 455 printf("unknown board configuration\n"); 456 return; 457 } 458 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name); 459 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname, 460 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht, 461 sc->sc_dc->dc_tgaconf->tgac_phys_depth, 462 sc->sc_dc->dc_ramdac_funcs->ramdac_name); 463 464 if (intrstr != NULL) 465 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname, 466 intrstr); 467 468 aa.console = console; 469 aa.scrdata = &tga_screenlist; 470 aa.accessops = &tga_accessops; 471 aa.accesscookie = sc; 472 473 config_found(self, &aa, wsemuldisplaydevprint); 474 475 config_interrupts(self, tga_config_interrupts); 476 } 477 478 static void 479 tga_config_interrupts (d) 480 struct device *d; 481 { 482 struct tga_softc *sc = (struct tga_softc *)d; 483 sc->sc_dc->dc_intrenabled = 1; 484 } 485 486 487 int 488 tga_ioctl(v, cmd, data, flag, p) 489 void *v; 490 u_long cmd; 491 caddr_t data; 492 int flag; 493 struct proc *p; 494 { 495 struct tga_softc *sc = v; 496 struct tga_devconfig *dc = sc->sc_dc; 497 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 498 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 499 500 switch (cmd) { 501 case WSDISPLAYIO_GTYPE: 502 *(u_int *)data = WSDISPLAY_TYPE_TGA; 503 return (0); 504 505 case WSDISPLAYIO_GINFO: 506 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 507 wsd_fbip->height = sc->sc_dc->dc_ht; 508 wsd_fbip->width = sc->sc_dc->dc_wid; 509 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 510 wsd_fbip->cmsize = 256; /* XXX ??? */ 511 #undef wsd_fbip 512 return (0); 513 514 case WSDISPLAYIO_GETCMAP: 515 return (*dcrf->ramdac_get_cmap)(dcrc, 516 (struct wsdisplay_cmap *)data); 517 518 case WSDISPLAYIO_PUTCMAP: 519 return (*dcrf->ramdac_set_cmap)(dcrc, 520 (struct wsdisplay_cmap *)data); 521 522 case WSDISPLAYIO_SVIDEO: 523 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 524 tga_blank(sc->sc_dc); 525 else 526 tga_unblank(sc->sc_dc); 527 return (0); 528 529 case WSDISPLAYIO_GVIDEO: 530 *(u_int *)data = dc->dc_blanked ? 531 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 532 return (0); 533 534 case WSDISPLAYIO_GCURPOS: 535 return (*dcrf->ramdac_get_curpos)(dcrc, 536 (struct wsdisplay_curpos *)data); 537 538 case WSDISPLAYIO_SCURPOS: 539 return (*dcrf->ramdac_set_curpos)(dcrc, 540 (struct wsdisplay_curpos *)data); 541 542 case WSDISPLAYIO_GCURMAX: 543 return (*dcrf->ramdac_get_curmax)(dcrc, 544 (struct wsdisplay_curpos *)data); 545 546 case WSDISPLAYIO_GCURSOR: 547 return (*dcrf->ramdac_get_cursor)(dcrc, 548 (struct wsdisplay_cursor *)data); 549 550 case WSDISPLAYIO_SCURSOR: 551 return (*dcrf->ramdac_set_cursor)(dcrc, 552 (struct wsdisplay_cursor *)data); 553 } 554 return (-1); 555 } 556 557 static int 558 tga_sched_update(v, f) 559 void *v; 560 void (*f) __P((void *)); 561 { 562 struct tga_devconfig *dc = v; 563 564 if (dc->dc_intrenabled) { 565 /* Arrange for f to be called at the next end-of-frame interrupt */ 566 dc->dc_ramdac_intr = f; 567 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 568 } else { 569 /* Spin until the end-of-frame, then call f */ 570 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 571 TGAREGWB(dc, TGA_REG_SISR, 1); 572 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 573 ; 574 f(dc->dc_ramdac_cookie); 575 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 576 TGAREGWB(dc, TGA_REG_SISR, 1); 577 } 578 579 return 0; 580 } 581 582 static int 583 tga_intr(v) 584 void *v; 585 { 586 struct tga_devconfig *dc = v; 587 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 588 589 u_int32_t reg; 590 591 reg = TGARREG(dc, TGA_REG_SISR); 592 if (( reg & 0x00010001) != 0x00010001) { 593 /* Odd. We never set any of the other interrupt enables. */ 594 if ((reg & 0x1f) != 0) { 595 /* Clear the mysterious pending interrupts. */ 596 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 597 TGAREGWB(dc, TGA_REG_SISR, 1); 598 /* This was our interrupt, even if we're puzzled as to why 599 * we got it. Don't make the interrupt handler think it 600 * was a stray. 601 */ 602 return -1; 603 } else { 604 return 0; 605 } 606 } 607 dc->dc_ramdac_intr(dcrc); 608 dc->dc_ramdac_intr = NULL; 609 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 610 TGAREGWB(dc, TGA_REG_SISR, 1); 611 return (1); 612 } 613 614 paddr_t 615 tga_mmap(v, offset, prot) 616 void *v; 617 off_t offset; 618 int prot; 619 { 620 621 /* XXX NEW MAPPING CODE... */ 622 623 #if defined(__alpha__) 624 struct tga_softc *sc = v; 625 626 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 627 return -1; 628 return alpha_btop(sc->sc_dc->dc_paddr + offset); 629 #elif defined(__mips__) 630 struct tga_softc *sc = v; 631 632 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 633 return -1; 634 return mips_btop(sc->sc_dc->dc_paddr + offset); 635 #else 636 return (-1); 637 #endif 638 } 639 640 static int 641 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp) 642 void *v; 643 const struct wsscreen_descr *type; 644 void **cookiep; 645 int *curxp, *curyp; 646 long *attrp; 647 { 648 struct tga_softc *sc = v; 649 long defattr; 650 651 if (sc->nscreens > 0) 652 return (ENOMEM); 653 654 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 655 *curxp = 0; 656 *curyp = 0; 657 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo, 658 0, 0, 0, &defattr); 659 *attrp = defattr; 660 sc->nscreens++; 661 return (0); 662 } 663 664 static void 665 tga_free_screen(v, cookie) 666 void *v; 667 void *cookie; 668 { 669 struct tga_softc *sc = v; 670 671 if (sc->sc_dc == &tga_console_dc) 672 panic("tga_free_screen: console"); 673 674 sc->nscreens--; 675 } 676 677 static int 678 tga_show_screen(v, cookie, waitok, cb, cbarg) 679 void *v; 680 void *cookie; 681 int waitok; 682 void (*cb) __P((void *, int, int)); 683 void *cbarg; 684 { 685 686 return (0); 687 } 688 689 int 690 tga_cnattach(iot, memt, pc, bus, device, function) 691 bus_space_tag_t iot, memt; 692 pci_chipset_tag_t pc; 693 int bus, device, function; 694 { 695 struct tga_devconfig *dcp = &tga_console_dc; 696 long defattr; 697 698 tga_getdevconfig(memt, pc, 699 pci_make_tag(pc, bus, device, function), dcp); 700 701 /* sanity checks */ 702 if (dcp->dc_vaddr == NULL) 703 panic("tga_console(%d, %d): couldn't map memory space", 704 device, function); 705 if (dcp->dc_tgaconf == NULL) 706 panic("tga_console(%d, %d): unknown board configuration", 707 device, function); 708 709 /* 710 * Initialize the RAMDAC but DO NOT allocate any private storage. 711 * Initialization includes disabling cursor, setting a sane 712 * colormap, etc. It will be reinitialized in tgaattach(). 713 */ 714 if (dcp->dc_tga2) 715 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 716 tga2_ramdac_rd); 717 else { 718 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 719 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 720 tga_ramdac_rd); 721 else { 722 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 723 tga_bt463_rd); 724 } 725 } 726 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 727 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 728 729 return(0); 730 } 731 732 /* 733 * Functions to blank and unblank the display. 734 */ 735 static void 736 tga_blank(dc) 737 struct tga_devconfig *dc; 738 { 739 740 if (!dc->dc_blanked) { 741 dc->dc_blanked = 1; 742 /* XXX */ 743 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 744 } 745 } 746 747 static void 748 tga_unblank(dc) 749 struct tga_devconfig *dc; 750 { 751 752 if (dc->dc_blanked) { 753 dc->dc_blanked = 0; 754 /* XXX */ 755 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 756 } 757 } 758 759 /* 760 * Functions to manipulate the built-in cursor handing hardware. 761 */ 762 int 763 tga_builtin_set_cursor(dc, cursorp) 764 struct tga_devconfig *dc; 765 struct wsdisplay_cursor *cursorp; 766 { 767 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 768 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 769 int count, error, v; 770 771 v = cursorp->which; 772 if (v & WSDISPLAY_CURSOR_DOCMAP) { 773 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 774 if (error) 775 return (error); 776 } 777 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 778 if ((u_int)cursorp->size.x != 64 || 779 (u_int)cursorp->size.y > 64) 780 return (EINVAL); 781 /* The cursor is 2 bits deep, and there is no mask */ 782 count = (cursorp->size.y * 64 * 2) / NBBY; 783 if (!uvm_useracc(cursorp->image, count, B_READ)) 784 return (EFAULT); 785 } 786 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 787 return EINVAL; 788 789 /* parameters are OK; do it */ 790 if (v & WSDISPLAY_CURSOR_DOCUR) { 791 if (cursorp->enable) 792 /* XXX */ 793 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04); 794 else 795 /* XXX */ 796 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04); 797 } 798 if (v & WSDISPLAY_CURSOR_DOPOS) { 799 TGAWREG(dc, TGA_REG_CXYR, 800 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff)); 801 } 802 if (v & WSDISPLAY_CURSOR_DOCMAP) { 803 /* can't fail. */ 804 dcrf->ramdac_set_curcmap(dcrc, cursorp); 805 } 806 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 807 count = ((64 * 2) / NBBY) * cursorp->size.y; 808 TGAWREG(dc, TGA_REG_CCBR, 809 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10)); 810 copyin(cursorp->image, (char *)(dc->dc_vaddr + 811 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 812 count); /* can't fail. */ 813 } 814 return (0); 815 } 816 817 int 818 tga_builtin_get_cursor(dc, cursorp) 819 struct tga_devconfig *dc; 820 struct wsdisplay_cursor *cursorp; 821 { 822 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 823 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 824 int count, error; 825 826 cursorp->which = WSDISPLAY_CURSOR_DOALL & 827 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 828 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 829 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 830 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 831 cursorp->size.x = 64; 832 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 833 834 if (cursorp->image != NULL) { 835 count = (cursorp->size.y * 64 * 2) / NBBY; 836 error = copyout((char *)(dc->dc_vaddr + 837 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 838 cursorp->image, count); 839 if (error) 840 return (error); 841 /* No mask */ 842 } 843 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 844 return (error); 845 } 846 847 int 848 tga_builtin_set_curpos(dc, curposp) 849 struct tga_devconfig *dc; 850 struct wsdisplay_curpos *curposp; 851 { 852 853 TGAWREG(dc, TGA_REG_CXYR, 854 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 855 return (0); 856 } 857 858 int 859 tga_builtin_get_curpos(dc, curposp) 860 struct tga_devconfig *dc; 861 struct wsdisplay_curpos *curposp; 862 { 863 864 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 865 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 866 return (0); 867 } 868 869 int 870 tga_builtin_get_curmax(dc, curposp) 871 struct tga_devconfig *dc; 872 struct wsdisplay_curpos *curposp; 873 { 874 875 curposp->x = curposp->y = 64; 876 return (0); 877 } 878 879 /* 880 * Copy columns (characters) in a row (line). 881 */ 882 static void 883 tga_copycols(id, row, srccol, dstcol, ncols) 884 void *id; 885 int row, srccol, dstcol, ncols; 886 { 887 struct rasops_info *ri = id; 888 int y, srcx, dstx, nx; 889 890 y = ri->ri_font->fontheight * row; 891 srcx = ri->ri_font->fontwidth * srccol; 892 dstx = ri->ri_font->fontwidth * dstcol; 893 nx = ri->ri_font->fontwidth * ncols; 894 895 tga_rop(ri, dstx, y, 896 nx, ri->ri_font->fontheight, RAS_SRC, 897 ri, srcx, y); 898 } 899 900 /* 901 * Copy rows (lines). 902 */ 903 static void 904 tga_copyrows(id, srcrow, dstrow, nrows) 905 void *id; 906 int srcrow, dstrow, nrows; 907 { 908 struct rasops_info *ri = id; 909 int srcy, dsty, ny; 910 911 srcy = ri->ri_font->fontheight * srcrow; 912 dsty = ri->ri_font->fontheight * dstrow; 913 ny = ri->ri_font->fontheight * nrows; 914 915 tga_rop(ri, 0, dsty, 916 ri->ri_emuwidth, ny, RAS_SRC, 917 ri, 0, srcy); 918 } 919 920 /* Do we need the src? */ 921 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 922 923 /* A mapping between our API and the TGA card */ 924 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 925 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 926 }; 927 928 /* 929 * Generic TGA raster op. 930 * This covers all possible raster ops, and 931 * clips the sizes and all of that. 932 */ 933 static int 934 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy) 935 struct rasops_info *dst; 936 int dx, dy, w, h, rop; 937 struct rasops_info *src; 938 int sx, sy; 939 { 940 if (!dst) 941 return -1; 942 if (needsrc[RAS_GETOP(rop)]) { 943 if (src == NULL) 944 return -1; /* We want a src */ 945 /* Clip against src */ 946 if (sx < 0) { 947 w += sx; 948 sx = 0; 949 } 950 if (sy < 0) { 951 h += sy; 952 sy = 0; 953 } 954 if (sx + w > src->ri_emuwidth) 955 w = src->ri_emuwidth - sx; 956 if (sy + h > src->ri_emuheight) 957 h = src->ri_emuheight - sy; 958 } else { 959 if (src != NULL) 960 return -1; /* We need no src */ 961 } 962 /* Clip against dst. We modify src regardless of using it, 963 * since it really doesn't matter. 964 */ 965 if (dx < 0) { 966 w += dx; 967 sx -= dx; 968 dx = 0; 969 } 970 if (dy < 0) { 971 h += dy; 972 sy -= dy; 973 dy = 0; 974 } 975 if (dx + w > dst->ri_emuwidth) 976 w = dst->ri_emuwidth - dx; 977 if (dy + h > dst->ri_emuheight) 978 h = dst->ri_emuheight - dy; 979 if (w <= 0 || h <= 0) 980 return 0; /* Vacuously true; */ 981 if (!src) { 982 /* XXX Punt! */ 983 return -1; 984 } 985 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 986 } 987 988 989 990 /* 991 * Video to Video raster ops. 992 * This function deals with all raster ops that have a src and dst 993 * that are on the card. 994 */ 995 static int 996 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy) 997 struct rasops_info *dst; 998 int dx, dy, w, h, rop; 999 struct rasops_info *src; 1000 int sx, sy; 1001 { 1002 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw; 1003 int srcb, dstb; 1004 int x, y; 1005 int xstart, xend, xdir, xinc; 1006 int ystart, yend, ydir, yinc; 1007 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1008 1009 /* 1010 * I don't yet want to deal with unaligned guys, really. And we don't 1011 * deal with copies from one card to another. 1012 */ 1013 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1014 /* XXX Punt! */ 1015 /* XXX should never happen, since it's only being used to 1016 * XXX copy 8-pixel-wide characters. 1017 */ 1018 return -1; 1019 } 1020 1021 if (sy >= dy) { 1022 ystart = 0; 1023 yend = h; 1024 ydir = 1; 1025 } else { 1026 ystart = h; 1027 yend = 0; 1028 ydir = -1; 1029 } 1030 if (sx >= dx) { 1031 xstart = 0; 1032 xend = w * (dst->ri_depth / 8); 1033 xdir = 1; 1034 } else { 1035 xstart = w * (dst->ri_depth / 8); 1036 xend = 0; 1037 xdir = -1; 1038 } 1039 xinc = xdir * 4 * 64; 1040 yinc = ydir * dst->ri_stride; 1041 ystart *= dst->ri_stride; 1042 yend *= dst->ri_stride; 1043 srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1044 (sx + src->ri_xorigin) * (src->ri_depth/8); 1045 dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1046 (dx + dst->ri_xorigin ) * (dst->ri_depth/8); 1047 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1048 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1049 for (y = ystart; (ydir * y) < (ydir * yend); y += yinc) { 1050 for (x = xstart; (xdir * x) < (xdir * xend); x += xinc) { 1051 /* XXX XXX Eight writes to different addresses should fill 1052 * XXX XXX up the write buffers on 21064 and 21164 chips, 1053 * XXX XXX but later CPUs might have larger write buffers which 1054 * XXX XXX require further unrolling of this loop, or the 1055 * XXX XXX insertion of memory barriers. 1056 */ 1057 TGAWALREG(dc, TGA_REG_GCSR, 0, srcb + y + x + 3 * 64); 1058 TGAWALREG(dc, TGA_REG_GCDR, 0, dstb + y + x + 3 * 64); 1059 TGAWALREG(dc, TGA_REG_GCSR, 1, srcb + y + x + 2 * 64); 1060 TGAWALREG(dc, TGA_REG_GCDR, 1, dstb + y + x + 2 * 64); 1061 TGAWALREG(dc, TGA_REG_GCSR, 2, srcb + y + x + 1 * 64); 1062 TGAWALREG(dc, TGA_REG_GCDR, 2, dstb + y + x + 1 * 64); 1063 TGAWALREG(dc, TGA_REG_GCSR, 3, srcb + y + x + 0 * 64); 1064 TGAWALREG(dc, TGA_REG_GCDR, 3, dstb + y + x + 0 * 64); 1065 } 1066 } 1067 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1068 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1069 return 0; 1070 } 1071 1072 1073 void tga_putchar (c, row, col, uc, attr) 1074 void *c; 1075 int row, col; 1076 u_int uc; 1077 long attr; 1078 { 1079 struct rasops_info *ri = c; 1080 struct tga_devconfig *dc = ri->ri_hw; 1081 int fs, height, width; 1082 u_char *fr; 1083 int32_t *rp; 1084 1085 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1086 1087 height = ri->ri_font->fontheight; 1088 width = ri->ri_font->fontwidth; 1089 1090 uc -= ri->ri_font->firstchar; 1091 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale; 1092 fs = ri->ri_font->stride; 1093 1094 /* Set foreground and background color. XXX memoize this somehow? 1095 * The rasops code has already expanded the color entry to 32 bits 1096 * for us, even for 8-bit displays, so we don't have to do anything. 1097 */ 1098 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1099 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1100 1101 /* Set raster operation to "copy"... */ 1102 if (ri->ri_depth == 8) 1103 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1104 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1105 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1106 1107 /* Set which pixels we're drawing (of a possible 32). */ 1108 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1109 1110 /* Set drawing mode to opaque stipple. */ 1111 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1112 1113 /* Insert write barrier before actually sending data */ 1114 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1115 TGAREGWB(dc, TGA_REG_GMOR, 1); 1116 1117 while(height--) { 1118 /* The actual stipple write */ 1119 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1120 1121 fr += fs; 1122 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1123 } 1124 1125 /* Do underline */ 1126 if ((attr & 1) != 0) { 1127 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1)); 1128 *rp = 0xffffffff; 1129 } 1130 1131 /* Set grapics mode back to normal. */ 1132 TGAWREG(dc, TGA_REG_GMOR, 0); 1133 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1134 1135 } 1136 1137 static void 1138 tga_eraserows(c, row, num, attr) 1139 void *c; 1140 int row, num; 1141 long attr; 1142 { 1143 struct rasops_info *ri = c; 1144 struct tga_devconfig *dc = ri->ri_hw; 1145 int32_t color, lines, pixels; 1146 int32_t *rp; 1147 1148 color = ri->ri_devcmap[(attr >> 16) & 15]; 1149 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1150 lines = num * ri->ri_font->fontheight; 1151 pixels = ri->ri_emuwidth - 1; 1152 1153 /* Set fill color in block-color registers */ 1154 TGAWREG(dc, TGA_REG_GBCR0, color); 1155 TGAWREG(dc, TGA_REG_GBCR1, color); 1156 if (ri->ri_depth != 8) { 1157 TGAWREG(dc, TGA_REG_GBCR2, color); 1158 TGAWREG(dc, TGA_REG_GBCR3, color); 1159 TGAWREG(dc, TGA_REG_GBCR4, color); 1160 TGAWREG(dc, TGA_REG_GBCR5, color); 1161 TGAWREG(dc, TGA_REG_GBCR6, color); 1162 TGAWREG(dc, TGA_REG_GBCR7, color); 1163 } 1164 1165 /* Set raster operation to "copy"... */ 1166 if (ri->ri_depth == 8) 1167 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1168 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1169 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1170 1171 /* Set which pixels we're drawing (of a possible 32). */ 1172 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1173 1174 /* Set drawing mode to block fill. */ 1175 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1176 1177 /* Insert write barrier before actually sending data */ 1178 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1179 TGAREGWB(dc, TGA_REG_GMOR, 1); 1180 1181 while (lines--) { 1182 *rp = pixels; 1183 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1184 } 1185 1186 /* Set grapics mode back to normal. */ 1187 TGAWREG(dc, TGA_REG_GMOR, 0); 1188 1189 } 1190 1191 static void 1192 tga_erasecols (c, row, col, num, attr) 1193 void *c; 1194 int row, col, num; 1195 long attr; 1196 { 1197 struct rasops_info *ri = c; 1198 struct tga_devconfig *dc = ri->ri_hw; 1199 int32_t color, lines, pixels; 1200 int32_t *rp; 1201 1202 color = ri->ri_devcmap[(attr >> 16) & 15]; 1203 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1204 lines = ri->ri_font->fontheight; 1205 pixels = (num * ri->ri_font->fontwidth) - 1; 1206 1207 /* Set fill color in block-color registers */ 1208 TGAWREG(dc, TGA_REG_GBCR0, color); 1209 TGAWREG(dc, TGA_REG_GBCR1, color); 1210 if (ri->ri_depth != 8) { 1211 TGAWREG(dc, TGA_REG_GBCR2, color); 1212 TGAWREG(dc, TGA_REG_GBCR3, color); 1213 TGAWREG(dc, TGA_REG_GBCR4, color); 1214 TGAWREG(dc, TGA_REG_GBCR5, color); 1215 TGAWREG(dc, TGA_REG_GBCR6, color); 1216 TGAWREG(dc, TGA_REG_GBCR7, color); 1217 } 1218 1219 /* Set raster operation to "copy"... */ 1220 if (ri->ri_depth == 8) 1221 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1222 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1223 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1224 1225 /* Set which pixels we're drawing (of a possible 32). */ 1226 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1227 1228 /* Set drawing mode to block fill. */ 1229 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1230 1231 /* Insert write barrier before actually sending data */ 1232 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1233 TGAREGWB(dc, TGA_REG_GMOR, 1); 1234 1235 while (lines--) { 1236 *rp = pixels; 1237 rp = (int32_t *)((caddr_t)rp + ri->ri_stride); 1238 } 1239 1240 /* Set grapics mode back to normal. */ 1241 TGAWREG(dc, TGA_REG_GMOR, 0); 1242 } 1243 1244 1245 static void 1246 tga_ramdac_wr(v, btreg, val) 1247 void *v; 1248 u_int btreg; 1249 u_int8_t val; 1250 { 1251 struct tga_devconfig *dc = v; 1252 1253 if (btreg > BT485_REG_MAX) 1254 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1255 1256 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1257 TGAREGWB(dc, TGA_REG_EPDR, 1); 1258 } 1259 1260 static void 1261 tga2_ramdac_wr(v, btreg, val) 1262 void *v; 1263 u_int btreg; 1264 u_int8_t val; 1265 { 1266 struct tga_devconfig *dc = v; 1267 bus_space_handle_t ramdac; 1268 1269 if (btreg > BT485_REG_MAX) 1270 panic("tga_ramdac_wr: reg %d out of range\n", btreg); 1271 1272 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1273 (0xe << 12) + (btreg << 8), 4, &ramdac); 1274 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1275 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1276 } 1277 1278 static u_int8_t 1279 tga_bt463_rd(v, btreg) 1280 void *v; 1281 u_int btreg; 1282 { 1283 struct tga_devconfig *dc = v; 1284 tga_reg_t rdval; 1285 1286 /* 1287 * Strobe CE# (high->low->high) since status and data are latched on 1288 * the falling and rising edges (repsectively) of this active-low signal. 1289 */ 1290 1291 TGAREGWB(dc, TGA_REG_EPSR, 1); 1292 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1293 TGAREGWB(dc, TGA_REG_EPSR, 1); 1294 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1295 1296 TGAREGRB(dc, TGA_REG_EPSR, 1); 1297 1298 rdval = TGARREG(dc, TGA_REG_EPDR); 1299 TGAREGWB(dc, TGA_REG_EPSR, 1); 1300 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1301 1302 return (rdval >> 16) & 0xff; 1303 } 1304 1305 static void 1306 tga_bt463_wr(v, btreg, val) 1307 void *v; 1308 u_int btreg; 1309 u_int8_t val; 1310 { 1311 struct tga_devconfig *dc = v; 1312 1313 /* 1314 * In spite of the 21030 documentation, to set the MPU bus bits for 1315 * a write, you set them in the upper bits of EPDR, not EPSR. 1316 */ 1317 1318 /* 1319 * Strobe CE# (high->low->high) since status and data are latched on 1320 * the falling and rising edges of this active-low signal. 1321 */ 1322 1323 TGAREGWB(dc, TGA_REG_EPDR, 1); 1324 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1325 TGAREGWB(dc, TGA_REG_EPDR, 1); 1326 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1327 TGAREGWB(dc, TGA_REG_EPDR, 1); 1328 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1329 1330 } 1331 1332 static u_int8_t 1333 tga_ramdac_rd(v, btreg) 1334 void *v; 1335 u_int btreg; 1336 { 1337 struct tga_devconfig *dc = v; 1338 tga_reg_t rdval; 1339 1340 if (btreg > BT485_REG_MAX) 1341 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1342 1343 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1344 TGAREGWB(dc, TGA_REG_EPSR, 1); 1345 1346 rdval = TGARREG(dc, TGA_REG_EPDR); 1347 return (rdval >> 16) & 0xff; /* XXX */ 1348 } 1349 1350 static u_int8_t 1351 tga2_ramdac_rd(v, btreg) 1352 void *v; 1353 u_int btreg; 1354 { 1355 struct tga_devconfig *dc = v; 1356 bus_space_handle_t ramdac; 1357 u_int8_t retval; 1358 1359 if (btreg > BT485_REG_MAX) 1360 panic("tga_ramdac_rd: reg %d out of range\n", btreg); 1361 1362 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC + 1363 (0xe << 12) + (btreg << 8), 4, &ramdac); 1364 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1365 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1366 return retval; 1367 } 1368 1369 #include <dev/ic/decmonitors.c> 1370 void tga2_ics9110_wr __P(( 1371 struct tga_devconfig *dc, 1372 int dotclock 1373 )); 1374 1375 void 1376 tga2_init(dc, m) 1377 struct tga_devconfig *dc; 1378 int m; 1379 { 1380 1381 tga2_ics9110_wr(dc, decmonitors[m].dotclock); 1382 #if 0 1383 TGAWREG(dc, TGA_REG_VHCR, 1384 ((decmonitors[m].hbp / 4) << 21) | 1385 ((decmonitors[m].hsync / 4) << 14) | 1386 (((decmonitors[m].hfp - 4) / 4) << 9) | 1387 ((decmonitors[m].cols + 4) / 4)); 1388 #else 1389 TGAWREG(dc, TGA_REG_VHCR, 1390 ((decmonitors[m].hbp / 4) << 21) | 1391 ((decmonitors[m].hsync / 4) << 14) | 1392 (((decmonitors[m].hfp) / 4) << 9) | 1393 ((decmonitors[m].cols) / 4)); 1394 #endif 1395 TGAWREG(dc, TGA_REG_VVCR, 1396 (decmonitors[m].vbp << 22) | 1397 (decmonitors[m].vsync << 16) | 1398 (decmonitors[m].vfp << 11) | 1399 (decmonitors[m].rows)); 1400 TGAWREG(dc, TGA_REG_VVBR, 1); 1401 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1402 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1403 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1404 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1405 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1406 } 1407 1408 void 1409 tga2_ics9110_wr(dc, dotclock) 1410 struct tga_devconfig *dc; 1411 int dotclock; 1412 { 1413 bus_space_handle_t clock; 1414 u_int32_t valU; 1415 int N, M, R, V, X; 1416 int i; 1417 1418 switch (dotclock) { 1419 case 130808000: 1420 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1421 case 119840000: 1422 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1423 case 108180000: 1424 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1425 case 103994000: 1426 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1427 case 175000000: 1428 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1429 case 75000000: 1430 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1431 case 74000000: 1432 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1433 case 69000000: 1434 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1435 case 65000000: 1436 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1437 case 50000000: 1438 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1439 case 40000000: 1440 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1441 case 31500000: 1442 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1443 case 25175000: 1444 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1445 case 135000000: 1446 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1447 case 110000000: 1448 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1449 case 202500000: 1450 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1451 default: 1452 panic("unrecognized clock rate %d\n", dotclock); 1453 } 1454 1455 /* XXX -- hard coded, bad */ 1456 valU = N | ( M << 7 ) | (V << 14); 1457 valU |= (X << 15) | (R << 17); 1458 valU |= 0x17 << 19; 1459 1460 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1461 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1462 1463 for (i=24; i>0; i--) { 1464 u_int32_t writeval; 1465 1466 writeval = valU & 0x1; 1467 if (i == 1) 1468 writeval |= 0x2; 1469 valU >>= 1; 1470 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1471 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE); 1472 } 1473 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1474 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1475 &clock); /* XXX */ 1476 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1477 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1478 } 1479
Indexes created Wed Sep 24 15:09:51 GMT 2025