tga.c revision 1.37 1 /* $NetBSD: tga.c,v 1.37 2001/11/13 07:48:49 lukem Exp $ */
2
3 /*
4 * Copyright (c) 1995, 1996 Carnegie-Mellon University.
5 * All rights reserved.
6 *
7 * Author: Chris G. Demetriou
8 *
9 * Permission to use, copy, modify and distribute this software and
10 * its documentation is hereby granted, provided that both the copyright
11 * notice and this permission notice appear in all copies of the
12 * software, derivative works or modified versions, and any portions
13 * thereof, and that both notices appear in supporting documentation.
14 *
15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
18 *
19 * Carnegie Mellon requests users of this software to return to
20 *
21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
22 * School of Computer Science
23 * Carnegie Mellon University
24 * Pittsburgh PA 15213-3890
25 *
26 * any improvements or extensions that they make and grant Carnegie the
27 * rights to redistribute these changes.
28 */
29
30 #include <sys/cdefs.h>
31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.37 2001/11/13 07:48:49 lukem Exp $");
32
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/device.h>
37 #include <sys/conf.h>
38 #include <sys/malloc.h>
39 #include <sys/buf.h>
40 #include <sys/ioctl.h>
41
42 #include <machine/bus.h>
43 #include <machine/intr.h>
44
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
47 #include <dev/pci/pcidevs.h>
48 #include <dev/pci/tgareg.h>
49 #include <dev/pci/tgavar.h>
50 #include <dev/ic/bt485reg.h>
51 #include <dev/ic/bt485var.h>
52 #include <dev/ic/bt463reg.h>
53 #include <dev/ic/bt463var.h>
54
55 #include <dev/wscons/wsconsio.h>
56 #include <dev/wscons/wscons_raster.h>
57 #include <dev/rasops/rasops.h>
58 #include <dev/wsfont/wsfont.h>
59 #include <uvm/uvm_extern.h>
60
61 #ifdef __alpha__
62 #include <machine/pte.h>
63 #endif
64 #ifdef __mips__
65 #include <mips/pte.h>
66 #endif
67
68 int tgamatch __P((struct device *, struct cfdata *, void *));
69 void tgaattach __P((struct device *, struct device *, void *));
70 int tgaprint __P((void *, const char *));
71
72 struct cfattach tga_ca = {
73 sizeof(struct tga_softc), tgamatch, tgaattach,
74 };
75
76 int tga_identify __P((struct tga_devconfig *));
77 const struct tga_conf *tga_getconf __P((int));
78 static void tga_init __P((bus_space_tag_t memt, pci_chipset_tag_t pc,
79 pcitag_t tag, struct tga_devconfig *dc));
80
81 static int tga_matchcommon __P((bus_space_tag_t, pci_chipset_tag_t, pcitag_t));
82 static void tga_mapaddrs __P((bus_space_tag_t memt, pci_chipset_tag_t pc,
83 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc));
84
85 struct tga_devconfig tga_console_dc;
86
87 int tga_ioctl __P((void *, u_long, caddr_t, int, struct proc *));
88 paddr_t tga_mmap __P((void *, off_t, int));
89 static void tga_copyrows __P((void *, int, int, int));
90 static void tga_copycols __P((void *, int, int, int, int));
91 static int tga_alloc_screen __P((void *, const struct wsscreen_descr *,
92 void **, int *, int *, long *));
93 static void tga_free_screen __P((void *, void *));
94 static int tga_show_screen __P((void *, void *, int,
95 void (*) (void *, int, int), void *));
96 static int tga_rop __P((struct rasops_info *, int, int, int, int, int,
97 struct rasops_info *, int, int));
98 static int tga_rop_vtov __P((struct rasops_info *, int, int, int, int,
99 int, struct rasops_info *, int, int ));
100 static void tga_putchar __P((void *c, int row, int col,
101 u_int uc, long attr));
102 static void tga_eraserows __P((void *, int, int, long));
103 static void tga_erasecols __P((void *, int, int, int, long));
104 void tga2_init __P((struct tga_devconfig *, int));
105
106 static void tga_config_interrupts __P((struct device *));
107
108 /* RAMDAC interface functions */
109 static int tga_sched_update __P((void *, void (*)(void *)));
110 static void tga_ramdac_wr __P((void *, u_int, u_int8_t));
111 static u_int8_t tga_ramdac_rd __P((void *, u_int));
112 static void tga_bt463_wr __P((void *, u_int, u_int8_t));
113 static u_int8_t tga_bt463_rd __P((void *, u_int));
114 static void tga2_ramdac_wr __P((void *, u_int, u_int8_t));
115 static u_int8_t tga2_ramdac_rd __P((void *, u_int));
116
117 /* Interrupt handler */
118 static int tga_intr __P((void *));
119
120 /* The NULL entries will get filled in by rasops_init().
121 * XXX and the non-NULL ones will be overwritten; reset after calling it.
122 */
123 struct wsdisplay_emulops tga_emulops = {
124 NULL,
125 NULL,
126 tga_putchar,
127 tga_copycols,
128 tga_erasecols,
129 tga_copyrows,
130 tga_eraserows,
131 NULL,
132 };
133
134 struct wsscreen_descr tga_stdscreen = {
135 "std",
136 0, 0, /* will be filled in -- XXX shouldn't, it's global */
137 &tga_emulops,
138 0, 0,
139 WSSCREEN_REVERSE
140 };
141
142 const struct wsscreen_descr *_tga_scrlist[] = {
143 &tga_stdscreen,
144 /* XXX other formats, graphics screen? */
145 };
146
147 struct wsscreen_list tga_screenlist = {
148 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist
149 };
150
151 struct wsdisplay_accessops tga_accessops = {
152 tga_ioctl,
153 tga_mmap,
154 tga_alloc_screen,
155 tga_free_screen,
156 tga_show_screen,
157 0 /* load_font */
158 };
159
160 static void tga_blank __P((struct tga_devconfig *));
161 static void tga_unblank __P((struct tga_devconfig *));
162
163 int
164 tga_cnmatch(iot, memt, pc, tag)
165 bus_space_tag_t iot, memt;
166 pci_chipset_tag_t pc;
167 pcitag_t tag;
168 {
169 return tga_matchcommon(memt, pc, tag);
170 }
171
172 int
173 tgamatch(parent, match, aux)
174 struct device *parent;
175 struct cfdata *match;
176 void *aux;
177 {
178 struct pci_attach_args *pa = aux;
179
180 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC)
181 return (0);
182
183 switch (PCI_PRODUCT(pa->pa_id)) {
184 case PCI_PRODUCT_DEC_21030:
185 case PCI_PRODUCT_DEC_PBXGB:
186 break;
187 default:
188 return 0;
189 }
190
191 /* short-circuit the following test, as we
192 * already have the memory mapped and hence
193 * cannot perform it---and we are the console
194 * anyway.
195 */
196 if (pa->pa_tag == tga_console_dc.dc_pcitag)
197 return 10;
198
199 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag);
200 }
201
202 static int
203 tga_matchcommon(memt, pc, tag)
204 bus_space_tag_t memt;
205 pci_chipset_tag_t pc;
206 pcitag_t tag;
207 {
208 struct tga_devconfig tmp_dc;
209 struct tga_devconfig *dc = &tmp_dc;
210 bus_size_t pcisize;
211
212 tga_mapaddrs(memt, pc, tag, &pcisize, dc);
213 dc->dc_tga_type = tga_identify(dc);
214
215 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
216 bus_space_unmap(memt, dc->dc_memh, pcisize);
217 if (dc->dc_tgaconf)
218 return 10;
219 return 0;
220 }
221
222 static void
223 tga_mapaddrs(memt, pc, tag, pcisize, dc)
224 bus_space_tag_t memt;
225 pci_chipset_tag_t pc;
226 pcitag_t tag;
227 bus_size_t *pcisize;
228 struct tga_devconfig *dc;
229 {
230 int flags;
231
232 dc->dc_memt = memt;
233 dc->dc_tgaconf = NULL;
234
235 /* XXX magic number */
236 if (pci_mapreg_info(pc, tag, 0x10,
237 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT,
238 &dc->dc_pcipaddr, pcisize, &flags))
239 panic("tga_mapaddrs: pci_mapreg_info() failed");
240 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */
241 panic("tga memory not prefetchable");
242
243 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize,
244 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh))
245 panic("tga_mapaddrs: could not map TGA address space");
246 dc->dc_vaddr = (vaddr_t) bus_space_vaddr(memt, dc->dc_memh);
247
248 bus_space_subregion(dc->dc_memt, dc->dc_memh,
249 TGA_MEM_CREGS, TGA_CREGS_SIZE,
250 &dc->dc_regs);
251 }
252
253 static void
254 tga_init(memt, pc, tag, dc)
255 bus_space_tag_t memt;
256 pci_chipset_tag_t pc;
257 pcitag_t tag;
258 struct tga_devconfig *dc;
259 {
260 const struct tga_conf *tgac;
261 struct rasops_info *rip;
262 int cookie;
263 bus_size_t pcisize;
264 int i;
265
266 dc->dc_pcitag = tag;
267 tga_mapaddrs(memt, pc, tag, &pcisize, dc);
268 dc->dc_tga_type = tga_identify(dc);
269 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type);
270 #if 0
271 /* XXX on the Alpha, pcisize = 4 * cspace_size. */
272 if (tgac->tgac_cspace_size != pcisize) /* sanity */
273 panic("tga_init: memory size mismatch?");
274 #endif
275
276 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) {
277 case 0x01:
278 case 0x02:
279 case 0x03:
280 case 0x04:
281 dc->dc_tga2 = 0;
282 break;
283 case 0x20:
284 case 0x21:
285 case 0x22:
286 dc->dc_tga2 = 1;
287 break;
288 default:
289 panic("tga_init: TGA Revision not recognized");
290 }
291
292 if (dc->dc_tga2) {
293 int monitor;
294
295 monitor = (~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f;
296 tga2_init(dc, monitor);
297 }
298
299 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */
300 case 0:
301 dc->dc_wid = 8192;
302 break;
303
304 case 1:
305 dc->dc_wid = 8196;
306 break;
307
308 default:
309 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */
310 break;
311 }
312
313 /*
314 * XXX XXX Turning off "odd" shouldn't be necessary,
315 * XXX XXX but I can't make X work with the weird size.
316 */
317 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */
318 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */
319 TGAWREG(dc, TGA_REG_VHCR,
320 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001));
321 dc->dc_wid -= 4;
322 }
323
324 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8);
325 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */
326
327 /* XXX this seems to be what DEC does */
328 TGAWREG(dc, TGA_REG_CCBR, 0);
329 TGAWREG(dc, TGA_REG_VVBR, 1);
330 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] +
331 1 * tgac->tgac_vvbr_units;
332 dc->dc_blanked = 1;
333 tga_unblank(dc);
334
335 /*
336 * Set all bits in the pixel mask, to enable writes to all pixels.
337 * It seems that the console firmware clears some of them
338 * under some circumstances, which causes cute vertical stripes.
339 */
340 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
341
342 /* clear the screen */
343 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(u_int32_t))
344 *(u_int32_t *)(dc->dc_videobase + i) = 0;
345
346 /* Initialize rasops descriptor */
347 rip = &dc->dc_rinfo;
348 rip->ri_flg = RI_CENTER;
349 rip->ri_depth = tgac->tgac_phys_depth;
350 rip->ri_bits = (void *)dc->dc_videobase;
351 rip->ri_width = dc->dc_wid;
352 rip->ri_height = dc->dc_ht;
353 rip->ri_stride = dc->dc_rowbytes;
354 rip->ri_hw = dc;
355
356 if (tgac->tgac_phys_depth == 32) {
357 rip->ri_rnum = 8;
358 rip->ri_gnum = 8;
359 rip->ri_bnum = 8;
360 rip->ri_rpos = 16;
361 rip->ri_gpos = 8;
362 rip->ri_bpos = 0;
363 }
364
365 wsfont_init();
366 /* prefer 8 pixel wide font */
367 if ((cookie = wsfont_find(NULL, 8, 0, 0)) <= 0)
368 cookie = wsfont_find(NULL, 0, 0, 0);
369 if (cookie <= 0) {
370 printf("tga: no appropriate fonts.\n");
371 return;
372 }
373
374 /* the accelerated tga_putchar() needs LSbit left */
375 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font,
376 WSDISPLAY_FONTORDER_R2L, WSDISPLAY_FONTORDER_L2R) <= 0) {
377 printf("tga: couldn't lock font\n");
378 return;
379 }
380 dc->dc_rinfo.ri_wsfcookie = cookie;
381
382 rasops_init(rip, 34, 80);
383
384 /* add our accelerated functions */
385 /* XXX shouldn't have to do this; rasops should leave non-NULL
386 * XXX entries alone.
387 */
388 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows;
389 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows;
390 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols;
391 dc->dc_rinfo.ri_ops.copycols = tga_copycols;
392 dc->dc_rinfo.ri_ops.putchar = tga_putchar;
393
394 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows;
395 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols;
396 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops;
397 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps;
398
399
400 dc->dc_intrenabled = 0;
401 }
402
403 void
404 tgaattach(parent, self, aux)
405 struct device *parent, *self;
406 void *aux;
407 {
408 struct pci_attach_args *pa = aux;
409 struct tga_softc *sc = (struct tga_softc *)self;
410 struct wsemuldisplaydev_attach_args aa;
411 pci_intr_handle_t intrh;
412 const char *intrstr;
413 u_int8_t rev;
414 int console;
415
416 #if defined(__alpha__) || defined(arc)
417 console = (pa->pa_tag == tga_console_dc.dc_pcitag);
418 #else
419 console = 0;
420 #endif
421 if (console) {
422 sc->sc_dc = &tga_console_dc;
423 sc->nscreens = 1;
424 } else {
425 sc->sc_dc = (struct tga_devconfig *)
426 malloc(sizeof(struct tga_devconfig), M_DEVBUF, M_WAITOK);
427 memset(sc->sc_dc, 0, sizeof(struct tga_devconfig));
428 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc);
429 }
430 if (sc->sc_dc->dc_vaddr == NULL) {
431 printf(": couldn't map memory space; punt!\n");
432 return;
433 }
434
435 /* XXX say what's going on. */
436 intrstr = NULL;
437 if (pci_intr_map(pa, &intrh)) {
438 printf(": couldn't map interrupt");
439 return;
440 }
441 intrstr = pci_intr_string(pa->pa_pc, intrh);
442 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr,
443 sc->sc_dc);
444 if (sc->sc_intr == NULL) {
445 printf(": couldn't establish interrupt");
446 if (intrstr != NULL)
447 printf("at %s", intrstr);
448 printf("\n");
449 return;
450 }
451
452 rev = PCI_REVISION(pa->pa_class);
453 switch (rev) {
454 case 0x1:
455 case 0x2:
456 case 0x3:
457 printf(": DC21030 step %c", 'A' + rev - 1);
458 break;
459 case 0x20:
460 printf(": TGA2 abstract software model");
461 break;
462 case 0x21:
463 case 0x22:
464 printf(": TGA2 pass %d", rev - 0x20);
465 break;
466
467 default:
468 printf("unknown stepping (0x%x)", rev);
469 break;
470 }
471 printf(", ");
472
473 /*
474 * Get RAMDAC function vectors and call the RAMDAC functions
475 * to allocate its private storage and pass that back to us.
476 */
477
478 sc->sc_dc->dc_ramdac_funcs = sc->sc_dc->dc_tgaconf->ramdac_funcs();
479 if (!sc->sc_dc->dc_tga2) {
480 if (sc->sc_dc->dc_tgaconf->ramdac_funcs == bt485_funcs)
481 sc->sc_dc->dc_ramdac_cookie =
482 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
483 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd);
484 else
485 sc->sc_dc->dc_ramdac_cookie =
486 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
487 tga_sched_update, tga_bt463_wr, tga_bt463_rd);
488 } else {
489 sc->sc_dc->dc_ramdac_cookie =
490 sc->sc_dc->dc_ramdac_funcs->ramdac_register(sc->sc_dc,
491 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd);
492 }
493
494 /*
495 * Initialize the RAMDAC. Initialization includes disabling
496 * cursor, setting a sane colormap, etc.
497 */
498 (*sc->sc_dc->dc_ramdac_funcs->ramdac_init)(sc->sc_dc->dc_ramdac_cookie);
499 TGAWREG(sc->sc_dc, TGA_REG_SISR, 0x00000001); /* XXX */
500
501 if (sc->sc_dc->dc_tgaconf == NULL) {
502 printf("unknown board configuration\n");
503 return;
504 }
505 printf("board type %s\n", sc->sc_dc->dc_tgaconf->tgac_name);
506 printf("%s: %d x %d, %dbpp, %s RAMDAC\n", sc->sc_dev.dv_xname,
507 sc->sc_dc->dc_wid, sc->sc_dc->dc_ht,
508 sc->sc_dc->dc_tgaconf->tgac_phys_depth,
509 sc->sc_dc->dc_ramdac_funcs->ramdac_name);
510
511 if (intrstr != NULL)
512 printf("%s: interrupting at %s\n", sc->sc_dev.dv_xname,
513 intrstr);
514
515 aa.console = console;
516 aa.scrdata = &tga_screenlist;
517 aa.accessops = &tga_accessops;
518 aa.accesscookie = sc;
519
520 config_found(self, &aa, wsemuldisplaydevprint);
521
522 config_interrupts(self, tga_config_interrupts);
523 }
524
525 static void
526 tga_config_interrupts (d)
527 struct device *d;
528 {
529 struct tga_softc *sc = (struct tga_softc *)d;
530 sc->sc_dc->dc_intrenabled = 1;
531 }
532
533 int
534 tga_ioctl(v, cmd, data, flag, p)
535 void *v;
536 u_long cmd;
537 caddr_t data;
538 int flag;
539 struct proc *p;
540 {
541 struct tga_softc *sc = v;
542 struct tga_devconfig *dc = sc->sc_dc;
543 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
544 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
545
546 switch (cmd) {
547 case WSDISPLAYIO_GTYPE:
548 *(u_int *)data = WSDISPLAY_TYPE_TGA;
549 return (0);
550
551 case WSDISPLAYIO_GINFO:
552 #define wsd_fbip ((struct wsdisplay_fbinfo *)data)
553 wsd_fbip->height = sc->sc_dc->dc_ht;
554 wsd_fbip->width = sc->sc_dc->dc_wid;
555 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth;
556 wsd_fbip->cmsize = 256; /* XXX ??? */
557 #undef wsd_fbip
558 return (0);
559
560 case WSDISPLAYIO_GETCMAP:
561 return (*dcrf->ramdac_get_cmap)(dcrc,
562 (struct wsdisplay_cmap *)data);
563
564 case WSDISPLAYIO_PUTCMAP:
565 return (*dcrf->ramdac_set_cmap)(dcrc,
566 (struct wsdisplay_cmap *)data);
567
568 case WSDISPLAYIO_SVIDEO:
569 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF)
570 tga_blank(sc->sc_dc);
571 else
572 tga_unblank(sc->sc_dc);
573 return (0);
574
575 case WSDISPLAYIO_GVIDEO:
576 *(u_int *)data = dc->dc_blanked ?
577 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON;
578 return (0);
579
580 case WSDISPLAYIO_GCURPOS:
581 return (*dcrf->ramdac_get_curpos)(dcrc,
582 (struct wsdisplay_curpos *)data);
583
584 case WSDISPLAYIO_SCURPOS:
585 return (*dcrf->ramdac_set_curpos)(dcrc,
586 (struct wsdisplay_curpos *)data);
587
588 case WSDISPLAYIO_GCURMAX:
589 return (*dcrf->ramdac_get_curmax)(dcrc,
590 (struct wsdisplay_curpos *)data);
591
592 case WSDISPLAYIO_GCURSOR:
593 return (*dcrf->ramdac_get_cursor)(dcrc,
594 (struct wsdisplay_cursor *)data);
595
596 case WSDISPLAYIO_SCURSOR:
597 return (*dcrf->ramdac_set_cursor)(dcrc,
598 (struct wsdisplay_cursor *)data);
599 }
600 return (-1);
601 }
602
603 static int
604 tga_sched_update(v, f)
605 void *v;
606 void (*f) __P((void *));
607 {
608 struct tga_devconfig *dc = v;
609
610 if (dc->dc_intrenabled) {
611 /* Arrange for f to be called at the next end-of-frame interrupt */
612 dc->dc_ramdac_intr = f;
613 TGAWREG(dc, TGA_REG_SISR, 0x00010000);
614 } else {
615 /* Spin until the end-of-frame, then call f */
616 TGAWREG(dc, TGA_REG_SISR, 0x00010001);
617 TGAREGWB(dc, TGA_REG_SISR, 1);
618 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0)
619 ;
620 f(dc->dc_ramdac_cookie);
621 TGAWREG(dc, TGA_REG_SISR, 0x00000001);
622 TGAREGWB(dc, TGA_REG_SISR, 1);
623 }
624
625 return 0;
626 }
627
628 static int
629 tga_intr(v)
630 void *v;
631 {
632 struct tga_devconfig *dc = v;
633 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie;
634
635 u_int32_t reg;
636
637 reg = TGARREG(dc, TGA_REG_SISR);
638 if (( reg & 0x00010001) != 0x00010001) {
639 /* Odd. We never set any of the other interrupt enables. */
640 if ((reg & 0x1f) != 0) {
641 /* Clear the mysterious pending interrupts. */
642 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f));
643 TGAREGWB(dc, TGA_REG_SISR, 1);
644 /* This was our interrupt, even if we're puzzled as to why
645 * we got it. Don't make the interrupt handler think it
646 * was a stray.
647 */
648 return -1;
649 } else {
650 return 0;
651 }
652 }
653 /* if we have something to do, do it */
654 if (dc->dc_ramdac_intr) {
655 dc->dc_ramdac_intr(dcrc);
656 dc->dc_ramdac_intr = NULL;
657 }
658 TGAWREG(dc, TGA_REG_SISR, 0x00000001);
659 TGAREGWB(dc, TGA_REG_SISR, 1);
660 return (1);
661 }
662
663 paddr_t
664 tga_mmap(v, offset, prot)
665 void *v;
666 off_t offset;
667 int prot;
668 {
669 struct tga_softc *sc = v;
670
671 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0)
672 return -1;
673
674 return (bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr,
675 offset, prot, BUS_SPACE_MAP_LINEAR));
676 }
677
678 static int
679 tga_alloc_screen(v, type, cookiep, curxp, curyp, attrp)
680 void *v;
681 const struct wsscreen_descr *type;
682 void **cookiep;
683 int *curxp, *curyp;
684 long *attrp;
685 {
686 struct tga_softc *sc = v;
687 long defattr;
688
689 if (sc->nscreens > 0)
690 return (ENOMEM);
691
692 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */
693 *curxp = 0;
694 *curyp = 0;
695 sc->sc_dc->dc_rinfo.ri_ops.alloc_attr(&sc->sc_dc->dc_rinfo,
696 0, 0, 0, &defattr);
697 *attrp = defattr;
698 sc->nscreens++;
699 return (0);
700 }
701
702 static void
703 tga_free_screen(v, cookie)
704 void *v;
705 void *cookie;
706 {
707 struct tga_softc *sc = v;
708
709 if (sc->sc_dc == &tga_console_dc)
710 panic("tga_free_screen: console");
711
712 sc->nscreens--;
713 }
714
715 static int
716 tga_show_screen(v, cookie, waitok, cb, cbarg)
717 void *v;
718 void *cookie;
719 int waitok;
720 void (*cb) __P((void *, int, int));
721 void *cbarg;
722 {
723
724 return (0);
725 }
726
727 int
728 tga_cnattach(iot, memt, pc, bus, device, function)
729 bus_space_tag_t iot, memt;
730 pci_chipset_tag_t pc;
731 int bus, device, function;
732 {
733 struct tga_devconfig *dcp = &tga_console_dc;
734 long defattr;
735
736 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp);
737
738 /* sanity checks */
739 if (dcp->dc_vaddr == NULL)
740 panic("tga_console(%d, %d): couldn't map memory space",
741 device, function);
742 if (dcp->dc_tgaconf == NULL)
743 panic("tga_console(%d, %d): unknown board configuration",
744 device, function);
745
746 /*
747 * Initialize the RAMDAC but DO NOT allocate any private storage.
748 * Initialization includes disabling cursor, setting a sane
749 * colormap, etc. It will be reinitialized in tgaattach().
750 */
751 if (dcp->dc_tga2)
752 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr,
753 tga2_ramdac_rd);
754 else {
755 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs)
756 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr,
757 tga_ramdac_rd);
758 else {
759 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr,
760 tga_bt463_rd);
761 }
762 }
763 dcp->dc_rinfo.ri_ops.alloc_attr(&dcp->dc_rinfo, 0, 0, 0, &defattr);
764 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr);
765
766 return(0);
767 }
768
769 /*
770 * Functions to blank and unblank the display.
771 */
772 static void
773 tga_blank(dc)
774 struct tga_devconfig *dc;
775 {
776
777 if (!dc->dc_blanked) {
778 dc->dc_blanked = 1;
779 /* XXX */
780 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK);
781 }
782 }
783
784 static void
785 tga_unblank(dc)
786 struct tga_devconfig *dc;
787 {
788
789 if (dc->dc_blanked) {
790 dc->dc_blanked = 0;
791 /* XXX */
792 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK);
793 }
794 }
795
796 /*
797 * Functions to manipulate the built-in cursor handing hardware.
798 */
799 int
800 tga_builtin_set_cursor(dc, cursorp)
801 struct tga_devconfig *dc;
802 struct wsdisplay_cursor *cursorp;
803 {
804 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
805 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
806 u_int count, v;
807 int error;
808
809 v = cursorp->which;
810 if (v & WSDISPLAY_CURSOR_DOCMAP) {
811 error = dcrf->ramdac_check_curcmap(dcrc, cursorp);
812 if (error)
813 return (error);
814 }
815 if (v & WSDISPLAY_CURSOR_DOSHAPE) {
816 if ((u_int)cursorp->size.x != 64 ||
817 (u_int)cursorp->size.y > 64)
818 return (EINVAL);
819 /* The cursor is 2 bits deep, and there is no mask */
820 count = (cursorp->size.y * 64 * 2) / NBBY;
821 if (!uvm_useracc(cursorp->image, count, B_READ))
822 return (EFAULT);
823 }
824 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */
825 return EINVAL;
826
827 /* parameters are OK; do it */
828 if (v & WSDISPLAY_CURSOR_DOCUR) {
829 if (cursorp->enable)
830 /* XXX */
831 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 0x04);
832 else
833 /* XXX */
834 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) & ~0x04);
835 }
836 if (v & WSDISPLAY_CURSOR_DOPOS) {
837 TGAWREG(dc, TGA_REG_CXYR,
838 ((cursorp->pos.y & 0xfff) << 12) | (cursorp->pos.x & 0xfff));
839 }
840 if (v & WSDISPLAY_CURSOR_DOCMAP) {
841 /* can't fail. */
842 dcrf->ramdac_set_curcmap(dcrc, cursorp);
843 }
844 if (v & WSDISPLAY_CURSOR_DOSHAPE) {
845 count = ((64 * 2) / NBBY) * cursorp->size.y;
846 TGAWREG(dc, TGA_REG_CCBR,
847 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | (cursorp->size.y << 10));
848 copyin(cursorp->image, (char *)(dc->dc_vaddr +
849 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
850 count); /* can't fail. */
851 }
852 return (0);
853 }
854
855 int
856 tga_builtin_get_cursor(dc, cursorp)
857 struct tga_devconfig *dc;
858 struct wsdisplay_cursor *cursorp;
859 {
860 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs;
861 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie;
862 int count, error;
863
864 cursorp->which = WSDISPLAY_CURSOR_DOALL &
865 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP);
866 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0;
867 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
868 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
869 cursorp->size.x = 64;
870 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f;
871
872 if (cursorp->image != NULL) {
873 count = (cursorp->size.y * 64 * 2) / NBBY;
874 error = copyout((char *)(dc->dc_vaddr +
875 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)),
876 cursorp->image, count);
877 if (error)
878 return (error);
879 /* No mask */
880 }
881 error = dcrf->ramdac_get_curcmap(dcrc, cursorp);
882 return (error);
883 }
884
885 int
886 tga_builtin_set_curpos(dc, curposp)
887 struct tga_devconfig *dc;
888 struct wsdisplay_curpos *curposp;
889 {
890
891 TGAWREG(dc, TGA_REG_CXYR,
892 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff));
893 return (0);
894 }
895
896 int
897 tga_builtin_get_curpos(dc, curposp)
898 struct tga_devconfig *dc;
899 struct wsdisplay_curpos *curposp;
900 {
901
902 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff;
903 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff;
904 return (0);
905 }
906
907 int
908 tga_builtin_get_curmax(dc, curposp)
909 struct tga_devconfig *dc;
910 struct wsdisplay_curpos *curposp;
911 {
912
913 curposp->x = curposp->y = 64;
914 return (0);
915 }
916
917 /*
918 * Copy columns (characters) in a row (line).
919 */
920 static void
921 tga_copycols(id, row, srccol, dstcol, ncols)
922 void *id;
923 int row, srccol, dstcol, ncols;
924 {
925 struct rasops_info *ri = id;
926 int y, srcx, dstx, nx;
927
928 y = ri->ri_font->fontheight * row;
929 srcx = ri->ri_font->fontwidth * srccol;
930 dstx = ri->ri_font->fontwidth * dstcol;
931 nx = ri->ri_font->fontwidth * ncols;
932
933 tga_rop(ri, dstx, y,
934 nx, ri->ri_font->fontheight, RAS_SRC,
935 ri, srcx, y);
936 }
937
938 /*
939 * Copy rows (lines).
940 */
941 static void
942 tga_copyrows(id, srcrow, dstrow, nrows)
943 void *id;
944 int srcrow, dstrow, nrows;
945 {
946 struct rasops_info *ri = id;
947 int srcy, dsty, ny;
948
949 srcy = ri->ri_font->fontheight * srcrow;
950 dsty = ri->ri_font->fontheight * dstrow;
951 ny = ri->ri_font->fontheight * nrows;
952
953 tga_rop(ri, 0, dsty,
954 ri->ri_emuwidth, ny, RAS_SRC,
955 ri, 0, srcy);
956 }
957
958 /* Do we need the src? */
959 static int needsrc[16] = { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 };
960
961 /* A mapping between our API and the TGA card */
962 static int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6,
963 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf
964 };
965
966 /*
967 * Generic TGA raster op.
968 * This covers all possible raster ops, and
969 * clips the sizes and all of that.
970 */
971 static int
972 tga_rop(dst, dx, dy, w, h, rop, src, sx, sy)
973 struct rasops_info *dst;
974 int dx, dy, w, h, rop;
975 struct rasops_info *src;
976 int sx, sy;
977 {
978 if (!dst)
979 return -1;
980 if (needsrc[RAS_GETOP(rop)]) {
981 if (src == NULL)
982 return -1; /* We want a src */
983 /* Clip against src */
984 if (sx < 0) {
985 w += sx;
986 sx = 0;
987 }
988 if (sy < 0) {
989 h += sy;
990 sy = 0;
991 }
992 if (sx + w > src->ri_emuwidth)
993 w = src->ri_emuwidth - sx;
994 if (sy + h > src->ri_emuheight)
995 h = src->ri_emuheight - sy;
996 } else {
997 if (src != NULL)
998 return -1; /* We need no src */
999 }
1000 /* Clip against dst. We modify src regardless of using it,
1001 * since it really doesn't matter.
1002 */
1003 if (dx < 0) {
1004 w += dx;
1005 sx -= dx;
1006 dx = 0;
1007 }
1008 if (dy < 0) {
1009 h += dy;
1010 sy -= dy;
1011 dy = 0;
1012 }
1013 if (dx + w > dst->ri_emuwidth)
1014 w = dst->ri_emuwidth - dx;
1015 if (dy + h > dst->ri_emuheight)
1016 h = dst->ri_emuheight - dy;
1017 if (w <= 0 || h <= 0)
1018 return 0; /* Vacuously true; */
1019 if (!src) {
1020 /* XXX Punt! */
1021 return -1;
1022 }
1023 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy);
1024 }
1025
1026
1027
1028 /*
1029 * Video to Video raster ops.
1030 * This function deals with all raster ops that have a src and dst
1031 * that are on the card.
1032 */
1033 static int
1034 tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy)
1035 struct rasops_info *dst;
1036 int dx, dy, w, h, rop;
1037 struct rasops_info *src;
1038 int sx, sy;
1039 {
1040 struct tga_devconfig *dc = (struct tga_devconfig *)dst->ri_hw;
1041 int srcb, dstb, tga_srcb, tga_dstb;
1042 int x, y, wb;
1043 int xstart, xend, xdir;
1044 int ystart, yend, ydir, yinc;
1045 int xleft, lastx, lastleft;
1046 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units;
1047
1048 /*
1049 * I don't yet want to deal with unaligned guys, really. And we don't
1050 * deal with copies from one card to another.
1051 */
1052 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) {
1053 /* XXX Punt! */
1054 /* XXX should never happen, since it's only being used to
1055 * XXX copy 8-pixel-wide characters.
1056 */
1057 return -1;
1058 }
1059
1060 wb = w * (dst->ri_depth / 8);
1061 if (sy >= dy) {
1062 ystart = 0;
1063 yend = h;
1064 ydir = 1;
1065 } else {
1066 ystart = h;
1067 yend = 0;
1068 ydir = -1;
1069 }
1070 if (sx >= dx) { /* moving to the left */
1071 xstart = 0;
1072 xend = w * (dst->ri_depth / 8) - 4;
1073 xdir = 1;
1074 } else { /* moving to the right */
1075 xstart = wb - ( wb >= 4*64 ? 4*64 : wb >= 64 ? 64 : 4 );
1076 xend = 0;
1077 xdir = -1;
1078 }
1079 #define XINC4 4
1080 #define XINC64 64
1081 #define XINC256 (64*4)
1082 yinc = ydir * dst->ri_stride;
1083 ystart *= dst->ri_stride;
1084 yend *= dst->ri_stride;
1085
1086 srcb = sy * src->ri_stride + sx * (src->ri_depth/8);
1087 dstb = dy * dst->ri_stride + dx * (dst->ri_depth/8);
1088 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride +
1089 (sx + src->ri_xorigin) * (src->ri_depth/8);
1090 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride +
1091 (dx + dst->ri_xorigin) * (dst->ri_depth/8);
1092
1093 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */
1094 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */
1095
1096 /*
1097 * we have 3 sizes of pixels to move in X direction:
1098 * 4 * 64 (unrolled TGA ops)
1099 * 64 (single TGA op)
1100 * 4 (CPU, using long word)
1101 */
1102
1103 if (xdir == 1) { /* move to the left */
1104
1105 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
1106
1107 /* 4*64 byte chunks */
1108 for (xleft = wb, x = xstart;
1109 x <= xend && xleft >= 4*64;
1110 x += XINC256, xleft -= XINC256) {
1111
1112 /* XXX XXX Eight writes to different addresses should fill
1113 * XXX XXX up the write buffers on 21064 and 21164 chips,
1114 * XXX XXX but later CPUs might have larger write buffers which
1115 * XXX XXX require further unrolling of this loop, or the
1116 * XXX XXX insertion of memory barriers.
1117 */
1118 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
1119 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
1120 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 1 * 64);
1121 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 1 * 64);
1122 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 2 * 64);
1123 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 2 * 64);
1124 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 3 * 64);
1125 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 3 * 64);
1126 }
1127
1128 /* 64 byte chunks */
1129 for ( ; x <= xend && xleft >= 64;
1130 x += XINC64, xleft -= XINC64) {
1131 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
1132 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
1133 }
1134 lastx = x; lastleft = xleft; /* remember for CPU loop */
1135
1136 }
1137 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
1138 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
1139
1140 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
1141 /* 4 byte granularity */
1142 for (x = lastx, xleft = lastleft;
1143 x <= xend && xleft >= 4;
1144 x += XINC4, xleft -= XINC4) {
1145 *(uint32_t *)(dst->ri_bits + dstb + y + x) =
1146 *(uint32_t *)(dst->ri_bits + srcb + y + x);
1147 }
1148 }
1149 }
1150 else { /* above move to the left, below move to the right */
1151
1152 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
1153
1154 /* 4*64 byte chunks */
1155 for (xleft = wb, x = xstart;
1156 x >= xend && xleft >= 4*64;
1157 x -= XINC256, xleft -= XINC256) {
1158
1159 /* XXX XXX Eight writes to different addresses should fill
1160 * XXX XXX up the write buffers on 21064 and 21164 chips,
1161 * XXX XXX but later CPUs might have larger write buffers which
1162 * XXX XXX require further unrolling of this loop, or the
1163 * XXX XXX insertion of memory barriers.
1164 */
1165 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 3 * 64);
1166 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 3 * 64);
1167 TGAWALREG(dc, TGA_REG_GCSR, 1, tga_srcb + y + x + 2 * 64);
1168 TGAWALREG(dc, TGA_REG_GCDR, 1, tga_dstb + y + x + 2 * 64);
1169 TGAWALREG(dc, TGA_REG_GCSR, 2, tga_srcb + y + x + 1 * 64);
1170 TGAWALREG(dc, TGA_REG_GCDR, 2, tga_dstb + y + x + 1 * 64);
1171 TGAWALREG(dc, TGA_REG_GCSR, 3, tga_srcb + y + x + 0 * 64);
1172 TGAWALREG(dc, TGA_REG_GCDR, 3, tga_dstb + y + x + 0 * 64);
1173 }
1174
1175 if (xleft) x += XINC256 - XINC64;
1176
1177 /* 64 byte chunks */
1178 for ( ; x >= xend && xleft >= 64;
1179 x -= XINC64, xleft -= XINC64) {
1180 TGAWALREG(dc, TGA_REG_GCSR, 0, tga_srcb + y + x + 0 * 64);
1181 TGAWALREG(dc, TGA_REG_GCDR, 0, tga_dstb + y + x + 0 * 64);
1182 }
1183 if (xleft) x += XINC64 - XINC4;
1184 lastx = x; lastleft = xleft; /* remember for CPU loop */
1185 }
1186 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */
1187 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */
1188
1189 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) {
1190 /* 4 byte granularity */
1191 for (x = lastx, xleft = lastleft;
1192 x >= xend && xleft >= 4;
1193 x -= XINC4, xleft -= XINC4) {
1194 *(uint32_t *)(dst->ri_bits + dstb + y + x) =
1195 *(uint32_t *)(dst->ri_bits + srcb + y + x);
1196 }
1197 }
1198 }
1199 return 0;
1200 }
1201
1202
1203 void tga_putchar (c, row, col, uc, attr)
1204 void *c;
1205 int row, col;
1206 u_int uc;
1207 long attr;
1208 {
1209 struct rasops_info *ri = c;
1210 struct tga_devconfig *dc = ri->ri_hw;
1211 int fs, height, width;
1212 u_char *fr;
1213 int32_t *rp;
1214
1215 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale);
1216
1217 height = ri->ri_font->fontheight;
1218 width = ri->ri_font->fontwidth;
1219
1220 uc -= ri->ri_font->firstchar;
1221 fr = (u_char *)ri->ri_font->data + uc * ri->ri_fontscale;
1222 fs = ri->ri_font->stride;
1223
1224 /* Set foreground and background color. XXX memoize this somehow?
1225 * The rasops code has already expanded the color entry to 32 bits
1226 * for us, even for 8-bit displays, so we don't have to do anything.
1227 */
1228 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]);
1229 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]);
1230
1231 /* Set raster operation to "copy"... */
1232 if (ri->ri_depth == 8)
1233 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1234 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */
1235 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1236
1237 /* Set which pixels we're drawing (of a possible 32). */
1238 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1);
1239
1240 /* Set drawing mode to opaque stipple. */
1241 TGAWREG(dc, TGA_REG_GMOR, 0x1);
1242
1243 /* Insert write barrier before actually sending data */
1244 /* XXX Abuses the fact that there is only one write barrier on Alphas */
1245 TGAREGWB(dc, TGA_REG_GMOR, 1);
1246
1247 while(height--) {
1248 /* The actual stipple write */
1249 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24);
1250
1251 fr += fs;
1252 rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
1253 }
1254
1255 /* Do underline */
1256 if ((attr & 1) != 0) {
1257 rp = (int32_t *)((caddr_t)rp - (ri->ri_stride << 1));
1258 *rp = 0xffffffff;
1259 }
1260
1261 /* Set grapics mode back to normal. */
1262 TGAWREG(dc, TGA_REG_GMOR, 0);
1263 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff);
1264
1265 }
1266
1267 static void
1268 tga_eraserows(c, row, num, attr)
1269 void *c;
1270 int row, num;
1271 long attr;
1272 {
1273 struct rasops_info *ri = c;
1274 struct tga_devconfig *dc = ri->ri_hw;
1275 int32_t color, lines, pixels;
1276 int32_t *rp;
1277
1278 color = ri->ri_devcmap[(attr >> 16) & 15];
1279 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale);
1280 lines = num * ri->ri_font->fontheight;
1281 pixels = ri->ri_emuwidth - 1;
1282
1283 /* Set fill color in block-color registers */
1284 TGAWREG(dc, TGA_REG_GBCR0, color);
1285 TGAWREG(dc, TGA_REG_GBCR1, color);
1286 if (ri->ri_depth != 8) {
1287 TGAWREG(dc, TGA_REG_GBCR2, color);
1288 TGAWREG(dc, TGA_REG_GBCR3, color);
1289 TGAWREG(dc, TGA_REG_GBCR4, color);
1290 TGAWREG(dc, TGA_REG_GBCR5, color);
1291 TGAWREG(dc, TGA_REG_GBCR6, color);
1292 TGAWREG(dc, TGA_REG_GBCR7, color);
1293 }
1294
1295 /* Set raster operation to "copy"... */
1296 if (ri->ri_depth == 8)
1297 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1298 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */
1299 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1300
1301 /* Set which pixels we're drawing (of a possible 32). */
1302 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
1303
1304 /* Set drawing mode to block fill. */
1305 TGAWREG(dc, TGA_REG_GMOR, 0x2d);
1306
1307 /* Insert write barrier before actually sending data */
1308 /* XXX Abuses the fact that there is only one write barrier on Alphas */
1309 TGAREGWB(dc, TGA_REG_GMOR, 1);
1310
1311 while (lines--) {
1312 *rp = pixels;
1313 rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
1314 }
1315
1316 /* Set grapics mode back to normal. */
1317 TGAWREG(dc, TGA_REG_GMOR, 0);
1318
1319 }
1320
1321 static void
1322 tga_erasecols (c, row, col, num, attr)
1323 void *c;
1324 int row, col, num;
1325 long attr;
1326 {
1327 struct rasops_info *ri = c;
1328 struct tga_devconfig *dc = ri->ri_hw;
1329 int32_t color, lines, pixels;
1330 int32_t *rp;
1331
1332 color = ri->ri_devcmap[(attr >> 16) & 15];
1333 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale);
1334 lines = ri->ri_font->fontheight;
1335 pixels = (num * ri->ri_font->fontwidth) - 1;
1336
1337 /* Set fill color in block-color registers */
1338 TGAWREG(dc, TGA_REG_GBCR0, color);
1339 TGAWREG(dc, TGA_REG_GBCR1, color);
1340 if (ri->ri_depth != 8) {
1341 TGAWREG(dc, TGA_REG_GBCR2, color);
1342 TGAWREG(dc, TGA_REG_GBCR3, color);
1343 TGAWREG(dc, TGA_REG_GBCR4, color);
1344 TGAWREG(dc, TGA_REG_GBCR5, color);
1345 TGAWREG(dc, TGA_REG_GBCR6, color);
1346 TGAWREG(dc, TGA_REG_GBCR7, color);
1347 }
1348
1349 /* Set raster operation to "copy"... */
1350 if (ri->ri_depth == 8)
1351 TGAWREG(dc, TGA_REG_GOPR, 0x3);
1352 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */
1353 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8));
1354
1355 /* Set which pixels we're drawing (of a possible 32). */
1356 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff);
1357
1358 /* Set drawing mode to block fill. */
1359 TGAWREG(dc, TGA_REG_GMOR, 0x2d);
1360
1361 /* Insert write barrier before actually sending data */
1362 /* XXX Abuses the fact that there is only one write barrier on Alphas */
1363 TGAREGWB(dc, TGA_REG_GMOR, 1);
1364
1365 while (lines--) {
1366 *rp = pixels;
1367 rp = (int32_t *)((caddr_t)rp + ri->ri_stride);
1368 }
1369
1370 /* Set grapics mode back to normal. */
1371 TGAWREG(dc, TGA_REG_GMOR, 0);
1372 }
1373
1374
1375 static void
1376 tga_ramdac_wr(v, btreg, val)
1377 void *v;
1378 u_int btreg;
1379 u_int8_t val;
1380 {
1381 struct tga_devconfig *dc = v;
1382
1383 if (btreg > BT485_REG_MAX)
1384 panic("tga_ramdac_wr: reg %d out of range\n", btreg);
1385
1386 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */
1387 TGAREGWB(dc, TGA_REG_EPDR, 1);
1388 }
1389
1390 static void
1391 tga2_ramdac_wr(v, btreg, val)
1392 void *v;
1393 u_int btreg;
1394 u_int8_t val;
1395 {
1396 struct tga_devconfig *dc = v;
1397 bus_space_handle_t ramdac;
1398
1399 if (btreg > BT485_REG_MAX)
1400 panic("tga_ramdac_wr: reg %d out of range\n", btreg);
1401
1402 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
1403 (0xe << 12) + (btreg << 8), 4, &ramdac);
1404 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff);
1405 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE);
1406 }
1407
1408 static u_int8_t
1409 tga_bt463_rd(v, btreg)
1410 void *v;
1411 u_int btreg;
1412 {
1413 struct tga_devconfig *dc = v;
1414 tga_reg_t rdval;
1415
1416 /*
1417 * Strobe CE# (high->low->high) since status and data are latched on
1418 * the falling and rising edges (repsectively) of this active-low signal.
1419 */
1420
1421 TGAREGWB(dc, TGA_REG_EPSR, 1);
1422 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
1423 TGAREGWB(dc, TGA_REG_EPSR, 1);
1424 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0);
1425
1426 TGAREGRB(dc, TGA_REG_EPSR, 1);
1427
1428 rdval = TGARREG(dc, TGA_REG_EPDR);
1429 TGAREGWB(dc, TGA_REG_EPSR, 1);
1430 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1);
1431
1432 return (rdval >> 16) & 0xff;
1433 }
1434
1435 static void
1436 tga_bt463_wr(v, btreg, val)
1437 void *v;
1438 u_int btreg;
1439 u_int8_t val;
1440 {
1441 struct tga_devconfig *dc = v;
1442
1443 /*
1444 * In spite of the 21030 documentation, to set the MPU bus bits for
1445 * a write, you set them in the upper bits of EPDR, not EPSR.
1446 */
1447
1448 /*
1449 * Strobe CE# (high->low->high) since status and data are latched on
1450 * the falling and rising edges of this active-low signal.
1451 */
1452
1453 TGAREGWB(dc, TGA_REG_EPDR, 1);
1454 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
1455 TGAREGWB(dc, TGA_REG_EPDR, 1);
1456 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val);
1457 TGAREGWB(dc, TGA_REG_EPDR, 1);
1458 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val);
1459
1460 }
1461
1462 static u_int8_t
1463 tga_ramdac_rd(v, btreg)
1464 void *v;
1465 u_int btreg;
1466 {
1467 struct tga_devconfig *dc = v;
1468 tga_reg_t rdval;
1469
1470 if (btreg > BT485_REG_MAX)
1471 panic("tga_ramdac_rd: reg %d out of range\n", btreg);
1472
1473 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */
1474 TGAREGWB(dc, TGA_REG_EPSR, 1);
1475
1476 rdval = TGARREG(dc, TGA_REG_EPDR);
1477 return (rdval >> 16) & 0xff; /* XXX */
1478 }
1479
1480 static u_int8_t
1481 tga2_ramdac_rd(v, btreg)
1482 void *v;
1483 u_int btreg;
1484 {
1485 struct tga_devconfig *dc = v;
1486 bus_space_handle_t ramdac;
1487 u_int8_t retval;
1488
1489 if (btreg > BT485_REG_MAX)
1490 panic("tga_ramdac_rd: reg %d out of range\n", btreg);
1491
1492 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_RAMDAC +
1493 (0xe << 12) + (btreg << 8), 4, &ramdac);
1494 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff;
1495 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ);
1496 return retval;
1497 }
1498
1499 #include <dev/ic/decmonitors.c>
1500 void tga2_ics9110_wr __P((
1501 struct tga_devconfig *dc,
1502 int dotclock
1503 ));
1504
1505 void
1506 tga2_init(dc, m)
1507 struct tga_devconfig *dc;
1508 int m;
1509 {
1510
1511 tga2_ics9110_wr(dc, decmonitors[m].dotclock);
1512 #if 0
1513 TGAWREG(dc, TGA_REG_VHCR,
1514 ((decmonitors[m].hbp / 4) << 21) |
1515 ((decmonitors[m].hsync / 4) << 14) |
1516 (((decmonitors[m].hfp - 4) / 4) << 9) |
1517 ((decmonitors[m].cols + 4) / 4));
1518 #else
1519 TGAWREG(dc, TGA_REG_VHCR,
1520 ((decmonitors[m].hbp / 4) << 21) |
1521 ((decmonitors[m].hsync / 4) << 14) |
1522 (((decmonitors[m].hfp) / 4) << 9) |
1523 ((decmonitors[m].cols) / 4));
1524 #endif
1525 TGAWREG(dc, TGA_REG_VVCR,
1526 (decmonitors[m].vbp << 22) |
1527 (decmonitors[m].vsync << 16) |
1528 (decmonitors[m].vfp << 11) |
1529 (decmonitors[m].rows));
1530 TGAWREG(dc, TGA_REG_VVBR, 1);
1531 TGAREGRWB(dc, TGA_REG_VHCR, 3);
1532 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1);
1533 TGAREGRWB(dc, TGA_REG_VVVR, 1);
1534 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff);
1535 TGAREGRWB(dc, TGA_REG_GPMR, 1);
1536 }
1537
1538 void
1539 tga2_ics9110_wr(dc, dotclock)
1540 struct tga_devconfig *dc;
1541 int dotclock;
1542 {
1543 bus_space_handle_t clock;
1544 u_int32_t valU;
1545 int N, M, R, V, X;
1546 int i;
1547
1548 switch (dotclock) {
1549 case 130808000:
1550 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break;
1551 case 119840000:
1552 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break;
1553 case 108180000:
1554 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break;
1555 case 103994000:
1556 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break;
1557 case 175000000:
1558 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break;
1559 case 75000000:
1560 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break;
1561 case 74000000:
1562 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break;
1563 case 69000000:
1564 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break;
1565 case 65000000:
1566 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break;
1567 case 50000000:
1568 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break;
1569 case 40000000:
1570 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break;
1571 case 31500000:
1572 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break;
1573 case 25175000:
1574 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break;
1575 case 135000000:
1576 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break;
1577 case 110000000:
1578 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break;
1579 case 202500000:
1580 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break;
1581 default:
1582 panic("unrecognized clock rate %d\n", dotclock);
1583 }
1584
1585 /* XXX -- hard coded, bad */
1586 valU = N | ( M << 7 ) | (V << 14);
1587 valU |= (X << 15) | (R << 17);
1588 valU |= 0x17 << 19;
1589
1590 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
1591 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */
1592
1593 for (i=24; i>0; i--) {
1594 u_int32_t writeval;
1595
1596 writeval = valU & 0x1;
1597 if (i == 1)
1598 writeval |= 0x2;
1599 valU >>= 1;
1600 bus_space_write_4(dc->dc_memt, clock, 0, writeval);
1601 bus_space_barrier(dc->dc_memt, clock, 0, 4, BUS_SPACE_BARRIER_WRITE);
1602 }
1603 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV +
1604 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4,
1605 &clock); /* XXX */
1606 bus_space_write_4(dc->dc_memt, clock, 0, 0x0);
1607 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE);
1608 }
1609