tga.c revision 1.79
1 /* $NetBSD: tga.c,v 1.79 2010/05/15 08:53:27 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.79 2010/05/15 08:53:27 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <uvm/uvm_extern.h> 62 63 int tgamatch(device_t, cfdata_t, void *); 64 void tgaattach(device_t, device_t, void *); 65 int tgaprint(void *, const char *); 66 67 CFATTACH_DECL_NEW(tga, sizeof(struct tga_softc), 68 tgamatch, tgaattach, NULL, NULL); 69 70 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 71 pcitag_t tag, struct tga_devconfig *dc); 72 73 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 74 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 75 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 76 unsigned int tga_getdotclock(struct tga_devconfig *dc); 77 78 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 79 paddr_t tga_mmap(void *, void *, off_t, int); 80 static void tga_copyrows(void *, int, int, int); 81 static void tga_copycols(void *, int, int, int, int); 82 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 83 void **, int *, int *, long *); 84 static void tga_free_screen(void *, void *); 85 static int tga_show_screen(void *, void *, int, 86 void (*) (void *, int, int), void *); 87 static int tga_rop(struct rasops_info *, int, int, int, int, int, 88 struct rasops_info *, int, int); 89 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 90 int, struct rasops_info *, int, int); 91 static void tga_putchar(void *c, int row, int col, u_int uc, long attr); 92 static void tga_eraserows(void *, int, int, long); 93 static void tga_erasecols(void *, int, int, int, long); 94 void tga2_init(struct tga_devconfig *); 95 96 static void tga_config_interrupts(device_t); 97 98 /* RAMDAC interface functions */ 99 static int tga_sched_update(void *, void (*)(void *)); 100 static void tga_ramdac_wr(void *, u_int, uint8_t); 101 static uint8_t tga_ramdac_rd(void *, u_int); 102 static void tga_bt463_wr(void *, u_int, uint8_t); 103 static uint8_t tga_bt463_rd(void *, u_int); 104 static void tga2_ramdac_wr(void *, u_int, uint8_t); 105 static uint8_t tga2_ramdac_rd(void *, u_int); 106 107 /* Interrupt handler */ 108 static int tga_intr(void *); 109 110 struct tga_devconfig tga_console_dc; 111 112 /* The NULL entries will get filled in by rasops_init(). 113 * XXX and the non-NULL ones will be overwritten; reset after calling it. 114 */ 115 struct wsdisplay_emulops tga_emulops = { 116 NULL, 117 NULL, 118 tga_putchar, 119 tga_copycols, 120 tga_erasecols, 121 tga_copyrows, 122 tga_eraserows, 123 NULL, 124 NULL, 125 }; 126 127 struct wsscreen_descr tga_stdscreen = { 128 "std", 129 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 130 &tga_emulops, 131 0, 0, 132 WSSCREEN_REVERSE, 133 NULL, 134 }; 135 136 const struct wsscreen_descr *_tga_scrlist[] = { 137 &tga_stdscreen, 138 /* XXX other formats, graphics screen? */ 139 }; 140 141 struct wsscreen_list tga_screenlist = { 142 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 143 }; 144 145 struct wsdisplay_accessops tga_accessops = { 146 tga_ioctl, 147 tga_mmap, 148 tga_alloc_screen, 149 tga_free_screen, 150 tga_show_screen, 151 NULL, /* load_font */ 152 NULL, 153 NULL, 154 }; 155 156 static void tga_blank(struct tga_devconfig *); 157 static void tga_unblank(struct tga_devconfig *); 158 159 int 160 tga_cnmatch(bus_space_tag_t iot, bus_space_tag_t memt, 161 pci_chipset_tag_t pc, pcitag_t tag) 162 { 163 164 return tga_matchcommon(memt, pc, tag); 165 } 166 167 int 168 tgamatch(device_t parent, cfdata_t match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 173 return (0); 174 175 switch (PCI_PRODUCT(pa->pa_id)) { 176 case PCI_PRODUCT_DEC_21030: 177 case PCI_PRODUCT_DEC_PBXGB: 178 break; 179 default: 180 return 0; 181 } 182 183 #if defined(__alpha__) || defined(arc) 184 /* short-circuit the following test, as we 185 * already have the memory mapped and hence 186 * cannot perform it---and we are the console 187 * anyway. 188 */ 189 if (pa->pa_tag == tga_console_dc.dc_pcitag) 190 return 10; 191 #endif 192 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 193 } 194 195 static int 196 tga_matchcommon(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 197 { 198 struct tga_devconfig tmp_dc; 199 struct tga_devconfig *dc = &tmp_dc; 200 bus_size_t pcisize; 201 202 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 203 dc->dc_tga_type = tga_identify(dc); 204 205 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 206 bus_space_unmap(memt, dc->dc_memh, pcisize); 207 if (dc->dc_tgaconf) 208 return 10; 209 return 0; 210 } 211 212 static void 213 tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 214 bus_size_t *pcisize, struct tga_devconfig *dc) 215 { 216 int flags; 217 218 dc->dc_memt = memt; 219 dc->dc_tgaconf = NULL; 220 221 /* XXX magic number */ 222 if (pci_mapreg_info(pc, tag, 0x10, 223 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 224 &dc->dc_pcipaddr, pcisize, &flags)) 225 panic("tga_mapaddrs: pci_mapreg_info() failed"); 226 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 227 panic("tga memory not prefetchable"); 228 229 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 230 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 231 panic("tga_mapaddrs: could not map TGA address space"); 232 dc->dc_vaddr = (vaddr_t)bus_space_vaddr(memt, dc->dc_memh); 233 234 bus_space_subregion(dc->dc_memt, dc->dc_memh, 235 TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs); 236 } 237 238 static void 239 tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 240 struct tga_devconfig *dc) 241 { 242 const struct tga_conf *tgac; 243 struct rasops_info *rip; 244 int cookie; 245 bus_size_t pcisize; 246 int i; 247 248 dc->dc_pc = pc; 249 dc->dc_pcitag = tag; 250 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 251 dc->dc_tga_type = tga_identify(dc); 252 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 253 #if 0 254 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 255 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 256 panic("tga_init: memory size mismatch?"); 257 #endif 258 259 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 260 case 0x01: 261 case 0x02: 262 case 0x03: 263 case 0x04: 264 dc->dc_tga2 = 0; 265 break; 266 case 0x20: 267 case 0x21: 268 case 0x22: 269 dc->dc_tga2 = 1; 270 break; 271 default: 272 panic("tga_init: TGA Revision not recognized"); 273 } 274 275 if (dc->dc_tga2) 276 tga2_init(dc); 277 278 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 279 case 0: 280 dc->dc_wid = 8192; 281 break; 282 283 case 1: 284 dc->dc_wid = 8196; 285 break; 286 287 default: 288 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 289 break; 290 } 291 292 /* 293 * XXX XXX Turning off "odd" shouldn't be necessary, 294 * XXX XXX but I can't make X work with the weird size. 295 */ 296 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 297 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 298 TGAWREG(dc, TGA_REG_VHCR, 299 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 300 dc->dc_wid -= 4; 301 } 302 303 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 304 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 305 306 /* XXX this seems to be what DEC does */ 307 TGAWREG(dc, TGA_REG_CCBR, 0); 308 TGAWREG(dc, TGA_REG_VVBR, 1); 309 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 310 1 * tgac->tgac_vvbr_units; 311 dc->dc_blanked = 1; 312 tga_unblank(dc); 313 314 /* 315 * Set all bits in the pixel mask, to enable writes to all pixels. 316 * It seems that the console firmware clears some of them 317 * under some circumstances, which causes cute vertical stripes. 318 */ 319 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 320 321 /* clear the screen */ 322 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(uint32_t)) 323 *(uint32_t *)(dc->dc_videobase + i) = 0; 324 325 /* Initialize rasops descriptor */ 326 rip = &dc->dc_rinfo; 327 rip->ri_flg = RI_CENTER; 328 rip->ri_depth = tgac->tgac_phys_depth; 329 rip->ri_bits = (void *)dc->dc_videobase; 330 rip->ri_width = dc->dc_wid; 331 rip->ri_height = dc->dc_ht; 332 rip->ri_stride = dc->dc_rowbytes; 333 rip->ri_hw = dc; 334 if (dc == &tga_console_dc) 335 rip->ri_flg |= RI_NO_AUTO; 336 337 if (tgac->tgac_phys_depth == 32) { 338 rip->ri_rnum = 8; 339 rip->ri_gnum = 8; 340 rip->ri_bnum = 8; 341 rip->ri_rpos = 16; 342 rip->ri_gpos = 8; 343 rip->ri_bpos = 0; 344 } 345 346 wsfont_init(); 347 /* prefer 8 pixel wide font */ 348 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 349 WSDISPLAY_FONTORDER_L2R); 350 if (cookie <= 0) 351 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 352 WSDISPLAY_FONTORDER_L2R); 353 if (cookie <= 0) { 354 printf("tga: no appropriate fonts.\n"); 355 return; 356 } 357 358 /* the accelerated tga_putchar() needs LSbit left */ 359 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 360 printf("tga: couldn't lock font\n"); 361 return; 362 } 363 dc->dc_rinfo.ri_wsfcookie = cookie; 364 365 rasops_init(rip, 34, 80); 366 367 /* add our accelerated functions */ 368 /* XXX shouldn't have to do this; rasops should leave non-NULL 369 * XXX entries alone. 370 */ 371 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 372 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 373 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 374 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 375 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 376 377 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 378 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 379 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 380 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 381 382 383 dc->dc_intrenabled = 0; 384 } 385 386 void 387 tgaattach(device_t parent, device_t self, void *aux) 388 { 389 struct pci_attach_args *pa = aux; 390 struct tga_softc *sc = device_private(self); 391 struct tga_devconfig *dc; 392 struct wsemuldisplaydev_attach_args aa; 393 pci_intr_handle_t intrh; 394 const char *intrstr; 395 uint8_t rev; 396 int console; 397 398 sc->sc_dev = self; 399 400 #if defined(__alpha__) || defined(arc) 401 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 402 #else 403 console = 0; 404 #endif 405 if (console) { 406 sc->sc_dc = &tga_console_dc; 407 sc->sc_dc->dc_rinfo.ri_flg &= ~RI_NO_AUTO; 408 sc->nscreens = 1; 409 } else { 410 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 411 M_WAITOK|M_ZERO); 412 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 413 } 414 if (sc->sc_dc->dc_vaddr == 0) { 415 aprint_error(": couldn't map memory space; punt!\n"); 416 return; 417 } 418 419 /* XXX say what's going on. */ 420 intrstr = NULL; 421 if (pci_intr_map(pa, &intrh)) { 422 aprint_error(": couldn't map interrupt"); 423 return; 424 } 425 intrstr = pci_intr_string(pa->pa_pc, intrh); 426 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 427 sc->sc_dc); 428 if (sc->sc_intr == NULL) { 429 aprint_error(": couldn't establish interrupt"); 430 if (intrstr != NULL) 431 aprint_error("at %s", intrstr); 432 aprint_error("\n"); 433 return; 434 } 435 436 rev = PCI_REVISION(pa->pa_class); 437 switch (rev) { 438 case 0x1: 439 case 0x2: 440 case 0x3: 441 aprint_normal(": DC21030 step %c", 'A' + rev - 1); 442 break; 443 case 0x20: 444 aprint_normal(": TGA2 abstract software model"); 445 break; 446 case 0x21: 447 case 0x22: 448 aprint_normal(": TGA2 pass %d", rev - 0x20); 449 break; 450 451 default: 452 aprint_normal("unknown stepping (0x%x)", rev); 453 break; 454 } 455 aprint_normal(", "); 456 457 /* 458 * Get RAMDAC function vectors and call the RAMDAC functions 459 * to allocate its private storage and pass that back to us. 460 */ 461 462 dc = sc->sc_dc; 463 dc->dc_ramdac_funcs = dc->dc_tgaconf->ramdac_funcs(); 464 if (!dc->dc_tga2) { 465 if (dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 466 dc->dc_ramdac_cookie = 467 dc->dc_ramdac_funcs->ramdac_register(dc, 468 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 469 else 470 dc->dc_ramdac_cookie = 471 dc->dc_ramdac_funcs->ramdac_register(dc, 472 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 473 } else { 474 dc->dc_ramdac_cookie = dc->dc_ramdac_funcs->ramdac_register(dc, 475 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 476 477 /* XXX this is a bit of a hack, setting the dotclock here */ 478 if (dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 479 (*dc->dc_ramdac_funcs->ramdac_set_dotclock) 480 (dc->dc_ramdac_cookie, tga_getdotclock(dc)); 481 } 482 483 /* 484 * Initialize the RAMDAC. Initialization includes disabling 485 * cursor, setting a sane colormap, etc. We presume that we've 486 * filled in the necessary dot clock for PowerStorm 4d20. 487 */ 488 (*dc->dc_ramdac_funcs->ramdac_init)(dc->dc_ramdac_cookie); 489 TGAWREG(dc, TGA_REG_SISR, 0x00000001); /* XXX */ 490 491 if (dc->dc_tgaconf == NULL) { 492 aprint_error("unknown board configuration\n"); 493 return; 494 } 495 aprint_normal("board type %s\n", dc->dc_tgaconf->tgac_name); 496 aprint_normal_dev(self, "%d x %d, %dbpp, %s RAMDAC\n", 497 dc->dc_wid, dc->dc_ht, 498 dc->dc_tgaconf->tgac_phys_depth, 499 dc->dc_ramdac_funcs->ramdac_name); 500 501 if (intrstr != NULL) 502 aprint_normal_dev(self, "interrupting at %s\n", 503 intrstr); 504 505 aa.console = console; 506 aa.scrdata = &tga_screenlist; 507 aa.accessops = &tga_accessops; 508 aa.accesscookie = sc; 509 510 config_found(self, &aa, wsemuldisplaydevprint); 511 512 config_interrupts(self, tga_config_interrupts); 513 } 514 515 static void 516 tga_config_interrupts(device_t self) 517 { 518 struct tga_softc *sc; 519 520 sc = device_private(self); 521 sc->sc_dc->dc_intrenabled = 1; 522 } 523 524 int 525 tga_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 526 { 527 struct tga_softc *sc = v; 528 struct tga_devconfig *dc = sc->sc_dc; 529 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 530 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 531 532 switch (cmd) { 533 case WSDISPLAYIO_GTYPE: 534 *(u_int *)data = WSDISPLAY_TYPE_TGA; 535 return 0; 536 537 case WSDISPLAYIO_GINFO: 538 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 539 wsd_fbip->height = sc->sc_dc->dc_ht; 540 wsd_fbip->width = sc->sc_dc->dc_wid; 541 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 542 #if 0 543 wsd_fbip->cmsize = 256; /* XXX ??? */ 544 #else 545 wsd_fbip->cmsize = 1024; /* XXX ??? */ 546 #endif 547 #undef wsd_fbip 548 return 0; 549 550 case WSDISPLAYIO_GETCMAP: 551 return (*dcrf->ramdac_get_cmap)(dcrc, 552 (struct wsdisplay_cmap *)data); 553 554 case WSDISPLAYIO_PUTCMAP: 555 return (*dcrf->ramdac_set_cmap)(dcrc, 556 (struct wsdisplay_cmap *)data); 557 558 case WSDISPLAYIO_SVIDEO: 559 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 560 tga_blank(sc->sc_dc); 561 else 562 tga_unblank(sc->sc_dc); 563 return 0; 564 565 case WSDISPLAYIO_GVIDEO: 566 *(u_int *)data = dc->dc_blanked ? 567 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 568 return 0; 569 570 case WSDISPLAYIO_GCURPOS: 571 return (*dcrf->ramdac_get_curpos)(dcrc, 572 (struct wsdisplay_curpos *)data); 573 574 case WSDISPLAYIO_SCURPOS: 575 return (*dcrf->ramdac_set_curpos)(dcrc, 576 (struct wsdisplay_curpos *)data); 577 578 case WSDISPLAYIO_GCURMAX: 579 return (*dcrf->ramdac_get_curmax)(dcrc, 580 (struct wsdisplay_curpos *)data); 581 582 case WSDISPLAYIO_GCURSOR: 583 return (*dcrf->ramdac_get_cursor)(dcrc, 584 (struct wsdisplay_cursor *)data); 585 586 case WSDISPLAYIO_SCURSOR: 587 return (*dcrf->ramdac_set_cursor)(dcrc, 588 (struct wsdisplay_cursor *)data); 589 590 case WSDISPLAYIO_LINEBYTES: 591 *(u_int *)data = dc->dc_rowbytes; 592 return 0; 593 594 /* PCI config read/write passthrough. */ 595 case PCI_IOC_CFGREAD: 596 case PCI_IOC_CFGWRITE: 597 return pci_devioctl(dc->dc_pc, dc->dc_pcitag, 598 cmd, data, flag, l); 599 } 600 return EPASSTHROUGH; 601 } 602 603 static int 604 tga_sched_update(void *v, void (*f)(void *)) 605 { 606 struct tga_devconfig *dc = v; 607 608 if (dc->dc_intrenabled) { 609 /* 610 * Arrange for f to be called at the next end-of-frame 611 * interrupt. 612 */ 613 dc->dc_ramdac_intr = f; 614 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 615 } else { 616 /* Spin until the end-of-frame, then call f */ 617 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 618 TGAREGWB(dc, TGA_REG_SISR, 1); 619 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 620 continue; 621 f(dc->dc_ramdac_cookie); 622 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 623 TGAREGWB(dc, TGA_REG_SISR, 1); 624 } 625 626 return 0; 627 } 628 629 static int 630 tga_intr(void *v) 631 { 632 struct tga_devconfig *dc = v; 633 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 634 635 uint32_t reg; 636 637 reg = TGARREG(dc, TGA_REG_SISR); 638 if (( reg & 0x00010001) != 0x00010001) { 639 /* Odd. We never set any of the other interrupt enables. */ 640 if ((reg & 0x1f) != 0) { 641 /* Clear the mysterious pending interrupts. */ 642 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 643 TGAREGWB(dc, TGA_REG_SISR, 1); 644 /* 645 * This was our interrupt, even if we're puzzled 646 * as to why we got it. Don't make the interrupt 647 * handler think it was a stray. 648 */ 649 return -1; 650 } else { 651 return 0; 652 } 653 } 654 /* if we have something to do, do it */ 655 if (dc->dc_ramdac_intr) { 656 dc->dc_ramdac_intr(dcrc); 657 dc->dc_ramdac_intr = NULL; 658 } 659 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 660 TGAREGWB(dc, TGA_REG_SISR, 1); 661 return 1; 662 } 663 664 paddr_t 665 tga_mmap(void *v, void *vs, off_t offset, int prot) 666 { 667 struct tga_softc *sc = v; 668 669 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 670 return -1; 671 672 return bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 673 offset, prot, BUS_SPACE_MAP_LINEAR); 674 } 675 676 static int 677 tga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 678 int *curxp, int *curyp, long *attrp) 679 { 680 struct tga_softc *sc = v; 681 long defattr; 682 683 if (sc->nscreens > 0) 684 return ENOMEM; 685 686 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 687 *curxp = 0; 688 *curyp = 0; 689 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 690 0, 0, 0, &defattr); 691 *attrp = defattr; 692 sc->nscreens++; 693 return 0; 694 } 695 696 static void 697 tga_free_screen(void *v, void *cookie) 698 { 699 struct tga_softc *sc = v; 700 701 if (sc->sc_dc == &tga_console_dc) 702 panic("tga_free_screen: console"); 703 704 sc->nscreens--; 705 } 706 707 static int 708 tga_show_screen(void *v, void *cookie, int waitok, 709 void (*cb)(void *, int, int), void *cbarg) 710 { 711 712 return 0; 713 } 714 715 int 716 tga_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 717 pci_chipset_tag_t pc, int bus, int device, int function) 718 { 719 struct tga_devconfig *dcp = &tga_console_dc; 720 long defattr; 721 722 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 723 724 /* sanity checks */ 725 if (dcp->dc_vaddr == 0) 726 panic("tga_console(%d, %d): couldn't map memory space", 727 device, function); 728 if (dcp->dc_tgaconf == NULL) 729 panic("tga_console(%d, %d): unknown board configuration", 730 device, function); 731 732 /* 733 * Initialize the RAMDAC but DO NOT allocate any private storage. 734 * Initialization includes disabling cursor, setting a sane 735 * colormap, etc. It will be reinitialized in tgaattach(). 736 */ 737 if (dcp->dc_tga2) { 738 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 739 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 740 tga2_ramdac_rd); 741 else 742 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 743 tga2_ramdac_rd, tga_getdotclock(dcp)); 744 } else { 745 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 746 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 747 tga_ramdac_rd); 748 else { 749 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 750 tga_bt463_rd); 751 } 752 } 753 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 754 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 755 756 return 0; 757 } 758 759 /* 760 * Functions to blank and unblank the display. 761 */ 762 static void 763 tga_blank(struct tga_devconfig *dc) 764 { 765 766 if (!dc->dc_blanked) { 767 dc->dc_blanked = 1; 768 /* XXX */ 769 TGAWREG(dc, TGA_REG_VVVR, 770 TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 771 } 772 } 773 774 static void 775 tga_unblank(struct tga_devconfig *dc) 776 { 777 778 if (dc->dc_blanked) { 779 dc->dc_blanked = 0; 780 /* XXX */ 781 TGAWREG(dc, TGA_REG_VVVR, 782 TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 783 } 784 } 785 786 /* 787 * Functions to manipulate the built-in cursor handing hardware. 788 */ 789 int 790 tga_builtin_set_cursor(struct tga_devconfig *dc, 791 struct wsdisplay_cursor *cursorp) 792 { 793 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 794 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 795 uint8_t image[512]; 796 u_int count, v; 797 int error; 798 799 v = cursorp->which; 800 if (v & WSDISPLAY_CURSOR_DOCMAP) { 801 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 802 if (error) 803 return error; 804 } 805 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 806 if ((u_int)cursorp->size.x != 64 || 807 (u_int)cursorp->size.y > 64) 808 return EINVAL; 809 /* The cursor is 2 bits deep, and there is no mask */ 810 count = (cursorp->size.y * 64 * 2) / NBBY; 811 error = copyin(cursorp->image, image, count); 812 if (error) 813 return error; 814 } 815 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 816 return EINVAL; 817 818 /* parameters are OK; do it */ 819 if (v & WSDISPLAY_CURSOR_DOCUR) { 820 if (cursorp->enable) 821 /* XXX */ 822 TGAWREG(dc, TGA_REG_VVVR, 823 TGARREG(dc, TGA_REG_VVVR) | 0x04); 824 else 825 /* XXX */ 826 TGAWREG(dc, TGA_REG_VVVR, 827 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 828 } 829 if (v & WSDISPLAY_CURSOR_DOPOS) { 830 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 831 (cursorp->pos.x & 0xfff)); 832 } 833 if (v & WSDISPLAY_CURSOR_DOCMAP) { 834 dcrf->ramdac_set_curcmap(dcrc, cursorp); 835 } 836 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 837 count = ((64 * 2) / NBBY) * cursorp->size.y; 838 TGAWREG(dc, TGA_REG_CCBR, 839 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 840 (cursorp->size.y << 10)); 841 memcpy((void *)(dc->dc_vaddr + 842 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 843 image, count); 844 } 845 return 0; 846 } 847 848 int 849 tga_builtin_get_cursor(struct tga_devconfig *dc, 850 struct wsdisplay_cursor *cursorp) 851 { 852 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 853 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 854 int count, error; 855 856 cursorp->which = WSDISPLAY_CURSOR_DOALL & 857 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 858 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 859 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 860 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 861 cursorp->size.x = 64; 862 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 863 864 if (cursorp->image != NULL) { 865 count = (cursorp->size.y * 64 * 2) / NBBY; 866 error = copyout((char *)(dc->dc_vaddr + 867 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 868 cursorp->image, count); 869 if (error) 870 return error; 871 /* No mask */ 872 } 873 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 874 return error; 875 } 876 877 int 878 tga_builtin_set_curpos(struct tga_devconfig *dc, 879 struct wsdisplay_curpos *curposp) 880 { 881 882 TGAWREG(dc, TGA_REG_CXYR, 883 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 884 return 0; 885 } 886 887 int 888 tga_builtin_get_curpos(struct tga_devconfig *dc, 889 struct wsdisplay_curpos *curposp) 890 { 891 892 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 893 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 894 return 0; 895 } 896 897 int 898 tga_builtin_get_curmax(struct tga_devconfig *dc, 899 struct wsdisplay_curpos *curposp) 900 { 901 902 curposp->x = curposp->y = 64; 903 return 0; 904 } 905 906 /* 907 * Copy columns (characters) in a row (line). 908 */ 909 static void 910 tga_copycols(void *id, int row, int srccol, int dstcol, int ncols) 911 { 912 struct rasops_info *ri = id; 913 int y, srcx, dstx, nx; 914 915 y = ri->ri_font->fontheight * row; 916 srcx = ri->ri_font->fontwidth * srccol; 917 dstx = ri->ri_font->fontwidth * dstcol; 918 nx = ri->ri_font->fontwidth * ncols; 919 920 tga_rop(ri, dstx, y, 921 nx, ri->ri_font->fontheight, RAS_SRC, 922 ri, srcx, y); 923 } 924 925 /* 926 * Copy rows (lines). 927 */ 928 static void 929 tga_copyrows(void *id, int srcrow, int dstrow, int nrows) 930 { 931 struct rasops_info *ri = id; 932 int srcy, dsty, ny; 933 934 srcy = ri->ri_font->fontheight * srcrow; 935 dsty = ri->ri_font->fontheight * dstrow; 936 ny = ri->ri_font->fontheight * nrows; 937 938 tga_rop(ri, 0, dsty, 939 ri->ri_emuwidth, ny, RAS_SRC, 940 ri, 0, srcy); 941 } 942 943 /* Do we need the src? */ 944 static const int needsrc[16] = 945 { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 946 947 /* A mapping between our API and the TGA card */ 948 static const int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 949 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 950 }; 951 952 /* 953 * Generic TGA raster op. 954 * This covers all possible raster ops, and 955 * clips the sizes and all of that. 956 */ 957 static int 958 tga_rop(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 959 struct rasops_info *src, int sx, int sy) 960 { 961 962 if (dst == NULL) 963 return -1; 964 if (needsrc[RAS_GETOP(rop)]) { 965 if (src == NULL) 966 return -1; /* We want a src */ 967 /* Clip against src */ 968 if (sx < 0) { 969 w += sx; 970 sx = 0; 971 } 972 if (sy < 0) { 973 h += sy; 974 sy = 0; 975 } 976 if (sx + w > src->ri_emuwidth) 977 w = src->ri_emuwidth - sx; 978 if (sy + h > src->ri_emuheight) 979 h = src->ri_emuheight - sy; 980 } else { 981 if (src != NULL) 982 return -1; /* We need no src */ 983 } 984 /* Clip against dst. We modify src regardless of using it, 985 * since it really doesn't matter. 986 */ 987 if (dx < 0) { 988 w += dx; 989 sx -= dx; 990 dx = 0; 991 } 992 if (dy < 0) { 993 h += dy; 994 sy -= dy; 995 dy = 0; 996 } 997 if (dx + w > dst->ri_emuwidth) 998 w = dst->ri_emuwidth - dx; 999 if (dy + h > dst->ri_emuheight) 1000 h = dst->ri_emuheight - dy; 1001 if (w <= 0 || h <= 0) 1002 return 0; /* Vacuously true; */ 1003 if (src == NULL) { 1004 /* XXX Punt! */ 1005 return -1; 1006 } 1007 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1008 } 1009 1010 1011 1012 /* 1013 * Video to Video raster ops. 1014 * This function deals with all raster ops that have a src and dst 1015 * that are on the card. 1016 */ 1017 static int 1018 tga_rop_vtov(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 1019 struct rasops_info *src, int sx, int sy) 1020 { 1021 struct tga_devconfig *dc = dst->ri_hw; 1022 int srcb, dstb, tga_srcb, tga_dstb; 1023 int x, y, wb; 1024 int xstart, xend, xdir; 1025 int ystart, yend, ydir, yinc; 1026 int xleft, lastx, lastleft; 1027 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1028 1029 /* 1030 * I don't yet want to deal with unaligned guys, really. And we don't 1031 * deal with copies from one card to another. 1032 */ 1033 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1034 /* XXX Punt! */ 1035 /* XXX should never happen, since it's only being used to 1036 * XXX copy 8-pixel-wide characters. 1037 */ 1038 return -1; 1039 } 1040 1041 srcb = sy * src->ri_stride + sx * (src->ri_depth / 8); 1042 dstb = dy * dst->ri_stride + dx * (dst->ri_depth / 8); 1043 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1044 (sx + src->ri_xorigin) * (src->ri_depth / 8); 1045 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1046 (dx + dst->ri_xorigin) * (dst->ri_depth / 8); 1047 1048 if (sy >= dy) { 1049 ystart = 0; 1050 yend = (h - 1) * dst->ri_stride; 1051 ydir = 1; 1052 } else { 1053 ystart = (h - 1) * dst->ri_stride; 1054 yend = 0; 1055 ydir = -1; 1056 } 1057 yinc = ydir * dst->ri_stride; 1058 1059 wb = w * (dst->ri_depth / 8); 1060 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1061 xstart = 0; 1062 xend = wb; 1063 xdir = 1; 1064 } else { /* copy backwards */ 1065 xstart = wb; 1066 xend = 0; 1067 xdir = -1; 1068 } 1069 1070 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1071 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1072 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1073 1074 /* 1075 * we have 3 sizes of pixels to move in X direction: 1076 * 4 * 64 (unrolled TGA ops) 1077 * 64 (single TGA op) 1078 * 4 (CPU, using long word) 1079 */ 1080 1081 if (xdir == 1) { /* move to the left */ 1082 1083 if (wb & ~63) 1084 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1085 /* 4 * 64 byte chunks */ 1086 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1087 x += 4 * 64, xleft -= 4 * 64) { 1088 1089 /* 1090 * XXX XXX Eight writes to different addresses 1091 * XXX XXX should fill up the write buffers on 1092 * XXX XXX 21064 and 21164 chips, but later 1093 * XXX XXX CPUs might have larger write buffers 1094 * XXX XXX which require further unrolling of 1095 * XXX XXX this loop, or the insertion of 1096 * XXX XXX memory barriers. 1097 */ 1098 TGAWALREG(dc, TGA_REG_GCSR, 0, 1099 tga_srcb + y + x + 0 * 64); 1100 TGAWALREG(dc, TGA_REG_GCDR, 0, 1101 tga_dstb + y + x + 0 * 64); 1102 TGAWALREG(dc, TGA_REG_GCSR, 1, 1103 tga_srcb + y + x + 1 * 64); 1104 TGAWALREG(dc, TGA_REG_GCDR, 1, 1105 tga_dstb + y + x + 1 * 64); 1106 TGAWALREG(dc, TGA_REG_GCSR, 2, 1107 tga_srcb + y + x + 2 * 64); 1108 TGAWALREG(dc, TGA_REG_GCDR, 2, 1109 tga_dstb + y + x + 2 * 64); 1110 TGAWALREG(dc, TGA_REG_GCSR, 3, 1111 tga_srcb + y + x + 3 * 64); 1112 TGAWALREG(dc, TGA_REG_GCDR, 3, 1113 tga_dstb + y + x + 3 * 64); 1114 } 1115 1116 /* 64 byte chunks */ 1117 for (; xleft >= 64; x += 64, xleft -= 64) { 1118 TGAWALREG(dc, TGA_REG_GCSR, 0, 1119 tga_srcb + y + x + 0 * 64); 1120 TGAWALREG(dc, TGA_REG_GCDR, 0, 1121 tga_dstb + y + x + 0 * 64); 1122 } 1123 } 1124 1125 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1126 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1127 1128 lastleft = wb & 63; 1129 if (lastleft) { 1130 lastx = xstart + (wb & ~63); 1131 for (y = ystart; (ydir * y) <= (ydir * yend); 1132 y += yinc) { 1133 /* 4 byte granularity */ 1134 for (x = lastx, xleft = lastleft; xleft >= 4; 1135 x += 4, xleft -= 4) { 1136 *(uint32_t *)(dst->ri_bits + dstb + 1137 y + x + 0 * 4) = 1138 *(uint32_t *)(dst->ri_bits + srcb + 1139 y + x + 0 * 4); 1140 } 1141 } 1142 } 1143 } else { /* above move to the left, below move to the right */ 1144 1145 if (wb & ~63) 1146 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1147 /* 4 * 64 byte chunks */ 1148 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1149 x -= 4 * 64, xleft -= 4 * 64) { 1150 1151 /* 1152 * XXX XXX Eight writes to different addresses 1153 * XXX XXX should fill up the write buffers on 1154 * XXX XXX 21064 and 21164 chips, but later 1155 * XXX XXX CPUs might have larger write buffers 1156 * XXX XXX which require further unrolling of 1157 * XXX XXX this loop, or the insertion of 1158 * XXX XXX memory barriers. 1159 */ 1160 TGAWALREG(dc, TGA_REG_GCSR, 0, 1161 tga_srcb + y + x - 1 * 64); 1162 TGAWALREG(dc, TGA_REG_GCDR, 0, 1163 tga_dstb + y + x - 1 * 64); 1164 TGAWALREG(dc, TGA_REG_GCSR, 1, 1165 tga_srcb + y + x - 2 * 64); 1166 TGAWALREG(dc, TGA_REG_GCDR, 1, 1167 tga_dstb + y + x - 2 * 64); 1168 TGAWALREG(dc, TGA_REG_GCSR, 2, 1169 tga_srcb + y + x - 3 * 64); 1170 TGAWALREG(dc, TGA_REG_GCDR, 2, 1171 tga_dstb + y + x - 3 * 64); 1172 TGAWALREG(dc, TGA_REG_GCSR, 3, 1173 tga_srcb + y + x - 4 * 64); 1174 TGAWALREG(dc, TGA_REG_GCDR, 3, 1175 tga_dstb + y + x - 4 * 64); 1176 } 1177 1178 /* 64 byte chunks */ 1179 for (; xleft >= 64; x -= 64, xleft -= 64) { 1180 TGAWALREG(dc, TGA_REG_GCSR, 0, 1181 tga_srcb + y + x - 1 * 64); 1182 TGAWALREG(dc, TGA_REG_GCDR, 0, 1183 tga_dstb + y + x - 1 * 64); 1184 } 1185 } 1186 1187 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1188 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1189 1190 lastleft = wb & 63; 1191 if (lastleft) { 1192 lastx = xstart - (wb & ~63); 1193 for (y = ystart; (ydir * y) <= (ydir * yend); 1194 y += yinc) { 1195 /* 4 byte granularity */ 1196 for (x = lastx, xleft = lastleft; xleft >= 4; 1197 x -= 4, xleft -= 4) { 1198 *(uint32_t *)(dst->ri_bits + dstb + 1199 y + x - 1 * 4) = 1200 *(uint32_t *)(dst->ri_bits + srcb + 1201 y + x - 1 * 4); 1202 } 1203 } 1204 } 1205 } 1206 return 0; 1207 } 1208 1209 1210 void tga_putchar(void *c, int row, int col, u_int uc, long attr) 1211 { 1212 struct rasops_info *ri = c; 1213 struct tga_devconfig *dc = ri->ri_hw; 1214 int fs, height, width; 1215 uint8_t *fr; 1216 int32_t *rp; 1217 1218 rp = (int32_t *)(ri->ri_bits + 1219 row * ri->ri_yscale + col * ri->ri_xscale); 1220 1221 height = ri->ri_font->fontheight; 1222 width = ri->ri_font->fontwidth; 1223 1224 uc -= ri->ri_font->firstchar; 1225 fr = (uint8_t *)ri->ri_font->data + uc * ri->ri_fontscale; 1226 fs = ri->ri_font->stride; 1227 1228 /* Set foreground and background color. XXX memoize this somehow? 1229 * The rasops code has already expanded the color entry to 32 bits 1230 * for us, even for 8-bit displays, so we don't have to do anything. 1231 */ 1232 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1233 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1234 1235 /* Set raster operation to "copy"... */ 1236 if (ri->ri_depth == 8) 1237 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1238 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1239 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1240 1241 /* Set which pixels we're drawing (of a possible 32). */ 1242 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1243 1244 /* Set drawing mode to opaque stipple. */ 1245 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1246 1247 /* Insert write barrier before actually sending data */ 1248 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1249 TGAREGWB(dc, TGA_REG_GMOR, 1); 1250 1251 while (height--) { 1252 /* The actual stipple write */ 1253 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1254 1255 fr += fs; 1256 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1257 } 1258 1259 /* Do underline */ 1260 if ((attr & 1) != 0) { 1261 rp = (int32_t *)((uint8_t *)rp - (ri->ri_stride << 1)); 1262 *rp = 0xffffffff; 1263 } 1264 1265 /* Set grapics mode back to normal. */ 1266 TGAWREG(dc, TGA_REG_GMOR, 0); 1267 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1268 } 1269 1270 static void 1271 tga_eraserows(void *c, int row, int num, long attr) 1272 { 1273 struct rasops_info *ri = c; 1274 struct tga_devconfig *dc = ri->ri_hw; 1275 int32_t color, lines, pixels; 1276 int32_t *rp; 1277 1278 color = ri->ri_devcmap[(attr >> 16) & 15]; 1279 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1280 lines = num * ri->ri_font->fontheight; 1281 pixels = ri->ri_emuwidth - 1; 1282 1283 /* Set fill color in block-color registers */ 1284 TGAWREG(dc, TGA_REG_GBCR0, color); 1285 TGAWREG(dc, TGA_REG_GBCR1, color); 1286 if (ri->ri_depth != 8) { 1287 TGAWREG(dc, TGA_REG_GBCR2, color); 1288 TGAWREG(dc, TGA_REG_GBCR3, color); 1289 TGAWREG(dc, TGA_REG_GBCR4, color); 1290 TGAWREG(dc, TGA_REG_GBCR5, color); 1291 TGAWREG(dc, TGA_REG_GBCR6, color); 1292 TGAWREG(dc, TGA_REG_GBCR7, color); 1293 } 1294 1295 /* Set raster operation to "copy"... */ 1296 if (ri->ri_depth == 8) 1297 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1298 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1299 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1300 1301 /* Set which pixels we're drawing (of a possible 32). */ 1302 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1303 1304 /* Set drawing mode to block fill. */ 1305 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1306 1307 /* Insert write barrier before actually sending data */ 1308 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1309 TGAREGWB(dc, TGA_REG_GMOR, 1); 1310 1311 while (lines--) { 1312 *rp = pixels; 1313 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1314 } 1315 1316 /* Set grapics mode back to normal. */ 1317 TGAWREG(dc, TGA_REG_GMOR, 0); 1318 } 1319 1320 static void 1321 tga_erasecols (void *c, int row, int col, int num, long attr) 1322 { 1323 struct rasops_info *ri = c; 1324 struct tga_devconfig *dc = ri->ri_hw; 1325 int32_t color, lines, pixels; 1326 int32_t *rp; 1327 1328 color = ri->ri_devcmap[(attr >> 16) & 15]; 1329 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1330 lines = ri->ri_font->fontheight; 1331 pixels = (num * ri->ri_font->fontwidth) - 1; 1332 1333 /* Set fill color in block-color registers */ 1334 TGAWREG(dc, TGA_REG_GBCR0, color); 1335 TGAWREG(dc, TGA_REG_GBCR1, color); 1336 if (ri->ri_depth != 8) { 1337 TGAWREG(dc, TGA_REG_GBCR2, color); 1338 TGAWREG(dc, TGA_REG_GBCR3, color); 1339 TGAWREG(dc, TGA_REG_GBCR4, color); 1340 TGAWREG(dc, TGA_REG_GBCR5, color); 1341 TGAWREG(dc, TGA_REG_GBCR6, color); 1342 TGAWREG(dc, TGA_REG_GBCR7, color); 1343 } 1344 1345 /* Set raster operation to "copy"... */ 1346 if (ri->ri_depth == 8) 1347 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1348 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1349 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1350 1351 /* Set which pixels we're drawing (of a possible 32). */ 1352 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1353 1354 /* Set drawing mode to block fill. */ 1355 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1356 1357 /* Insert write barrier before actually sending data */ 1358 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1359 TGAREGWB(dc, TGA_REG_GMOR, 1); 1360 1361 while (lines--) { 1362 *rp = pixels; 1363 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1364 } 1365 1366 /* Set grapics mode back to normal. */ 1367 TGAWREG(dc, TGA_REG_GMOR, 0); 1368 } 1369 1370 1371 static void 1372 tga_ramdac_wr(void *v, u_int btreg, uint8_t val) 1373 { 1374 struct tga_devconfig *dc = v; 1375 1376 if (btreg > BT485_REG_MAX) 1377 panic("tga_ramdac_wr: reg %d out of range", btreg); 1378 1379 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1380 TGAREGWB(dc, TGA_REG_EPDR, 1); 1381 } 1382 1383 static void 1384 tga2_ramdac_wr(void *v, u_int btreg, uint8_t val) 1385 { 1386 struct tga_devconfig *dc = v; 1387 bus_space_handle_t ramdac; 1388 1389 if (btreg > BT485_REG_MAX) 1390 panic("tga_ramdac_wr: reg %d out of range", btreg); 1391 1392 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1393 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1394 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1395 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1396 } 1397 1398 static uint8_t 1399 tga_bt463_rd(void *v, u_int btreg) 1400 { 1401 struct tga_devconfig *dc = v; 1402 tga_reg_t rdval; 1403 1404 /* 1405 * Strobe CE# (high->low->high) since status and data are latched on 1406 * the falling and rising edges (repsectively) of this active-low 1407 * signal. 1408 */ 1409 1410 TGAREGWB(dc, TGA_REG_EPSR, 1); 1411 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1412 TGAREGWB(dc, TGA_REG_EPSR, 1); 1413 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1414 1415 TGAREGRB(dc, TGA_REG_EPSR, 1); 1416 1417 rdval = TGARREG(dc, TGA_REG_EPDR); 1418 TGAREGWB(dc, TGA_REG_EPSR, 1); 1419 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1420 1421 return (rdval >> 16) & 0xff; 1422 } 1423 1424 static void 1425 tga_bt463_wr(void *v, u_int btreg, uint8_t val) 1426 { 1427 struct tga_devconfig *dc = v; 1428 1429 /* 1430 * In spite of the 21030 documentation, to set the MPU bus bits for 1431 * a write, you set them in the upper bits of EPDR, not EPSR. 1432 */ 1433 1434 /* 1435 * Strobe CE# (high->low->high) since status and data are latched on 1436 * the falling and rising edges of this active-low signal. 1437 */ 1438 1439 TGAREGWB(dc, TGA_REG_EPDR, 1); 1440 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1441 TGAREGWB(dc, TGA_REG_EPDR, 1); 1442 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1443 TGAREGWB(dc, TGA_REG_EPDR, 1); 1444 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1445 } 1446 1447 static uint8_t 1448 tga_ramdac_rd(void *v, u_int btreg) 1449 { 1450 struct tga_devconfig *dc = v; 1451 tga_reg_t rdval; 1452 1453 if (btreg > BT485_REG_MAX) 1454 panic("tga_ramdac_rd: reg %d out of range", btreg); 1455 1456 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1457 TGAREGWB(dc, TGA_REG_EPSR, 1); 1458 1459 rdval = TGARREG(dc, TGA_REG_EPDR); 1460 return (rdval >> 16) & 0xff; /* XXX */ 1461 } 1462 1463 static uint8_t 1464 tga2_ramdac_rd(void *v, u_int btreg) 1465 { 1466 struct tga_devconfig *dc = v; 1467 bus_space_handle_t ramdac; 1468 uint8_t retval; 1469 1470 if (btreg > BT485_REG_MAX) 1471 panic("tga_ramdac_rd: reg %d out of range", btreg); 1472 1473 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1474 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1475 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1476 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1477 return retval; 1478 } 1479 1480 #include <dev/ic/decmonitors.c> 1481 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1482 1483 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1484 1485 void 1486 tga2_init(struct tga_devconfig *dc) 1487 { 1488 struct monitor *m = tga_getmonitor(dc); 1489 1490 /* Deal with the dot clocks. 1491 */ 1492 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1493 /* 1494 * Set this up as a reference clock for the 1495 * ibm561's PLL. 1496 */ 1497 tga2_ics9110_wr(dc, 14300000); 1498 /* 1499 * XXX Can't set up the dotclock properly, until such time 1500 * as the RAMDAC is configured. 1501 */ 1502 } else { 1503 /* otherwise the ics9110 is our clock. */ 1504 tga2_ics9110_wr(dc, m->dotclock); 1505 } 1506 #if 0 1507 TGAWREG(dc, TGA_REG_VHCR, 1508 ((m->hbp / 4) << 21) | 1509 ((m->hsync / 4) << 14) | 1510 (((m->hfp - 4) / 4) << 9) | 1511 ((m->cols + 4) / 4)); 1512 #else 1513 TGAWREG(dc, TGA_REG_VHCR, 1514 ((m->hbp / 4) << 21) | 1515 ((m->hsync / 4) << 14) | 1516 (((m->hfp) / 4) << 9) | 1517 ((m->cols) / 4)); 1518 #endif 1519 TGAWREG(dc, TGA_REG_VVCR, 1520 (m->vbp << 22) | 1521 (m->vsync << 16) | 1522 (m->vfp << 11) | 1523 (m->rows)); 1524 TGAWREG(dc, TGA_REG_VVBR, 1); 1525 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1526 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1527 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1528 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1529 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1530 } 1531 1532 void 1533 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock) 1534 { 1535 bus_space_handle_t clock; 1536 uint32_t valU; 1537 int N, M, R, V, X; 1538 int i; 1539 1540 switch (dotclock) { 1541 case 130808000: 1542 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1543 case 119840000: 1544 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1545 case 108180000: 1546 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1547 case 103994000: 1548 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1549 case 175000000: 1550 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1551 case 75000000: 1552 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1553 case 74000000: 1554 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1555 case 69000000: 1556 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1557 case 65000000: 1558 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1559 case 50000000: 1560 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1561 case 40000000: 1562 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1563 case 31500000: 1564 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1565 case 25175000: 1566 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1567 case 135000000: 1568 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1569 case 110000000: 1570 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1571 case 202500000: 1572 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1573 case 14300000: /* this one is just a ref clock */ 1574 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1575 default: 1576 panic("unrecognized clock rate %d", dotclock); 1577 } 1578 1579 /* XXX -- hard coded, bad */ 1580 valU = N | ( M << 7 ) | (V << 14); 1581 valU |= (X << 15) | (R << 17); 1582 valU |= 0x17 << 19; 1583 1584 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1585 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1586 1587 for (i = 24; i > 0; i--) { 1588 uint32_t writeval; 1589 1590 writeval = valU & 0x1; 1591 if (i == 1) 1592 writeval |= 0x2; 1593 valU >>= 1; 1594 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1595 bus_space_barrier(dc->dc_memt, clock, 0, 4, 1596 BUS_SPACE_BARRIER_WRITE); 1597 } 1598 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1599 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1600 &clock); /* XXX */ 1601 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1602 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1603 } 1604 1605 struct monitor * 1606 tga_getmonitor(struct tga_devconfig *dc) 1607 { 1608 1609 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1610 } 1611 1612 unsigned int 1613 tga_getdotclock(struct tga_devconfig *dc) 1614 { 1615 1616 return tga_getmonitor(dc)->dotclock; 1617 } 1618
Indexes created Mon Sep 22 13:09:51 GMT 2025