tga.c revision 1.83
1 /* $NetBSD: tga.c,v 1.83 2012/01/11 20:50:00 macallan Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.83 2012/01/11 20:50:00 macallan Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/pci/wsdisplay_pci.h> 62 63 int tgamatch(device_t, cfdata_t, void *); 64 void tgaattach(device_t, device_t, void *); 65 int tgaprint(void *, const char *); 66 67 CFATTACH_DECL_NEW(tga, sizeof(struct tga_softc), 68 tgamatch, tgaattach, NULL, NULL); 69 70 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 71 pcitag_t tag, struct tga_devconfig *dc); 72 73 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 74 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 75 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 76 unsigned int tga_getdotclock(struct tga_devconfig *dc); 77 78 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 79 paddr_t tga_mmap(void *, void *, off_t, int); 80 static void tga_copyrows(void *, int, int, int); 81 static void tga_copycols(void *, int, int, int, int); 82 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 83 void **, int *, int *, long *); 84 static void tga_free_screen(void *, void *); 85 static int tga_show_screen(void *, void *, int, 86 void (*) (void *, int, int), void *); 87 static int tga_rop(struct rasops_info *, int, int, int, int, int, 88 struct rasops_info *, int, int); 89 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 90 int, struct rasops_info *, int, int); 91 static void tga_putchar(void *c, int row, int col, u_int uc, long attr); 92 static void tga_eraserows(void *, int, int, long); 93 static void tga_erasecols(void *, int, int, int, long); 94 void tga2_init(struct tga_devconfig *); 95 96 static void tga_config_interrupts(device_t); 97 98 /* RAMDAC interface functions */ 99 static int tga_sched_update(void *, void (*)(void *)); 100 static void tga_ramdac_wr(void *, u_int, uint8_t); 101 static uint8_t tga_ramdac_rd(void *, u_int); 102 static void tga_bt463_wr(void *, u_int, uint8_t); 103 static uint8_t tga_bt463_rd(void *, u_int); 104 static void tga2_ramdac_wr(void *, u_int, uint8_t); 105 static uint8_t tga2_ramdac_rd(void *, u_int); 106 107 /* Interrupt handler */ 108 static int tga_intr(void *); 109 110 struct tga_devconfig tga_console_dc; 111 112 /* The NULL entries will get filled in by rasops_init(). 113 * XXX and the non-NULL ones will be overwritten; reset after calling it. 114 */ 115 struct wsdisplay_emulops tga_emulops = { 116 NULL, 117 NULL, 118 tga_putchar, 119 tga_copycols, 120 tga_erasecols, 121 tga_copyrows, 122 tga_eraserows, 123 NULL, 124 NULL, 125 }; 126 127 struct wsscreen_descr tga_stdscreen = { 128 "std", 129 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 130 &tga_emulops, 131 0, 0, 132 WSSCREEN_REVERSE, 133 NULL, 134 }; 135 136 const struct wsscreen_descr *_tga_scrlist[] = { 137 &tga_stdscreen, 138 /* XXX other formats, graphics screen? */ 139 }; 140 141 struct wsscreen_list tga_screenlist = { 142 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 143 }; 144 145 struct wsdisplay_accessops tga_accessops = { 146 tga_ioctl, 147 tga_mmap, 148 tga_alloc_screen, 149 tga_free_screen, 150 tga_show_screen, 151 NULL, /* load_font */ 152 NULL, 153 NULL, 154 }; 155 156 static void tga_blank(struct tga_devconfig *); 157 static void tga_unblank(struct tga_devconfig *); 158 159 int 160 tga_cnmatch(bus_space_tag_t iot, bus_space_tag_t memt, 161 pci_chipset_tag_t pc, pcitag_t tag) 162 { 163 164 return tga_matchcommon(memt, pc, tag); 165 } 166 167 int 168 tgamatch(device_t parent, cfdata_t match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 173 return (0); 174 175 switch (PCI_PRODUCT(pa->pa_id)) { 176 case PCI_PRODUCT_DEC_21030: 177 case PCI_PRODUCT_DEC_PBXGB: 178 break; 179 default: 180 return 0; 181 } 182 183 #if defined(__alpha__) || defined(arc) 184 /* short-circuit the following test, as we 185 * already have the memory mapped and hence 186 * cannot perform it---and we are the console 187 * anyway. 188 */ 189 if (pa->pa_tag == tga_console_dc.dc_pcitag) 190 return 10; 191 #endif 192 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 193 } 194 195 static int 196 tga_matchcommon(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 197 { 198 struct tga_devconfig tmp_dc; 199 struct tga_devconfig *dc = &tmp_dc; 200 bus_size_t pcisize; 201 202 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 203 dc->dc_tga_type = tga_identify(dc); 204 205 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 206 bus_space_unmap(memt, dc->dc_memh, pcisize); 207 if (dc->dc_tgaconf) 208 return 10; 209 return 0; 210 } 211 212 static void 213 tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 214 bus_size_t *pcisize, struct tga_devconfig *dc) 215 { 216 int flags; 217 218 dc->dc_memt = memt; 219 dc->dc_tgaconf = NULL; 220 221 /* XXX magic number */ 222 if (pci_mapreg_info(pc, tag, 0x10, 223 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 224 &dc->dc_pcipaddr, pcisize, &flags)) 225 panic("tga_mapaddrs: pci_mapreg_info() failed"); 226 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 227 panic("tga memory not prefetchable"); 228 229 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 230 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 231 panic("tga_mapaddrs: could not map TGA address space"); 232 dc->dc_vaddr = (vaddr_t)bus_space_vaddr(memt, dc->dc_memh); 233 234 bus_space_subregion(dc->dc_memt, dc->dc_memh, 235 TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs); 236 } 237 238 static void 239 tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 240 struct tga_devconfig *dc) 241 { 242 const struct tga_conf *tgac; 243 struct rasops_info *rip; 244 int cookie; 245 bus_size_t pcisize; 246 int i; 247 248 dc->dc_pc = pc; 249 dc->dc_pcitag = tag; 250 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 251 dc->dc_tga_type = tga_identify(dc); 252 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 253 #if 0 254 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 255 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 256 panic("tga_init: memory size mismatch?"); 257 #endif 258 259 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 260 case 0x01: 261 case 0x02: 262 case 0x03: 263 case 0x04: 264 dc->dc_tga2 = 0; 265 break; 266 case 0x20: 267 case 0x21: 268 case 0x22: 269 dc->dc_tga2 = 1; 270 break; 271 default: 272 panic("tga_init: TGA Revision not recognized"); 273 } 274 275 if (dc->dc_tga2) 276 tga2_init(dc); 277 278 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 279 case 0: 280 dc->dc_wid = 8192; 281 break; 282 283 case 1: 284 dc->dc_wid = 8196; 285 break; 286 287 default: 288 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 289 break; 290 } 291 292 /* 293 * XXX XXX Turning off "odd" shouldn't be necessary, 294 * XXX XXX but I can't make X work with the weird size. 295 */ 296 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 297 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 298 TGAWREG(dc, TGA_REG_VHCR, 299 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 300 dc->dc_wid -= 4; 301 } 302 303 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 304 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 305 306 /* XXX this seems to be what DEC does */ 307 TGAWREG(dc, TGA_REG_CCBR, 0); 308 TGAWREG(dc, TGA_REG_VVBR, 1); 309 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 310 1 * tgac->tgac_vvbr_units; 311 dc->dc_blanked = 1; 312 tga_unblank(dc); 313 314 /* 315 * Set all bits in the pixel mask, to enable writes to all pixels. 316 * It seems that the console firmware clears some of them 317 * under some circumstances, which causes cute vertical stripes. 318 */ 319 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 320 321 /* clear the screen */ 322 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(uint32_t)) 323 *(uint32_t *)(dc->dc_videobase + i) = 0; 324 325 /* Initialize rasops descriptor */ 326 rip = &dc->dc_rinfo; 327 rip->ri_flg = RI_CENTER; 328 rip->ri_depth = tgac->tgac_phys_depth; 329 rip->ri_bits = (void *)dc->dc_videobase; 330 rip->ri_width = dc->dc_wid; 331 rip->ri_height = dc->dc_ht; 332 rip->ri_stride = dc->dc_rowbytes; 333 rip->ri_hw = dc; 334 if (dc == &tga_console_dc) 335 rip->ri_flg |= RI_NO_AUTO; 336 337 if (tgac->tgac_phys_depth == 32) { 338 rip->ri_rnum = 8; 339 rip->ri_gnum = 8; 340 rip->ri_bnum = 8; 341 rip->ri_rpos = 16; 342 rip->ri_gpos = 8; 343 rip->ri_bpos = 0; 344 } 345 346 wsfont_init(); 347 /* prefer 8 pixel wide font */ 348 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 349 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 350 if (cookie <= 0) 351 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 352 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 353 if (cookie <= 0) { 354 printf("tga: no appropriate fonts.\n"); 355 return; 356 } 357 358 /* the accelerated tga_putchar() needs LSbit left */ 359 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 360 printf("tga: couldn't lock font\n"); 361 return; 362 } 363 dc->dc_rinfo.ri_wsfcookie = cookie; 364 365 rasops_init(rip, 34, 80); 366 367 /* add our accelerated functions */ 368 /* XXX shouldn't have to do this; rasops should leave non-NULL 369 * XXX entries alone. 370 */ 371 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 372 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 373 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 374 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 375 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 376 377 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 378 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 379 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 380 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 381 382 383 dc->dc_intrenabled = 0; 384 } 385 386 void 387 tgaattach(device_t parent, device_t self, void *aux) 388 { 389 struct pci_attach_args *pa = aux; 390 struct tga_softc *sc = device_private(self); 391 struct tga_devconfig *dc; 392 struct wsemuldisplaydev_attach_args aa; 393 pci_intr_handle_t intrh; 394 const char *intrstr; 395 uint8_t rev; 396 int console; 397 398 sc->sc_dev = self; 399 400 #if defined(__alpha__) || defined(arc) 401 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 402 #else 403 console = 0; 404 #endif 405 if (console) { 406 sc->sc_dc = &tga_console_dc; 407 sc->sc_dc->dc_rinfo.ri_flg &= ~RI_NO_AUTO; 408 sc->nscreens = 1; 409 } else { 410 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 411 M_WAITOK|M_ZERO); 412 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 413 } 414 if (sc->sc_dc->dc_vaddr == 0) { 415 aprint_error(": couldn't map memory space; punt!\n"); 416 return; 417 } 418 419 /* XXX say what's going on. */ 420 intrstr = NULL; 421 if (pci_intr_map(pa, &intrh)) { 422 aprint_error(": couldn't map interrupt"); 423 return; 424 } 425 intrstr = pci_intr_string(pa->pa_pc, intrh); 426 sc->sc_intr = pci_intr_establish(pa->pa_pc, intrh, IPL_TTY, tga_intr, 427 sc->sc_dc); 428 if (sc->sc_intr == NULL) { 429 aprint_error(": couldn't establish interrupt"); 430 if (intrstr != NULL) 431 aprint_error("at %s", intrstr); 432 aprint_error("\n"); 433 return; 434 } 435 436 rev = PCI_REVISION(pa->pa_class); 437 switch (rev) { 438 case 0x1: 439 case 0x2: 440 case 0x3: 441 aprint_normal(": DC21030 step %c", 'A' + rev - 1); 442 break; 443 case 0x20: 444 aprint_normal(": TGA2 abstract software model"); 445 break; 446 case 0x21: 447 case 0x22: 448 aprint_normal(": TGA2 pass %d", rev - 0x20); 449 break; 450 451 default: 452 aprint_normal("unknown stepping (0x%x)", rev); 453 break; 454 } 455 aprint_normal(", "); 456 457 /* 458 * Get RAMDAC function vectors and call the RAMDAC functions 459 * to allocate its private storage and pass that back to us. 460 */ 461 462 dc = sc->sc_dc; 463 dc->dc_ramdac_funcs = dc->dc_tgaconf->ramdac_funcs(); 464 if (!dc->dc_tga2) { 465 if (dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 466 dc->dc_ramdac_cookie = 467 dc->dc_ramdac_funcs->ramdac_register(dc, 468 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 469 else 470 dc->dc_ramdac_cookie = 471 dc->dc_ramdac_funcs->ramdac_register(dc, 472 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 473 } else { 474 dc->dc_ramdac_cookie = dc->dc_ramdac_funcs->ramdac_register(dc, 475 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 476 477 /* XXX this is a bit of a hack, setting the dotclock here */ 478 if (dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 479 (*dc->dc_ramdac_funcs->ramdac_set_dotclock) 480 (dc->dc_ramdac_cookie, tga_getdotclock(dc)); 481 } 482 483 /* 484 * Initialize the RAMDAC. Initialization includes disabling 485 * cursor, setting a sane colormap, etc. We presume that we've 486 * filled in the necessary dot clock for PowerStorm 4d20. 487 */ 488 (*dc->dc_ramdac_funcs->ramdac_init)(dc->dc_ramdac_cookie); 489 TGAWREG(dc, TGA_REG_SISR, 0x00000001); /* XXX */ 490 491 if (dc->dc_tgaconf == NULL) { 492 aprint_error("unknown board configuration\n"); 493 return; 494 } 495 aprint_normal("board type %s\n", dc->dc_tgaconf->tgac_name); 496 aprint_normal_dev(self, "%d x %d, %dbpp, %s RAMDAC\n", 497 dc->dc_wid, dc->dc_ht, 498 dc->dc_tgaconf->tgac_phys_depth, 499 dc->dc_ramdac_funcs->ramdac_name); 500 501 if (intrstr != NULL) 502 aprint_normal_dev(self, "interrupting at %s\n", 503 intrstr); 504 505 aa.console = console; 506 aa.scrdata = &tga_screenlist; 507 aa.accessops = &tga_accessops; 508 aa.accesscookie = sc; 509 510 config_found(self, &aa, wsemuldisplaydevprint); 511 512 config_interrupts(self, tga_config_interrupts); 513 } 514 515 static void 516 tga_config_interrupts(device_t self) 517 { 518 struct tga_softc *sc; 519 520 sc = device_private(self); 521 sc->sc_dc->dc_intrenabled = 1; 522 } 523 524 int 525 tga_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 526 { 527 struct tga_softc *sc = v; 528 struct tga_devconfig *dc = sc->sc_dc; 529 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 530 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 531 532 switch (cmd) { 533 case WSDISPLAYIO_GTYPE: 534 *(u_int *)data = WSDISPLAY_TYPE_TGA; 535 return 0; 536 537 case WSDISPLAYIO_GINFO: 538 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 539 wsd_fbip->height = sc->sc_dc->dc_ht; 540 wsd_fbip->width = sc->sc_dc->dc_wid; 541 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 542 #if 0 543 wsd_fbip->cmsize = 256; /* XXX ??? */ 544 #else 545 wsd_fbip->cmsize = 1024; /* XXX ??? */ 546 #endif 547 #undef wsd_fbip 548 return 0; 549 550 case WSDISPLAYIO_GETCMAP: 551 return (*dcrf->ramdac_get_cmap)(dcrc, 552 (struct wsdisplay_cmap *)data); 553 554 case WSDISPLAYIO_PUTCMAP: 555 return (*dcrf->ramdac_set_cmap)(dcrc, 556 (struct wsdisplay_cmap *)data); 557 558 case WSDISPLAYIO_SVIDEO: 559 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 560 tga_blank(sc->sc_dc); 561 else 562 tga_unblank(sc->sc_dc); 563 return 0; 564 565 case WSDISPLAYIO_GVIDEO: 566 *(u_int *)data = dc->dc_blanked ? 567 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 568 return 0; 569 570 case WSDISPLAYIO_GCURPOS: 571 return (*dcrf->ramdac_get_curpos)(dcrc, 572 (struct wsdisplay_curpos *)data); 573 574 case WSDISPLAYIO_SCURPOS: 575 return (*dcrf->ramdac_set_curpos)(dcrc, 576 (struct wsdisplay_curpos *)data); 577 578 case WSDISPLAYIO_GCURMAX: 579 return (*dcrf->ramdac_get_curmax)(dcrc, 580 (struct wsdisplay_curpos *)data); 581 582 case WSDISPLAYIO_GCURSOR: 583 return (*dcrf->ramdac_get_cursor)(dcrc, 584 (struct wsdisplay_cursor *)data); 585 586 case WSDISPLAYIO_SCURSOR: 587 return (*dcrf->ramdac_set_cursor)(dcrc, 588 (struct wsdisplay_cursor *)data); 589 590 case WSDISPLAYIO_LINEBYTES: 591 *(u_int *)data = dc->dc_rowbytes; 592 return 0; 593 594 /* PCI config read/write passthrough. */ 595 case PCI_IOC_CFGREAD: 596 case PCI_IOC_CFGWRITE: 597 return pci_devioctl(dc->dc_pc, dc->dc_pcitag, 598 cmd, data, flag, l); 599 600 case WSDISPLAYIO_GET_BUSID: 601 return wsdisplayio_busid_pci(sc->sc_dev, dc->dc_pc, 602 dc->dc_pcitag, data); 603 } 604 return EPASSTHROUGH; 605 } 606 607 static int 608 tga_sched_update(void *v, void (*f)(void *)) 609 { 610 struct tga_devconfig *dc = v; 611 612 if (dc->dc_intrenabled) { 613 /* 614 * Arrange for f to be called at the next end-of-frame 615 * interrupt. 616 */ 617 dc->dc_ramdac_intr = f; 618 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 619 } else { 620 /* Spin until the end-of-frame, then call f */ 621 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 622 TGAREGWB(dc, TGA_REG_SISR, 1); 623 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 624 continue; 625 f(dc->dc_ramdac_cookie); 626 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 627 TGAREGWB(dc, TGA_REG_SISR, 1); 628 } 629 630 return 0; 631 } 632 633 static int 634 tga_intr(void *v) 635 { 636 struct tga_devconfig *dc = v; 637 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 638 639 uint32_t reg; 640 641 reg = TGARREG(dc, TGA_REG_SISR); 642 if (( reg & 0x00010001) != 0x00010001) { 643 /* Odd. We never set any of the other interrupt enables. */ 644 if ((reg & 0x1f) != 0) { 645 /* Clear the mysterious pending interrupts. */ 646 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 647 TGAREGWB(dc, TGA_REG_SISR, 1); 648 /* 649 * This was our interrupt, even if we're puzzled 650 * as to why we got it. Don't make the interrupt 651 * handler think it was a stray. 652 */ 653 return -1; 654 } else { 655 return 0; 656 } 657 } 658 /* if we have something to do, do it */ 659 if (dc->dc_ramdac_intr) { 660 dc->dc_ramdac_intr(dcrc); 661 dc->dc_ramdac_intr = NULL; 662 } 663 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 664 TGAREGWB(dc, TGA_REG_SISR, 1); 665 return 1; 666 } 667 668 paddr_t 669 tga_mmap(void *v, void *vs, off_t offset, int prot) 670 { 671 struct tga_softc *sc = v; 672 673 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 674 return -1; 675 676 return bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 677 offset, prot, BUS_SPACE_MAP_LINEAR); 678 } 679 680 static int 681 tga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 682 int *curxp, int *curyp, long *attrp) 683 { 684 struct tga_softc *sc = v; 685 long defattr; 686 687 if (sc->nscreens > 0) 688 return ENOMEM; 689 690 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 691 *curxp = 0; 692 *curyp = 0; 693 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 694 0, 0, 0, &defattr); 695 *attrp = defattr; 696 sc->nscreens++; 697 return 0; 698 } 699 700 static void 701 tga_free_screen(void *v, void *cookie) 702 { 703 struct tga_softc *sc = v; 704 705 if (sc->sc_dc == &tga_console_dc) 706 panic("tga_free_screen: console"); 707 708 sc->nscreens--; 709 } 710 711 static int 712 tga_show_screen(void *v, void *cookie, int waitok, 713 void (*cb)(void *, int, int), void *cbarg) 714 { 715 716 return 0; 717 } 718 719 int 720 tga_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 721 pci_chipset_tag_t pc, int bus, int device, int function) 722 { 723 struct tga_devconfig *dcp = &tga_console_dc; 724 long defattr; 725 726 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 727 728 /* sanity checks */ 729 if (dcp->dc_vaddr == 0) 730 panic("tga_console(%d, %d): couldn't map memory space", 731 device, function); 732 if (dcp->dc_tgaconf == NULL) 733 panic("tga_console(%d, %d): unknown board configuration", 734 device, function); 735 736 /* 737 * Initialize the RAMDAC but DO NOT allocate any private storage. 738 * Initialization includes disabling cursor, setting a sane 739 * colormap, etc. It will be reinitialized in tgaattach(). 740 */ 741 if (dcp->dc_tga2) { 742 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 743 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 744 tga2_ramdac_rd); 745 else 746 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 747 tga2_ramdac_rd, tga_getdotclock(dcp)); 748 } else { 749 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 750 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 751 tga_ramdac_rd); 752 else { 753 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 754 tga_bt463_rd); 755 } 756 } 757 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 758 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 759 760 return 0; 761 } 762 763 /* 764 * Functions to blank and unblank the display. 765 */ 766 static void 767 tga_blank(struct tga_devconfig *dc) 768 { 769 770 if (!dc->dc_blanked) { 771 dc->dc_blanked = 1; 772 /* XXX */ 773 TGAWREG(dc, TGA_REG_VVVR, 774 TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 775 } 776 } 777 778 static void 779 tga_unblank(struct tga_devconfig *dc) 780 { 781 782 if (dc->dc_blanked) { 783 dc->dc_blanked = 0; 784 /* XXX */ 785 TGAWREG(dc, TGA_REG_VVVR, 786 TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 787 } 788 } 789 790 /* 791 * Functions to manipulate the built-in cursor handing hardware. 792 */ 793 int 794 tga_builtin_set_cursor(struct tga_devconfig *dc, 795 struct wsdisplay_cursor *cursorp) 796 { 797 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 798 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 799 uint8_t image[512]; 800 u_int count, v; 801 int error; 802 803 v = cursorp->which; 804 if (v & WSDISPLAY_CURSOR_DOCMAP) { 805 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 806 if (error) 807 return error; 808 } 809 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 810 if ((u_int)cursorp->size.x != 64 || 811 (u_int)cursorp->size.y > 64) 812 return EINVAL; 813 /* The cursor is 2 bits deep, and there is no mask */ 814 count = (cursorp->size.y * 64 * 2) / NBBY; 815 error = copyin(cursorp->image, image, count); 816 if (error) 817 return error; 818 } 819 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 820 return EINVAL; 821 822 /* parameters are OK; do it */ 823 if (v & WSDISPLAY_CURSOR_DOCUR) { 824 if (cursorp->enable) 825 /* XXX */ 826 TGAWREG(dc, TGA_REG_VVVR, 827 TGARREG(dc, TGA_REG_VVVR) | 0x04); 828 else 829 /* XXX */ 830 TGAWREG(dc, TGA_REG_VVVR, 831 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 832 } 833 if (v & WSDISPLAY_CURSOR_DOPOS) { 834 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 835 (cursorp->pos.x & 0xfff)); 836 } 837 if (v & WSDISPLAY_CURSOR_DOCMAP) { 838 dcrf->ramdac_set_curcmap(dcrc, cursorp); 839 } 840 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 841 count = ((64 * 2) / NBBY) * cursorp->size.y; 842 TGAWREG(dc, TGA_REG_CCBR, 843 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 844 (cursorp->size.y << 10)); 845 memcpy((void *)(dc->dc_vaddr + 846 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 847 image, count); 848 } 849 return 0; 850 } 851 852 int 853 tga_builtin_get_cursor(struct tga_devconfig *dc, 854 struct wsdisplay_cursor *cursorp) 855 { 856 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 857 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 858 int count, error; 859 860 cursorp->which = WSDISPLAY_CURSOR_DOALL & 861 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 862 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 863 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 864 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 865 cursorp->size.x = 64; 866 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 867 868 if (cursorp->image != NULL) { 869 count = (cursorp->size.y * 64 * 2) / NBBY; 870 error = copyout((char *)(dc->dc_vaddr + 871 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 872 cursorp->image, count); 873 if (error) 874 return error; 875 /* No mask */ 876 } 877 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 878 return error; 879 } 880 881 int 882 tga_builtin_set_curpos(struct tga_devconfig *dc, 883 struct wsdisplay_curpos *curposp) 884 { 885 886 TGAWREG(dc, TGA_REG_CXYR, 887 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 888 return 0; 889 } 890 891 int 892 tga_builtin_get_curpos(struct tga_devconfig *dc, 893 struct wsdisplay_curpos *curposp) 894 { 895 896 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 897 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 898 return 0; 899 } 900 901 int 902 tga_builtin_get_curmax(struct tga_devconfig *dc, 903 struct wsdisplay_curpos *curposp) 904 { 905 906 curposp->x = curposp->y = 64; 907 return 0; 908 } 909 910 /* 911 * Copy columns (characters) in a row (line). 912 */ 913 static void 914 tga_copycols(void *id, int row, int srccol, int dstcol, int ncols) 915 { 916 struct rasops_info *ri = id; 917 int y, srcx, dstx, nx; 918 919 y = ri->ri_font->fontheight * row; 920 srcx = ri->ri_font->fontwidth * srccol; 921 dstx = ri->ri_font->fontwidth * dstcol; 922 nx = ri->ri_font->fontwidth * ncols; 923 924 tga_rop(ri, dstx, y, 925 nx, ri->ri_font->fontheight, RAS_SRC, 926 ri, srcx, y); 927 } 928 929 /* 930 * Copy rows (lines). 931 */ 932 static void 933 tga_copyrows(void *id, int srcrow, int dstrow, int nrows) 934 { 935 struct rasops_info *ri = id; 936 int srcy, dsty, ny; 937 938 srcy = ri->ri_font->fontheight * srcrow; 939 dsty = ri->ri_font->fontheight * dstrow; 940 ny = ri->ri_font->fontheight * nrows; 941 942 tga_rop(ri, 0, dsty, 943 ri->ri_emuwidth, ny, RAS_SRC, 944 ri, 0, srcy); 945 } 946 947 /* Do we need the src? */ 948 static const int needsrc[16] = 949 { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 950 951 /* A mapping between our API and the TGA card */ 952 static const int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 953 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 954 }; 955 956 /* 957 * Generic TGA raster op. 958 * This covers all possible raster ops, and 959 * clips the sizes and all of that. 960 */ 961 static int 962 tga_rop(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 963 struct rasops_info *src, int sx, int sy) 964 { 965 966 if (dst == NULL) 967 return -1; 968 if (needsrc[RAS_GETOP(rop)]) { 969 if (src == NULL) 970 return -1; /* We want a src */ 971 /* Clip against src */ 972 if (sx < 0) { 973 w += sx; 974 sx = 0; 975 } 976 if (sy < 0) { 977 h += sy; 978 sy = 0; 979 } 980 if (sx + w > src->ri_emuwidth) 981 w = src->ri_emuwidth - sx; 982 if (sy + h > src->ri_emuheight) 983 h = src->ri_emuheight - sy; 984 } else { 985 if (src != NULL) 986 return -1; /* We need no src */ 987 } 988 /* Clip against dst. We modify src regardless of using it, 989 * since it really doesn't matter. 990 */ 991 if (dx < 0) { 992 w += dx; 993 sx -= dx; 994 dx = 0; 995 } 996 if (dy < 0) { 997 h += dy; 998 sy -= dy; 999 dy = 0; 1000 } 1001 if (dx + w > dst->ri_emuwidth) 1002 w = dst->ri_emuwidth - dx; 1003 if (dy + h > dst->ri_emuheight) 1004 h = dst->ri_emuheight - dy; 1005 if (w <= 0 || h <= 0) 1006 return 0; /* Vacuously true; */ 1007 if (src == NULL) { 1008 /* XXX Punt! */ 1009 return -1; 1010 } 1011 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1012 } 1013 1014 1015 1016 /* 1017 * Video to Video raster ops. 1018 * This function deals with all raster ops that have a src and dst 1019 * that are on the card. 1020 */ 1021 static int 1022 tga_rop_vtov(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 1023 struct rasops_info *src, int sx, int sy) 1024 { 1025 struct tga_devconfig *dc = dst->ri_hw; 1026 int srcb, dstb, tga_srcb, tga_dstb; 1027 int x, y, wb; 1028 int xstart, xend, xdir; 1029 int ystart, yend, ydir, yinc; 1030 int xleft, lastx, lastleft; 1031 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1032 1033 /* 1034 * I don't yet want to deal with unaligned guys, really. And we don't 1035 * deal with copies from one card to another. 1036 */ 1037 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1038 /* XXX Punt! */ 1039 /* XXX should never happen, since it's only being used to 1040 * XXX copy 8-pixel-wide characters. 1041 */ 1042 return -1; 1043 } 1044 1045 srcb = sy * src->ri_stride + sx * (src->ri_depth / 8); 1046 dstb = dy * dst->ri_stride + dx * (dst->ri_depth / 8); 1047 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1048 (sx + src->ri_xorigin) * (src->ri_depth / 8); 1049 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1050 (dx + dst->ri_xorigin) * (dst->ri_depth / 8); 1051 1052 if (sy >= dy) { 1053 ystart = 0; 1054 yend = (h - 1) * dst->ri_stride; 1055 ydir = 1; 1056 } else { 1057 ystart = (h - 1) * dst->ri_stride; 1058 yend = 0; 1059 ydir = -1; 1060 } 1061 yinc = ydir * dst->ri_stride; 1062 1063 wb = w * (dst->ri_depth / 8); 1064 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1065 xstart = 0; 1066 xend = wb; 1067 xdir = 1; 1068 } else { /* copy backwards */ 1069 xstart = wb; 1070 xend = 0; 1071 xdir = -1; 1072 } 1073 1074 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1075 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1076 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1077 1078 /* 1079 * we have 3 sizes of pixels to move in X direction: 1080 * 4 * 64 (unrolled TGA ops) 1081 * 64 (single TGA op) 1082 * 4 (CPU, using long word) 1083 */ 1084 1085 if (xdir == 1) { /* move to the left */ 1086 1087 if (wb & ~63) 1088 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1089 /* 4 * 64 byte chunks */ 1090 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1091 x += 4 * 64, xleft -= 4 * 64) { 1092 1093 /* 1094 * XXX XXX Eight writes to different addresses 1095 * XXX XXX should fill up the write buffers on 1096 * XXX XXX 21064 and 21164 chips, but later 1097 * XXX XXX CPUs might have larger write buffers 1098 * XXX XXX which require further unrolling of 1099 * XXX XXX this loop, or the insertion of 1100 * XXX XXX memory barriers. 1101 */ 1102 TGAWALREG(dc, TGA_REG_GCSR, 0, 1103 tga_srcb + y + x + 0 * 64); 1104 TGAWALREG(dc, TGA_REG_GCDR, 0, 1105 tga_dstb + y + x + 0 * 64); 1106 TGAWALREG(dc, TGA_REG_GCSR, 1, 1107 tga_srcb + y + x + 1 * 64); 1108 TGAWALREG(dc, TGA_REG_GCDR, 1, 1109 tga_dstb + y + x + 1 * 64); 1110 TGAWALREG(dc, TGA_REG_GCSR, 2, 1111 tga_srcb + y + x + 2 * 64); 1112 TGAWALREG(dc, TGA_REG_GCDR, 2, 1113 tga_dstb + y + x + 2 * 64); 1114 TGAWALREG(dc, TGA_REG_GCSR, 3, 1115 tga_srcb + y + x + 3 * 64); 1116 TGAWALREG(dc, TGA_REG_GCDR, 3, 1117 tga_dstb + y + x + 3 * 64); 1118 } 1119 1120 /* 64 byte chunks */ 1121 for (; xleft >= 64; x += 64, xleft -= 64) { 1122 TGAWALREG(dc, TGA_REG_GCSR, 0, 1123 tga_srcb + y + x + 0 * 64); 1124 TGAWALREG(dc, TGA_REG_GCDR, 0, 1125 tga_dstb + y + x + 0 * 64); 1126 } 1127 } 1128 1129 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1130 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1131 1132 lastleft = wb & 63; 1133 if (lastleft) { 1134 lastx = xstart + (wb & ~63); 1135 for (y = ystart; (ydir * y) <= (ydir * yend); 1136 y += yinc) { 1137 /* 4 byte granularity */ 1138 for (x = lastx, xleft = lastleft; xleft >= 4; 1139 x += 4, xleft -= 4) { 1140 *(uint32_t *)(dst->ri_bits + dstb + 1141 y + x + 0 * 4) = 1142 *(uint32_t *)(dst->ri_bits + srcb + 1143 y + x + 0 * 4); 1144 } 1145 } 1146 } 1147 } else { /* above move to the left, below move to the right */ 1148 1149 if (wb & ~63) 1150 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1151 /* 4 * 64 byte chunks */ 1152 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1153 x -= 4 * 64, xleft -= 4 * 64) { 1154 1155 /* 1156 * XXX XXX Eight writes to different addresses 1157 * XXX XXX should fill up the write buffers on 1158 * XXX XXX 21064 and 21164 chips, but later 1159 * XXX XXX CPUs might have larger write buffers 1160 * XXX XXX which require further unrolling of 1161 * XXX XXX this loop, or the insertion of 1162 * XXX XXX memory barriers. 1163 */ 1164 TGAWALREG(dc, TGA_REG_GCSR, 0, 1165 tga_srcb + y + x - 1 * 64); 1166 TGAWALREG(dc, TGA_REG_GCDR, 0, 1167 tga_dstb + y + x - 1 * 64); 1168 TGAWALREG(dc, TGA_REG_GCSR, 1, 1169 tga_srcb + y + x - 2 * 64); 1170 TGAWALREG(dc, TGA_REG_GCDR, 1, 1171 tga_dstb + y + x - 2 * 64); 1172 TGAWALREG(dc, TGA_REG_GCSR, 2, 1173 tga_srcb + y + x - 3 * 64); 1174 TGAWALREG(dc, TGA_REG_GCDR, 2, 1175 tga_dstb + y + x - 3 * 64); 1176 TGAWALREG(dc, TGA_REG_GCSR, 3, 1177 tga_srcb + y + x - 4 * 64); 1178 TGAWALREG(dc, TGA_REG_GCDR, 3, 1179 tga_dstb + y + x - 4 * 64); 1180 } 1181 1182 /* 64 byte chunks */ 1183 for (; xleft >= 64; x -= 64, xleft -= 64) { 1184 TGAWALREG(dc, TGA_REG_GCSR, 0, 1185 tga_srcb + y + x - 1 * 64); 1186 TGAWALREG(dc, TGA_REG_GCDR, 0, 1187 tga_dstb + y + x - 1 * 64); 1188 } 1189 } 1190 1191 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1192 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1193 1194 lastleft = wb & 63; 1195 if (lastleft) { 1196 lastx = xstart - (wb & ~63); 1197 for (y = ystart; (ydir * y) <= (ydir * yend); 1198 y += yinc) { 1199 /* 4 byte granularity */ 1200 for (x = lastx, xleft = lastleft; xleft >= 4; 1201 x -= 4, xleft -= 4) { 1202 *(uint32_t *)(dst->ri_bits + dstb + 1203 y + x - 1 * 4) = 1204 *(uint32_t *)(dst->ri_bits + srcb + 1205 y + x - 1 * 4); 1206 } 1207 } 1208 } 1209 } 1210 return 0; 1211 } 1212 1213 1214 void tga_putchar(void *c, int row, int col, u_int uc, long attr) 1215 { 1216 struct rasops_info *ri = c; 1217 struct tga_devconfig *dc = ri->ri_hw; 1218 int fs, height, width; 1219 uint8_t *fr; 1220 int32_t *rp; 1221 1222 rp = (int32_t *)(ri->ri_bits + 1223 row * ri->ri_yscale + col * ri->ri_xscale); 1224 1225 height = ri->ri_font->fontheight; 1226 width = ri->ri_font->fontwidth; 1227 1228 uc -= ri->ri_font->firstchar; 1229 fr = (uint8_t *)ri->ri_font->data + uc * ri->ri_fontscale; 1230 fs = ri->ri_font->stride; 1231 1232 /* Set foreground and background color. XXX memoize this somehow? 1233 * The rasops code has already expanded the color entry to 32 bits 1234 * for us, even for 8-bit displays, so we don't have to do anything. 1235 */ 1236 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1237 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1238 1239 /* Set raster operation to "copy"... */ 1240 if (ri->ri_depth == 8) 1241 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1242 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1243 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1244 1245 /* Set which pixels we're drawing (of a possible 32). */ 1246 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1247 1248 /* Set drawing mode to opaque stipple. */ 1249 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1250 1251 /* Insert write barrier before actually sending data */ 1252 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1253 TGAREGWB(dc, TGA_REG_GMOR, 1); 1254 1255 while (height--) { 1256 /* The actual stipple write */ 1257 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1258 1259 fr += fs; 1260 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1261 } 1262 1263 /* Do underline */ 1264 if ((attr & 1) != 0) { 1265 rp = (int32_t *)((uint8_t *)rp - (ri->ri_stride << 1)); 1266 *rp = 0xffffffff; 1267 } 1268 1269 /* Set grapics mode back to normal. */ 1270 TGAWREG(dc, TGA_REG_GMOR, 0); 1271 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1272 } 1273 1274 static void 1275 tga_eraserows(void *c, int row, int num, long attr) 1276 { 1277 struct rasops_info *ri = c; 1278 struct tga_devconfig *dc = ri->ri_hw; 1279 int32_t color, lines, pixels; 1280 int32_t *rp; 1281 1282 color = ri->ri_devcmap[(attr >> 16) & 15]; 1283 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1284 lines = num * ri->ri_font->fontheight; 1285 pixels = ri->ri_emuwidth - 1; 1286 1287 /* Set fill color in block-color registers */ 1288 TGAWREG(dc, TGA_REG_GBCR0, color); 1289 TGAWREG(dc, TGA_REG_GBCR1, color); 1290 if (ri->ri_depth != 8) { 1291 TGAWREG(dc, TGA_REG_GBCR2, color); 1292 TGAWREG(dc, TGA_REG_GBCR3, color); 1293 TGAWREG(dc, TGA_REG_GBCR4, color); 1294 TGAWREG(dc, TGA_REG_GBCR5, color); 1295 TGAWREG(dc, TGA_REG_GBCR6, color); 1296 TGAWREG(dc, TGA_REG_GBCR7, color); 1297 } 1298 1299 /* Set raster operation to "copy"... */ 1300 if (ri->ri_depth == 8) 1301 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1302 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1303 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1304 1305 /* Set which pixels we're drawing (of a possible 32). */ 1306 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1307 1308 /* Set drawing mode to block fill. */ 1309 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1310 1311 /* Insert write barrier before actually sending data */ 1312 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1313 TGAREGWB(dc, TGA_REG_GMOR, 1); 1314 1315 while (lines--) { 1316 *rp = pixels; 1317 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1318 } 1319 1320 /* Set grapics mode back to normal. */ 1321 TGAWREG(dc, TGA_REG_GMOR, 0); 1322 } 1323 1324 static void 1325 tga_erasecols (void *c, int row, int col, int num, long attr) 1326 { 1327 struct rasops_info *ri = c; 1328 struct tga_devconfig *dc = ri->ri_hw; 1329 int32_t color, lines, pixels; 1330 int32_t *rp; 1331 1332 color = ri->ri_devcmap[(attr >> 16) & 15]; 1333 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1334 lines = ri->ri_font->fontheight; 1335 pixels = (num * ri->ri_font->fontwidth) - 1; 1336 1337 /* Set fill color in block-color registers */ 1338 TGAWREG(dc, TGA_REG_GBCR0, color); 1339 TGAWREG(dc, TGA_REG_GBCR1, color); 1340 if (ri->ri_depth != 8) { 1341 TGAWREG(dc, TGA_REG_GBCR2, color); 1342 TGAWREG(dc, TGA_REG_GBCR3, color); 1343 TGAWREG(dc, TGA_REG_GBCR4, color); 1344 TGAWREG(dc, TGA_REG_GBCR5, color); 1345 TGAWREG(dc, TGA_REG_GBCR6, color); 1346 TGAWREG(dc, TGA_REG_GBCR7, color); 1347 } 1348 1349 /* Set raster operation to "copy"... */ 1350 if (ri->ri_depth == 8) 1351 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1352 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1353 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1354 1355 /* Set which pixels we're drawing (of a possible 32). */ 1356 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1357 1358 /* Set drawing mode to block fill. */ 1359 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1360 1361 /* Insert write barrier before actually sending data */ 1362 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1363 TGAREGWB(dc, TGA_REG_GMOR, 1); 1364 1365 while (lines--) { 1366 *rp = pixels; 1367 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1368 } 1369 1370 /* Set grapics mode back to normal. */ 1371 TGAWREG(dc, TGA_REG_GMOR, 0); 1372 } 1373 1374 1375 static void 1376 tga_ramdac_wr(void *v, u_int btreg, uint8_t val) 1377 { 1378 struct tga_devconfig *dc = v; 1379 1380 if (btreg > BT485_REG_MAX) 1381 panic("tga_ramdac_wr: reg %d out of range", btreg); 1382 1383 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1384 TGAREGWB(dc, TGA_REG_EPDR, 1); 1385 } 1386 1387 static void 1388 tga2_ramdac_wr(void *v, u_int btreg, uint8_t val) 1389 { 1390 struct tga_devconfig *dc = v; 1391 bus_space_handle_t ramdac; 1392 1393 if (btreg > BT485_REG_MAX) 1394 panic("tga_ramdac_wr: reg %d out of range", btreg); 1395 1396 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1397 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1398 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1399 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1400 } 1401 1402 static uint8_t 1403 tga_bt463_rd(void *v, u_int btreg) 1404 { 1405 struct tga_devconfig *dc = v; 1406 tga_reg_t rdval; 1407 1408 /* 1409 * Strobe CE# (high->low->high) since status and data are latched on 1410 * the falling and rising edges (repsectively) of this active-low 1411 * signal. 1412 */ 1413 1414 TGAREGWB(dc, TGA_REG_EPSR, 1); 1415 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1416 TGAREGWB(dc, TGA_REG_EPSR, 1); 1417 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1418 1419 TGAREGRB(dc, TGA_REG_EPSR, 1); 1420 1421 rdval = TGARREG(dc, TGA_REG_EPDR); 1422 TGAREGWB(dc, TGA_REG_EPSR, 1); 1423 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1424 1425 return (rdval >> 16) & 0xff; 1426 } 1427 1428 static void 1429 tga_bt463_wr(void *v, u_int btreg, uint8_t val) 1430 { 1431 struct tga_devconfig *dc = v; 1432 1433 /* 1434 * In spite of the 21030 documentation, to set the MPU bus bits for 1435 * a write, you set them in the upper bits of EPDR, not EPSR. 1436 */ 1437 1438 /* 1439 * Strobe CE# (high->low->high) since status and data are latched on 1440 * the falling and rising edges of this active-low signal. 1441 */ 1442 1443 TGAREGWB(dc, TGA_REG_EPDR, 1); 1444 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1445 TGAREGWB(dc, TGA_REG_EPDR, 1); 1446 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1447 TGAREGWB(dc, TGA_REG_EPDR, 1); 1448 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1449 } 1450 1451 static uint8_t 1452 tga_ramdac_rd(void *v, u_int btreg) 1453 { 1454 struct tga_devconfig *dc = v; 1455 tga_reg_t rdval; 1456 1457 if (btreg > BT485_REG_MAX) 1458 panic("tga_ramdac_rd: reg %d out of range", btreg); 1459 1460 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1461 TGAREGWB(dc, TGA_REG_EPSR, 1); 1462 1463 rdval = TGARREG(dc, TGA_REG_EPDR); 1464 return (rdval >> 16) & 0xff; /* XXX */ 1465 } 1466 1467 static uint8_t 1468 tga2_ramdac_rd(void *v, u_int btreg) 1469 { 1470 struct tga_devconfig *dc = v; 1471 bus_space_handle_t ramdac; 1472 uint8_t retval; 1473 1474 if (btreg > BT485_REG_MAX) 1475 panic("tga_ramdac_rd: reg %d out of range", btreg); 1476 1477 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1478 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1479 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1480 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1481 return retval; 1482 } 1483 1484 #include <dev/ic/decmonitors.c> 1485 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1486 1487 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1488 1489 void 1490 tga2_init(struct tga_devconfig *dc) 1491 { 1492 struct monitor *m = tga_getmonitor(dc); 1493 1494 /* Deal with the dot clocks. 1495 */ 1496 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1497 /* 1498 * Set this up as a reference clock for the 1499 * ibm561's PLL. 1500 */ 1501 tga2_ics9110_wr(dc, 14300000); 1502 /* 1503 * XXX Can't set up the dotclock properly, until such time 1504 * as the RAMDAC is configured. 1505 */ 1506 } else { 1507 /* otherwise the ics9110 is our clock. */ 1508 tga2_ics9110_wr(dc, m->dotclock); 1509 } 1510 #if 0 1511 TGAWREG(dc, TGA_REG_VHCR, 1512 ((m->hbp / 4) << 21) | 1513 ((m->hsync / 4) << 14) | 1514 (((m->hfp - 4) / 4) << 9) | 1515 ((m->cols + 4) / 4)); 1516 #else 1517 TGAWREG(dc, TGA_REG_VHCR, 1518 ((m->hbp / 4) << 21) | 1519 ((m->hsync / 4) << 14) | 1520 (((m->hfp) / 4) << 9) | 1521 ((m->cols) / 4)); 1522 #endif 1523 TGAWREG(dc, TGA_REG_VVCR, 1524 (m->vbp << 22) | 1525 (m->vsync << 16) | 1526 (m->vfp << 11) | 1527 (m->rows)); 1528 TGAWREG(dc, TGA_REG_VVBR, 1); 1529 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1530 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1531 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1532 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1533 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1534 } 1535 1536 void 1537 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock) 1538 { 1539 bus_space_handle_t clock; 1540 uint32_t valU; 1541 int N, M, R, V, X; 1542 int i; 1543 1544 switch (dotclock) { 1545 case 130808000: 1546 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1547 case 119840000: 1548 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1549 case 108180000: 1550 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1551 case 103994000: 1552 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1553 case 175000000: 1554 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1555 case 75000000: 1556 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1557 case 74000000: 1558 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1559 case 69000000: 1560 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1561 case 65000000: 1562 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1563 case 50000000: 1564 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1565 case 40000000: 1566 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1567 case 31500000: 1568 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1569 case 25175000: 1570 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1571 case 135000000: 1572 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1573 case 110000000: 1574 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1575 case 202500000: 1576 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1577 case 14300000: /* this one is just a ref clock */ 1578 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1579 default: 1580 panic("unrecognized clock rate %d", dotclock); 1581 } 1582 1583 /* XXX -- hard coded, bad */ 1584 valU = N | ( M << 7 ) | (V << 14); 1585 valU |= (X << 15) | (R << 17); 1586 valU |= 0x17 << 19; 1587 1588 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1589 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1590 1591 for (i = 24; i > 0; i--) { 1592 uint32_t writeval; 1593 1594 writeval = valU & 0x1; 1595 if (i == 1) 1596 writeval |= 0x2; 1597 valU >>= 1; 1598 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1599 bus_space_barrier(dc->dc_memt, clock, 0, 4, 1600 BUS_SPACE_BARRIER_WRITE); 1601 } 1602 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1603 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1604 &clock); /* XXX */ 1605 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1606 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1607 } 1608 1609 struct monitor * 1610 tga_getmonitor(struct tga_devconfig *dc) 1611 { 1612 1613 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1614 } 1615 1616 unsigned int 1617 tga_getdotclock(struct tga_devconfig *dc) 1618 { 1619 1620 return tga_getmonitor(dc)->dotclock; 1621 } 1622
Indexes created Thu Sep 25 16:09:42 GMT 2025