tga.c revision 1.88
1 /* $NetBSD: tga.c,v 1.88 2021/08/07 16:19:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: tga.c,v 1.88 2021/08/07 16:19:14 thorpej Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/kernel.h> 36 #include <sys/device.h> 37 #include <sys/conf.h> 38 #include <sys/malloc.h> 39 #include <sys/buf.h> 40 #include <sys/ioctl.h> 41 42 #include <sys/bus.h> 43 #include <sys/intr.h> 44 45 #include <dev/pci/pcireg.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcidevs.h> 48 #include <dev/pci/pciio.h> 49 #include <dev/pci/tgareg.h> 50 #include <dev/pci/tgavar.h> 51 #include <dev/ic/bt485reg.h> 52 #include <dev/ic/bt485var.h> 53 #include <dev/ic/bt463reg.h> 54 #include <dev/ic/bt463var.h> 55 #include <dev/ic/ibm561var.h> 56 57 #include <dev/wscons/wsconsio.h> 58 #include <dev/wscons/wscons_raster.h> 59 #include <dev/rasops/rasops.h> 60 #include <dev/wsfont/wsfont.h> 61 #include <dev/pci/wsdisplay_pci.h> 62 63 int tgamatch(device_t, cfdata_t, void *); 64 void tgaattach(device_t, device_t, void *); 65 int tgaprint(void *, const char *); 66 67 CFATTACH_DECL_NEW(tga, sizeof(struct tga_softc), 68 tgamatch, tgaattach, NULL, NULL); 69 70 static void tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, 71 pcitag_t tag, struct tga_devconfig *dc); 72 73 static int tga_matchcommon(bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 74 static void tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, 75 pcitag_t, bus_size_t *pcisize, struct tga_devconfig *dc); 76 unsigned int tga_getdotclock(struct tga_devconfig *dc); 77 78 int tga_ioctl(void *, void *, u_long, void *, int, struct lwp *); 79 paddr_t tga_mmap(void *, void *, off_t, int); 80 static void tga_copyrows(void *, int, int, int); 81 static void tga_copycols(void *, int, int, int, int); 82 static int tga_alloc_screen(void *, const struct wsscreen_descr *, 83 void **, int *, int *, long *); 84 static void tga_free_screen(void *, void *); 85 static int tga_show_screen(void *, void *, int, 86 void (*) (void *, int, int), void *); 87 static int tga_rop(struct rasops_info *, int, int, int, int, int, 88 struct rasops_info *, int, int); 89 static int tga_rop_vtov(struct rasops_info *, int, int, int, int, 90 int, struct rasops_info *, int, int); 91 static void tga_putchar(void *c, int row, int col, u_int uc, long attr); 92 static void tga_eraserows(void *, int, int, long); 93 static void tga_erasecols(void *, int, int, int, long); 94 void tga2_init(struct tga_devconfig *); 95 96 static void tga_config_interrupts(device_t); 97 98 /* RAMDAC interface functions */ 99 static int tga_sched_update(void *, void (*)(void *)); 100 static void tga_ramdac_wr(void *, u_int, uint8_t); 101 static uint8_t tga_ramdac_rd(void *, u_int); 102 static void tga_bt463_wr(void *, u_int, uint8_t); 103 static uint8_t tga_bt463_rd(void *, u_int); 104 static void tga2_ramdac_wr(void *, u_int, uint8_t); 105 static uint8_t tga2_ramdac_rd(void *, u_int); 106 107 /* Interrupt handler */ 108 static int tga_intr(void *); 109 110 struct tga_devconfig tga_console_dc; 111 112 /* The NULL entries will get filled in by rasops_init(). 113 * XXX and the non-NULL ones will be overwritten; reset after calling it. 114 */ 115 struct wsdisplay_emulops tga_emulops = { 116 NULL, 117 NULL, 118 tga_putchar, 119 tga_copycols, 120 tga_erasecols, 121 tga_copyrows, 122 tga_eraserows, 123 NULL, 124 NULL, 125 }; 126 127 struct wsscreen_descr tga_stdscreen = { 128 "std", 129 0, 0, /* will be filled in -- XXX shouldn't, it's global */ 130 &tga_emulops, 131 0, 0, 132 WSSCREEN_REVERSE, 133 NULL, 134 }; 135 136 const struct wsscreen_descr *_tga_scrlist[] = { 137 &tga_stdscreen, 138 /* XXX other formats, graphics screen? */ 139 }; 140 141 struct wsscreen_list tga_screenlist = { 142 sizeof(_tga_scrlist) / sizeof(struct wsscreen_descr *), _tga_scrlist 143 }; 144 145 struct wsdisplay_accessops tga_accessops = { 146 tga_ioctl, 147 tga_mmap, 148 tga_alloc_screen, 149 tga_free_screen, 150 tga_show_screen, 151 NULL, /* load_font */ 152 NULL, 153 NULL, 154 }; 155 156 static void tga_blank(struct tga_devconfig *); 157 static void tga_unblank(struct tga_devconfig *); 158 159 int 160 tga_cnmatch(bus_space_tag_t iot, bus_space_tag_t memt, 161 pci_chipset_tag_t pc, pcitag_t tag) 162 { 163 164 return tga_matchcommon(memt, pc, tag); 165 } 166 167 int 168 tgamatch(device_t parent, cfdata_t match, void *aux) 169 { 170 struct pci_attach_args *pa = aux; 171 172 if (PCI_VENDOR(pa->pa_id) != PCI_VENDOR_DEC) 173 return (0); 174 175 switch (PCI_PRODUCT(pa->pa_id)) { 176 case PCI_PRODUCT_DEC_21030: 177 case PCI_PRODUCT_DEC_PBXGB: 178 break; 179 default: 180 return 0; 181 } 182 183 #if defined(__alpha__) || defined(arc) 184 /* short-circuit the following test, as we 185 * already have the memory mapped and hence 186 * cannot perform it---and we are the console 187 * anyway. 188 */ 189 if (pa->pa_tag == tga_console_dc.dc_pcitag) 190 return 10; 191 #endif 192 return tga_matchcommon(pa->pa_memt, pa->pa_pc, pa->pa_tag); 193 } 194 195 static int 196 tga_matchcommon(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag) 197 { 198 struct tga_devconfig tmp_dc; 199 struct tga_devconfig *dc = &tmp_dc; 200 bus_size_t pcisize; 201 202 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 203 dc->dc_tga_type = tga_identify(dc); 204 205 dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 206 bus_space_unmap(memt, dc->dc_memh, pcisize); 207 if (dc->dc_tgaconf) 208 return 10; 209 return 0; 210 } 211 212 static void 213 tga_mapaddrs(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 214 bus_size_t *pcisize, struct tga_devconfig *dc) 215 { 216 int flags; 217 218 dc->dc_memt = memt; 219 dc->dc_tgaconf = NULL; 220 221 /* XXX magic number */ 222 if (pci_mapreg_info(pc, tag, 0x10, 223 PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT, 224 &dc->dc_pcipaddr, pcisize, &flags)) 225 panic("tga_mapaddrs: pci_mapreg_info() failed"); 226 if ((flags & BUS_SPACE_MAP_PREFETCHABLE) == 0) /* XXX */ 227 panic("tga memory not prefetchable"); 228 229 if (bus_space_map(memt, dc->dc_pcipaddr, *pcisize, 230 BUS_SPACE_MAP_PREFETCHABLE | BUS_SPACE_MAP_LINEAR, &dc->dc_memh)) 231 panic("tga_mapaddrs: could not map TGA address space"); 232 dc->dc_vaddr = (vaddr_t)bus_space_vaddr(memt, dc->dc_memh); 233 234 bus_space_subregion(dc->dc_memt, dc->dc_memh, 235 TGA_MEM_CREGS, TGA_CREGS_SIZE, &dc->dc_regs); 236 } 237 238 static void 239 tga_init(bus_space_tag_t memt, pci_chipset_tag_t pc, pcitag_t tag, 240 struct tga_devconfig *dc) 241 { 242 const struct tga_conf *tgac; 243 struct rasops_info *rip; 244 int cookie; 245 bus_size_t pcisize; 246 int i; 247 248 dc->dc_pc = pc; 249 dc->dc_pcitag = tag; 250 tga_mapaddrs(memt, pc, tag, &pcisize, dc); 251 dc->dc_tga_type = tga_identify(dc); 252 tgac = dc->dc_tgaconf = tga_getconf(dc->dc_tga_type); 253 #if 0 254 /* XXX on the Alpha, pcisize = 4 * cspace_size. */ 255 if (tgac->tgac_cspace_size != pcisize) /* sanity */ 256 panic("tga_init: memory size mismatch?"); 257 #endif 258 259 switch (TGARREG(dc, TGA_REG_GREV) & 0xff) { 260 case 0x01: 261 case 0x02: 262 case 0x03: 263 case 0x04: 264 dc->dc_tga2 = 0; 265 break; 266 case 0x20: 267 case 0x21: 268 case 0x22: 269 dc->dc_tga2 = 1; 270 break; 271 default: 272 panic("tga_init: TGA Revision not recognized"); 273 } 274 275 if (dc->dc_tga2) 276 tga2_init(dc); 277 278 switch (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) { /* XXX */ 279 case 0: 280 dc->dc_wid = 8192; 281 break; 282 283 case 1: 284 dc->dc_wid = 8196; 285 break; 286 287 default: 288 dc->dc_wid = (TGARREG(dc, TGA_REG_VHCR) & 0x1ff) * 4; /* XXX */ 289 break; 290 } 291 292 /* 293 * XXX XXX Turning off "odd" shouldn't be necessary, 294 * XXX XXX but I can't make X work with the weird size. 295 */ 296 if ((TGARREG(dc, TGA_REG_VHCR) & 0x00000001) != 0 && /* XXX */ 297 (TGARREG(dc, TGA_REG_VHCR) & 0x80000000) != 0) { /* XXX */ 298 TGAWREG(dc, TGA_REG_VHCR, 299 (TGARREG(dc, TGA_REG_VHCR) & ~0x80000001)); 300 dc->dc_wid -= 4; 301 } 302 303 dc->dc_rowbytes = dc->dc_wid * (dc->dc_tgaconf->tgac_phys_depth / 8); 304 dc->dc_ht = (TGARREG(dc, TGA_REG_VVCR) & 0x7ff); /* XXX */ 305 306 /* XXX this seems to be what DEC does */ 307 TGAWREG(dc, TGA_REG_CCBR, 0); 308 TGAWREG(dc, TGA_REG_VVBR, 1); 309 dc->dc_videobase = dc->dc_vaddr + tgac->tgac_dbuf[0] + 310 1 * tgac->tgac_vvbr_units; 311 dc->dc_blanked = 1; 312 tga_unblank(dc); 313 314 /* 315 * Set all bits in the pixel mask, to enable writes to all pixels. 316 * It seems that the console firmware clears some of them 317 * under some circumstances, which causes cute vertical stripes. 318 */ 319 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 320 321 /* clear the screen */ 322 for (i = 0; i < dc->dc_ht * dc->dc_rowbytes; i += sizeof(uint32_t)) 323 *(uint32_t *)(dc->dc_videobase + i) = 0; 324 325 /* Initialize rasops descriptor */ 326 rip = &dc->dc_rinfo; 327 rip->ri_flg = RI_CENTER; 328 rip->ri_depth = tgac->tgac_phys_depth; 329 rip->ri_bits = (void *)dc->dc_videobase; 330 rip->ri_width = dc->dc_wid; 331 rip->ri_height = dc->dc_ht; 332 rip->ri_stride = dc->dc_rowbytes; 333 rip->ri_hw = dc; 334 if (dc == &tga_console_dc) 335 rip->ri_flg |= RI_NO_AUTO; 336 337 if (tgac->tgac_phys_depth == 32) { 338 rip->ri_rnum = 8; 339 rip->ri_gnum = 8; 340 rip->ri_bnum = 8; 341 rip->ri_rpos = 16; 342 rip->ri_gpos = 8; 343 rip->ri_bpos = 0; 344 } 345 346 wsfont_init(); 347 /* prefer 8 pixel wide font */ 348 cookie = wsfont_find(NULL, 8, 0, 0, WSDISPLAY_FONTORDER_R2L, 349 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 350 if (cookie <= 0) 351 cookie = wsfont_find(NULL, 0, 0, 0, WSDISPLAY_FONTORDER_R2L, 352 WSDISPLAY_FONTORDER_L2R, WSFONT_FIND_BITMAP); 353 if (cookie <= 0) { 354 printf("tga: no appropriate fonts.\n"); 355 return; 356 } 357 358 /* the accelerated tga_putchar() needs LSbit left */ 359 if (wsfont_lock(cookie, &dc->dc_rinfo.ri_font)) { 360 printf("tga: couldn't lock font\n"); 361 return; 362 } 363 dc->dc_rinfo.ri_wsfcookie = cookie; 364 365 rasops_init(rip, 34, 80); 366 367 /* add our accelerated functions */ 368 /* XXX shouldn't have to do this; rasops should leave non-NULL 369 * XXX entries alone. 370 */ 371 dc->dc_rinfo.ri_ops.copyrows = tga_copyrows; 372 dc->dc_rinfo.ri_ops.eraserows = tga_eraserows; 373 dc->dc_rinfo.ri_ops.erasecols = tga_erasecols; 374 dc->dc_rinfo.ri_ops.copycols = tga_copycols; 375 dc->dc_rinfo.ri_ops.putchar = tga_putchar; 376 377 tga_stdscreen.nrows = dc->dc_rinfo.ri_rows; 378 tga_stdscreen.ncols = dc->dc_rinfo.ri_cols; 379 tga_stdscreen.textops = &dc->dc_rinfo.ri_ops; 380 tga_stdscreen.capabilities = dc->dc_rinfo.ri_caps; 381 382 383 dc->dc_intrenabled = 0; 384 } 385 386 void 387 tgaattach(device_t parent, device_t self, void *aux) 388 { 389 struct pci_attach_args *pa = aux; 390 struct tga_softc *sc = device_private(self); 391 struct tga_devconfig *dc; 392 struct wsemuldisplaydev_attach_args aa; 393 pci_intr_handle_t intrh; 394 const char *intrstr; 395 uint8_t rev; 396 int console; 397 char intrbuf[PCI_INTRSTR_LEN]; 398 399 sc->sc_dev = self; 400 401 #if defined(__alpha__) || defined(arc) 402 console = (pa->pa_tag == tga_console_dc.dc_pcitag); 403 #else 404 console = 0; 405 #endif 406 if (console) { 407 sc->sc_dc = &tga_console_dc; 408 sc->sc_dc->dc_rinfo.ri_flg &= ~RI_NO_AUTO; 409 sc->nscreens = 1; 410 } else { 411 sc->sc_dc = malloc(sizeof(struct tga_devconfig), M_DEVBUF, 412 M_WAITOK|M_ZERO); 413 tga_init(pa->pa_memt, pa->pa_pc, pa->pa_tag, sc->sc_dc); 414 } 415 if (sc->sc_dc->dc_vaddr == 0) { 416 aprint_error(": couldn't map memory space; punt!\n"); 417 return; 418 } 419 420 /* XXX say what's going on. */ 421 intrstr = NULL; 422 if (pci_intr_map(pa, &intrh)) { 423 aprint_error(": couldn't map interrupt"); 424 return; 425 } 426 intrstr = pci_intr_string(pa->pa_pc, intrh, intrbuf, sizeof(intrbuf)); 427 sc->sc_intr = pci_intr_establish_xname(pa->pa_pc, intrh, IPL_TTY, 428 tga_intr, sc->sc_dc, device_xname(self)); 429 if (sc->sc_intr == NULL) { 430 aprint_error(": couldn't establish interrupt"); 431 if (intrstr != NULL) 432 aprint_error("at %s", intrstr); 433 aprint_error("\n"); 434 return; 435 } 436 437 rev = PCI_REVISION(pa->pa_class); 438 switch (rev) { 439 case 0x1: 440 case 0x2: 441 case 0x3: 442 aprint_normal(": DC21030 step %c", 'A' + rev - 1); 443 break; 444 case 0x20: 445 aprint_normal(": TGA2 abstract software model"); 446 break; 447 case 0x21: 448 case 0x22: 449 aprint_normal(": TGA2 pass %d", rev - 0x20); 450 break; 451 452 default: 453 aprint_normal("unknown stepping (0x%x)", rev); 454 break; 455 } 456 aprint_normal(", "); 457 458 /* 459 * Get RAMDAC function vectors and call the RAMDAC functions 460 * to allocate its private storage and pass that back to us. 461 */ 462 463 dc = sc->sc_dc; 464 dc->dc_ramdac_funcs = dc->dc_tgaconf->ramdac_funcs(); 465 if (!dc->dc_tga2) { 466 if (dc->dc_tgaconf->ramdac_funcs == bt485_funcs) 467 dc->dc_ramdac_cookie = 468 dc->dc_ramdac_funcs->ramdac_register(dc, 469 tga_sched_update, tga_ramdac_wr, tga_ramdac_rd); 470 else 471 dc->dc_ramdac_cookie = 472 dc->dc_ramdac_funcs->ramdac_register(dc, 473 tga_sched_update, tga_bt463_wr, tga_bt463_rd); 474 } else { 475 dc->dc_ramdac_cookie = dc->dc_ramdac_funcs->ramdac_register(dc, 476 tga_sched_update, tga2_ramdac_wr, tga2_ramdac_rd); 477 478 /* XXX this is a bit of a hack, setting the dotclock here */ 479 if (dc->dc_tgaconf->ramdac_funcs != bt485_funcs) 480 (*dc->dc_ramdac_funcs->ramdac_set_dotclock) 481 (dc->dc_ramdac_cookie, tga_getdotclock(dc)); 482 } 483 484 /* 485 * Initialize the RAMDAC. Initialization includes disabling 486 * cursor, setting a sane colormap, etc. We presume that we've 487 * filled in the necessary dot clock for PowerStorm 4d20. 488 */ 489 (*dc->dc_ramdac_funcs->ramdac_init)(dc->dc_ramdac_cookie); 490 TGAWREG(dc, TGA_REG_SISR, 0x00000001); /* XXX */ 491 492 if (dc->dc_tgaconf == NULL) { 493 aprint_error("unknown board configuration\n"); 494 return; 495 } 496 aprint_normal("board type %s\n", dc->dc_tgaconf->tgac_name); 497 aprint_normal_dev(self, "%d x %d, %dbpp, %s RAMDAC\n", 498 dc->dc_wid, dc->dc_ht, 499 dc->dc_tgaconf->tgac_phys_depth, 500 dc->dc_ramdac_funcs->ramdac_name); 501 502 if (intrstr != NULL) 503 aprint_normal_dev(self, "interrupting at %s\n", 504 intrstr); 505 506 aa.console = console; 507 aa.scrdata = &tga_screenlist; 508 aa.accessops = &tga_accessops; 509 aa.accesscookie = sc; 510 511 config_found(self, &aa, wsemuldisplaydevprint, CFARGS_NONE); 512 513 config_interrupts(self, tga_config_interrupts); 514 } 515 516 static void 517 tga_config_interrupts(device_t self) 518 { 519 struct tga_softc *sc; 520 521 sc = device_private(self); 522 sc->sc_dc->dc_intrenabled = 1; 523 } 524 525 int 526 tga_ioctl(void *v, void *vs, u_long cmd, void *data, int flag, struct lwp *l) 527 { 528 struct tga_softc *sc = v; 529 struct tga_devconfig *dc = sc->sc_dc; 530 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 531 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 532 533 switch (cmd) { 534 case WSDISPLAYIO_GTYPE: 535 *(u_int *)data = WSDISPLAY_TYPE_TGA; 536 return 0; 537 538 case WSDISPLAYIO_GINFO: 539 #define wsd_fbip ((struct wsdisplay_fbinfo *)data) 540 wsd_fbip->height = sc->sc_dc->dc_ht; 541 wsd_fbip->width = sc->sc_dc->dc_wid; 542 wsd_fbip->depth = sc->sc_dc->dc_tgaconf->tgac_phys_depth; 543 #if 0 544 wsd_fbip->cmsize = 256; /* XXX ??? */ 545 #else 546 wsd_fbip->cmsize = 1024; /* XXX ??? */ 547 #endif 548 #undef wsd_fbip 549 return 0; 550 551 case WSDISPLAYIO_GETCMAP: 552 return (*dcrf->ramdac_get_cmap)(dcrc, 553 (struct wsdisplay_cmap *)data); 554 555 case WSDISPLAYIO_PUTCMAP: 556 return (*dcrf->ramdac_set_cmap)(dcrc, 557 (struct wsdisplay_cmap *)data); 558 559 case WSDISPLAYIO_SVIDEO: 560 if (*(u_int *)data == WSDISPLAYIO_VIDEO_OFF) 561 tga_blank(sc->sc_dc); 562 else 563 tga_unblank(sc->sc_dc); 564 return 0; 565 566 case WSDISPLAYIO_GVIDEO: 567 *(u_int *)data = dc->dc_blanked ? 568 WSDISPLAYIO_VIDEO_OFF : WSDISPLAYIO_VIDEO_ON; 569 return 0; 570 571 case WSDISPLAYIO_GCURPOS: 572 return (*dcrf->ramdac_get_curpos)(dcrc, 573 (struct wsdisplay_curpos *)data); 574 575 case WSDISPLAYIO_SCURPOS: 576 return (*dcrf->ramdac_set_curpos)(dcrc, 577 (struct wsdisplay_curpos *)data); 578 579 case WSDISPLAYIO_GCURMAX: 580 return (*dcrf->ramdac_get_curmax)(dcrc, 581 (struct wsdisplay_curpos *)data); 582 583 case WSDISPLAYIO_GCURSOR: 584 return (*dcrf->ramdac_get_cursor)(dcrc, 585 (struct wsdisplay_cursor *)data); 586 587 case WSDISPLAYIO_SCURSOR: 588 return (*dcrf->ramdac_set_cursor)(dcrc, 589 (struct wsdisplay_cursor *)data); 590 591 case WSDISPLAYIO_LINEBYTES: 592 *(u_int *)data = dc->dc_rowbytes; 593 return 0; 594 595 /* PCI config read/write passthrough. */ 596 case PCI_IOC_CFGREAD: 597 case PCI_IOC_CFGWRITE: 598 return pci_devioctl(dc->dc_pc, dc->dc_pcitag, 599 cmd, data, flag, l); 600 601 case WSDISPLAYIO_GET_BUSID: 602 return wsdisplayio_busid_pci(sc->sc_dev, dc->dc_pc, 603 dc->dc_pcitag, data); 604 } 605 return EPASSTHROUGH; 606 } 607 608 static int 609 tga_sched_update(void *v, void (*f)(void *)) 610 { 611 struct tga_devconfig *dc = v; 612 613 if (dc->dc_intrenabled) { 614 /* 615 * Arrange for f to be called at the next end-of-frame 616 * interrupt. 617 */ 618 dc->dc_ramdac_intr = f; 619 TGAWREG(dc, TGA_REG_SISR, 0x00010000); 620 } else { 621 /* Spin until the end-of-frame, then call f */ 622 TGAWREG(dc, TGA_REG_SISR, 0x00010001); 623 TGAREGWB(dc, TGA_REG_SISR, 1); 624 while ((TGARREG(dc, TGA_REG_SISR) & 0x00000001) == 0) 625 continue; 626 f(dc->dc_ramdac_cookie); 627 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 628 TGAREGWB(dc, TGA_REG_SISR, 1); 629 } 630 631 return 0; 632 } 633 634 static int 635 tga_intr(void *v) 636 { 637 struct tga_devconfig *dc = v; 638 struct ramdac_cookie *dcrc= dc->dc_ramdac_cookie; 639 640 uint32_t reg; 641 642 reg = TGARREG(dc, TGA_REG_SISR); 643 if (( reg & 0x00010001) != 0x00010001) { 644 /* Odd. We never set any of the other interrupt enables. */ 645 if ((reg & 0x1f) != 0) { 646 /* Clear the mysterious pending interrupts. */ 647 TGAWREG(dc, TGA_REG_SISR, (reg & 0x1f)); 648 TGAREGWB(dc, TGA_REG_SISR, 1); 649 /* 650 * This was our interrupt, even if we're puzzled 651 * as to why we got it. Don't make the interrupt 652 * handler think it was a stray. 653 */ 654 return -1; 655 } else { 656 return 0; 657 } 658 } 659 /* if we have something to do, do it */ 660 if (dc->dc_ramdac_intr) { 661 dc->dc_ramdac_intr(dcrc); 662 dc->dc_ramdac_intr = NULL; 663 } 664 TGAWREG(dc, TGA_REG_SISR, 0x00000001); 665 TGAREGWB(dc, TGA_REG_SISR, 1); 666 return 1; 667 } 668 669 paddr_t 670 tga_mmap(void *v, void *vs, off_t offset, int prot) 671 { 672 struct tga_softc *sc = v; 673 674 if (offset >= sc->sc_dc->dc_tgaconf->tgac_cspace_size || offset < 0) 675 return -1; 676 677 return bus_space_mmap(sc->sc_dc->dc_memt, sc->sc_dc->dc_pcipaddr, 678 offset, prot, BUS_SPACE_MAP_LINEAR); 679 } 680 681 static int 682 tga_alloc_screen(void *v, const struct wsscreen_descr *type, void **cookiep, 683 int *curxp, int *curyp, long *attrp) 684 { 685 struct tga_softc *sc = v; 686 long defattr; 687 688 if (sc->nscreens > 0) 689 return ENOMEM; 690 691 *cookiep = &sc->sc_dc->dc_rinfo; /* one and only for now */ 692 *curxp = 0; 693 *curyp = 0; 694 sc->sc_dc->dc_rinfo.ri_ops.allocattr(&sc->sc_dc->dc_rinfo, 695 0, 0, 0, &defattr); 696 *attrp = defattr; 697 sc->nscreens++; 698 return 0; 699 } 700 701 static void 702 tga_free_screen(void *v, void *cookie) 703 { 704 struct tga_softc *sc = v; 705 706 if (sc->sc_dc == &tga_console_dc) 707 panic("tga_free_screen: console"); 708 709 sc->nscreens--; 710 } 711 712 static int 713 tga_show_screen(void *v, void *cookie, int waitok, 714 void (*cb)(void *, int, int), void *cbarg) 715 { 716 717 return 0; 718 } 719 720 int 721 tga_cnattach(bus_space_tag_t iot, bus_space_tag_t memt, 722 pci_chipset_tag_t pc, int bus, int device, int function) 723 { 724 struct tga_devconfig *dcp = &tga_console_dc; 725 long defattr; 726 727 tga_init(memt, pc, pci_make_tag(pc, bus, device, function), dcp); 728 729 /* sanity checks */ 730 if (dcp->dc_vaddr == 0) 731 panic("tga_console(%d, %d): couldn't map memory space", 732 device, function); 733 if (dcp->dc_tgaconf == NULL) 734 panic("tga_console(%d, %d): unknown board configuration", 735 device, function); 736 737 /* 738 * Initialize the RAMDAC but DO NOT allocate any private storage. 739 * Initialization includes disabling cursor, setting a sane 740 * colormap, etc. It will be reinitialized in tgaattach(). 741 */ 742 if (dcp->dc_tga2) { 743 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 744 bt485_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 745 tga2_ramdac_rd); 746 else 747 ibm561_cninit(dcp, tga_sched_update, tga2_ramdac_wr, 748 tga2_ramdac_rd, tga_getdotclock(dcp)); 749 } else { 750 if (dcp->dc_tgaconf->ramdac_funcs == bt485_funcs) 751 bt485_cninit(dcp, tga_sched_update, tga_ramdac_wr, 752 tga_ramdac_rd); 753 else { 754 bt463_cninit(dcp, tga_sched_update, tga_bt463_wr, 755 tga_bt463_rd); 756 } 757 } 758 dcp->dc_rinfo.ri_ops.allocattr(&dcp->dc_rinfo, 0, 0, 0, &defattr); 759 wsdisplay_cnattach(&tga_stdscreen, &dcp->dc_rinfo, 0, 0, defattr); 760 761 return 0; 762 } 763 764 /* 765 * Functions to blank and unblank the display. 766 */ 767 static void 768 tga_blank(struct tga_devconfig *dc) 769 { 770 771 if (!dc->dc_blanked) { 772 dc->dc_blanked = 1; 773 /* XXX */ 774 TGAWREG(dc, TGA_REG_VVVR, 775 TGARREG(dc, TGA_REG_VVVR) | VVR_BLANK); 776 } 777 } 778 779 static void 780 tga_unblank(struct tga_devconfig *dc) 781 { 782 783 if (dc->dc_blanked) { 784 dc->dc_blanked = 0; 785 /* XXX */ 786 TGAWREG(dc, TGA_REG_VVVR, 787 TGARREG(dc, TGA_REG_VVVR) & ~VVR_BLANK); 788 } 789 } 790 791 /* 792 * Functions to manipulate the built-in cursor handing hardware. 793 */ 794 int 795 tga_builtin_set_cursor(struct tga_devconfig *dc, 796 struct wsdisplay_cursor *cursorp) 797 { 798 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 799 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 800 uint8_t image[512]; 801 u_int count, v; 802 int error; 803 804 v = cursorp->which; 805 if (v & WSDISPLAY_CURSOR_DOCMAP) { 806 error = dcrf->ramdac_check_curcmap(dcrc, cursorp); 807 if (error) 808 return error; 809 } 810 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 811 if ((u_int)cursorp->size.x != 64 || 812 (u_int)cursorp->size.y > 64) 813 return EINVAL; 814 /* The cursor is 2 bits deep, and there is no mask */ 815 count = (cursorp->size.y * 64 * 2) / NBBY; 816 error = copyin(cursorp->image, image, count); 817 if (error) 818 return error; 819 } 820 if (v & WSDISPLAY_CURSOR_DOHOT) /* not supported */ 821 return EINVAL; 822 823 /* parameters are OK; do it */ 824 if (v & WSDISPLAY_CURSOR_DOCUR) { 825 if (cursorp->enable) 826 /* XXX */ 827 TGAWREG(dc, TGA_REG_VVVR, 828 TGARREG(dc, TGA_REG_VVVR) | 0x04); 829 else 830 /* XXX */ 831 TGAWREG(dc, TGA_REG_VVVR, 832 TGARREG(dc, TGA_REG_VVVR) & ~0x04); 833 } 834 if (v & WSDISPLAY_CURSOR_DOPOS) { 835 TGAWREG(dc, TGA_REG_CXYR, ((cursorp->pos.y & 0xfff) << 12) | 836 (cursorp->pos.x & 0xfff)); 837 } 838 if (v & WSDISPLAY_CURSOR_DOCMAP) { 839 dcrf->ramdac_set_curcmap(dcrc, cursorp); 840 } 841 if (v & WSDISPLAY_CURSOR_DOSHAPE) { 842 count = ((64 * 2) / NBBY) * cursorp->size.y; 843 TGAWREG(dc, TGA_REG_CCBR, 844 (TGARREG(dc, TGA_REG_CCBR) & ~0xfc00) | 845 (cursorp->size.y << 10)); 846 memcpy((void *)(dc->dc_vaddr + 847 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 848 image, count); 849 } 850 return 0; 851 } 852 853 int 854 tga_builtin_get_cursor(struct tga_devconfig *dc, 855 struct wsdisplay_cursor *cursorp) 856 { 857 struct ramdac_funcs *dcrf = dc->dc_ramdac_funcs; 858 struct ramdac_cookie *dcrc = dc->dc_ramdac_cookie; 859 int count, error; 860 861 cursorp->which = WSDISPLAY_CURSOR_DOALL & 862 ~(WSDISPLAY_CURSOR_DOHOT | WSDISPLAY_CURSOR_DOCMAP); 863 cursorp->enable = (TGARREG(dc, TGA_REG_VVVR) & 0x04) != 0; 864 cursorp->pos.x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 865 cursorp->pos.y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 866 cursorp->size.x = 64; 867 cursorp->size.y = (TGARREG(dc, TGA_REG_CCBR) >> 10) & 0x3f; 868 869 if (cursorp->image != NULL) { 870 count = (cursorp->size.y * 64 * 2) / NBBY; 871 error = copyout((char *)(dc->dc_vaddr + 872 (TGARREG(dc, TGA_REG_CCBR) & 0x3ff)), 873 cursorp->image, count); 874 if (error) 875 return error; 876 /* No mask */ 877 } 878 error = dcrf->ramdac_get_curcmap(dcrc, cursorp); 879 return error; 880 } 881 882 int 883 tga_builtin_set_curpos(struct tga_devconfig *dc, 884 struct wsdisplay_curpos *curposp) 885 { 886 887 TGAWREG(dc, TGA_REG_CXYR, 888 ((curposp->y & 0xfff) << 12) | (curposp->x & 0xfff)); 889 return 0; 890 } 891 892 int 893 tga_builtin_get_curpos(struct tga_devconfig *dc, 894 struct wsdisplay_curpos *curposp) 895 { 896 897 curposp->x = TGARREG(dc, TGA_REG_CXYR) & 0xfff; 898 curposp->y = (TGARREG(dc, TGA_REG_CXYR) >> 12) & 0xfff; 899 return 0; 900 } 901 902 int 903 tga_builtin_get_curmax(struct tga_devconfig *dc, 904 struct wsdisplay_curpos *curposp) 905 { 906 907 curposp->x = curposp->y = 64; 908 return 0; 909 } 910 911 /* 912 * Copy columns (characters) in a row (line). 913 */ 914 static void 915 tga_copycols(void *id, int row, int srccol, int dstcol, int ncols) 916 { 917 struct rasops_info *ri = id; 918 int y, srcx, dstx, nx; 919 920 y = ri->ri_font->fontheight * row; 921 srcx = ri->ri_font->fontwidth * srccol; 922 dstx = ri->ri_font->fontwidth * dstcol; 923 nx = ri->ri_font->fontwidth * ncols; 924 925 tga_rop(ri, dstx, y, 926 nx, ri->ri_font->fontheight, RAS_SRC, 927 ri, srcx, y); 928 } 929 930 /* 931 * Copy rows (lines). 932 */ 933 static void 934 tga_copyrows(void *id, int srcrow, int dstrow, int nrows) 935 { 936 struct rasops_info *ri = id; 937 int srcy, dsty, ny; 938 939 srcy = ri->ri_font->fontheight * srcrow; 940 dsty = ri->ri_font->fontheight * dstrow; 941 ny = ri->ri_font->fontheight * nrows; 942 943 tga_rop(ri, 0, dsty, 944 ri->ri_emuwidth, ny, RAS_SRC, 945 ri, 0, srcy); 946 } 947 948 /* Do we need the src? */ 949 static const int needsrc[16] = 950 { 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0, 1, 1, 1, 1, 0 }; 951 952 /* A mapping between our API and the TGA card */ 953 static const int map_rop[16] = { 0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 954 0xe, 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf 955 }; 956 957 /* 958 * Generic TGA raster op. 959 * This covers all possible raster ops, and 960 * clips the sizes and all of that. 961 */ 962 static int 963 tga_rop(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 964 struct rasops_info *src, int sx, int sy) 965 { 966 967 if (dst == NULL) 968 return -1; 969 if (needsrc[RAS_GETOP(rop)]) { 970 if (src == NULL) 971 return -1; /* We want a src */ 972 /* Clip against src */ 973 if (sx < 0) { 974 w += sx; 975 sx = 0; 976 } 977 if (sy < 0) { 978 h += sy; 979 sy = 0; 980 } 981 if (sx + w > src->ri_emuwidth) 982 w = src->ri_emuwidth - sx; 983 if (sy + h > src->ri_emuheight) 984 h = src->ri_emuheight - sy; 985 } else { 986 if (src != NULL) 987 return -1; /* We need no src */ 988 } 989 /* Clip against dst. We modify src regardless of using it, 990 * since it really doesn't matter. 991 */ 992 if (dx < 0) { 993 w += dx; 994 sx -= dx; 995 dx = 0; 996 } 997 if (dy < 0) { 998 h += dy; 999 sy -= dy; 1000 dy = 0; 1001 } 1002 if (dx + w > dst->ri_emuwidth) 1003 w = dst->ri_emuwidth - dx; 1004 if (dy + h > dst->ri_emuheight) 1005 h = dst->ri_emuheight - dy; 1006 if (w <= 0 || h <= 0) 1007 return 0; /* Vacuously true; */ 1008 if (src == NULL) { 1009 /* XXX Punt! */ 1010 return -1; 1011 } 1012 return tga_rop_vtov(dst, dx, dy, w, h, rop, src, sx, sy); 1013 } 1014 1015 1016 1017 /* 1018 * Video to Video raster ops. 1019 * This function deals with all raster ops that have a src and dst 1020 * that are on the card. 1021 */ 1022 static int 1023 tga_rop_vtov(struct rasops_info *dst, int dx, int dy, int w, int h, int rop, 1024 struct rasops_info *src, int sx, int sy) 1025 { 1026 struct tga_devconfig *dc = dst->ri_hw; 1027 int srcb, dstb, tga_srcb, tga_dstb; 1028 int x, y, wb; 1029 int xstart, xdir; 1030 int ystart, yend, ydir, yinc; 1031 int xleft, lastx, lastleft; 1032 int offset = 1 * dc->dc_tgaconf->tgac_vvbr_units; 1033 1034 /* 1035 * I don't yet want to deal with unaligned guys, really. And we don't 1036 * deal with copies from one card to another. 1037 */ 1038 if (dx % 8 != 0 || sx % 8 != 0 || src != dst) { 1039 /* XXX Punt! */ 1040 /* XXX should never happen, since it's only being used to 1041 * XXX copy 8-pixel-wide characters. 1042 */ 1043 return -1; 1044 } 1045 1046 srcb = sy * src->ri_stride + sx * (src->ri_depth / 8); 1047 dstb = dy * dst->ri_stride + dx * (dst->ri_depth / 8); 1048 tga_srcb = offset + (sy + src->ri_yorigin) * src->ri_stride + 1049 (sx + src->ri_xorigin) * (src->ri_depth / 8); 1050 tga_dstb = offset + (dy + dst->ri_yorigin) * dst->ri_stride + 1051 (dx + dst->ri_xorigin) * (dst->ri_depth / 8); 1052 1053 if (sy >= dy) { 1054 ystart = 0; 1055 yend = (h - 1) * dst->ri_stride; 1056 ydir = 1; 1057 } else { 1058 ystart = (h - 1) * dst->ri_stride; 1059 yend = 0; 1060 ydir = -1; 1061 } 1062 yinc = ydir * dst->ri_stride; 1063 1064 wb = w * (dst->ri_depth / 8); 1065 if (sx >= dx || (sx + w) <= dx) { /* copy forwards */ 1066 xstart = 0; 1067 xdir = 1; 1068 } else { /* copy backwards */ 1069 xstart = wb; 1070 xdir = -1; 1071 } 1072 1073 TGAWALREG(dc, TGA_REG_GMOR, 3, 0x0007); /* Copy mode */ 1074 TGAWALREG(dc, TGA_REG_GOPR, 3, map_rop[rop]); /* Set up the op */ 1075 TGAWALREG(dc, TGA_REG_GPSR, 3, 0); /* No shift */ 1076 1077 /* 1078 * we have 3 sizes of pixels to move in X direction: 1079 * 4 * 64 (unrolled TGA ops) 1080 * 64 (single TGA op) 1081 * 4 (CPU, using long word) 1082 */ 1083 1084 if (xdir == 1) { /* move to the left */ 1085 1086 if (wb & ~63) 1087 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1088 /* 4 * 64 byte chunks */ 1089 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1090 x += 4 * 64, xleft -= 4 * 64) { 1091 1092 /* 1093 * XXX XXX Eight writes to different addresses 1094 * XXX XXX should fill up the write buffers on 1095 * XXX XXX 21064 and 21164 chips, but later 1096 * XXX XXX CPUs might have larger write buffers 1097 * XXX XXX which require further unrolling of 1098 * XXX XXX this loop, or the insertion of 1099 * XXX XXX memory barriers. 1100 */ 1101 TGAWALREG(dc, TGA_REG_GCSR, 0, 1102 tga_srcb + y + x + 0 * 64); 1103 TGAWALREG(dc, TGA_REG_GCDR, 0, 1104 tga_dstb + y + x + 0 * 64); 1105 TGAWALREG(dc, TGA_REG_GCSR, 1, 1106 tga_srcb + y + x + 1 * 64); 1107 TGAWALREG(dc, TGA_REG_GCDR, 1, 1108 tga_dstb + y + x + 1 * 64); 1109 TGAWALREG(dc, TGA_REG_GCSR, 2, 1110 tga_srcb + y + x + 2 * 64); 1111 TGAWALREG(dc, TGA_REG_GCDR, 2, 1112 tga_dstb + y + x + 2 * 64); 1113 TGAWALREG(dc, TGA_REG_GCSR, 3, 1114 tga_srcb + y + x + 3 * 64); 1115 TGAWALREG(dc, TGA_REG_GCDR, 3, 1116 tga_dstb + y + x + 3 * 64); 1117 } 1118 1119 /* 64 byte chunks */ 1120 for (; xleft >= 64; x += 64, xleft -= 64) { 1121 TGAWALREG(dc, TGA_REG_GCSR, 0, 1122 tga_srcb + y + x + 0 * 64); 1123 TGAWALREG(dc, TGA_REG_GCDR, 0, 1124 tga_dstb + y + x + 0 * 64); 1125 } 1126 } 1127 1128 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1129 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1130 1131 lastleft = wb & 63; 1132 if (lastleft) { 1133 lastx = xstart + (wb & ~63); 1134 for (y = ystart; (ydir * y) <= (ydir * yend); 1135 y += yinc) { 1136 /* 4 byte granularity */ 1137 for (x = lastx, xleft = lastleft; xleft >= 4; 1138 x += 4, xleft -= 4) { 1139 *(uint32_t *)(dst->ri_bits + dstb + 1140 y + x + 0 * 4) = 1141 *(uint32_t *)(dst->ri_bits + srcb + 1142 y + x + 0 * 4); 1143 } 1144 } 1145 } 1146 } else { /* above move to the left, below move to the right */ 1147 1148 if (wb & ~63) 1149 for (y = ystart; (ydir * y) <= (ydir * yend); y += yinc) { 1150 /* 4 * 64 byte chunks */ 1151 for (xleft = wb, x = xstart; xleft >= 4 * 64; 1152 x -= 4 * 64, xleft -= 4 * 64) { 1153 1154 /* 1155 * XXX XXX Eight writes to different addresses 1156 * XXX XXX should fill up the write buffers on 1157 * XXX XXX 21064 and 21164 chips, but later 1158 * XXX XXX CPUs might have larger write buffers 1159 * XXX XXX which require further unrolling of 1160 * XXX XXX this loop, or the insertion of 1161 * XXX XXX memory barriers. 1162 */ 1163 TGAWALREG(dc, TGA_REG_GCSR, 0, 1164 tga_srcb + y + x - 1 * 64); 1165 TGAWALREG(dc, TGA_REG_GCDR, 0, 1166 tga_dstb + y + x - 1 * 64); 1167 TGAWALREG(dc, TGA_REG_GCSR, 1, 1168 tga_srcb + y + x - 2 * 64); 1169 TGAWALREG(dc, TGA_REG_GCDR, 1, 1170 tga_dstb + y + x - 2 * 64); 1171 TGAWALREG(dc, TGA_REG_GCSR, 2, 1172 tga_srcb + y + x - 3 * 64); 1173 TGAWALREG(dc, TGA_REG_GCDR, 2, 1174 tga_dstb + y + x - 3 * 64); 1175 TGAWALREG(dc, TGA_REG_GCSR, 3, 1176 tga_srcb + y + x - 4 * 64); 1177 TGAWALREG(dc, TGA_REG_GCDR, 3, 1178 tga_dstb + y + x - 4 * 64); 1179 } 1180 1181 /* 64 byte chunks */ 1182 for (; xleft >= 64; x -= 64, xleft -= 64) { 1183 TGAWALREG(dc, TGA_REG_GCSR, 0, 1184 tga_srcb + y + x - 1 * 64); 1185 TGAWALREG(dc, TGA_REG_GCDR, 0, 1186 tga_dstb + y + x - 1 * 64); 1187 } 1188 } 1189 1190 TGAWALREG(dc, TGA_REG_GOPR, 0, 0x0003); /* op -> dst = src */ 1191 TGAWALREG(dc, TGA_REG_GMOR, 0, 0x0000); /* Simple mode */ 1192 1193 lastleft = wb & 63; 1194 if (lastleft) { 1195 lastx = xstart - (wb & ~63); 1196 for (y = ystart; (ydir * y) <= (ydir * yend); 1197 y += yinc) { 1198 /* 4 byte granularity */ 1199 for (x = lastx, xleft = lastleft; xleft >= 4; 1200 x -= 4, xleft -= 4) { 1201 *(uint32_t *)(dst->ri_bits + dstb + 1202 y + x - 1 * 4) = 1203 *(uint32_t *)(dst->ri_bits + srcb + 1204 y + x - 1 * 4); 1205 } 1206 } 1207 } 1208 } 1209 return 0; 1210 } 1211 1212 1213 void tga_putchar(void *c, int row, int col, u_int uc, long attr) 1214 { 1215 struct rasops_info *ri = c; 1216 struct tga_devconfig *dc = ri->ri_hw; 1217 int fs, height, width; 1218 uint8_t *fr; 1219 int32_t *rp; 1220 1221 rp = (int32_t *)(ri->ri_bits + 1222 row * ri->ri_yscale + col * ri->ri_xscale); 1223 1224 height = ri->ri_font->fontheight; 1225 width = ri->ri_font->fontwidth; 1226 1227 uc -= ri->ri_font->firstchar; 1228 fr = (uint8_t *)ri->ri_font->data + uc * ri->ri_fontscale; 1229 fs = ri->ri_font->stride; 1230 1231 /* Set foreground and background color. XXX memoize this somehow? 1232 * The rasops code has already expanded the color entry to 32 bits 1233 * for us, even for 8-bit displays, so we don't have to do anything. 1234 */ 1235 TGAWREG(dc, TGA_REG_GFGR, ri->ri_devcmap[(attr >> 24) & 15]); 1236 TGAWREG(dc, TGA_REG_GBGR, ri->ri_devcmap[(attr >> 16) & 15]); 1237 1238 /* Set raster operation to "copy"... */ 1239 if (ri->ri_depth == 8) 1240 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1241 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1242 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1243 1244 /* Set which pixels we're drawing (of a possible 32). */ 1245 TGAWREG(dc, TGA_REG_GPXR_P, (1 << width) - 1); 1246 1247 /* Set drawing mode to opaque stipple. */ 1248 TGAWREG(dc, TGA_REG_GMOR, 0x1); 1249 1250 /* Insert write barrier before actually sending data */ 1251 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1252 TGAREGWB(dc, TGA_REG_GMOR, 1); 1253 1254 while (height--) { 1255 /* The actual stipple write */ 1256 *rp = fr[0] | (fr[1] << 8) | (fr[2] << 16) | (fr[3] << 24); 1257 1258 fr += fs; 1259 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1260 } 1261 1262 /* Do underline */ 1263 if ((attr & 1) != 0) { 1264 rp = (int32_t *)((uint8_t *)rp - (ri->ri_stride << 1)); 1265 *rp = 0xffffffff; 1266 } 1267 1268 /* Set grapics mode back to normal. */ 1269 TGAWREG(dc, TGA_REG_GMOR, 0); 1270 TGAWREG(dc, TGA_REG_GPXR_P, 0xffffffff); 1271 } 1272 1273 static void 1274 tga_eraserows(void *c, int row, int num, long attr) 1275 { 1276 struct rasops_info *ri = c; 1277 struct tga_devconfig *dc = ri->ri_hw; 1278 int32_t color, lines, pixels; 1279 int32_t *rp; 1280 1281 color = ri->ri_devcmap[(attr >> 16) & 15]; 1282 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale); 1283 lines = num * ri->ri_font->fontheight; 1284 pixels = ri->ri_emuwidth - 1; 1285 1286 /* Set fill color in block-color registers */ 1287 TGAWREG(dc, TGA_REG_GBCR0, color); 1288 TGAWREG(dc, TGA_REG_GBCR1, color); 1289 if (ri->ri_depth != 8) { 1290 TGAWREG(dc, TGA_REG_GBCR2, color); 1291 TGAWREG(dc, TGA_REG_GBCR3, color); 1292 TGAWREG(dc, TGA_REG_GBCR4, color); 1293 TGAWREG(dc, TGA_REG_GBCR5, color); 1294 TGAWREG(dc, TGA_REG_GBCR6, color); 1295 TGAWREG(dc, TGA_REG_GBCR7, color); 1296 } 1297 1298 /* Set raster operation to "copy"... */ 1299 if (ri->ri_depth == 8) 1300 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1301 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1302 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1303 1304 /* Set which pixels we're drawing (of a possible 32). */ 1305 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1306 1307 /* Set drawing mode to block fill. */ 1308 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1309 1310 /* Insert write barrier before actually sending data */ 1311 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1312 TGAREGWB(dc, TGA_REG_GMOR, 1); 1313 1314 while (lines--) { 1315 *rp = pixels; 1316 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1317 } 1318 1319 /* Set grapics mode back to normal. */ 1320 TGAWREG(dc, TGA_REG_GMOR, 0); 1321 } 1322 1323 static void 1324 tga_erasecols (void *c, int row, int col, int num, long attr) 1325 { 1326 struct rasops_info *ri = c; 1327 struct tga_devconfig *dc = ri->ri_hw; 1328 int32_t color, lines, pixels; 1329 int32_t *rp; 1330 1331 color = ri->ri_devcmap[(attr >> 16) & 15]; 1332 rp = (int32_t *)(ri->ri_bits + row*ri->ri_yscale + col*ri->ri_xscale); 1333 lines = ri->ri_font->fontheight; 1334 pixels = (num * ri->ri_font->fontwidth) - 1; 1335 1336 /* Set fill color in block-color registers */ 1337 TGAWREG(dc, TGA_REG_GBCR0, color); 1338 TGAWREG(dc, TGA_REG_GBCR1, color); 1339 if (ri->ri_depth != 8) { 1340 TGAWREG(dc, TGA_REG_GBCR2, color); 1341 TGAWREG(dc, TGA_REG_GBCR3, color); 1342 TGAWREG(dc, TGA_REG_GBCR4, color); 1343 TGAWREG(dc, TGA_REG_GBCR5, color); 1344 TGAWREG(dc, TGA_REG_GBCR6, color); 1345 TGAWREG(dc, TGA_REG_GBCR7, color); 1346 } 1347 1348 /* Set raster operation to "copy"... */ 1349 if (ri->ri_depth == 8) 1350 TGAWREG(dc, TGA_REG_GOPR, 0x3); 1351 else /* ... and in 24-bit mode, set the destination bitmap to 24-bit. */ 1352 TGAWREG(dc, TGA_REG_GOPR, 0x3 | (0x3 << 8)); 1353 1354 /* Set which pixels we're drawing (of a possible 32). */ 1355 TGAWREG(dc, TGA_REG_GDAR, 0xffffffff); 1356 1357 /* Set drawing mode to block fill. */ 1358 TGAWREG(dc, TGA_REG_GMOR, 0x2d); 1359 1360 /* Insert write barrier before actually sending data */ 1361 /* XXX Abuses the fact that there is only one write barrier on Alphas */ 1362 TGAREGWB(dc, TGA_REG_GMOR, 1); 1363 1364 while (lines--) { 1365 *rp = pixels; 1366 rp = (int32_t *)((uint8_t *)rp + ri->ri_stride); 1367 } 1368 1369 /* Set grapics mode back to normal. */ 1370 TGAWREG(dc, TGA_REG_GMOR, 0); 1371 } 1372 1373 1374 static void 1375 tga_ramdac_wr(void *v, u_int btreg, uint8_t val) 1376 { 1377 struct tga_devconfig *dc = v; 1378 1379 if (btreg > BT485_REG_MAX) 1380 panic("tga_ramdac_wr: reg %d out of range", btreg); 1381 1382 TGAWREG(dc, TGA_REG_EPDR, (btreg << 9) | (0 << 8 ) | val); /* XXX */ 1383 TGAREGWB(dc, TGA_REG_EPDR, 1); 1384 } 1385 1386 static void 1387 tga2_ramdac_wr(void *v, u_int btreg, uint8_t val) 1388 { 1389 struct tga_devconfig *dc = v; 1390 bus_space_handle_t ramdac; 1391 1392 if (btreg > BT485_REG_MAX) 1393 panic("tga_ramdac_wr: reg %d out of range", btreg); 1394 1395 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1396 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1397 bus_space_write_4(dc->dc_memt, ramdac, 0, val & 0xff); 1398 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_WRITE); 1399 } 1400 1401 static uint8_t 1402 tga_bt463_rd(void *v, u_int btreg) 1403 { 1404 struct tga_devconfig *dc = v; 1405 tga_reg_t rdval; 1406 1407 /* 1408 * Strobe CE# (high->low->high) since status and data are latched on 1409 * the falling and rising edges (repsectively) of this active-low 1410 * signal. 1411 */ 1412 1413 TGAREGWB(dc, TGA_REG_EPSR, 1); 1414 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1415 TGAREGWB(dc, TGA_REG_EPSR, 1); 1416 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 0); 1417 1418 TGAREGRB(dc, TGA_REG_EPSR, 1); 1419 1420 rdval = TGARREG(dc, TGA_REG_EPDR); 1421 TGAREGWB(dc, TGA_REG_EPSR, 1); 1422 TGAWREG(dc, TGA_REG_EPSR, (btreg << 2) | 2 | 1); 1423 1424 return (rdval >> 16) & 0xff; 1425 } 1426 1427 static void 1428 tga_bt463_wr(void *v, u_int btreg, uint8_t val) 1429 { 1430 struct tga_devconfig *dc = v; 1431 1432 /* 1433 * In spite of the 21030 documentation, to set the MPU bus bits for 1434 * a write, you set them in the upper bits of EPDR, not EPSR. 1435 */ 1436 1437 /* 1438 * Strobe CE# (high->low->high) since status and data are latched on 1439 * the falling and rising edges of this active-low signal. 1440 */ 1441 1442 TGAREGWB(dc, TGA_REG_EPDR, 1); 1443 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1444 TGAREGWB(dc, TGA_REG_EPDR, 1); 1445 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x000 | val); 1446 TGAREGWB(dc, TGA_REG_EPDR, 1); 1447 TGAWREG(dc, TGA_REG_EPDR, (btreg << 10) | 0x100 | val); 1448 } 1449 1450 static uint8_t 1451 tga_ramdac_rd(void *v, u_int btreg) 1452 { 1453 struct tga_devconfig *dc = v; 1454 tga_reg_t rdval; 1455 1456 if (btreg > BT485_REG_MAX) 1457 panic("tga_ramdac_rd: reg %d out of range", btreg); 1458 1459 TGAWREG(dc, TGA_REG_EPSR, (btreg << 1) | 0x1); /* XXX */ 1460 TGAREGWB(dc, TGA_REG_EPSR, 1); 1461 1462 rdval = TGARREG(dc, TGA_REG_EPDR); 1463 return (rdval >> 16) & 0xff; /* XXX */ 1464 } 1465 1466 static uint8_t 1467 tga2_ramdac_rd(void *v, u_int btreg) 1468 { 1469 struct tga_devconfig *dc = v; 1470 bus_space_handle_t ramdac; 1471 uint8_t retval; 1472 1473 if (btreg > BT485_REG_MAX) 1474 panic("tga_ramdac_rd: reg %d out of range", btreg); 1475 1476 bus_space_subregion(dc->dc_memt, dc->dc_memh, 1477 TGA2_MEM_RAMDAC + (0xe << 12) + (btreg << 8), 4, &ramdac); 1478 retval = bus_space_read_4(dc->dc_memt, ramdac, 0) & 0xff; 1479 bus_space_barrier(dc->dc_memt, ramdac, 0, 4, BUS_SPACE_BARRIER_READ); 1480 return retval; 1481 } 1482 1483 #include <dev/ic/decmonitors.c> 1484 void tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock); 1485 1486 struct monitor *tga_getmonitor(struct tga_devconfig *dc); 1487 1488 void 1489 tga2_init(struct tga_devconfig *dc) 1490 { 1491 struct monitor *m = tga_getmonitor(dc); 1492 1493 /* Deal with the dot clocks. 1494 */ 1495 if (dc->dc_tga_type == TGA_TYPE_POWERSTORM_4D20) { 1496 /* 1497 * Set this up as a reference clock for the 1498 * ibm561's PLL. 1499 */ 1500 tga2_ics9110_wr(dc, 14300000); 1501 /* 1502 * XXX Can't set up the dotclock properly, until such time 1503 * as the RAMDAC is configured. 1504 */ 1505 } else { 1506 /* otherwise the ics9110 is our clock. */ 1507 tga2_ics9110_wr(dc, m->dotclock); 1508 } 1509 #if 0 1510 TGAWREG(dc, TGA_REG_VHCR, 1511 ((m->hbp / 4) << 21) | 1512 ((m->hsync / 4) << 14) | 1513 (((m->hfp - 4) / 4) << 9) | 1514 ((m->cols + 4) / 4)); 1515 #else 1516 TGAWREG(dc, TGA_REG_VHCR, 1517 ((m->hbp / 4) << 21) | 1518 ((m->hsync / 4) << 14) | 1519 (((m->hfp) / 4) << 9) | 1520 ((m->cols) / 4)); 1521 #endif 1522 TGAWREG(dc, TGA_REG_VVCR, 1523 (m->vbp << 22) | 1524 (m->vsync << 16) | 1525 (m->vfp << 11) | 1526 (m->rows)); 1527 TGAWREG(dc, TGA_REG_VVBR, 1); 1528 TGAREGRWB(dc, TGA_REG_VHCR, 3); 1529 TGAWREG(dc, TGA_REG_VVVR, TGARREG(dc, TGA_REG_VVVR) | 1); 1530 TGAREGRWB(dc, TGA_REG_VVVR, 1); 1531 TGAWREG(dc, TGA_REG_GPMR, 0xffffffff); 1532 TGAREGRWB(dc, TGA_REG_GPMR, 1); 1533 } 1534 1535 void 1536 tga2_ics9110_wr(struct tga_devconfig *dc, int dotclock) 1537 { 1538 bus_space_handle_t clock; 1539 uint32_t valU; 1540 int N, M, R, V, X; 1541 int i; 1542 1543 switch (dotclock) { 1544 case 130808000: 1545 N = 0x40; M = 0x7; V = 0x0; X = 0x1; R = 0x1; break; 1546 case 119840000: 1547 N = 0x2d; M = 0x2b; V = 0x1; X = 0x1; R = 0x1; break; 1548 case 108180000: 1549 N = 0x11; M = 0x9; V = 0x1; X = 0x1; R = 0x2; break; 1550 case 103994000: 1551 N = 0x6d; M = 0xf; V = 0x0; X = 0x1; R = 0x1; break; 1552 case 175000000: 1553 N = 0x5F; M = 0x3E; V = 0x1; X = 0x1; R = 0x1; break; 1554 case 75000000: 1555 N = 0x6e; M = 0x15; V = 0x0; X = 0x1; R = 0x1; break; 1556 case 74000000: 1557 N = 0x2a; M = 0x41; V = 0x1; X = 0x1; R = 0x1; break; 1558 case 69000000: 1559 N = 0x35; M = 0xb; V = 0x0; X = 0x1; R = 0x1; break; 1560 case 65000000: 1561 N = 0x6d; M = 0x0c; V = 0x0; X = 0x1; R = 0x2; break; 1562 case 50000000: 1563 N = 0x37; M = 0x3f; V = 0x1; X = 0x1; R = 0x2; break; 1564 case 40000000: 1565 N = 0x5f; M = 0x11; V = 0x0; X = 0x1; R = 0x2; break; 1566 case 31500000: 1567 N = 0x16; M = 0x05; V = 0x0; X = 0x1; R = 0x2; break; 1568 case 25175000: 1569 N = 0x66; M = 0x1d; V = 0x0; X = 0x1; R = 0x2; break; 1570 case 135000000: 1571 N = 0x42; M = 0x07; V = 0x0; X = 0x1; R = 0x1; break; 1572 case 110000000: 1573 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1574 case 202500000: 1575 N = 0x60; M = 0x32; V = 0x1; X = 0x1; R = 0x2; break; 1576 case 14300000: /* this one is just a ref clock */ 1577 N = 0x03; M = 0x03; V = 0x1; X = 0x1; R = 0x3; break; 1578 default: 1579 panic("unrecognized clock rate %d", dotclock); 1580 } 1581 1582 /* XXX -- hard coded, bad */ 1583 valU = N | ( M << 7 ) | (V << 14); 1584 valU |= (X << 15) | (R << 17); 1585 valU |= 0x17 << 19; 1586 1587 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1588 TGA2_MEM_CLOCK + (0xe << 12), 4, &clock); /* XXX */ 1589 1590 for (i = 24; i > 0; i--) { 1591 uint32_t writeval; 1592 1593 writeval = valU & 0x1; 1594 if (i == 1) 1595 writeval |= 0x2; 1596 valU >>= 1; 1597 bus_space_write_4(dc->dc_memt, clock, 0, writeval); 1598 bus_space_barrier(dc->dc_memt, clock, 0, 4, 1599 BUS_SPACE_BARRIER_WRITE); 1600 } 1601 bus_space_subregion(dc->dc_memt, dc->dc_memh, TGA2_MEM_EXTDEV + 1602 TGA2_MEM_CLOCK + (0xe << 12) + (0x1 << 11) + (0x1 << 11), 4, 1603 &clock); /* XXX */ 1604 bus_space_write_4(dc->dc_memt, clock, 0, 0x0); 1605 bus_space_barrier(dc->dc_memt, clock, 0, 0, BUS_SPACE_BARRIER_WRITE); 1606 } 1607 1608 struct monitor * 1609 tga_getmonitor(struct tga_devconfig *dc) 1610 { 1611 1612 return &decmonitors[(~TGARREG(dc, TGA_REG_GREV) >> 16) & 0x0f]; 1613 } 1614 1615 unsigned int 1616 tga_getdotclock(struct tga_devconfig *dc) 1617 { 1618 1619 return tga_getmonitor(dc)->dotclock; 1620 } 1621
Indexes created Tue Sep 23 21:09:50 GMT 2025