trm.c revision 1.4.2.5
1 1.4.2.5 nathanw /* $NetBSD: trm.c,v 1.4.2.5 2002/04/17 00:06:06 nathanw Exp $ */ 2 1.4.2.2 nathanw /* 3 1.4.2.2 nathanw * Device Driver for Tekram DC395U/UW/F, DC315/U 4 1.4.2.2 nathanw * PCI SCSI Bus Master Host Adapter 5 1.4.2.2 nathanw * (SCSI chip set used Tekram ASIC TRM-S1040) 6 1.4.2.2 nathanw * 7 1.4.2.4 nathanw * Copyright (c) 2002 Izumi Tsutsui 8 1.4.2.2 nathanw * Copyright (c) 2001 Rui-Xiang Guo 9 1.4.2.2 nathanw * All rights reserved. 10 1.4.2.2 nathanw * 11 1.4.2.2 nathanw * Redistribution and use in source and binary forms, with or without 12 1.4.2.2 nathanw * modification, are permitted provided that the following conditions 13 1.4.2.2 nathanw * are met: 14 1.4.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 15 1.4.2.2 nathanw * notice, this list of conditions and the following disclaimer. 16 1.4.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 17 1.4.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 18 1.4.2.2 nathanw * documentation and/or other materials provided with the distribution. 19 1.4.2.2 nathanw * 3. The name of the author may not be used to endorse or promote products 20 1.4.2.2 nathanw * derived from this software without specific prior written permission. 21 1.4.2.2 nathanw * 22 1.4.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 1.4.2.2 nathanw * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 1.4.2.2 nathanw * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.4.2.2 nathanw * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 1.4.2.2 nathanw * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 1.4.2.2 nathanw * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 1.4.2.2 nathanw * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 1.4.2.2 nathanw * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 1.4.2.2 nathanw * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 1.4.2.2 nathanw * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 1.4.2.2 nathanw */ 33 1.4.2.2 nathanw /* 34 1.4.2.2 nathanw * Ported from 35 1.4.2.2 nathanw * dc395x_trm.c 36 1.4.2.2 nathanw * 37 1.4.2.2 nathanw * Written for NetBSD 1.4.x by 38 1.4.2.2 nathanw * Erich Chen (erich (at) tekram.com.tw) 39 1.4.2.2 nathanw * 40 1.4.2.2 nathanw * Provided by 41 1.4.2.2 nathanw * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 1.4.2.2 nathanw */ 43 1.4.2.2 nathanw 44 1.4.2.2 nathanw #include <sys/cdefs.h> 45 1.4.2.5 nathanw __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.4.2.5 2002/04/17 00:06:06 nathanw Exp $"); 46 1.4.2.2 nathanw 47 1.4.2.2 nathanw /* #define TRM_DEBUG */ 48 1.4.2.4 nathanw #ifdef TRM_DEBUG 49 1.4.2.4 nathanw int trm_debug = 1; 50 1.4.2.4 nathanw #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 1.4.2.4 nathanw #else 52 1.4.2.4 nathanw #define DPRINTF(arg) 53 1.4.2.4 nathanw #endif 54 1.4.2.2 nathanw 55 1.4.2.2 nathanw #include <sys/param.h> 56 1.4.2.2 nathanw #include <sys/systm.h> 57 1.4.2.2 nathanw #include <sys/malloc.h> 58 1.4.2.2 nathanw #include <sys/buf.h> 59 1.4.2.2 nathanw #include <sys/kernel.h> 60 1.4.2.2 nathanw #include <sys/device.h> 61 1.4.2.4 nathanw #include <sys/queue.h> 62 1.4.2.2 nathanw 63 1.4.2.2 nathanw #include <machine/bus.h> 64 1.4.2.2 nathanw #include <machine/intr.h> 65 1.4.2.2 nathanw 66 1.4.2.2 nathanw #include <uvm/uvm_extern.h> 67 1.4.2.2 nathanw 68 1.4.2.2 nathanw #include <dev/scsipi/scsi_all.h> 69 1.4.2.2 nathanw #include <dev/scsipi/scsi_message.h> 70 1.4.2.2 nathanw #include <dev/scsipi/scsipi_all.h> 71 1.4.2.2 nathanw #include <dev/scsipi/scsiconf.h> 72 1.4.2.2 nathanw 73 1.4.2.2 nathanw #include <dev/pci/pcidevs.h> 74 1.4.2.2 nathanw #include <dev/pci/pcireg.h> 75 1.4.2.2 nathanw #include <dev/pci/pcivar.h> 76 1.4.2.2 nathanw #include <dev/pci/trmreg.h> 77 1.4.2.2 nathanw 78 1.4.2.2 nathanw /* 79 1.4.2.2 nathanw * feature of chip set MAX value 80 1.4.2.2 nathanw */ 81 1.4.2.2 nathanw #define TRM_MAX_TARGETS 16 82 1.4.2.4 nathanw #define TRM_MAX_LUNS 8 83 1.4.2.2 nathanw #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 1.4.2.4 nathanw #define TRM_MAX_SRB 32 /* XXX */ 85 1.4.2.4 nathanw #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 1.4.2.4 nathanw #define TRM_MAX_OFFSET 15 87 1.4.2.4 nathanw #define TRM_MAX_PERIOD 125 88 1.4.2.2 nathanw 89 1.4.2.2 nathanw /* 90 1.4.2.2 nathanw * Segment Entry 91 1.4.2.2 nathanw */ 92 1.4.2.2 nathanw struct trm_sg_entry { 93 1.4.2.2 nathanw u_int32_t address; 94 1.4.2.2 nathanw u_int32_t length; 95 1.4.2.2 nathanw }; 96 1.4.2.2 nathanw 97 1.4.2.2 nathanw #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 1.4.2.2 nathanw 99 1.4.2.2 nathanw /* 100 1.4.2.2 nathanw ********************************************************************** 101 1.4.2.2 nathanw * The SEEPROM structure for TRM_S1040 102 1.4.2.2 nathanw ********************************************************************** 103 1.4.2.2 nathanw */ 104 1.4.2.2 nathanw struct nvram_target { 105 1.4.2.2 nathanw u_int8_t config0; /* Target configuration byte 0 */ 106 1.4.2.2 nathanw #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 1.4.2.4 nathanw #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 1.4.2.2 nathanw #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 1.4.2.2 nathanw #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 1.4.2.2 nathanw #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 1.4.2.3 nathanw #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 1.4.2.2 nathanw u_int8_t period; /* Target period */ 113 1.4.2.2 nathanw u_int8_t config2; /* Target configuration byte 2 */ 114 1.4.2.2 nathanw u_int8_t config3; /* Target configuration byte 3 */ 115 1.4.2.2 nathanw }; 116 1.4.2.2 nathanw 117 1.4.2.2 nathanw struct trm_nvram { 118 1.4.2.2 nathanw u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 1.4.2.2 nathanw u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 1.4.2.2 nathanw u_int8_t subclass; /* 4 Sub Class */ 121 1.4.2.2 nathanw u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 1.4.2.2 nathanw u_int8_t device_id[2]; /* 7,8 Device ID */ 123 1.4.2.2 nathanw u_int8_t reserved0; /* 9 Reserved */ 124 1.4.2.2 nathanw struct nvram_target target[TRM_MAX_TARGETS]; 125 1.4.2.2 nathanw /* 10,11,12,13 126 1.4.2.2 nathanw * 14,15,16,17 127 1.4.2.2 nathanw * .... 128 1.4.2.2 nathanw * 70,71,72,73 */ 129 1.4.2.2 nathanw u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 1.4.2.2 nathanw u_int8_t channel_cfg; /* 75 Channel configuration */ 131 1.4.2.2 nathanw #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 1.4.2.2 nathanw #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 1.4.2.2 nathanw #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 1.4.2.2 nathanw #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 1.4.2.2 nathanw #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 1.4.2.2 nathanw u_int8_t delay_time; /* 76 Power on delay time */ 137 1.4.2.2 nathanw u_int8_t max_tag; /* 77 Maximum tags */ 138 1.4.2.2 nathanw u_int8_t reserved1; /* 78 */ 139 1.4.2.2 nathanw u_int8_t boot_target; /* 79 */ 140 1.4.2.2 nathanw u_int8_t boot_lun; /* 80 */ 141 1.4.2.2 nathanw u_int8_t reserved2; /* 81 */ 142 1.4.2.2 nathanw u_int8_t reserved3[44]; /* 82,..125 */ 143 1.4.2.2 nathanw u_int8_t checksum0; /* 126 */ 144 1.4.2.2 nathanw u_int8_t checksum1; /* 127 */ 145 1.4.2.2 nathanw #define TRM_NVRAM_CKSUM 0x1234 146 1.4.2.2 nathanw }; 147 1.4.2.2 nathanw 148 1.4.2.2 nathanw /* Nvram Initiater bits definition */ 149 1.4.2.2 nathanw #define MORE2_DRV 0x00000001 150 1.4.2.2 nathanw #define GREATER_1G 0x00000002 151 1.4.2.2 nathanw #define RST_SCSI_BUS 0x00000004 152 1.4.2.2 nathanw #define ACTIVE_NEGATION 0x00000008 153 1.4.2.2 nathanw #define NO_SEEK 0x00000010 154 1.4.2.2 nathanw #define LUN_CHECK 0x00000020 155 1.4.2.2 nathanw 156 1.4.2.4 nathanw #define trm_eeprom_wait() DELAY(30) 157 1.4.2.2 nathanw 158 1.4.2.2 nathanw /* 159 1.4.2.2 nathanw *----------------------------------------------------------------------- 160 1.4.2.2 nathanw * SCSI Request Block 161 1.4.2.2 nathanw *----------------------------------------------------------------------- 162 1.4.2.2 nathanw */ 163 1.4.2.2 nathanw struct trm_srb { 164 1.4.2.4 nathanw TAILQ_ENTRY(trm_srb) next; 165 1.4.2.2 nathanw 166 1.4.2.2 nathanw struct trm_sg_entry *sgentry; 167 1.4.2.3 nathanw struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 1.4.2.2 nathanw bus_dmamap_t dmap; 169 1.4.2.2 nathanw bus_size_t sgoffset; /* Xfer buf offset */ 170 1.4.2.2 nathanw 171 1.4.2.2 nathanw u_int32_t buflen; /* Total xfer length */ 172 1.4.2.2 nathanw u_int32_t sgaddr; /* SGList physical starting address */ 173 1.4.2.2 nathanw 174 1.4.2.2 nathanw int sgcnt; 175 1.4.2.2 nathanw int sgindex; 176 1.4.2.2 nathanw 177 1.4.2.2 nathanw int hastat; /* Host Adapter Status */ 178 1.4.2.2 nathanw #define H_STATUS_GOOD 0x00 179 1.4.2.2 nathanw #define H_SEL_TIMEOUT 0x11 180 1.4.2.2 nathanw #define H_OVER_UNDER_RUN 0x12 181 1.4.2.2 nathanw #define H_UNEXP_BUS_FREE 0x13 182 1.4.2.2 nathanw #define H_TARGET_PHASE_F 0x14 183 1.4.2.2 nathanw #define H_INVALID_CCB_OP 0x16 184 1.4.2.2 nathanw #define H_LINK_CCB_BAD 0x17 185 1.4.2.2 nathanw #define H_BAD_TARGET_DIR 0x18 186 1.4.2.2 nathanw #define H_DUPLICATE_CCB 0x19 187 1.4.2.2 nathanw #define H_BAD_CCB_OR_SG 0x1A 188 1.4.2.2 nathanw #define H_ABORT 0xFF 189 1.4.2.2 nathanw int tastat; /* Target SCSI Status Byte */ 190 1.4.2.2 nathanw int flag; /* SRBFlag */ 191 1.4.2.2 nathanw #define AUTO_REQSENSE 0x0001 192 1.4.2.4 nathanw #define PARITY_ERROR 0x0002 193 1.4.2.4 nathanw #define SRB_TIMEOUT 0x0004 194 1.4.2.2 nathanw 195 1.4.2.2 nathanw int cmdlen; /* SCSI command length */ 196 1.4.2.2 nathanw u_int8_t cmd[12]; /* SCSI command */ 197 1.4.2.2 nathanw 198 1.4.2.4 nathanw u_int8_t tag[2]; 199 1.4.2.2 nathanw }; 200 1.4.2.2 nathanw 201 1.4.2.2 nathanw /* 202 1.4.2.4 nathanw * some info about each target and lun on the SCSI bus 203 1.4.2.2 nathanw */ 204 1.4.2.4 nathanw struct trm_linfo { 205 1.4.2.4 nathanw int used; /* number of slots in use */ 206 1.4.2.4 nathanw int avail; /* where to start scanning */ 207 1.4.2.4 nathanw int busy; /* lun in use */ 208 1.4.2.4 nathanw struct trm_srb *untagged; 209 1.4.2.4 nathanw struct trm_srb *queued[TRM_MAX_TAG]; 210 1.4.2.4 nathanw }; 211 1.4.2.2 nathanw 212 1.4.2.4 nathanw struct trm_tinfo { 213 1.4.2.4 nathanw u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 1.4.2.4 nathanw #define SYNC_NEGO_ENABLE 0x0001 215 1.4.2.4 nathanw #define SYNC_NEGO_DOING 0x0002 216 1.4.2.4 nathanw #define SYNC_NEGO_DONE 0x0004 217 1.4.2.4 nathanw #define WIDE_NEGO_ENABLE 0x0008 218 1.4.2.4 nathanw #define WIDE_NEGO_DOING 0x0010 219 1.4.2.4 nathanw #define WIDE_NEGO_DONE 0x0020 220 1.4.2.4 nathanw #define USE_TAG_QUEUING 0x0040 221 1.4.2.4 nathanw #define NO_RESELECT 0x0080 222 1.4.2.4 nathanw struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 1.4.2.2 nathanw 224 1.4.2.4 nathanw u_int8_t config0; /* Target Config */ 225 1.4.2.2 nathanw u_int8_t period; /* Max Period for nego. */ 226 1.4.2.2 nathanw u_int8_t synctl; /* Sync control for reg. */ 227 1.4.2.2 nathanw u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 1.4.2.2 nathanw }; 229 1.4.2.2 nathanw 230 1.4.2.2 nathanw /* 231 1.4.2.2 nathanw *----------------------------------------------------------------------- 232 1.4.2.2 nathanw * Adapter Control Block 233 1.4.2.2 nathanw *----------------------------------------------------------------------- 234 1.4.2.2 nathanw */ 235 1.4.2.2 nathanw struct trm_softc { 236 1.4.2.2 nathanw struct device sc_dev; 237 1.4.2.2 nathanw 238 1.4.2.2 nathanw bus_space_tag_t sc_iot; 239 1.4.2.2 nathanw bus_space_handle_t sc_ioh; 240 1.4.2.2 nathanw bus_dma_tag_t sc_dmat; 241 1.4.2.2 nathanw bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 1.4.2.2 nathanw 243 1.4.2.4 nathanw struct trm_srb *sc_actsrb; 244 1.4.2.4 nathanw struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 1.4.2.2 nathanw 246 1.4.2.4 nathanw TAILQ_HEAD(, trm_srb) sc_freesrb, 247 1.4.2.4 nathanw sc_readysrb; 248 1.4.2.2 nathanw struct trm_srb *sc_srb; /* SRB array */ 249 1.4.2.2 nathanw 250 1.4.2.2 nathanw struct trm_sg_entry *sc_sglist; 251 1.4.2.2 nathanw 252 1.4.2.4 nathanw int sc_maxid; 253 1.4.2.2 nathanw /* 254 1.4.2.2 nathanw * Link to the generic SCSI driver 255 1.4.2.2 nathanw */ 256 1.4.2.2 nathanw struct scsipi_channel sc_channel; 257 1.4.2.2 nathanw struct scsipi_adapter sc_adapter; 258 1.4.2.2 nathanw 259 1.4.2.2 nathanw int sc_id; /* Adapter SCSI Target ID */ 260 1.4.2.2 nathanw 261 1.4.2.4 nathanw int sc_state; /* SRB State */ 262 1.4.2.4 nathanw #define TRM_IDLE 0 263 1.4.2.4 nathanw #define TRM_WAIT 1 264 1.4.2.4 nathanw #define TRM_READY 2 265 1.4.2.4 nathanw #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 1.4.2.4 nathanw #define TRM_MSGIN 4 267 1.4.2.4 nathanw #define TRM_EXTEND_MSGIN 5 268 1.4.2.4 nathanw #define TRM_COMMAND 6 269 1.4.2.4 nathanw #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 1.4.2.4 nathanw #define TRM_DISCONNECTED 8 271 1.4.2.4 nathanw #define TRM_DATA_XFER 9 272 1.4.2.4 nathanw #define TRM_XFERPAD 10 273 1.4.2.4 nathanw #define TRM_STATUS 11 274 1.4.2.4 nathanw #define TRM_COMPLETED 12 275 1.4.2.4 nathanw #define TRM_ABORT_SENT 13 276 1.4.2.4 nathanw #define TRM_UNEXPECT_RESEL 14 277 1.4.2.2 nathanw 278 1.4.2.4 nathanw int sc_phase; /* SCSI phase */ 279 1.4.2.2 nathanw int sc_config; 280 1.4.2.4 nathanw #define HCC_WIDE_CARD 0x01 281 1.4.2.4 nathanw #define HCC_SCSI_RESET 0x02 282 1.4.2.4 nathanw #define HCC_PARITY 0x04 283 1.4.2.4 nathanw #define HCC_AUTOTERM 0x08 284 1.4.2.4 nathanw #define HCC_LOW8TERM 0x10 285 1.4.2.4 nathanw #define HCC_UP8TERM 0x20 286 1.4.2.4 nathanw 287 1.4.2.2 nathanw int sc_flag; 288 1.4.2.2 nathanw #define RESET_DEV 0x01 289 1.4.2.2 nathanw #define RESET_DETECT 0x02 290 1.4.2.2 nathanw #define RESET_DONE 0x04 291 1.4.2.4 nathanw #define WAIT_TAGMSG 0x08 /* XXX */ 292 1.4.2.4 nathanw 293 1.4.2.4 nathanw int sc_msgcnt; 294 1.4.2.4 nathanw 295 1.4.2.4 nathanw int resel_target; /* XXX */ 296 1.4.2.4 nathanw int resel_lun; /* XXX */ 297 1.4.2.4 nathanw 298 1.4.2.4 nathanw u_int8_t *sc_msg; 299 1.4.2.4 nathanw u_int8_t sc_msgbuf[6]; 300 1.4.2.2 nathanw }; 301 1.4.2.2 nathanw 302 1.4.2.2 nathanw /* 303 1.4.2.2 nathanw * SCSI Status codes not defined in scsi_all.h 304 1.4.2.2 nathanw */ 305 1.4.2.2 nathanw #define SCSI_COND_MET 0x04 /* Condition Met */ 306 1.4.2.2 nathanw #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 1.4.2.4 nathanw #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 1.4.2.4 nathanw #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 1.4.2.4 nathanw #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 1.4.2.4 nathanw 311 1.4.2.4 nathanw static int trm_probe(struct device *, struct cfdata *, void *); 312 1.4.2.4 nathanw static void trm_attach(struct device *, struct device *, void *); 313 1.4.2.4 nathanw 314 1.4.2.4 nathanw static int trm_init(struct trm_softc *); 315 1.4.2.4 nathanw 316 1.4.2.4 nathanw static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 1.4.2.4 nathanw void *); 318 1.4.2.4 nathanw static void trm_update_xfer_mode(struct trm_softc *, int); 319 1.4.2.4 nathanw static void trm_sched(struct trm_softc *); 320 1.4.2.4 nathanw static int trm_select(struct trm_softc *, struct trm_srb *); 321 1.4.2.4 nathanw static void trm_reset(struct trm_softc *); 322 1.4.2.4 nathanw static void trm_timeout(void *); 323 1.4.2.2 nathanw static int trm_intr(void *); 324 1.4.2.2 nathanw 325 1.4.2.4 nathanw static void trm_dataout_phase0(struct trm_softc *, int); 326 1.4.2.4 nathanw static void trm_datain_phase0(struct trm_softc *, int); 327 1.4.2.4 nathanw static void trm_status_phase0(struct trm_softc *); 328 1.4.2.4 nathanw static void trm_msgin_phase0(struct trm_softc *); 329 1.4.2.4 nathanw static void trm_command_phase1(struct trm_softc *); 330 1.4.2.4 nathanw static void trm_status_phase1(struct trm_softc *); 331 1.4.2.4 nathanw static void trm_msgout_phase1(struct trm_softc *); 332 1.4.2.4 nathanw static void trm_msgin_phase1(struct trm_softc *); 333 1.4.2.4 nathanw 334 1.4.2.4 nathanw static void trm_dataio_xfer(struct trm_softc *, int); 335 1.4.2.2 nathanw static void trm_disconnect(struct trm_softc *); 336 1.4.2.2 nathanw static void trm_reselect(struct trm_softc *); 337 1.4.2.4 nathanw static void trm_done(struct trm_softc *, struct trm_srb *); 338 1.4.2.4 nathanw static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 1.4.2.4 nathanw static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 1.4.2.4 nathanw 341 1.4.2.2 nathanw static void trm_scsi_reset_detect(struct trm_softc *); 342 1.4.2.2 nathanw static void trm_reset_scsi_bus(struct trm_softc *); 343 1.4.2.2 nathanw 344 1.4.2.4 nathanw static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 1.4.2.2 nathanw static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 1.4.2.2 nathanw static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 1.4.2.2 nathanw static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 1.4.2.2 nathanw static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 1.4.2.2 nathanw static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 1.4.2.2 nathanw 351 1.4.2.2 nathanw struct cfattach trm_ca = { 352 1.4.2.2 nathanw sizeof(struct trm_softc), trm_probe, trm_attach 353 1.4.2.2 nathanw }; 354 1.4.2.2 nathanw 355 1.4.2.2 nathanw /* real period: */ 356 1.4.2.2 nathanw static const u_int8_t trm_clock_period[] = { 357 1.4.2.4 nathanw 12, /* 48 ns 20.0 MB/sec */ 358 1.4.2.4 nathanw 18, /* 72 ns 13.3 MB/sec */ 359 1.4.2.4 nathanw 25, /* 100 ns 10.0 MB/sec */ 360 1.4.2.4 nathanw 31, /* 124 ns 8.0 MB/sec */ 361 1.4.2.4 nathanw 37, /* 148 ns 6.6 MB/sec */ 362 1.4.2.4 nathanw 43, /* 172 ns 5.7 MB/sec */ 363 1.4.2.4 nathanw 50, /* 200 ns 5.0 MB/sec */ 364 1.4.2.4 nathanw 62 /* 248 ns 4.0 MB/sec */ 365 1.4.2.2 nathanw }; 366 1.4.2.4 nathanw #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 1.4.2.4 nathanw 368 1.4.2.4 nathanw static int 369 1.4.2.4 nathanw trm_probe(parent, match, aux) 370 1.4.2.4 nathanw struct device *parent; 371 1.4.2.4 nathanw struct cfdata *match; 372 1.4.2.4 nathanw void *aux; 373 1.4.2.4 nathanw { 374 1.4.2.4 nathanw struct pci_attach_args *pa = aux; 375 1.4.2.4 nathanw 376 1.4.2.4 nathanw if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 377 1.4.2.4 nathanw switch (PCI_PRODUCT(pa->pa_id)) { 378 1.4.2.4 nathanw case PCI_PRODUCT_TEKRAM2_DC315: 379 1.4.2.4 nathanw return (1); 380 1.4.2.4 nathanw } 381 1.4.2.4 nathanw return (0); 382 1.4.2.4 nathanw } 383 1.4.2.2 nathanw 384 1.4.2.2 nathanw /* 385 1.4.2.4 nathanw * attach and init a host adapter 386 1.4.2.2 nathanw */ 387 1.4.2.2 nathanw static void 388 1.4.2.4 nathanw trm_attach(parent, self, aux) 389 1.4.2.4 nathanw struct device *parent; 390 1.4.2.4 nathanw struct device *self; 391 1.4.2.4 nathanw void *aux; 392 1.4.2.2 nathanw { 393 1.4.2.4 nathanw struct pci_attach_args *const pa = aux; 394 1.4.2.4 nathanw struct trm_softc *sc = (struct trm_softc *)self; 395 1.4.2.4 nathanw bus_space_tag_t iot; 396 1.4.2.4 nathanw bus_space_handle_t ioh; 397 1.4.2.4 nathanw pci_intr_handle_t ih; 398 1.4.2.4 nathanw pcireg_t command; 399 1.4.2.4 nathanw const char *intrstr; 400 1.4.2.2 nathanw 401 1.4.2.4 nathanw /* 402 1.4.2.4 nathanw * These cards do not allow memory mapped accesses 403 1.4.2.4 nathanw * pa_pc: chipset tag 404 1.4.2.4 nathanw * pa_tag: pci tag 405 1.4.2.4 nathanw */ 406 1.4.2.4 nathanw command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 407 1.4.2.4 nathanw if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 408 1.4.2.4 nathanw (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 409 1.4.2.4 nathanw command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 410 1.4.2.4 nathanw pci_conf_write(pa->pa_pc, pa->pa_tag, 411 1.4.2.4 nathanw PCI_COMMAND_STATUS_REG, command); 412 1.4.2.4 nathanw } 413 1.4.2.4 nathanw /* 414 1.4.2.4 nathanw * mask for get correct base address of pci IO port 415 1.4.2.4 nathanw */ 416 1.4.2.4 nathanw if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 417 1.4.2.4 nathanw &iot, &ioh, NULL, NULL)) { 418 1.4.2.4 nathanw printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 419 1.4.2.4 nathanw return; 420 1.4.2.4 nathanw } 421 1.4.2.4 nathanw /* 422 1.4.2.4 nathanw * test checksum of eeprom.. & initialize softc... 423 1.4.2.4 nathanw */ 424 1.4.2.4 nathanw sc->sc_iot = iot; 425 1.4.2.4 nathanw sc->sc_ioh = ioh; 426 1.4.2.4 nathanw sc->sc_dmat = pa->pa_dmat; 427 1.4.2.2 nathanw 428 1.4.2.4 nathanw if (trm_init(sc) != 0) { 429 1.4.2.4 nathanw /* 430 1.4.2.4 nathanw * Error during initialization! 431 1.4.2.4 nathanw */ 432 1.4.2.4 nathanw printf(": Error during initialization\n"); 433 1.4.2.4 nathanw return; 434 1.4.2.4 nathanw } 435 1.4.2.4 nathanw /* 436 1.4.2.4 nathanw * Now try to attach all the sub-devices 437 1.4.2.4 nathanw */ 438 1.4.2.4 nathanw if ((sc->sc_config & HCC_WIDE_CARD) != 0) 439 1.4.2.4 nathanw printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 440 1.4.2.4 nathanw "Ultra Wide SCSI Adapter\n"); 441 1.4.2.4 nathanw else 442 1.4.2.4 nathanw printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 443 1.4.2.4 nathanw "Ultra SCSI Adapter\n"); 444 1.4.2.2 nathanw 445 1.4.2.4 nathanw /* 446 1.4.2.4 nathanw * Now tell the generic SCSI layer about our bus. 447 1.4.2.4 nathanw * map and establish interrupt 448 1.4.2.4 nathanw */ 449 1.4.2.4 nathanw if (pci_intr_map(pa, &ih)) { 450 1.4.2.4 nathanw printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 451 1.4.2.4 nathanw return; 452 1.4.2.2 nathanw } 453 1.4.2.4 nathanw intrstr = pci_intr_string(pa->pa_pc, ih); 454 1.4.2.2 nathanw 455 1.4.2.4 nathanw if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 456 1.4.2.4 nathanw printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 457 1.4.2.4 nathanw if (intrstr != NULL) 458 1.4.2.4 nathanw printf(" at %s", intrstr); 459 1.4.2.4 nathanw printf("\n"); 460 1.4.2.4 nathanw return; 461 1.4.2.4 nathanw } 462 1.4.2.4 nathanw if (intrstr != NULL) 463 1.4.2.4 nathanw printf("%s: interrupting at %s\n", 464 1.4.2.4 nathanw sc->sc_dev.dv_xname, intrstr); 465 1.4.2.4 nathanw 466 1.4.2.4 nathanw sc->sc_adapter.adapt_dev = &sc->sc_dev; 467 1.4.2.4 nathanw sc->sc_adapter.adapt_nchannels = 1; 468 1.4.2.4 nathanw sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 469 1.4.2.4 nathanw sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 470 1.4.2.4 nathanw sc->sc_adapter.adapt_request = trm_scsipi_request; 471 1.4.2.4 nathanw sc->sc_adapter.adapt_minphys = minphys; 472 1.4.2.4 nathanw 473 1.4.2.4 nathanw sc->sc_channel.chan_adapter = &sc->sc_adapter; 474 1.4.2.4 nathanw sc->sc_channel.chan_bustype = &scsi_bustype; 475 1.4.2.4 nathanw sc->sc_channel.chan_channel = 0; 476 1.4.2.4 nathanw sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 477 1.4.2.4 nathanw sc->sc_channel.chan_nluns = 8; 478 1.4.2.4 nathanw sc->sc_channel.chan_id = sc->sc_id; 479 1.4.2.4 nathanw 480 1.4.2.4 nathanw config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 481 1.4.2.2 nathanw } 482 1.4.2.2 nathanw 483 1.4.2.4 nathanw /* 484 1.4.2.4 nathanw * initialize the internal structures for a given SCSI host 485 1.4.2.4 nathanw */ 486 1.4.2.4 nathanw static int 487 1.4.2.4 nathanw trm_init(sc) 488 1.4.2.2 nathanw struct trm_softc *sc; 489 1.4.2.2 nathanw { 490 1.4.2.4 nathanw bus_space_tag_t iot = sc->sc_iot; 491 1.4.2.4 nathanw bus_space_handle_t ioh = sc->sc_ioh; 492 1.4.2.4 nathanw bus_dma_segment_t seg; 493 1.4.2.4 nathanw struct trm_nvram eeprom; 494 1.4.2.2 nathanw struct trm_srb *srb; 495 1.4.2.4 nathanw struct trm_tinfo *ti; 496 1.4.2.4 nathanw struct nvram_target *tconf; 497 1.4.2.4 nathanw int error, rseg, all_sgsize; 498 1.4.2.4 nathanw int i, target; 499 1.4.2.4 nathanw u_int8_t bval; 500 1.4.2.2 nathanw 501 1.4.2.4 nathanw DPRINTF(("\n")); 502 1.4.2.2 nathanw 503 1.4.2.4 nathanw /* 504 1.4.2.4 nathanw * allocate the space for all SCSI control blocks (SRB) for DMA memory 505 1.4.2.4 nathanw */ 506 1.4.2.4 nathanw all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 507 1.4.2.4 nathanw if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 508 1.4.2.4 nathanw 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 509 1.4.2.4 nathanw printf(": unable to allocate SCSI REQUEST BLOCKS, " 510 1.4.2.4 nathanw "error = %d\n", error); 511 1.4.2.4 nathanw return (1); 512 1.4.2.2 nathanw } 513 1.4.2.4 nathanw if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 514 1.4.2.4 nathanw all_sgsize, (caddr_t *) &sc->sc_sglist, 515 1.4.2.4 nathanw BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 516 1.4.2.4 nathanw printf(": unable to map SCSI REQUEST BLOCKS, " 517 1.4.2.4 nathanw "error = %d\n", error); 518 1.4.2.4 nathanw return (1); 519 1.4.2.4 nathanw } 520 1.4.2.4 nathanw if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 521 1.4.2.4 nathanw all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 522 1.4.2.4 nathanw printf(": unable to create SRB DMA maps, " 523 1.4.2.4 nathanw "error = %d\n", error); 524 1.4.2.4 nathanw return (1); 525 1.4.2.4 nathanw } 526 1.4.2.4 nathanw if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 527 1.4.2.4 nathanw sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 528 1.4.2.4 nathanw printf(": unable to load SRB DMA maps, " 529 1.4.2.4 nathanw "error = %d\n", error); 530 1.4.2.4 nathanw return (1); 531 1.4.2.4 nathanw } 532 1.4.2.4 nathanw DPRINTF(("all_sgsize=%x\n", all_sgsize)); 533 1.4.2.4 nathanw memset(sc->sc_sglist, 0, all_sgsize); 534 1.4.2.2 nathanw 535 1.4.2.4 nathanw /* 536 1.4.2.4 nathanw * EEPROM CHECKSUM 537 1.4.2.4 nathanw */ 538 1.4.2.4 nathanw trm_check_eeprom(sc, &eeprom); 539 1.4.2.2 nathanw 540 1.4.2.4 nathanw sc->sc_maxid = 7; 541 1.4.2.4 nathanw sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 542 1.4.2.4 nathanw if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 543 1.4.2.4 nathanw sc->sc_config |= HCC_WIDE_CARD; 544 1.4.2.4 nathanw sc->sc_maxid = 15; 545 1.4.2.4 nathanw } 546 1.4.2.4 nathanw if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 547 1.4.2.4 nathanw sc->sc_config |= HCC_SCSI_RESET; 548 1.4.2.4 nathanw 549 1.4.2.4 nathanw sc->sc_actsrb = NULL; 550 1.4.2.4 nathanw sc->sc_id = eeprom.scsi_id; 551 1.4.2.4 nathanw sc->sc_flag = 0; 552 1.4.2.2 nathanw 553 1.4.2.2 nathanw /* 554 1.4.2.4 nathanw * initialize and link all device's SRB queues of this adapter 555 1.4.2.2 nathanw */ 556 1.4.2.4 nathanw TAILQ_INIT(&sc->sc_freesrb); 557 1.4.2.4 nathanw TAILQ_INIT(&sc->sc_readysrb); 558 1.4.2.2 nathanw 559 1.4.2.4 nathanw sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 560 1.4.2.4 nathanw M_DEVBUF, M_NOWAIT|M_ZERO); 561 1.4.2.4 nathanw DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 562 1.4.2.4 nathanw if (sc->sc_srb == NULL) { 563 1.4.2.4 nathanw printf(": can not allocate SRB\n"); 564 1.4.2.4 nathanw return (1); 565 1.4.2.2 nathanw } 566 1.4.2.4 nathanw 567 1.4.2.4 nathanw for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 568 1.4.2.4 nathanw srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 569 1.4.2.4 nathanw srb->sgoffset = TRM_SG_SIZE * i; 570 1.4.2.4 nathanw srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 571 1.4.2.2 nathanw /* 572 1.4.2.4 nathanw * map all SRB space to SRB_array 573 1.4.2.2 nathanw */ 574 1.4.2.4 nathanw if (bus_dmamap_create(sc->sc_dmat, 575 1.4.2.4 nathanw MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 576 1.4.2.4 nathanw BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 577 1.4.2.5 nathanw printf(": unable to create DMA transfer map...\n"); 578 1.4.2.4 nathanw free(sc->sc_srb, M_DEVBUF); 579 1.4.2.4 nathanw return (1); 580 1.4.2.2 nathanw } 581 1.4.2.4 nathanw TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 582 1.4.2.4 nathanw srb++; 583 1.4.2.2 nathanw } 584 1.4.2.2 nathanw 585 1.4.2.4 nathanw /* 586 1.4.2.4 nathanw * initialize all target info structures 587 1.4.2.4 nathanw */ 588 1.4.2.4 nathanw for (target = 0; target < TRM_MAX_TARGETS; target++) { 589 1.4.2.4 nathanw ti = &sc->sc_tinfo[target]; 590 1.4.2.4 nathanw ti->synctl = 0; 591 1.4.2.4 nathanw ti->offset = 0; 592 1.4.2.4 nathanw tconf = &eeprom.target[target]; 593 1.4.2.4 nathanw ti->config0 = tconf->config0; 594 1.4.2.4 nathanw ti->period = trm_clock_period[tconf->period & 0x07]; 595 1.4.2.4 nathanw ti->flag = 0; 596 1.4.2.4 nathanw if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 597 1.4.2.4 nathanw (sc->sc_config & HCC_WIDE_CARD) != 0) 598 1.4.2.4 nathanw ti->flag |= WIDE_NEGO_ENABLE; 599 1.4.2.4 nathanw if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 600 1.4.2.4 nathanw ti->flag |= SYNC_NEGO_ENABLE; 601 1.4.2.4 nathanw if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 602 1.4.2.4 nathanw #ifdef notyet 603 1.4.2.4 nathanw if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 604 1.4.2.4 nathanw ti->flag |= USE_TAG_QUEUING; 605 1.4.2.4 nathanw #endif 606 1.4.2.4 nathanw } else 607 1.4.2.4 nathanw ti->flag |= NO_RESELECT; 608 1.4.2.4 nathanw 609 1.4.2.4 nathanw DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 610 1.4.2.4 nathanw target, ti->config0, ti->period)); 611 1.4.2.4 nathanw DPRINTF((", flag = 0x%02x\n", ti->flag)); 612 1.4.2.4 nathanw } 613 1.4.2.2 nathanw 614 1.4.2.4 nathanw /* program configuration 0 */ 615 1.4.2.4 nathanw bval = PHASELATCH | INITIATOR | BLOCKRST; 616 1.4.2.4 nathanw if ((sc->sc_config & HCC_PARITY) != 0) 617 1.4.2.4 nathanw bval |= PARITYCHECK; 618 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 619 1.4.2.4 nathanw 620 1.4.2.4 nathanw /* program configuration 1 */ 621 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 622 1.4.2.4 nathanw ACTIVE_NEG | ACTIVE_NEGPLUS); 623 1.4.2.4 nathanw 624 1.4.2.4 nathanw /* 250ms selection timeout */ 625 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 626 1.4.2.4 nathanw 627 1.4.2.4 nathanw /* Mask all interrupts */ 628 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 629 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 630 1.4.2.4 nathanw 631 1.4.2.4 nathanw /* Reset SCSI module */ 632 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 633 1.4.2.4 nathanw 634 1.4.2.4 nathanw /* program Host ID */ 635 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 636 1.4.2.4 nathanw 637 1.4.2.4 nathanw /* set asynchronous transfer */ 638 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 639 1.4.2.4 nathanw 640 1.4.2.4 nathanw /* Turn LED control off */ 641 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 642 1.4.2.4 nathanw bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 643 1.4.2.4 nathanw 644 1.4.2.4 nathanw /* DMA config */ 645 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 646 1.4.2.4 nathanw bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 647 1.4.2.4 nathanw 648 1.4.2.4 nathanw /* Clear pending interrupt status */ 649 1.4.2.4 nathanw bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 650 1.4.2.4 nathanw 651 1.4.2.4 nathanw /* Enable SCSI interrupt */ 652 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 653 1.4.2.4 nathanw EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 654 1.4.2.4 nathanw EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 655 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 656 1.4.2.4 nathanw 657 1.4.2.4 nathanw trm_reset(sc); 658 1.4.2.4 nathanw 659 1.4.2.4 nathanw return (0); 660 1.4.2.4 nathanw } 661 1.4.2.4 nathanw 662 1.4.2.4 nathanw /* 663 1.4.2.4 nathanw * enqueues a SCSI command 664 1.4.2.4 nathanw * called by the higher level SCSI driver 665 1.4.2.4 nathanw */ 666 1.4.2.4 nathanw static void 667 1.4.2.4 nathanw trm_scsipi_request(chan, req, arg) 668 1.4.2.4 nathanw struct scsipi_channel *chan; 669 1.4.2.4 nathanw scsipi_adapter_req_t req; 670 1.4.2.4 nathanw void *arg; 671 1.4.2.4 nathanw { 672 1.4.2.4 nathanw bus_space_tag_t iot; 673 1.4.2.4 nathanw bus_space_handle_t ioh; 674 1.4.2.2 nathanw struct trm_softc *sc; 675 1.4.2.2 nathanw struct trm_srb *srb; 676 1.4.2.2 nathanw struct scsipi_xfer *xs; 677 1.4.2.4 nathanw int error, i, target, lun, s; 678 1.4.2.2 nathanw 679 1.4.2.2 nathanw sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 680 1.4.2.2 nathanw iot = sc->sc_iot; 681 1.4.2.2 nathanw ioh = sc->sc_ioh; 682 1.4.2.2 nathanw 683 1.4.2.2 nathanw switch (req) { 684 1.4.2.2 nathanw case ADAPTER_REQ_RUN_XFER: 685 1.4.2.2 nathanw xs = arg; 686 1.4.2.4 nathanw target = xs->xs_periph->periph_target; 687 1.4.2.2 nathanw lun = xs->xs_periph->periph_lun; 688 1.4.2.4 nathanw DPRINTF(("trm_scsipi_request.....\n")); 689 1.4.2.4 nathanw DPRINTF(("target= %d lun= %d\n", target, lun)); 690 1.4.2.2 nathanw if (xs->xs_control & XS_CTL_RESET) { 691 1.4.2.2 nathanw trm_reset(sc); 692 1.4.2.2 nathanw xs->error = XS_NOERROR | XS_RESET; 693 1.4.2.2 nathanw return; 694 1.4.2.2 nathanw } 695 1.4.2.2 nathanw if (xs->xs_status & XS_STS_DONE) { 696 1.4.2.2 nathanw printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 697 1.4.2.2 nathanw xs->xs_status &= ~XS_STS_DONE; 698 1.4.2.2 nathanw } 699 1.4.2.2 nathanw 700 1.4.2.2 nathanw s = splbio(); 701 1.4.2.2 nathanw 702 1.4.2.2 nathanw /* Get SRB */ 703 1.4.2.4 nathanw srb = TAILQ_FIRST(&sc->sc_freesrb); 704 1.4.2.2 nathanw if (srb != NULL) { 705 1.4.2.4 nathanw TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 706 1.4.2.2 nathanw } else { 707 1.4.2.2 nathanw xs->error = XS_RESOURCE_SHORTAGE; 708 1.4.2.2 nathanw scsipi_done(xs); 709 1.4.2.2 nathanw splx(s); 710 1.4.2.2 nathanw return; 711 1.4.2.2 nathanw } 712 1.4.2.4 nathanw 713 1.4.2.2 nathanw srb->xs = xs; 714 1.4.2.2 nathanw srb->cmdlen = xs->cmdlen; 715 1.4.2.2 nathanw memcpy(srb->cmd, xs->cmd, xs->cmdlen); 716 1.4.2.4 nathanw 717 1.4.2.3 nathanw if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 718 1.4.2.2 nathanw if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 719 1.4.2.2 nathanw xs->data, xs->datalen, NULL, 720 1.4.2.3 nathanw ((xs->xs_control & XS_CTL_NOSLEEP) ? 721 1.4.2.3 nathanw BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 722 1.4.2.3 nathanw BUS_DMA_STREAMING | 723 1.4.2.3 nathanw ((xs->xs_control & XS_CTL_DATA_IN) ? 724 1.4.2.3 nathanw BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 725 1.4.2.2 nathanw printf("%s: DMA transfer map unable to load, " 726 1.4.2.2 nathanw "error = %d\n", sc->sc_dev.dv_xname, error); 727 1.4.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 728 1.4.2.2 nathanw /* 729 1.4.2.2 nathanw * free SRB 730 1.4.2.2 nathanw */ 731 1.4.2.4 nathanw TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 732 1.4.2.2 nathanw splx(s); 733 1.4.2.2 nathanw return; 734 1.4.2.2 nathanw } 735 1.4.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 736 1.4.2.2 nathanw srb->dmap->dm_mapsize, 737 1.4.2.2 nathanw (xs->xs_control & XS_CTL_DATA_IN) ? 738 1.4.2.2 nathanw BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 739 1.4.2.2 nathanw 740 1.4.2.2 nathanw /* Set up the scatter gather list */ 741 1.4.2.2 nathanw for (i = 0; i < srb->dmap->dm_nsegs; i++) { 742 1.4.2.2 nathanw srb->sgentry[i].address = 743 1.4.2.2 nathanw htole32(srb->dmap->dm_segs[i].ds_addr); 744 1.4.2.2 nathanw srb->sgentry[i].length = 745 1.4.2.2 nathanw htole32(srb->dmap->dm_segs[i].ds_len); 746 1.4.2.2 nathanw } 747 1.4.2.2 nathanw srb->buflen = xs->datalen; 748 1.4.2.2 nathanw srb->sgcnt = srb->dmap->dm_nsegs; 749 1.4.2.2 nathanw } else { 750 1.4.2.2 nathanw srb->sgentry[0].address = 0; 751 1.4.2.2 nathanw srb->sgentry[0].length = 0; 752 1.4.2.2 nathanw srb->buflen = 0; 753 1.4.2.2 nathanw srb->sgcnt = 0; 754 1.4.2.2 nathanw } 755 1.4.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 756 1.4.2.2 nathanw srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 757 1.4.2.2 nathanw 758 1.4.2.4 nathanw sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 759 1.4.2.4 nathanw 760 1.4.2.2 nathanw srb->sgindex = 0; 761 1.4.2.2 nathanw srb->hastat = 0; 762 1.4.2.2 nathanw srb->tastat = 0; 763 1.4.2.2 nathanw srb->flag = 0; 764 1.4.2.2 nathanw 765 1.4.2.4 nathanw TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 766 1.4.2.4 nathanw if (sc->sc_actsrb == NULL) 767 1.4.2.4 nathanw trm_sched(sc); 768 1.4.2.2 nathanw splx(s); 769 1.4.2.2 nathanw 770 1.4.2.4 nathanw if ((xs->xs_control & XS_CTL_POLL) != 0) { 771 1.4.2.2 nathanw int timeout = xs->timeout; 772 1.4.2.4 nathanw 773 1.4.2.2 nathanw s = splbio(); 774 1.4.2.2 nathanw do { 775 1.4.2.4 nathanw while (--timeout) { 776 1.4.2.2 nathanw DELAY(1000); 777 1.4.2.2 nathanw if (bus_space_read_2(iot, ioh, 778 1.4.2.2 nathanw TRM_SCSI_STATUS) & SCSIINTERRUPT) 779 1.4.2.2 nathanw break; 780 1.4.2.2 nathanw } 781 1.4.2.4 nathanw if (timeout == 0) { 782 1.4.2.2 nathanw trm_timeout(srb); 783 1.4.2.2 nathanw break; 784 1.4.2.2 nathanw } else 785 1.4.2.2 nathanw trm_intr(sc); 786 1.4.2.2 nathanw } while ((xs->xs_status & XS_STS_DONE) == 0); 787 1.4.2.2 nathanw splx(s); 788 1.4.2.2 nathanw } 789 1.4.2.2 nathanw return; 790 1.4.2.2 nathanw 791 1.4.2.2 nathanw case ADAPTER_REQ_GROW_RESOURCES: 792 1.4.2.2 nathanw /* XXX Not supported. */ 793 1.4.2.2 nathanw return; 794 1.4.2.2 nathanw 795 1.4.2.2 nathanw case ADAPTER_REQ_SET_XFER_MODE: 796 1.4.2.4 nathanw { 797 1.4.2.4 nathanw struct trm_tinfo *ti; 798 1.4.2.4 nathanw struct scsipi_xfer_mode *xm; 799 1.4.2.4 nathanw 800 1.4.2.4 nathanw xm = arg; 801 1.4.2.4 nathanw ti = &sc->sc_tinfo[xm->xm_target]; 802 1.4.2.4 nathanw ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 803 1.4.2.4 nathanw 804 1.4.2.4 nathanw #ifdef notyet 805 1.4.2.4 nathanw if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 806 1.4.2.4 nathanw ti->flag |= USE_TAG_QUEUING; 807 1.4.2.4 nathanw else 808 1.4.2.4 nathanw #endif 809 1.4.2.4 nathanw ti->flag &= ~USE_TAG_QUEUING; 810 1.4.2.4 nathanw 811 1.4.2.4 nathanw if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 812 1.4.2.4 nathanw ti->flag |= WIDE_NEGO_ENABLE; 813 1.4.2.4 nathanw ti->flag &= ~WIDE_NEGO_DONE; 814 1.4.2.4 nathanw } 815 1.4.2.4 nathanw 816 1.4.2.4 nathanw if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 817 1.4.2.4 nathanw ti->flag |= SYNC_NEGO_ENABLE; 818 1.4.2.4 nathanw ti->flag &= ~SYNC_NEGO_DONE; 819 1.4.2.4 nathanw ti->period = trm_clock_period[0]; 820 1.4.2.4 nathanw } 821 1.4.2.4 nathanw 822 1.4.2.4 nathanw /* 823 1.4.2.4 nathanw * If we're not going to negotiate, send the 824 1.4.2.4 nathanw * notification now, since it won't happen later. 825 1.4.2.4 nathanw */ 826 1.4.2.4 nathanw if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 827 1.4.2.4 nathanw (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 828 1.4.2.4 nathanw trm_update_xfer_mode(sc, xm->xm_target); 829 1.4.2.4 nathanw 830 1.4.2.4 nathanw return; 831 1.4.2.4 nathanw } 832 1.4.2.2 nathanw } 833 1.4.2.2 nathanw } 834 1.4.2.2 nathanw 835 1.4.2.2 nathanw static void 836 1.4.2.4 nathanw trm_update_xfer_mode(sc, target) 837 1.4.2.2 nathanw struct trm_softc *sc; 838 1.4.2.4 nathanw int target; 839 1.4.2.2 nathanw { 840 1.4.2.4 nathanw struct scsipi_xfer_mode xm; 841 1.4.2.4 nathanw struct trm_tinfo *ti; 842 1.4.2.2 nathanw 843 1.4.2.4 nathanw ti = &sc->sc_tinfo[target]; 844 1.4.2.4 nathanw xm.xm_target = target; 845 1.4.2.4 nathanw xm.xm_mode = 0; 846 1.4.2.4 nathanw xm.xm_period = 0; 847 1.4.2.4 nathanw xm.xm_offset = 0; 848 1.4.2.2 nathanw 849 1.4.2.4 nathanw if ((ti->synctl & WIDE_SYNC) != 0) 850 1.4.2.4 nathanw xm.xm_mode |= PERIPH_CAP_WIDE16; 851 1.4.2.2 nathanw 852 1.4.2.4 nathanw if (ti->period > 0) { 853 1.4.2.4 nathanw xm.xm_mode |= PERIPH_CAP_SYNC; 854 1.4.2.4 nathanw xm.xm_period = ti->period; 855 1.4.2.4 nathanw xm.xm_offset = ti->offset; 856 1.4.2.2 nathanw } 857 1.4.2.4 nathanw 858 1.4.2.4 nathanw #ifdef notyet 859 1.4.2.4 nathanw if ((ti->flag & USE_TAG_QUEUING) != 0) 860 1.4.2.4 nathanw xm.xm_mode |= PERIPH_CAP_TQING; 861 1.4.2.4 nathanw #endif 862 1.4.2.4 nathanw 863 1.4.2.4 nathanw scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 864 1.4.2.2 nathanw } 865 1.4.2.2 nathanw 866 1.4.2.2 nathanw static void 867 1.4.2.4 nathanw trm_sched(sc) 868 1.4.2.2 nathanw struct trm_softc *sc; 869 1.4.2.2 nathanw { 870 1.4.2.4 nathanw struct trm_srb *srb; 871 1.4.2.4 nathanw struct scsipi_periph *periph; 872 1.4.2.4 nathanw struct trm_tinfo *ti; 873 1.4.2.4 nathanw struct trm_linfo *li; 874 1.4.2.4 nathanw int s, lun, tag; 875 1.4.2.2 nathanw 876 1.4.2.4 nathanw DPRINTF(("trm_sched...\n")); 877 1.4.2.4 nathanw 878 1.4.2.4 nathanw TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 879 1.4.2.4 nathanw periph = srb->xs->xs_periph; 880 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 881 1.4.2.4 nathanw lun = periph->periph_lun; 882 1.4.2.4 nathanw 883 1.4.2.4 nathanw /* select type of tag for this command */ 884 1.4.2.4 nathanw if ((ti->flag & NO_RESELECT) != 0 || 885 1.4.2.4 nathanw (ti->flag & USE_TAG_QUEUING) == 0 || 886 1.4.2.4 nathanw (srb->flag & AUTO_REQSENSE) != 0 || 887 1.4.2.4 nathanw (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 888 1.4.2.4 nathanw tag = 0; 889 1.4.2.4 nathanw else 890 1.4.2.4 nathanw tag = srb->xs->xs_tag_type; 891 1.4.2.4 nathanw #if 0 892 1.4.2.4 nathanw /* XXX use tags for polled commands? */ 893 1.4.2.4 nathanw if (srb->xs->xs_control & XS_CTL_POLL) 894 1.4.2.4 nathanw tag = 0; 895 1.4.2.4 nathanw #endif 896 1.4.2.4 nathanw 897 1.4.2.4 nathanw s = splbio(); 898 1.4.2.4 nathanw li = ti->linfo[lun]; 899 1.4.2.4 nathanw if (li == NULL) { 900 1.4.2.4 nathanw /* initialize lun info */ 901 1.4.2.4 nathanw if ((li = malloc(sizeof(*li), M_DEVBUF, 902 1.4.2.4 nathanw M_NOWAIT|M_ZERO)) == NULL) { 903 1.4.2.4 nathanw splx(s); 904 1.4.2.4 nathanw continue; 905 1.4.2.4 nathanw } 906 1.4.2.4 nathanw ti->linfo[lun] = li; 907 1.4.2.4 nathanw } 908 1.4.2.2 nathanw 909 1.4.2.4 nathanw if (tag == 0) { 910 1.4.2.4 nathanw /* try to issue this srb as an un-tagged command */ 911 1.4.2.4 nathanw if (li->untagged == NULL) 912 1.4.2.4 nathanw li->untagged = srb; 913 1.4.2.4 nathanw } 914 1.4.2.4 nathanw if (li->untagged != NULL) { 915 1.4.2.4 nathanw tag = 0; 916 1.4.2.4 nathanw if (li->busy != 1 && li->used == 0) { 917 1.4.2.4 nathanw /* we need to issue the untagged command now */ 918 1.4.2.4 nathanw srb = li->untagged; 919 1.4.2.4 nathanw periph = srb->xs->xs_periph; 920 1.4.2.2 nathanw } else { 921 1.4.2.4 nathanw /* not ready yet */ 922 1.4.2.4 nathanw splx(s); 923 1.4.2.4 nathanw continue; 924 1.4.2.2 nathanw } 925 1.4.2.2 nathanw } 926 1.4.2.4 nathanw srb->tag[0] = tag; 927 1.4.2.4 nathanw if (tag != 0) { 928 1.4.2.4 nathanw li->queued[srb->xs->xs_tag_id] = srb; 929 1.4.2.4 nathanw srb->tag[1] = srb->xs->xs_tag_id; 930 1.4.2.4 nathanw li->used++; 931 1.4.2.4 nathanw } 932 1.4.2.4 nathanw 933 1.4.2.4 nathanw if (li->untagged != NULL && li->busy != 1) { 934 1.4.2.4 nathanw li->busy = 1; 935 1.4.2.4 nathanw TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 936 1.4.2.4 nathanw sc->sc_actsrb = srb; 937 1.4.2.4 nathanw trm_select(sc, srb); 938 1.4.2.4 nathanw splx(s); 939 1.4.2.4 nathanw break; 940 1.4.2.4 nathanw } 941 1.4.2.4 nathanw if (li->untagged == NULL && tag != 0) { 942 1.4.2.4 nathanw TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 943 1.4.2.4 nathanw sc->sc_actsrb = srb; 944 1.4.2.4 nathanw trm_select(sc, srb); 945 1.4.2.4 nathanw splx(s); 946 1.4.2.4 nathanw break; 947 1.4.2.4 nathanw } else 948 1.4.2.4 nathanw splx(s); 949 1.4.2.4 nathanw } 950 1.4.2.4 nathanw } 951 1.4.2.4 nathanw 952 1.4.2.4 nathanw static int 953 1.4.2.4 nathanw trm_select(sc, srb) 954 1.4.2.4 nathanw struct trm_softc *sc; 955 1.4.2.4 nathanw struct trm_srb *srb; 956 1.4.2.4 nathanw { 957 1.4.2.4 nathanw bus_space_tag_t iot = sc->sc_iot; 958 1.4.2.4 nathanw bus_space_handle_t ioh = sc->sc_ioh; 959 1.4.2.4 nathanw struct scsipi_periph *periph = srb->xs->xs_periph; 960 1.4.2.4 nathanw int target = periph->periph_target; 961 1.4.2.4 nathanw int lun = periph->periph_lun; 962 1.4.2.4 nathanw struct trm_tinfo *ti = &sc->sc_tinfo[target]; 963 1.4.2.4 nathanw u_int8_t scsicmd; 964 1.4.2.4 nathanw 965 1.4.2.4 nathanw DPRINTF(("trm_select.....\n")); 966 1.4.2.4 nathanw 967 1.4.2.4 nathanw if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 968 1.4.2.5 nathanw callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 969 1.4.2.5 nathanw trm_timeout, srb); 970 1.4.2.4 nathanw } 971 1.4.2.4 nathanw 972 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 973 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 974 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 975 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 976 1.4.2.4 nathanw /* Flush FIFO */ 977 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 978 1.4.2.4 nathanw DELAY(10); 979 1.4.2.4 nathanw 980 1.4.2.4 nathanw sc->sc_phase = PH_BUS_FREE; /* initial phase */ 981 1.4.2.4 nathanw 982 1.4.2.4 nathanw DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 983 1.4.2.4 nathanw 984 1.4.2.4 nathanw if (((ti->flag & WIDE_NEGO_ENABLE) && 985 1.4.2.4 nathanw (ti->flag & WIDE_NEGO_DONE) == 0) || 986 1.4.2.4 nathanw ((ti->flag & SYNC_NEGO_ENABLE) && 987 1.4.2.4 nathanw (ti->flag & SYNC_NEGO_DONE) == 0)) { 988 1.4.2.4 nathanw sc->sc_state = TRM_MSGOUT; 989 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 990 1.4.2.4 nathanw MSG_IDENTIFY(lun, 0)); 991 1.4.2.4 nathanw bus_space_write_multi_1(iot, ioh, 992 1.4.2.4 nathanw TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 993 1.4.2.4 nathanw /* it's important for atn stop */ 994 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 995 1.4.2.4 nathanw DO_DATALATCH | DO_HWRESELECT); 996 1.4.2.4 nathanw /* SCSI command */ 997 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 998 1.4.2.4 nathanw DPRINTF(("select with SEL_ATNSTOP\n")); 999 1.4.2.4 nathanw return (0); 1000 1.4.2.4 nathanw } 1001 1.4.2.4 nathanw 1002 1.4.2.4 nathanw if (srb->tag[0] != 0) { 1003 1.4.2.4 nathanw /* Send identify message */ 1004 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1005 1.4.2.4 nathanw MSG_IDENTIFY(lun, 1)); 1006 1.4.2.4 nathanw /* Send Tag id */ 1007 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1008 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1009 1.4.2.4 nathanw scsicmd = SCMD_SEL_ATN3; 1010 1.4.2.4 nathanw DPRINTF(("select with SEL_ATN3\n")); 1011 1.4.2.4 nathanw } else { 1012 1.4.2.4 nathanw /* Send identify message */ 1013 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1014 1.4.2.4 nathanw MSG_IDENTIFY(lun, 1015 1.4.2.4 nathanw (ti->flag & NO_RESELECT) == 0 && 1016 1.4.2.4 nathanw (srb->flag & AUTO_REQSENSE) == 0 && 1017 1.4.2.4 nathanw (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1018 1.4.2.4 nathanw scsicmd = SCMD_SEL_ATN; 1019 1.4.2.4 nathanw DPRINTF(("select with SEL_ATN\n")); 1020 1.4.2.2 nathanw } 1021 1.4.2.4 nathanw sc->sc_state = TRM_START; 1022 1.4.2.4 nathanw 1023 1.4.2.4 nathanw /* 1024 1.4.2.4 nathanw * Send CDB ..command block... 1025 1.4.2.4 nathanw */ 1026 1.4.2.4 nathanw bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1027 1.4.2.4 nathanw 1028 1.4.2.4 nathanw /* 1029 1.4.2.4 nathanw * If trm_select returns 0: current interrupt status 1030 1.4.2.4 nathanw * is interrupt enable. It's said that SCSI processor is 1031 1.4.2.4 nathanw * unoccupied. 1032 1.4.2.4 nathanw */ 1033 1.4.2.4 nathanw sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1034 1.4.2.4 nathanw /* SCSI command */ 1035 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1036 1.4.2.4 nathanw return (0); 1037 1.4.2.2 nathanw } 1038 1.4.2.2 nathanw 1039 1.4.2.2 nathanw /* 1040 1.4.2.2 nathanw * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1041 1.4.2.2 nathanw */ 1042 1.4.2.2 nathanw static void 1043 1.4.2.2 nathanw trm_reset(sc) 1044 1.4.2.2 nathanw struct trm_softc *sc; 1045 1.4.2.2 nathanw { 1046 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1047 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1048 1.4.2.2 nathanw int s; 1049 1.4.2.2 nathanw 1050 1.4.2.4 nathanw DPRINTF(("trm_reset.........\n")); 1051 1.4.2.4 nathanw 1052 1.4.2.2 nathanw s = splbio(); 1053 1.4.2.2 nathanw 1054 1.4.2.2 nathanw /* disable SCSI and DMA interrupt */ 1055 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1056 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1057 1.4.2.2 nathanw 1058 1.4.2.2 nathanw trm_reset_scsi_bus(sc); 1059 1.4.2.4 nathanw DELAY(100000); 1060 1.4.2.2 nathanw 1061 1.4.2.2 nathanw /* Enable SCSI interrupt */ 1062 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1063 1.4.2.2 nathanw EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1064 1.4.2.2 nathanw EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1065 1.4.2.2 nathanw 1066 1.4.2.2 nathanw /* Enable DMA interrupt */ 1067 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1068 1.4.2.2 nathanw 1069 1.4.2.2 nathanw /* Clear DMA FIFO */ 1070 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1071 1.4.2.2 nathanw 1072 1.4.2.2 nathanw /* Clear SCSI FIFO */ 1073 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1074 1.4.2.2 nathanw 1075 1.4.2.4 nathanw sc->sc_actsrb = NULL; 1076 1.4.2.2 nathanw sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1077 1.4.2.2 nathanw 1078 1.4.2.2 nathanw splx(s); 1079 1.4.2.2 nathanw } 1080 1.4.2.2 nathanw 1081 1.4.2.2 nathanw static void 1082 1.4.2.2 nathanw trm_timeout(arg) 1083 1.4.2.2 nathanw void *arg; 1084 1.4.2.2 nathanw { 1085 1.4.2.2 nathanw struct trm_srb *srb = (struct trm_srb *)arg; 1086 1.4.2.2 nathanw struct scsipi_xfer *xs = srb->xs; 1087 1.4.2.2 nathanw struct scsipi_periph *periph = xs->xs_periph; 1088 1.4.2.2 nathanw struct trm_softc *sc; 1089 1.4.2.2 nathanw int s; 1090 1.4.2.2 nathanw 1091 1.4.2.2 nathanw if (xs == NULL) 1092 1.4.2.2 nathanw printf("trm_timeout called with xs == NULL\n"); 1093 1.4.2.2 nathanw 1094 1.4.2.2 nathanw else { 1095 1.4.2.2 nathanw scsipi_printaddr(xs->xs_periph); 1096 1.4.2.2 nathanw printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1097 1.4.2.2 nathanw } 1098 1.4.2.2 nathanw 1099 1.4.2.2 nathanw sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1100 1.4.2.2 nathanw 1101 1.4.2.2 nathanw trm_reset_scsi_bus(sc); 1102 1.4.2.4 nathanw s = splbio(); 1103 1.4.2.4 nathanw srb->flag |= SRB_TIMEOUT; 1104 1.4.2.4 nathanw trm_done(sc, srb); 1105 1.4.2.4 nathanw /* XXX needs more.. */ 1106 1.4.2.2 nathanw splx(s); 1107 1.4.2.2 nathanw } 1108 1.4.2.2 nathanw 1109 1.4.2.2 nathanw /* 1110 1.4.2.2 nathanw * Catch an interrupt from the adapter 1111 1.4.2.2 nathanw * Process pending device interrupts. 1112 1.4.2.2 nathanw */ 1113 1.4.2.2 nathanw static int 1114 1.4.2.4 nathanw trm_intr(arg) 1115 1.4.2.4 nathanw void *arg; 1116 1.4.2.2 nathanw { 1117 1.4.2.2 nathanw bus_space_tag_t iot; 1118 1.4.2.2 nathanw bus_space_handle_t ioh; 1119 1.4.2.2 nathanw struct trm_softc *sc; 1120 1.4.2.2 nathanw struct trm_srb *srb; 1121 1.4.2.4 nathanw int intstat, stat; 1122 1.4.2.2 nathanw 1123 1.4.2.4 nathanw DPRINTF(("trm_intr......\n")); 1124 1.4.2.4 nathanw sc = (struct trm_softc *)arg; 1125 1.4.2.2 nathanw if (sc == NULL) 1126 1.4.2.2 nathanw return (0); 1127 1.4.2.2 nathanw 1128 1.4.2.4 nathanw iot = sc->sc_iot; 1129 1.4.2.4 nathanw ioh = sc->sc_ioh; 1130 1.4.2.4 nathanw 1131 1.4.2.2 nathanw stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1132 1.4.2.2 nathanw if ((stat & SCSIINTERRUPT) == 0) 1133 1.4.2.2 nathanw return (0); 1134 1.4.2.2 nathanw 1135 1.4.2.4 nathanw DPRINTF(("stat = %04x, ", stat)); 1136 1.4.2.2 nathanw intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1137 1.4.2.2 nathanw 1138 1.4.2.4 nathanw DPRINTF(("intstat=%02x, ", intstat)); 1139 1.4.2.2 nathanw if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1140 1.4.2.4 nathanw DPRINTF(("\n")); 1141 1.4.2.2 nathanw trm_disconnect(sc); 1142 1.4.2.2 nathanw return (1); 1143 1.4.2.2 nathanw } 1144 1.4.2.2 nathanw if (intstat & INT_RESELECTED) { 1145 1.4.2.4 nathanw DPRINTF(("\n")); 1146 1.4.2.2 nathanw trm_reselect(sc); 1147 1.4.2.2 nathanw return (1); 1148 1.4.2.2 nathanw } 1149 1.4.2.2 nathanw if (intstat & INT_SCSIRESET) { 1150 1.4.2.4 nathanw DPRINTF(("\n")); 1151 1.4.2.2 nathanw trm_scsi_reset_detect(sc); 1152 1.4.2.2 nathanw return (1); 1153 1.4.2.2 nathanw } 1154 1.4.2.2 nathanw if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1155 1.4.2.4 nathanw srb = sc->sc_actsrb; 1156 1.4.2.4 nathanw DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1157 1.4.2.4 nathanw sc->sc_phase, sc->sc_state)); 1158 1.4.2.2 nathanw /* 1159 1.4.2.2 nathanw * software sequential machine 1160 1.4.2.2 nathanw */ 1161 1.4.2.2 nathanw 1162 1.4.2.2 nathanw /* 1163 1.4.2.4 nathanw * call phase0 functions... "phase entry" handle 1164 1.4.2.4 nathanw * every phase before start transfer 1165 1.4.2.2 nathanw */ 1166 1.4.2.4 nathanw switch (sc->sc_phase) { 1167 1.4.2.4 nathanw case PH_DATA_OUT: 1168 1.4.2.4 nathanw trm_dataout_phase0(sc, stat); 1169 1.4.2.4 nathanw break; 1170 1.4.2.4 nathanw case PH_DATA_IN: 1171 1.4.2.4 nathanw trm_datain_phase0(sc, stat); 1172 1.4.2.4 nathanw break; 1173 1.4.2.4 nathanw case PH_COMMAND: 1174 1.4.2.4 nathanw break; 1175 1.4.2.4 nathanw case PH_STATUS: 1176 1.4.2.4 nathanw trm_status_phase0(sc); 1177 1.4.2.4 nathanw stat = PH_BUS_FREE; 1178 1.4.2.4 nathanw break; 1179 1.4.2.4 nathanw case PH_MSG_OUT: 1180 1.4.2.4 nathanw if (sc->sc_state == TRM_UNEXPECT_RESEL || 1181 1.4.2.4 nathanw sc->sc_state == TRM_ABORT_SENT) 1182 1.4.2.4 nathanw stat = PH_BUS_FREE; 1183 1.4.2.4 nathanw break; 1184 1.4.2.4 nathanw case PH_MSG_IN: 1185 1.4.2.4 nathanw trm_msgin_phase0(sc); 1186 1.4.2.4 nathanw stat = PH_BUS_FREE; 1187 1.4.2.4 nathanw break; 1188 1.4.2.4 nathanw case PH_BUS_FREE: 1189 1.4.2.4 nathanw break; 1190 1.4.2.4 nathanw default: 1191 1.4.2.4 nathanw printf("%s: unexpected phase in trm_intr() phase0\n", 1192 1.4.2.4 nathanw sc->sc_dev.dv_xname); 1193 1.4.2.4 nathanw break; 1194 1.4.2.4 nathanw } 1195 1.4.2.2 nathanw 1196 1.4.2.4 nathanw sc->sc_phase = stat & PHASEMASK; 1197 1.4.2.4 nathanw 1198 1.4.2.4 nathanw switch (sc->sc_phase) { 1199 1.4.2.4 nathanw case PH_DATA_OUT: 1200 1.4.2.4 nathanw trm_dataio_xfer(sc, XFERDATAOUT); 1201 1.4.2.4 nathanw break; 1202 1.4.2.4 nathanw case PH_DATA_IN: 1203 1.4.2.4 nathanw trm_dataio_xfer(sc, XFERDATAIN); 1204 1.4.2.4 nathanw break; 1205 1.4.2.4 nathanw case PH_COMMAND: 1206 1.4.2.4 nathanw trm_command_phase1(sc); 1207 1.4.2.4 nathanw break; 1208 1.4.2.4 nathanw case PH_STATUS: 1209 1.4.2.4 nathanw trm_status_phase1(sc); 1210 1.4.2.4 nathanw break; 1211 1.4.2.4 nathanw case PH_MSG_OUT: 1212 1.4.2.4 nathanw trm_msgout_phase1(sc); 1213 1.4.2.4 nathanw break; 1214 1.4.2.4 nathanw case PH_MSG_IN: 1215 1.4.2.4 nathanw trm_msgin_phase1(sc); 1216 1.4.2.4 nathanw break; 1217 1.4.2.4 nathanw case PH_BUS_FREE: 1218 1.4.2.4 nathanw break; 1219 1.4.2.4 nathanw default: 1220 1.4.2.4 nathanw printf("%s: unexpected phase in trm_intr() phase1\n", 1221 1.4.2.4 nathanw sc->sc_dev.dv_xname); 1222 1.4.2.4 nathanw break; 1223 1.4.2.4 nathanw } 1224 1.4.2.2 nathanw 1225 1.4.2.2 nathanw return (1); 1226 1.4.2.2 nathanw } 1227 1.4.2.2 nathanw return (0); 1228 1.4.2.2 nathanw } 1229 1.4.2.2 nathanw 1230 1.4.2.2 nathanw static void 1231 1.4.2.4 nathanw trm_msgout_phase1(sc) 1232 1.4.2.2 nathanw struct trm_softc *sc; 1233 1.4.2.2 nathanw { 1234 1.4.2.4 nathanw bus_space_tag_t iot = sc->sc_iot; 1235 1.4.2.4 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1236 1.4.2.4 nathanw struct trm_srb *srb; 1237 1.4.2.4 nathanw struct scsipi_periph *periph; 1238 1.4.2.4 nathanw struct trm_tinfo *ti; 1239 1.4.2.2 nathanw 1240 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1241 1.4.2.2 nathanw 1242 1.4.2.4 nathanw srb = sc->sc_actsrb; 1243 1.4.2.2 nathanw 1244 1.4.2.4 nathanw /* message out phase */ 1245 1.4.2.4 nathanw if (srb != NULL) { 1246 1.4.2.4 nathanw periph = srb->xs->xs_periph; 1247 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 1248 1.4.2.4 nathanw 1249 1.4.2.4 nathanw if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1250 1.4.2.4 nathanw (ti->flag & WIDE_NEGO_ENABLE)) { 1251 1.4.2.4 nathanw /* send WDTR */ 1252 1.4.2.4 nathanw ti->flag &= ~SYNC_NEGO_DONE; 1253 1.4.2.4 nathanw 1254 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1255 1.4.2.4 nathanw sc->sc_msgbuf[1] = MSG_EXTENDED; 1256 1.4.2.4 nathanw sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1257 1.4.2.4 nathanw sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1258 1.4.2.4 nathanw sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1259 1.4.2.4 nathanw sc->sc_msgcnt = 5; 1260 1.4.2.4 nathanw 1261 1.4.2.4 nathanw ti->flag |= WIDE_NEGO_DOING; 1262 1.4.2.4 nathanw } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1263 1.4.2.4 nathanw (ti->flag & SYNC_NEGO_ENABLE)) { 1264 1.4.2.4 nathanw /* send SDTR */ 1265 1.4.2.4 nathanw int cnt = 0; 1266 1.4.2.4 nathanw 1267 1.4.2.4 nathanw if ((ti->flag & WIDE_NEGO_DONE) == 0) 1268 1.4.2.4 nathanw sc->sc_msgbuf[cnt++] = 1269 1.4.2.4 nathanw MSG_IDENTIFY(periph->periph_lun, 0); 1270 1.4.2.4 nathanw 1271 1.4.2.4 nathanw sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1272 1.4.2.4 nathanw sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1273 1.4.2.4 nathanw sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1274 1.4.2.4 nathanw sc->sc_msgbuf[cnt++] = ti->period; 1275 1.4.2.4 nathanw sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1276 1.4.2.4 nathanw sc->sc_msgcnt = cnt; 1277 1.4.2.4 nathanw ti->flag |= SYNC_NEGO_DOING; 1278 1.4.2.4 nathanw } 1279 1.4.2.4 nathanw } 1280 1.4.2.4 nathanw if (sc->sc_msgcnt == 0) { 1281 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_ABORT; 1282 1.4.2.4 nathanw sc->sc_msgcnt = 1; 1283 1.4.2.4 nathanw sc->sc_state = TRM_ABORT_SENT; 1284 1.4.2.4 nathanw } 1285 1.4.2.4 nathanw 1286 1.4.2.4 nathanw DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1287 1.4.2.4 nathanw DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1288 1.4.2.4 nathanw sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1289 1.4.2.4 nathanw sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1290 1.4.2.4 nathanw 1291 1.4.2.4 nathanw bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1292 1.4.2.4 nathanw sc->sc_msgbuf, sc->sc_msgcnt); 1293 1.4.2.4 nathanw sc->sc_msgcnt = 0; 1294 1.4.2.4 nathanw memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1295 1.4.2.2 nathanw 1296 1.4.2.2 nathanw /* it's important for atn stop */ 1297 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1298 1.4.2.2 nathanw 1299 1.4.2.2 nathanw /* 1300 1.4.2.4 nathanw * SCSI command 1301 1.4.2.2 nathanw */ 1302 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1303 1.4.2.2 nathanw } 1304 1.4.2.2 nathanw 1305 1.4.2.2 nathanw static void 1306 1.4.2.4 nathanw trm_command_phase1(sc) 1307 1.4.2.2 nathanw struct trm_softc *sc; 1308 1.4.2.2 nathanw { 1309 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1310 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1311 1.4.2.4 nathanw struct trm_srb *srb; 1312 1.4.2.4 nathanw 1313 1.4.2.4 nathanw srb = sc->sc_actsrb; 1314 1.4.2.4 nathanw if (srb == NULL) { 1315 1.4.2.4 nathanw DPRINTF(("trm_command_phase1: no active srb\n")); 1316 1.4.2.4 nathanw return; 1317 1.4.2.4 nathanw } 1318 1.4.2.2 nathanw 1319 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1320 1.4.2.3 nathanw bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1321 1.4.2.2 nathanw 1322 1.4.2.4 nathanw sc->sc_state = TRM_COMMAND; 1323 1.4.2.2 nathanw /* it's important for atn stop */ 1324 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1325 1.4.2.2 nathanw 1326 1.4.2.2 nathanw /* 1327 1.4.2.4 nathanw * SCSI command 1328 1.4.2.2 nathanw */ 1329 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1330 1.4.2.2 nathanw } 1331 1.4.2.2 nathanw 1332 1.4.2.2 nathanw static void 1333 1.4.2.4 nathanw trm_dataout_phase0(sc, stat) 1334 1.4.2.2 nathanw struct trm_softc *sc; 1335 1.4.2.4 nathanw int stat; 1336 1.4.2.2 nathanw { 1337 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1338 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1339 1.4.2.4 nathanw struct trm_srb *srb; 1340 1.4.2.4 nathanw struct scsipi_periph *periph; 1341 1.4.2.4 nathanw struct trm_tinfo *ti; 1342 1.4.2.2 nathanw struct trm_sg_entry *sg; 1343 1.4.2.2 nathanw int sgindex; 1344 1.4.2.2 nathanw u_int32_t xferlen, leftcnt = 0; 1345 1.4.2.2 nathanw 1346 1.4.2.4 nathanw if (sc->sc_state == TRM_XFERPAD) 1347 1.4.2.4 nathanw return; 1348 1.4.2.4 nathanw 1349 1.4.2.4 nathanw srb = sc->sc_actsrb; 1350 1.4.2.4 nathanw if (srb == NULL) { 1351 1.4.2.4 nathanw DPRINTF(("trm_dataout_phase0: no active srb\n")); 1352 1.4.2.4 nathanw return; 1353 1.4.2.4 nathanw } 1354 1.4.2.4 nathanw periph = srb->xs->xs_periph; 1355 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 1356 1.4.2.2 nathanw 1357 1.4.2.4 nathanw if ((stat & PARITYERROR) != 0) 1358 1.4.2.4 nathanw srb->flag |= PARITY_ERROR; 1359 1.4.2.2 nathanw 1360 1.4.2.4 nathanw if ((stat & SCSIXFERDONE) == 0) { 1361 1.4.2.4 nathanw /* 1362 1.4.2.4 nathanw * when data transfer from DMA FIFO to SCSI FIFO 1363 1.4.2.4 nathanw * if there was some data left in SCSI FIFO 1364 1.4.2.4 nathanw */ 1365 1.4.2.4 nathanw leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1366 1.4.2.4 nathanw SCSI_FIFOCNT_MASK; 1367 1.4.2.4 nathanw if (ti->synctl & WIDE_SYNC) 1368 1.4.2.2 nathanw /* 1369 1.4.2.4 nathanw * if WIDE scsi SCSI FIFOCNT unit is word 1370 1.4.2.4 nathanw * so need to * 2 1371 1.4.2.2 nathanw */ 1372 1.4.2.4 nathanw leftcnt <<= 1; 1373 1.4.2.4 nathanw } 1374 1.4.2.4 nathanw /* 1375 1.4.2.4 nathanw * calculate all the residue data that was not yet transferred 1376 1.4.2.4 nathanw * SCSI transfer counter + left in SCSI FIFO data 1377 1.4.2.4 nathanw * 1378 1.4.2.4 nathanw * .....TRM_SCSI_XCNT (24bits) 1379 1.4.2.4 nathanw * The counter always decrements by one for every SCSI 1380 1.4.2.4 nathanw * byte transfer. 1381 1.4.2.4 nathanw * .....TRM_SCSI_FIFOCNT ( 5bits) 1382 1.4.2.4 nathanw * The counter is SCSI FIFO offset counter 1383 1.4.2.4 nathanw */ 1384 1.4.2.4 nathanw leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1385 1.4.2.4 nathanw if (leftcnt == 1) { 1386 1.4.2.4 nathanw leftcnt = 0; 1387 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1388 1.4.2.4 nathanw } 1389 1.4.2.4 nathanw if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1390 1.4.2.4 nathanw while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1391 1.4.2.4 nathanw DMAXFERCOMP) == 0) 1392 1.4.2.4 nathanw ; /* XXX needs timeout */ 1393 1.4.2.4 nathanw 1394 1.4.2.4 nathanw srb->buflen = 0; 1395 1.4.2.4 nathanw } else { 1396 1.4.2.4 nathanw /* Update SG list */ 1397 1.4.2.4 nathanw 1398 1.4.2.2 nathanw /* 1399 1.4.2.4 nathanw * if transfer not yet complete 1400 1.4.2.4 nathanw * there were some data residue in SCSI FIFO or 1401 1.4.2.4 nathanw * SCSI transfer counter not empty 1402 1.4.2.2 nathanw */ 1403 1.4.2.4 nathanw if (srb->buflen != leftcnt) { 1404 1.4.2.4 nathanw /* data that had transferred length */ 1405 1.4.2.4 nathanw xferlen = srb->buflen - leftcnt; 1406 1.4.2.4 nathanw 1407 1.4.2.4 nathanw /* next time to be transferred length */ 1408 1.4.2.4 nathanw srb->buflen = leftcnt; 1409 1.4.2.2 nathanw 1410 1.4.2.2 nathanw /* 1411 1.4.2.4 nathanw * parsing from last time disconnect sgindex 1412 1.4.2.2 nathanw */ 1413 1.4.2.4 nathanw sg = srb->sgentry + srb->sgindex; 1414 1.4.2.4 nathanw for (sgindex = srb->sgindex; 1415 1.4.2.4 nathanw sgindex < srb->sgcnt; 1416 1.4.2.4 nathanw sgindex++, sg++) { 1417 1.4.2.2 nathanw /* 1418 1.4.2.4 nathanw * find last time which SG transfer 1419 1.4.2.4 nathanw * be disconnect 1420 1.4.2.2 nathanw */ 1421 1.4.2.4 nathanw if (xferlen >= le32toh(sg->length)) 1422 1.4.2.4 nathanw xferlen -= le32toh(sg->length); 1423 1.4.2.4 nathanw else { 1424 1.4.2.2 nathanw /* 1425 1.4.2.4 nathanw * update last time 1426 1.4.2.4 nathanw * disconnected SG list 1427 1.4.2.2 nathanw */ 1428 1.4.2.4 nathanw /* residue data length */ 1429 1.4.2.4 nathanw sg->length = 1430 1.4.2.4 nathanw htole32(le32toh(sg->length) 1431 1.4.2.4 nathanw - xferlen); 1432 1.4.2.4 nathanw /* residue data pointer */ 1433 1.4.2.4 nathanw sg->address = 1434 1.4.2.4 nathanw htole32(le32toh(sg->address) 1435 1.4.2.4 nathanw + xferlen); 1436 1.4.2.4 nathanw srb->sgindex = sgindex; 1437 1.4.2.4 nathanw break; 1438 1.4.2.2 nathanw } 1439 1.4.2.2 nathanw } 1440 1.4.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1441 1.4.2.4 nathanw srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1442 1.4.2.2 nathanw } 1443 1.4.2.2 nathanw } 1444 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1445 1.4.2.2 nathanw } 1446 1.4.2.2 nathanw 1447 1.4.2.2 nathanw static void 1448 1.4.2.4 nathanw trm_datain_phase0(sc, stat) 1449 1.4.2.2 nathanw struct trm_softc *sc; 1450 1.4.2.4 nathanw int stat; 1451 1.4.2.2 nathanw { 1452 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1453 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1454 1.4.2.4 nathanw struct trm_srb *srb; 1455 1.4.2.2 nathanw struct trm_sg_entry *sg; 1456 1.4.2.2 nathanw int sgindex; 1457 1.4.2.2 nathanw u_int32_t xferlen, leftcnt = 0; 1458 1.4.2.2 nathanw 1459 1.4.2.4 nathanw if (sc->sc_state == TRM_XFERPAD) 1460 1.4.2.4 nathanw return; 1461 1.4.2.2 nathanw 1462 1.4.2.4 nathanw srb = sc->sc_actsrb; 1463 1.4.2.4 nathanw if (srb == NULL) { 1464 1.4.2.4 nathanw DPRINTF(("trm_datain_phase0: no active srb\n")); 1465 1.4.2.4 nathanw return; 1466 1.4.2.4 nathanw } 1467 1.4.2.4 nathanw 1468 1.4.2.4 nathanw if (stat & PARITYERROR) 1469 1.4.2.4 nathanw srb->flag |= PARITY_ERROR; 1470 1.4.2.4 nathanw 1471 1.4.2.4 nathanw leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1472 1.4.2.4 nathanw if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1473 1.4.2.4 nathanw while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1474 1.4.2.4 nathanw DMAXFERCOMP) == 0) 1475 1.4.2.4 nathanw ; /* XXX needs timeout */ 1476 1.4.2.4 nathanw 1477 1.4.2.4 nathanw srb->buflen = 0; 1478 1.4.2.4 nathanw } else { /* phase changed */ 1479 1.4.2.4 nathanw /* 1480 1.4.2.4 nathanw * parsing the case: 1481 1.4.2.4 nathanw * when a transfer not yet complete 1482 1.4.2.4 nathanw * but be disconnected by upper layer 1483 1.4.2.4 nathanw * if transfer not yet complete 1484 1.4.2.4 nathanw * there were some data residue in SCSI FIFO or 1485 1.4.2.4 nathanw * SCSI transfer counter not empty 1486 1.4.2.4 nathanw */ 1487 1.4.2.4 nathanw if (srb->buflen != leftcnt) { 1488 1.4.2.2 nathanw /* 1489 1.4.2.4 nathanw * data that had transferred length 1490 1.4.2.2 nathanw */ 1491 1.4.2.4 nathanw xferlen = srb->buflen - leftcnt; 1492 1.4.2.2 nathanw 1493 1.4.2.4 nathanw /* 1494 1.4.2.4 nathanw * next time to be transferred length 1495 1.4.2.4 nathanw */ 1496 1.4.2.4 nathanw srb->buflen = leftcnt; 1497 1.4.2.2 nathanw 1498 1.4.2.4 nathanw /* 1499 1.4.2.4 nathanw * parsing from last time disconnect sgindex 1500 1.4.2.4 nathanw */ 1501 1.4.2.4 nathanw sg = srb->sgentry + srb->sgindex; 1502 1.4.2.4 nathanw for (sgindex = srb->sgindex; 1503 1.4.2.4 nathanw sgindex < srb->sgcnt; 1504 1.4.2.4 nathanw sgindex++, sg++) { 1505 1.4.2.2 nathanw /* 1506 1.4.2.4 nathanw * find last time which SG transfer 1507 1.4.2.4 nathanw * be disconnect 1508 1.4.2.2 nathanw */ 1509 1.4.2.4 nathanw if (xferlen >= le32toh(sg->length)) 1510 1.4.2.4 nathanw xferlen -= le32toh(sg->length); 1511 1.4.2.4 nathanw else { 1512 1.4.2.2 nathanw /* 1513 1.4.2.4 nathanw * update last time 1514 1.4.2.4 nathanw * disconnected SG list 1515 1.4.2.2 nathanw */ 1516 1.4.2.4 nathanw /* residue data length */ 1517 1.4.2.4 nathanw sg->length = 1518 1.4.2.4 nathanw htole32(le32toh(sg->length) 1519 1.4.2.4 nathanw - xferlen); 1520 1.4.2.4 nathanw /* residue data pointer */ 1521 1.4.2.4 nathanw sg->address = 1522 1.4.2.4 nathanw htole32(le32toh(sg->address) 1523 1.4.2.4 nathanw + xferlen); 1524 1.4.2.4 nathanw srb->sgindex = sgindex; 1525 1.4.2.4 nathanw break; 1526 1.4.2.2 nathanw } 1527 1.4.2.2 nathanw } 1528 1.4.2.4 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1529 1.4.2.4 nathanw srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1530 1.4.2.2 nathanw } 1531 1.4.2.2 nathanw } 1532 1.4.2.2 nathanw } 1533 1.4.2.2 nathanw 1534 1.4.2.2 nathanw static void 1535 1.4.2.4 nathanw trm_dataio_xfer(sc, iodir) 1536 1.4.2.2 nathanw struct trm_softc *sc; 1537 1.4.2.2 nathanw int iodir; 1538 1.4.2.2 nathanw { 1539 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1540 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1541 1.4.2.4 nathanw struct trm_srb *srb; 1542 1.4.2.4 nathanw struct scsipi_periph *periph; 1543 1.4.2.4 nathanw struct trm_tinfo *ti; 1544 1.4.2.4 nathanw 1545 1.4.2.4 nathanw srb = sc->sc_actsrb; 1546 1.4.2.4 nathanw if (srb == NULL) { 1547 1.4.2.4 nathanw DPRINTF(("trm_dataio_xfer: no active srb\n")); 1548 1.4.2.4 nathanw return; 1549 1.4.2.4 nathanw } 1550 1.4.2.4 nathanw periph = srb->xs->xs_periph; 1551 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 1552 1.4.2.2 nathanw 1553 1.4.2.2 nathanw if (srb->sgindex < srb->sgcnt) { 1554 1.4.2.2 nathanw if (srb->buflen > 0) { 1555 1.4.2.2 nathanw /* 1556 1.4.2.2 nathanw * load what physical address of Scatter/Gather 1557 1.4.2.2 nathanw * list table want to be transfer 1558 1.4.2.2 nathanw */ 1559 1.4.2.4 nathanw sc->sc_state = TRM_DATA_XFER; 1560 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1561 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1562 1.4.2.2 nathanw srb->sgaddr + 1563 1.4.2.2 nathanw srb->sgindex * sizeof(struct trm_sg_entry)); 1564 1.4.2.2 nathanw /* 1565 1.4.2.2 nathanw * load how many bytes in the Scatter/Gather list table 1566 1.4.2.2 nathanw */ 1567 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1568 1.4.2.2 nathanw (srb->sgcnt - srb->sgindex) 1569 1.4.2.2 nathanw * sizeof(struct trm_sg_entry)); 1570 1.4.2.2 nathanw /* 1571 1.4.2.2 nathanw * load total xfer length (24bits) max value 16Mbyte 1572 1.4.2.2 nathanw */ 1573 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1574 1.4.2.2 nathanw /* Start DMA transfer */ 1575 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1576 1.4.2.2 nathanw iodir | SGXFER); 1577 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1578 1.4.2.2 nathanw STARTDMAXFER); 1579 1.4.2.2 nathanw 1580 1.4.2.2 nathanw /* Start SCSI transfer */ 1581 1.4.2.2 nathanw /* it's important for atn stop */ 1582 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1583 1.4.2.2 nathanw DO_DATALATCH); 1584 1.4.2.2 nathanw 1585 1.4.2.2 nathanw /* 1586 1.4.2.4 nathanw * SCSI command 1587 1.4.2.2 nathanw */ 1588 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1589 1.4.2.2 nathanw (iodir == XFERDATAOUT) ? 1590 1.4.2.2 nathanw SCMD_DMA_OUT : SCMD_DMA_IN); 1591 1.4.2.2 nathanw } else { /* xfer pad */ 1592 1.4.2.2 nathanw if (srb->sgcnt) { 1593 1.4.2.2 nathanw srb->hastat = H_OVER_UNDER_RUN; 1594 1.4.2.2 nathanw } 1595 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1596 1.4.2.4 nathanw (ti->synctl & WIDE_SYNC) ? 2 : 1); 1597 1.4.2.2 nathanw 1598 1.4.2.2 nathanw if (iodir == XFERDATAOUT) 1599 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1600 1.4.2.2 nathanw else 1601 1.4.2.2 nathanw bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1602 1.4.2.2 nathanw 1603 1.4.2.4 nathanw sc->sc_state = TRM_XFERPAD; 1604 1.4.2.2 nathanw /* it's important for atn stop */ 1605 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1606 1.4.2.2 nathanw DO_DATALATCH); 1607 1.4.2.2 nathanw 1608 1.4.2.2 nathanw /* 1609 1.4.2.4 nathanw * SCSI command 1610 1.4.2.2 nathanw */ 1611 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1612 1.4.2.2 nathanw (iodir == XFERDATAOUT) ? 1613 1.4.2.2 nathanw SCMD_FIFO_OUT : SCMD_FIFO_IN); 1614 1.4.2.2 nathanw } 1615 1.4.2.2 nathanw } 1616 1.4.2.2 nathanw } 1617 1.4.2.2 nathanw 1618 1.4.2.2 nathanw static void 1619 1.4.2.4 nathanw trm_status_phase0(sc) 1620 1.4.2.2 nathanw struct trm_softc *sc; 1621 1.4.2.2 nathanw { 1622 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1623 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1624 1.4.2.4 nathanw struct trm_srb *srb; 1625 1.4.2.2 nathanw 1626 1.4.2.4 nathanw srb = sc->sc_actsrb; 1627 1.4.2.4 nathanw if (srb == NULL) { 1628 1.4.2.4 nathanw DPRINTF(("trm_status_phase0: no active srb\n")); 1629 1.4.2.4 nathanw return; 1630 1.4.2.4 nathanw } 1631 1.4.2.2 nathanw srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1632 1.4.2.4 nathanw sc->sc_state = TRM_COMPLETED; 1633 1.4.2.2 nathanw /* it's important for atn stop */ 1634 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1635 1.4.2.2 nathanw 1636 1.4.2.2 nathanw /* 1637 1.4.2.4 nathanw * SCSI command 1638 1.4.2.2 nathanw */ 1639 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1640 1.4.2.2 nathanw } 1641 1.4.2.2 nathanw 1642 1.4.2.2 nathanw static void 1643 1.4.2.4 nathanw trm_status_phase1(sc) 1644 1.4.2.2 nathanw struct trm_softc *sc; 1645 1.4.2.2 nathanw { 1646 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1647 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1648 1.4.2.2 nathanw 1649 1.4.2.2 nathanw if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1650 1.4.2.2 nathanw if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1651 1.4.2.2 nathanw & SCSI_FIFO_EMPTY) == 0) 1652 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1653 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_CLRFIFO); 1654 1.4.2.2 nathanw if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1655 1.4.2.2 nathanw & DMA_FIFO_EMPTY) == 0) 1656 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1657 1.4.2.2 nathanw } else { 1658 1.4.2.2 nathanw if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1659 1.4.2.2 nathanw & DMA_FIFO_EMPTY) == 0) 1660 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1661 1.4.2.2 nathanw if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1662 1.4.2.2 nathanw & SCSI_FIFO_EMPTY) == 0) 1663 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1664 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_CLRFIFO); 1665 1.4.2.2 nathanw } 1666 1.4.2.4 nathanw sc->sc_state = TRM_STATUS; 1667 1.4.2.2 nathanw /* it's important for atn stop */ 1668 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1669 1.4.2.2 nathanw 1670 1.4.2.2 nathanw /* 1671 1.4.2.4 nathanw * SCSI command 1672 1.4.2.2 nathanw */ 1673 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1674 1.4.2.2 nathanw } 1675 1.4.2.2 nathanw 1676 1.4.2.2 nathanw static void 1677 1.4.2.4 nathanw trm_msgin_phase0(sc) 1678 1.4.2.2 nathanw struct trm_softc *sc; 1679 1.4.2.2 nathanw { 1680 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1681 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1682 1.4.2.4 nathanw struct trm_srb *srb; 1683 1.4.2.4 nathanw struct scsipi_periph *periph; 1684 1.4.2.4 nathanw struct trm_tinfo *ti; 1685 1.4.2.4 nathanw int index; 1686 1.4.2.2 nathanw u_int8_t msgin_code; 1687 1.4.2.2 nathanw 1688 1.4.2.2 nathanw msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1689 1.4.2.4 nathanw if (sc->sc_state != TRM_EXTEND_MSGIN) { 1690 1.4.2.4 nathanw DPRINTF(("msgin: code = %02x\n", msgin_code)); 1691 1.4.2.4 nathanw switch (msgin_code) { 1692 1.4.2.4 nathanw case MSG_DISCONNECT: 1693 1.4.2.4 nathanw sc->sc_state = TRM_DISCONNECTED; 1694 1.4.2.4 nathanw break; 1695 1.4.2.4 nathanw 1696 1.4.2.4 nathanw case MSG_SAVEDATAPOINTER: 1697 1.4.2.4 nathanw break; 1698 1.4.2.4 nathanw 1699 1.4.2.4 nathanw case MSG_EXTENDED: 1700 1.4.2.4 nathanw case MSG_SIMPLE_Q_TAG: 1701 1.4.2.4 nathanw case MSG_HEAD_OF_Q_TAG: 1702 1.4.2.4 nathanw case MSG_ORDERED_Q_TAG: 1703 1.4.2.4 nathanw sc->sc_state = TRM_EXTEND_MSGIN; 1704 1.4.2.2 nathanw /* extended message (01h) */ 1705 1.4.2.4 nathanw sc->sc_msgbuf[0] = msgin_code; 1706 1.4.2.2 nathanw 1707 1.4.2.4 nathanw sc->sc_msgcnt = 1; 1708 1.4.2.2 nathanw /* extended message length (n) */ 1709 1.4.2.4 nathanw sc->sc_msg = &sc->sc_msgbuf[1]; 1710 1.4.2.2 nathanw 1711 1.4.2.4 nathanw break; 1712 1.4.2.4 nathanw case MSG_MESSAGE_REJECT: 1713 1.4.2.2 nathanw /* Reject message */ 1714 1.4.2.4 nathanw srb = sc->sc_actsrb; 1715 1.4.2.4 nathanw if (srb == NULL) { 1716 1.4.2.4 nathanw DPRINTF(("trm_msgin_phase0: " 1717 1.4.2.4 nathanw " message reject without actsrb\n")); 1718 1.4.2.4 nathanw break; 1719 1.4.2.4 nathanw } 1720 1.4.2.4 nathanw periph = srb->xs->xs_periph; 1721 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 1722 1.4.2.4 nathanw 1723 1.4.2.4 nathanw if (ti->flag & WIDE_NEGO_ENABLE) { 1724 1.4.2.4 nathanw /* do wide nego reject */ 1725 1.4.2.4 nathanw ti->flag |= WIDE_NEGO_DONE; 1726 1.4.2.4 nathanw ti->flag &= 1727 1.4.2.4 nathanw ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1728 1.4.2.4 nathanw if ((ti->flag & SYNC_NEGO_ENABLE) && 1729 1.4.2.4 nathanw (ti->flag & SYNC_NEGO_DONE) == 0) { 1730 1.4.2.2 nathanw /* Set ATN, in case ATN was clear */ 1731 1.4.2.4 nathanw sc->sc_state = TRM_MSGOUT; 1732 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1733 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_SETATN); 1734 1.4.2.2 nathanw } else 1735 1.4.2.2 nathanw /* Clear ATN */ 1736 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1737 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_CLRATN); 1738 1.4.2.4 nathanw } else if (ti->flag & SYNC_NEGO_ENABLE) { 1739 1.4.2.2 nathanw /* do sync nego reject */ 1740 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1741 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_CLRATN); 1742 1.4.2.4 nathanw if (ti->flag & SYNC_NEGO_DOING) { 1743 1.4.2.4 nathanw ti->flag &=~(SYNC_NEGO_ENABLE | 1744 1.4.2.2 nathanw SYNC_NEGO_DONE); 1745 1.4.2.4 nathanw ti->synctl = 0; 1746 1.4.2.4 nathanw ti->offset = 0; 1747 1.4.2.4 nathanw bus_space_write_1(iot, ioh, 1748 1.4.2.4 nathanw TRM_SCSI_SYNC, ti->synctl); 1749 1.4.2.4 nathanw bus_space_write_1(iot, ioh, 1750 1.4.2.4 nathanw TRM_SCSI_OFFSET, ti->offset); 1751 1.4.2.2 nathanw } 1752 1.4.2.2 nathanw } 1753 1.4.2.4 nathanw break; 1754 1.4.2.4 nathanw 1755 1.4.2.4 nathanw case MSG_IGN_WIDE_RESIDUE: 1756 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1757 1.4.2.2 nathanw bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1758 1.4.2.4 nathanw break; 1759 1.4.2.4 nathanw 1760 1.4.2.4 nathanw default: 1761 1.4.2.2 nathanw /* 1762 1.4.2.2 nathanw * Restore data pointer message 1763 1.4.2.2 nathanw * Save data pointer message 1764 1.4.2.2 nathanw * Completion message 1765 1.4.2.2 nathanw * NOP message 1766 1.4.2.2 nathanw */ 1767 1.4.2.4 nathanw break; 1768 1.4.2.2 nathanw } 1769 1.4.2.2 nathanw } else { 1770 1.4.2.2 nathanw /* 1771 1.4.2.4 nathanw * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1772 1.4.2.4 nathanw * Parsing incoming extented messages 1773 1.4.2.2 nathanw */ 1774 1.4.2.4 nathanw *sc->sc_msg++ = msgin_code; 1775 1.4.2.4 nathanw sc->sc_msgcnt++; 1776 1.4.2.4 nathanw 1777 1.4.2.4 nathanw DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1778 1.4.2.4 nathanw DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1779 1.4.2.4 nathanw sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1780 1.4.2.4 nathanw sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1781 1.4.2.4 nathanw 1782 1.4.2.4 nathanw switch (sc->sc_msgbuf[0]) { 1783 1.4.2.4 nathanw case MSG_SIMPLE_Q_TAG: 1784 1.4.2.4 nathanw case MSG_HEAD_OF_Q_TAG: 1785 1.4.2.4 nathanw case MSG_ORDERED_Q_TAG: 1786 1.4.2.2 nathanw /* 1787 1.4.2.2 nathanw * is QUEUE tag message : 1788 1.4.2.2 nathanw * 1789 1.4.2.2 nathanw * byte 0: 1790 1.4.2.2 nathanw * HEAD QUEUE TAG (20h) 1791 1.4.2.2 nathanw * ORDERED QUEUE TAG (21h) 1792 1.4.2.2 nathanw * SIMPLE QUEUE TAG (22h) 1793 1.4.2.2 nathanw * byte 1: 1794 1.4.2.2 nathanw * Queue tag (00h - FFh) 1795 1.4.2.2 nathanw */ 1796 1.4.2.4 nathanw if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1797 1.4.2.4 nathanw /* XXX XXX XXX */ 1798 1.4.2.4 nathanw struct trm_linfo *li; 1799 1.4.2.4 nathanw int tagid; 1800 1.4.2.4 nathanw 1801 1.4.2.4 nathanw sc->sc_flag &= ~WAIT_TAGMSG; 1802 1.4.2.4 nathanw tagid = sc->sc_msgbuf[1]; 1803 1.4.2.4 nathanw ti = &sc->sc_tinfo[sc->resel_target]; 1804 1.4.2.4 nathanw li = ti->linfo[sc->resel_lun]; 1805 1.4.2.4 nathanw srb = li->queued[tagid]; 1806 1.4.2.4 nathanw if (srb != NULL) { 1807 1.4.2.4 nathanw sc->sc_actsrb = srb; 1808 1.4.2.4 nathanw sc->sc_state = TRM_DATA_XFER; 1809 1.4.2.4 nathanw break; 1810 1.4.2.2 nathanw } else { 1811 1.4.2.4 nathanw printf("%s: invalid tag id\n", 1812 1.4.2.4 nathanw sc->sc_dev.dv_xname); 1813 1.4.2.2 nathanw } 1814 1.4.2.4 nathanw 1815 1.4.2.4 nathanw sc->sc_state = TRM_UNEXPECT_RESEL; 1816 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1817 1.4.2.4 nathanw sc->sc_msgcnt = 1; 1818 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1819 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_SETATN); 1820 1.4.2.4 nathanw } else 1821 1.4.2.4 nathanw sc->sc_state = TRM_IDLE; 1822 1.4.2.4 nathanw break; 1823 1.4.2.4 nathanw 1824 1.4.2.4 nathanw case MSG_EXTENDED: 1825 1.4.2.4 nathanw srb = sc->sc_actsrb; 1826 1.4.2.4 nathanw if (srb == NULL) { 1827 1.4.2.4 nathanw DPRINTF(("trm_msgin_phase0: " 1828 1.4.2.4 nathanw "extended message without actsrb\n")); 1829 1.4.2.4 nathanw break; 1830 1.4.2.2 nathanw } 1831 1.4.2.4 nathanw periph = srb->xs->xs_periph; 1832 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 1833 1.4.2.4 nathanw 1834 1.4.2.4 nathanw if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1835 1.4.2.4 nathanw sc->sc_msgcnt == 4) { 1836 1.4.2.4 nathanw /* 1837 1.4.2.4 nathanw * is Wide data xfer Extended message : 1838 1.4.2.4 nathanw * ====================================== 1839 1.4.2.4 nathanw * WIDE DATA TRANSFER REQUEST 1840 1.4.2.4 nathanw * ====================================== 1841 1.4.2.4 nathanw * byte 0 : Extended message (01h) 1842 1.4.2.4 nathanw * byte 1 : Extended message length (02h) 1843 1.4.2.4 nathanw * byte 2 : WIDE DATA TRANSFER code (03h) 1844 1.4.2.4 nathanw * byte 3 : Transfer width exponent 1845 1.4.2.4 nathanw */ 1846 1.4.2.4 nathanw if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1847 1.4.2.4 nathanw /* Length is wrong, reject it */ 1848 1.4.2.4 nathanw ti->flag &= ~(WIDE_NEGO_ENABLE | 1849 1.4.2.4 nathanw WIDE_NEGO_DONE); 1850 1.4.2.4 nathanw sc->sc_state = TRM_MSGOUT; 1851 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1852 1.4.2.4 nathanw sc->sc_msgcnt = 1; 1853 1.4.2.4 nathanw bus_space_write_2(iot, ioh, 1854 1.4.2.4 nathanw TRM_SCSI_CONTROL, DO_SETATN); 1855 1.4.2.4 nathanw break; 1856 1.4.2.4 nathanw } 1857 1.4.2.4 nathanw 1858 1.4.2.4 nathanw if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1859 1.4.2.4 nathanw sc->sc_msgbuf[3] = 1860 1.4.2.4 nathanw MSG_EXT_WDTR_BUS_8_BIT; 1861 1.4.2.4 nathanw 1862 1.4.2.4 nathanw if (sc->sc_msgbuf[3] > 1863 1.4.2.4 nathanw MSG_EXT_WDTR_BUS_32_BIT) { 1864 1.4.2.2 nathanw /* reject_msg: */ 1865 1.4.2.4 nathanw ti->flag &= ~(WIDE_NEGO_ENABLE | 1866 1.4.2.2 nathanw WIDE_NEGO_DONE); 1867 1.4.2.4 nathanw sc->sc_state = TRM_MSGOUT; 1868 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1869 1.4.2.4 nathanw sc->sc_msgcnt = 1; 1870 1.4.2.2 nathanw bus_space_write_2(iot, ioh, 1871 1.4.2.2 nathanw TRM_SCSI_CONTROL, DO_SETATN); 1872 1.4.2.4 nathanw break; 1873 1.4.2.2 nathanw } 1874 1.4.2.4 nathanw if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1875 1.4.2.2 nathanw /* do 16 bits */ 1876 1.4.2.4 nathanw sc->sc_msgbuf[3] = 1877 1.4.2.4 nathanw MSG_EXT_WDTR_BUS_16_BIT; 1878 1.4.2.4 nathanw if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1879 1.4.2.4 nathanw ti->flag |= WIDE_NEGO_DONE; 1880 1.4.2.4 nathanw ti->flag &= ~(SYNC_NEGO_DONE | 1881 1.4.2.4 nathanw WIDE_NEGO_ENABLE); 1882 1.4.2.4 nathanw if (sc->sc_msgbuf[3] != 1883 1.4.2.4 nathanw MSG_EXT_WDTR_BUS_8_BIT) 1884 1.4.2.4 nathanw /* is Wide data xfer */ 1885 1.4.2.4 nathanw ti->synctl |= WIDE_SYNC; 1886 1.4.2.4 nathanw trm_update_xfer_mode(sc, 1887 1.4.2.4 nathanw periph->periph_target); 1888 1.4.2.2 nathanw } 1889 1.4.2.2 nathanw 1890 1.4.2.4 nathanw sc->sc_state = TRM_MSGOUT; 1891 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1892 1.4.2.2 nathanw DO_SETATN); 1893 1.4.2.4 nathanw break; 1894 1.4.2.2 nathanw 1895 1.4.2.4 nathanw } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1896 1.4.2.4 nathanw sc->sc_msgcnt == 5) { 1897 1.4.2.2 nathanw /* 1898 1.4.2.4 nathanw * is 8bit transfer Extended message : 1899 1.4.2.4 nathanw * ================================= 1900 1.4.2.4 nathanw * SYNCHRONOUS DATA TRANSFER REQUEST 1901 1.4.2.4 nathanw * ================================= 1902 1.4.2.4 nathanw * byte 0 : Extended message (01h) 1903 1.4.2.4 nathanw * byte 1 : Extended message length (03) 1904 1.4.2.4 nathanw * byte 2 : SYNC DATA TRANSFER code (01h) 1905 1.4.2.4 nathanw * byte 3 : Transfer period factor 1906 1.4.2.4 nathanw * byte 4 : REQ/ACK offset 1907 1.4.2.2 nathanw */ 1908 1.4.2.4 nathanw if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1909 1.4.2.4 nathanw /* reject_msg */ 1910 1.4.2.4 nathanw sc->sc_state = TRM_MSGOUT; 1911 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1912 1.4.2.4 nathanw sc->sc_msgcnt = 1; 1913 1.4.2.4 nathanw bus_space_write_2(iot, ioh, 1914 1.4.2.4 nathanw TRM_SCSI_CONTROL, DO_SETATN); 1915 1.4.2.4 nathanw break; 1916 1.4.2.2 nathanw } 1917 1.4.2.4 nathanw 1918 1.4.2.4 nathanw if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1919 1.4.2.4 nathanw ti->flag &= 1920 1.4.2.4 nathanw ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1921 1.4.2.4 nathanw ti->flag |= SYNC_NEGO_DONE; 1922 1.4.2.4 nathanw if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1923 1.4.2.4 nathanw sc->sc_msgbuf[3] = 0; 1924 1.4.2.4 nathanw if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1925 1.4.2.4 nathanw sc->sc_msgbuf[4] = 1926 1.4.2.4 nathanw TRM_MAX_OFFSET; 1927 1.4.2.4 nathanw 1928 1.4.2.4 nathanw if (sc->sc_msgbuf[3] == 0 || 1929 1.4.2.4 nathanw sc->sc_msgbuf[4] == 0) { 1930 1.4.2.4 nathanw /* set async */ 1931 1.4.2.4 nathanw ti->synctl = 0; 1932 1.4.2.4 nathanw ti->offset = 0; 1933 1.4.2.4 nathanw } else { 1934 1.4.2.4 nathanw /* set sync */ 1935 1.4.2.4 nathanw /* Transfer period factor */ 1936 1.4.2.4 nathanw ti->period = sc->sc_msgbuf[3]; 1937 1.4.2.4 nathanw /* REQ/ACK offset */ 1938 1.4.2.4 nathanw ti->offset = sc->sc_msgbuf[4]; 1939 1.4.2.4 nathanw for (index = 0; 1940 1.4.2.4 nathanw index < NPERIOD; 1941 1.4.2.4 nathanw index++) 1942 1.4.2.4 nathanw if (ti->period <= 1943 1.4.2.4 nathanw trm_clock_period[ 1944 1.4.2.4 nathanw index]) 1945 1.4.2.4 nathanw break; 1946 1.4.2.4 nathanw 1947 1.4.2.4 nathanw ti->synctl |= ALT_SYNC | index; 1948 1.4.2.4 nathanw } 1949 1.4.2.4 nathanw /* 1950 1.4.2.4 nathanw * program SCSI control register 1951 1.4.2.4 nathanw */ 1952 1.4.2.4 nathanw bus_space_write_1(iot, ioh, 1953 1.4.2.4 nathanw TRM_SCSI_SYNC, ti->synctl); 1954 1.4.2.4 nathanw bus_space_write_1(iot, ioh, 1955 1.4.2.4 nathanw TRM_SCSI_OFFSET, ti->offset); 1956 1.4.2.4 nathanw trm_update_xfer_mode(sc, 1957 1.4.2.4 nathanw periph->periph_target); 1958 1.4.2.4 nathanw } 1959 1.4.2.4 nathanw sc->sc_state = TRM_IDLE; 1960 1.4.2.2 nathanw } 1961 1.4.2.4 nathanw break; 1962 1.4.2.4 nathanw default: 1963 1.4.2.4 nathanw break; 1964 1.4.2.2 nathanw } 1965 1.4.2.2 nathanw } 1966 1.4.2.4 nathanw 1967 1.4.2.2 nathanw /* it's important for atn stop */ 1968 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1969 1.4.2.2 nathanw 1970 1.4.2.2 nathanw /* 1971 1.4.2.4 nathanw * SCSI command 1972 1.4.2.2 nathanw */ 1973 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1974 1.4.2.2 nathanw } 1975 1.4.2.2 nathanw 1976 1.4.2.2 nathanw static void 1977 1.4.2.4 nathanw trm_msgin_phase1(sc) 1978 1.4.2.2 nathanw struct trm_softc *sc; 1979 1.4.2.2 nathanw { 1980 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 1981 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 1982 1.4.2.2 nathanw 1983 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1984 1.4.2.2 nathanw bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1985 1.4.2.4 nathanw if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1986 1.4.2.4 nathanw sc->sc_state = TRM_MSGIN; 1987 1.4.2.2 nathanw } 1988 1.4.2.4 nathanw 1989 1.4.2.2 nathanw /* it's important for atn stop */ 1990 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1991 1.4.2.2 nathanw 1992 1.4.2.2 nathanw /* 1993 1.4.2.4 nathanw * SCSI command 1994 1.4.2.2 nathanw */ 1995 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1996 1.4.2.2 nathanw } 1997 1.4.2.2 nathanw 1998 1.4.2.2 nathanw static void 1999 1.4.2.2 nathanw trm_disconnect(sc) 2000 1.4.2.2 nathanw struct trm_softc *sc; 2001 1.4.2.2 nathanw { 2002 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2003 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2004 1.4.2.4 nathanw struct trm_srb *srb; 2005 1.4.2.4 nathanw int s; 2006 1.4.2.2 nathanw 2007 1.4.2.2 nathanw s = splbio(); 2008 1.4.2.2 nathanw 2009 1.4.2.4 nathanw srb = sc->sc_actsrb; 2010 1.4.2.4 nathanw DPRINTF(("trm_disconnect...............\n")); 2011 1.4.2.4 nathanw 2012 1.4.2.4 nathanw if (srb == NULL) { 2013 1.4.2.4 nathanw DPRINTF(("trm_disconnect: no active srb\n")); 2014 1.4.2.2 nathanw DELAY(1000); /* 1 msec */ 2015 1.4.2.2 nathanw 2016 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2017 1.4.2.2 nathanw DO_CLRFIFO | DO_HWRESELECT); 2018 1.4.2.2 nathanw return; 2019 1.4.2.2 nathanw } 2020 1.4.2.4 nathanw sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2021 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2022 1.4.2.2 nathanw DO_CLRFIFO | DO_HWRESELECT); 2023 1.4.2.2 nathanw DELAY(100); 2024 1.4.2.4 nathanw 2025 1.4.2.4 nathanw switch (sc->sc_state) { 2026 1.4.2.4 nathanw case TRM_UNEXPECT_RESEL: 2027 1.4.2.4 nathanw sc->sc_state = TRM_IDLE; 2028 1.4.2.4 nathanw break; 2029 1.4.2.4 nathanw 2030 1.4.2.4 nathanw case TRM_ABORT_SENT: 2031 1.4.2.4 nathanw goto finish; 2032 1.4.2.4 nathanw 2033 1.4.2.4 nathanw case TRM_START: 2034 1.4.2.4 nathanw case TRM_MSGOUT: 2035 1.4.2.4 nathanw { 2036 1.4.2.4 nathanw /* Selection time out - discard all LUNs if empty */ 2037 1.4.2.4 nathanw struct scsipi_periph *periph; 2038 1.4.2.4 nathanw struct trm_tinfo *ti; 2039 1.4.2.4 nathanw struct trm_linfo *li; 2040 1.4.2.4 nathanw int lun; 2041 1.4.2.4 nathanw 2042 1.4.2.4 nathanw DPRINTF(("selection timeout\n")); 2043 1.4.2.4 nathanw 2044 1.4.2.4 nathanw srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2045 1.4.2.4 nathanw 2046 1.4.2.4 nathanw periph = srb->xs->xs_periph; 2047 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 2048 1.4.2.4 nathanw for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2049 1.4.2.4 nathanw li = ti->linfo[lun]; 2050 1.4.2.4 nathanw if (li != NULL && 2051 1.4.2.4 nathanw li->untagged == NULL && li->used == 0) { 2052 1.4.2.4 nathanw ti->linfo[lun] = NULL; 2053 1.4.2.4 nathanw free(li, M_DEVBUF); 2054 1.4.2.4 nathanw } 2055 1.4.2.2 nathanw } 2056 1.4.2.2 nathanw } 2057 1.4.2.4 nathanw goto finish; 2058 1.4.2.4 nathanw 2059 1.4.2.4 nathanw case TRM_DISCONNECTED: 2060 1.4.2.4 nathanw sc->sc_actsrb = NULL; 2061 1.4.2.4 nathanw sc->sc_state = TRM_IDLE; 2062 1.4.2.4 nathanw goto sched; 2063 1.4.2.4 nathanw 2064 1.4.2.4 nathanw case TRM_COMPLETED: 2065 1.4.2.4 nathanw goto finish; 2066 1.4.2.2 nathanw } 2067 1.4.2.4 nathanw 2068 1.4.2.4 nathanw out: 2069 1.4.2.2 nathanw splx(s); 2070 1.4.2.4 nathanw return; 2071 1.4.2.4 nathanw 2072 1.4.2.4 nathanw finish: 2073 1.4.2.4 nathanw sc->sc_state = TRM_IDLE; 2074 1.4.2.4 nathanw trm_done(sc, srb); 2075 1.4.2.4 nathanw goto out; 2076 1.4.2.4 nathanw 2077 1.4.2.4 nathanw sched: 2078 1.4.2.4 nathanw trm_sched(sc); 2079 1.4.2.4 nathanw goto out; 2080 1.4.2.2 nathanw } 2081 1.4.2.2 nathanw 2082 1.4.2.2 nathanw static void 2083 1.4.2.2 nathanw trm_reselect(sc) 2084 1.4.2.2 nathanw struct trm_softc *sc; 2085 1.4.2.2 nathanw { 2086 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2087 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2088 1.4.2.4 nathanw struct trm_tinfo *ti; 2089 1.4.2.4 nathanw struct trm_linfo *li; 2090 1.4.2.4 nathanw int target, lun; 2091 1.4.2.4 nathanw 2092 1.4.2.4 nathanw DPRINTF(("trm_reselect.................\n")); 2093 1.4.2.4 nathanw 2094 1.4.2.4 nathanw if (sc->sc_actsrb != NULL) { 2095 1.4.2.4 nathanw /* arbitration lost but reselection win */ 2096 1.4.2.4 nathanw sc->sc_state = TRM_READY; 2097 1.4.2.4 nathanw target = sc->sc_actsrb->xs->xs_periph->periph_target; 2098 1.4.2.4 nathanw ti = &sc->sc_tinfo[target]; 2099 1.4.2.2 nathanw } else { 2100 1.4.2.4 nathanw /* Read Reselected Target Id and LUN */ 2101 1.4.2.4 nathanw target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2102 1.4.2.4 nathanw lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2103 1.4.2.4 nathanw ti = &sc->sc_tinfo[target]; 2104 1.4.2.4 nathanw li = ti->linfo[lun]; 2105 1.4.2.4 nathanw DPRINTF(("target = %d, lun = %d\n", target, lun)); 2106 1.4.2.4 nathanw 2107 1.4.2.4 nathanw /* 2108 1.4.2.4 nathanw * Check to see if we are running an un-tagged command. 2109 1.4.2.4 nathanw * Otherwise ack the IDENTIFY and wait for a tag message. 2110 1.4.2.4 nathanw */ 2111 1.4.2.4 nathanw if (li != NULL) { 2112 1.4.2.4 nathanw if (li->untagged != NULL && li->busy) { 2113 1.4.2.4 nathanw sc->sc_actsrb = li->untagged; 2114 1.4.2.4 nathanw sc->sc_state = TRM_DATA_XFER; 2115 1.4.2.4 nathanw } else { 2116 1.4.2.4 nathanw sc->resel_target = target; 2117 1.4.2.4 nathanw sc->resel_lun = lun; 2118 1.4.2.4 nathanw /* XXX XXX XXX */ 2119 1.4.2.4 nathanw sc->sc_flag |= WAIT_TAGMSG; 2120 1.4.2.4 nathanw } 2121 1.4.2.4 nathanw } 2122 1.4.2.4 nathanw 2123 1.4.2.4 nathanw if ((ti->flag & USE_TAG_QUEUING) == 0 && 2124 1.4.2.4 nathanw sc->sc_actsrb == NULL) { 2125 1.4.2.4 nathanw printf("%s: reselect from target %d lun %d " 2126 1.4.2.4 nathanw "without nexus; sending abort\n", 2127 1.4.2.4 nathanw sc->sc_dev.dv_xname, target, lun); 2128 1.4.2.4 nathanw sc->sc_state = TRM_UNEXPECT_RESEL; 2129 1.4.2.4 nathanw sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2130 1.4.2.4 nathanw sc->sc_msgcnt = 1; 2131 1.4.2.4 nathanw bus_space_write_2(iot, ioh, 2132 1.4.2.4 nathanw TRM_SCSI_CONTROL, DO_SETATN); 2133 1.4.2.2 nathanw } 2134 1.4.2.2 nathanw } 2135 1.4.2.4 nathanw sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2136 1.4.2.2 nathanw /* 2137 1.4.2.2 nathanw * Program HA ID, target ID, period and offset 2138 1.4.2.2 nathanw */ 2139 1.4.2.2 nathanw /* target ID */ 2140 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2141 1.4.2.2 nathanw 2142 1.4.2.2 nathanw /* host ID */ 2143 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2144 1.4.2.2 nathanw 2145 1.4.2.2 nathanw /* period */ 2146 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2147 1.4.2.2 nathanw 2148 1.4.2.2 nathanw /* offset */ 2149 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2150 1.4.2.2 nathanw 2151 1.4.2.2 nathanw /* it's important for atn stop */ 2152 1.4.2.2 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2153 1.4.2.2 nathanw /* 2154 1.4.2.4 nathanw * SCSI command 2155 1.4.2.2 nathanw */ 2156 1.4.2.2 nathanw /* to rls the /ACK signal */ 2157 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2158 1.4.2.2 nathanw } 2159 1.4.2.2 nathanw 2160 1.4.2.2 nathanw /* 2161 1.4.2.2 nathanw * Complete execution of a SCSI command 2162 1.4.2.2 nathanw * Signal completion to the generic SCSI driver 2163 1.4.2.2 nathanw */ 2164 1.4.2.2 nathanw static void 2165 1.4.2.4 nathanw trm_done(sc, srb) 2166 1.4.2.2 nathanw struct trm_softc *sc; 2167 1.4.2.2 nathanw struct trm_srb *srb; 2168 1.4.2.2 nathanw { 2169 1.4.2.2 nathanw struct scsipi_xfer *xs = srb->xs; 2170 1.4.2.2 nathanw 2171 1.4.2.4 nathanw DPRINTF(("trm_done..................\n")); 2172 1.4.2.2 nathanw 2173 1.4.2.2 nathanw if (xs == NULL) 2174 1.4.2.2 nathanw return; 2175 1.4.2.2 nathanw 2176 1.4.2.3 nathanw if ((xs->xs_control & XS_CTL_POLL) == 0) 2177 1.4.2.3 nathanw callout_stop(&xs->xs_callout); 2178 1.4.2.2 nathanw 2179 1.4.2.3 nathanw if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2180 1.4.2.3 nathanw srb->flag & AUTO_REQSENSE) { 2181 1.4.2.3 nathanw bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2182 1.4.2.3 nathanw srb->dmap->dm_mapsize, 2183 1.4.2.3 nathanw ((xs->xs_control & XS_CTL_DATA_IN) || 2184 1.4.2.3 nathanw (srb->flag & AUTO_REQSENSE)) ? 2185 1.4.2.3 nathanw BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2186 1.4.2.3 nathanw bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2187 1.4.2.2 nathanw } 2188 1.4.2.3 nathanw 2189 1.4.2.2 nathanw /* 2190 1.4.2.2 nathanw * target status 2191 1.4.2.2 nathanw */ 2192 1.4.2.3 nathanw xs->status = srb->tastat; 2193 1.4.2.3 nathanw 2194 1.4.2.4 nathanw DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2195 1.4.2.4 nathanw 2196 1.4.2.3 nathanw switch (xs->status) { 2197 1.4.2.3 nathanw case SCSI_OK: 2198 1.4.2.2 nathanw /* 2199 1.4.2.2 nathanw * process initiator status...... 2200 1.4.2.2 nathanw * Adapter (initiator) status 2201 1.4.2.2 nathanw */ 2202 1.4.2.4 nathanw if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2203 1.4.2.4 nathanw printf("%s: over/under run error\n", 2204 1.4.2.4 nathanw sc->sc_dev.dv_xname); 2205 1.4.2.2 nathanw srb->tastat = 0; 2206 1.4.2.2 nathanw /* Illegal length (over/under run) */ 2207 1.4.2.2 nathanw xs->error = XS_DRIVER_STUFFUP; 2208 1.4.2.4 nathanw } else if ((srb->flag & PARITY_ERROR) != 0) { 2209 1.4.2.4 nathanw printf("%s: parity error\n", 2210 1.4.2.4 nathanw sc->sc_dev.dv_xname); 2211 1.4.2.2 nathanw /* Driver failed to perform operation */ 2212 1.4.2.4 nathanw xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2213 1.4.2.4 nathanw } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2214 1.4.2.4 nathanw xs->resid = srb->buflen; 2215 1.4.2.4 nathanw xs->error = XS_TIMEOUT; 2216 1.4.2.3 nathanw } else { 2217 1.4.2.3 nathanw /* No error */ 2218 1.4.2.4 nathanw xs->resid = srb->buflen; 2219 1.4.2.2 nathanw srb->hastat = 0; 2220 1.4.2.3 nathanw if (srb->flag & AUTO_REQSENSE) { 2221 1.4.2.3 nathanw /* there is no error, (sense is invalid) */ 2222 1.4.2.3 nathanw xs->error = XS_SENSE; 2223 1.4.2.3 nathanw } else { 2224 1.4.2.3 nathanw srb->tastat = 0; 2225 1.4.2.3 nathanw xs->error = XS_NOERROR; 2226 1.4.2.3 nathanw } 2227 1.4.2.3 nathanw } 2228 1.4.2.3 nathanw break; 2229 1.4.2.4 nathanw 2230 1.4.2.3 nathanw case SCSI_CHECK: 2231 1.4.2.3 nathanw if ((srb->flag & AUTO_REQSENSE) != 0 || 2232 1.4.2.4 nathanw trm_request_sense(sc, srb) != 0) { 2233 1.4.2.3 nathanw printf("%s: request sense failed\n", 2234 1.4.2.3 nathanw sc->sc_dev.dv_xname); 2235 1.4.2.3 nathanw xs->error = XS_DRIVER_STUFFUP; 2236 1.4.2.3 nathanw break; 2237 1.4.2.2 nathanw } 2238 1.4.2.3 nathanw xs->error = XS_SENSE; 2239 1.4.2.3 nathanw return; 2240 1.4.2.4 nathanw 2241 1.4.2.3 nathanw case SCSI_SEL_TIMEOUT: 2242 1.4.2.3 nathanw srb->hastat = H_SEL_TIMEOUT; 2243 1.4.2.3 nathanw srb->tastat = 0; 2244 1.4.2.4 nathanw xs->error = XS_SELTIMEOUT; 2245 1.4.2.3 nathanw break; 2246 1.4.2.4 nathanw 2247 1.4.2.4 nathanw case SCSI_QUEUE_FULL: 2248 1.4.2.3 nathanw case SCSI_BUSY: 2249 1.4.2.3 nathanw xs->error = XS_BUSY; 2250 1.4.2.3 nathanw break; 2251 1.4.2.4 nathanw 2252 1.4.2.3 nathanw case SCSI_RESV_CONFLICT: 2253 1.4.2.4 nathanw DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2254 1.4.2.4 nathanw DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2255 1.4.2.3 nathanw xs->error = XS_BUSY; 2256 1.4.2.3 nathanw break; 2257 1.4.2.4 nathanw 2258 1.4.2.3 nathanw default: 2259 1.4.2.3 nathanw srb->hastat = 0; 2260 1.4.2.4 nathanw printf("%s: trm_done(): unknown status = %02x\n", 2261 1.4.2.4 nathanw sc->sc_dev.dv_xname, xs->status); 2262 1.4.2.3 nathanw xs->error = XS_DRIVER_STUFFUP; 2263 1.4.2.3 nathanw break; 2264 1.4.2.2 nathanw } 2265 1.4.2.3 nathanw 2266 1.4.2.4 nathanw trm_dequeue(sc, srb); 2267 1.4.2.4 nathanw if (srb == sc->sc_actsrb) { 2268 1.4.2.4 nathanw sc->sc_actsrb = NULL; 2269 1.4.2.4 nathanw trm_sched(sc); 2270 1.4.2.4 nathanw } 2271 1.4.2.2 nathanw 2272 1.4.2.4 nathanw TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2273 1.4.2.2 nathanw 2274 1.4.2.2 nathanw /* Notify cmd done */ 2275 1.4.2.2 nathanw scsipi_done(xs); 2276 1.4.2.2 nathanw } 2277 1.4.2.2 nathanw 2278 1.4.2.4 nathanw static int 2279 1.4.2.4 nathanw trm_request_sense(sc, srb) 2280 1.4.2.2 nathanw struct trm_softc *sc; 2281 1.4.2.2 nathanw struct trm_srb *srb; 2282 1.4.2.2 nathanw { 2283 1.4.2.2 nathanw struct scsipi_xfer *xs; 2284 1.4.2.4 nathanw struct scsipi_periph *periph; 2285 1.4.2.4 nathanw struct trm_tinfo *ti; 2286 1.4.2.4 nathanw struct trm_linfo *li; 2287 1.4.2.4 nathanw struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2288 1.4.2.4 nathanw int error; 2289 1.4.2.2 nathanw 2290 1.4.2.4 nathanw DPRINTF(("trm_request_sense...\n")); 2291 1.4.2.2 nathanw 2292 1.4.2.4 nathanw xs = srb->xs; 2293 1.4.2.4 nathanw periph = xs->xs_periph; 2294 1.4.2.2 nathanw 2295 1.4.2.2 nathanw srb->flag |= AUTO_REQSENSE; 2296 1.4.2.2 nathanw 2297 1.4.2.2 nathanw /* Status of initiator/target */ 2298 1.4.2.2 nathanw srb->hastat = 0; 2299 1.4.2.2 nathanw srb->tastat = 0; 2300 1.4.2.2 nathanw 2301 1.4.2.2 nathanw ss->opcode = REQUEST_SENSE; 2302 1.4.2.4 nathanw ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2303 1.4.2.2 nathanw ss->unused[0] = ss->unused[1] = 0; 2304 1.4.2.2 nathanw ss->length = sizeof(struct scsipi_sense_data); 2305 1.4.2.2 nathanw ss->control = 0; 2306 1.4.2.2 nathanw 2307 1.4.2.2 nathanw srb->buflen = sizeof(struct scsipi_sense_data); 2308 1.4.2.2 nathanw srb->sgcnt = 1; 2309 1.4.2.2 nathanw srb->sgindex = 0; 2310 1.4.2.2 nathanw srb->cmdlen = sizeof(struct scsipi_sense); 2311 1.4.2.2 nathanw 2312 1.4.2.2 nathanw if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2313 1.4.2.2 nathanw &xs->sense.scsi_sense, srb->buflen, NULL, 2314 1.4.2.2 nathanw BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2315 1.4.2.3 nathanw return error; 2316 1.4.2.2 nathanw } 2317 1.4.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2318 1.4.2.2 nathanw srb->buflen, BUS_DMASYNC_PREREAD); 2319 1.4.2.2 nathanw 2320 1.4.2.2 nathanw srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2321 1.4.2.2 nathanw srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2322 1.4.2.2 nathanw bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2323 1.4.2.2 nathanw TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2324 1.4.2.2 nathanw 2325 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 2326 1.4.2.4 nathanw li = ti->linfo[periph->periph_lun]; 2327 1.4.2.4 nathanw if (li->busy > 0) 2328 1.4.2.4 nathanw li->busy = 0; 2329 1.4.2.4 nathanw trm_dequeue(sc, srb); 2330 1.4.2.4 nathanw li->untagged = srb; /* must be executed first to fix C/A */ 2331 1.4.2.4 nathanw li->busy = 2; 2332 1.4.2.4 nathanw 2333 1.4.2.4 nathanw if (srb == sc->sc_actsrb) 2334 1.4.2.4 nathanw trm_select(sc, srb); 2335 1.4.2.4 nathanw else { 2336 1.4.2.4 nathanw TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2337 1.4.2.4 nathanw if (sc->sc_actsrb == NULL) 2338 1.4.2.4 nathanw trm_sched(sc); 2339 1.4.2.4 nathanw } 2340 1.4.2.3 nathanw return 0; 2341 1.4.2.2 nathanw } 2342 1.4.2.2 nathanw 2343 1.4.2.2 nathanw static void 2344 1.4.2.4 nathanw trm_dequeue(sc, srb) 2345 1.4.2.2 nathanw struct trm_softc *sc; 2346 1.4.2.2 nathanw struct trm_srb *srb; 2347 1.4.2.2 nathanw { 2348 1.4.2.4 nathanw struct scsipi_periph *periph; 2349 1.4.2.4 nathanw struct trm_tinfo *ti; 2350 1.4.2.4 nathanw struct trm_linfo *li; 2351 1.4.2.4 nathanw 2352 1.4.2.4 nathanw periph = srb->xs->xs_periph; 2353 1.4.2.4 nathanw ti = &sc->sc_tinfo[periph->periph_target]; 2354 1.4.2.4 nathanw li = ti->linfo[periph->periph_lun]; 2355 1.4.2.2 nathanw 2356 1.4.2.4 nathanw if (li->untagged == srb) { 2357 1.4.2.4 nathanw li->busy = 0; 2358 1.4.2.4 nathanw li->untagged = NULL; 2359 1.4.2.4 nathanw } 2360 1.4.2.4 nathanw if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2361 1.4.2.4 nathanw li->queued[srb->tag[1]] = NULL; 2362 1.4.2.4 nathanw li->used--; 2363 1.4.2.4 nathanw } 2364 1.4.2.2 nathanw } 2365 1.4.2.2 nathanw 2366 1.4.2.2 nathanw static void 2367 1.4.2.4 nathanw trm_reset_scsi_bus(sc) 2368 1.4.2.2 nathanw struct trm_softc *sc; 2369 1.4.2.2 nathanw { 2370 1.4.2.4 nathanw bus_space_tag_t iot = sc->sc_iot; 2371 1.4.2.4 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2372 1.4.2.4 nathanw int timeout, s; 2373 1.4.2.2 nathanw 2374 1.4.2.4 nathanw DPRINTF(("trm_reset_scsi_bus.........\n")); 2375 1.4.2.2 nathanw 2376 1.4.2.2 nathanw s = splbio(); 2377 1.4.2.4 nathanw 2378 1.4.2.4 nathanw sc->sc_flag |= RESET_DEV; 2379 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2380 1.4.2.4 nathanw for (timeout = 20000; timeout >= 0; timeout--) { 2381 1.4.2.4 nathanw DELAY(1); 2382 1.4.2.4 nathanw if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2383 1.4.2.4 nathanw INT_SCSIRESET) == 0) 2384 1.4.2.4 nathanw break; 2385 1.4.2.2 nathanw } 2386 1.4.2.4 nathanw if (timeout == 0) 2387 1.4.2.4 nathanw printf(": scsibus reset timeout\n"); 2388 1.4.2.4 nathanw 2389 1.4.2.2 nathanw splx(s); 2390 1.4.2.2 nathanw } 2391 1.4.2.2 nathanw 2392 1.4.2.2 nathanw static void 2393 1.4.2.4 nathanw trm_scsi_reset_detect(sc) 2394 1.4.2.2 nathanw struct trm_softc *sc; 2395 1.4.2.2 nathanw { 2396 1.4.2.4 nathanw bus_space_tag_t iot = sc->sc_iot; 2397 1.4.2.4 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2398 1.4.2.4 nathanw int s; 2399 1.4.2.2 nathanw 2400 1.4.2.4 nathanw DPRINTF(("trm_scsi_reset_detect...............\n")); 2401 1.4.2.4 nathanw DELAY(1000000); /* delay 1 sec */ 2402 1.4.2.2 nathanw 2403 1.4.2.4 nathanw s = splbio(); 2404 1.4.2.4 nathanw 2405 1.4.2.4 nathanw bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2406 1.4.2.4 nathanw bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2407 1.4.2.4 nathanw 2408 1.4.2.4 nathanw if (sc->sc_flag & RESET_DEV) { 2409 1.4.2.4 nathanw sc->sc_flag |= RESET_DONE; 2410 1.4.2.4 nathanw } else { 2411 1.4.2.4 nathanw sc->sc_flag |= RESET_DETECT; 2412 1.4.2.4 nathanw sc->sc_actsrb = NULL; 2413 1.4.2.4 nathanw sc->sc_flag = 0; 2414 1.4.2.4 nathanw trm_sched(sc); 2415 1.4.2.2 nathanw } 2416 1.4.2.4 nathanw splx(s); 2417 1.4.2.2 nathanw } 2418 1.4.2.2 nathanw 2419 1.4.2.2 nathanw /* 2420 1.4.2.4 nathanw * read seeprom 128 bytes to struct eeprom and check checksum. 2421 1.4.2.4 nathanw * If it is wrong, update with default value. 2422 1.4.2.2 nathanw */ 2423 1.4.2.2 nathanw static void 2424 1.4.2.4 nathanw trm_check_eeprom(sc, eeprom) 2425 1.4.2.2 nathanw struct trm_softc *sc; 2426 1.4.2.2 nathanw struct trm_nvram *eeprom; 2427 1.4.2.4 nathanw { 2428 1.4.2.4 nathanw struct nvram_target *target; 2429 1.4.2.4 nathanw u_int16_t *ep; 2430 1.4.2.4 nathanw u_int16_t chksum; 2431 1.4.2.4 nathanw int i; 2432 1.4.2.2 nathanw 2433 1.4.2.4 nathanw DPRINTF(("trm_check_eeprom......\n")); 2434 1.4.2.4 nathanw trm_eeprom_read_all(sc, eeprom); 2435 1.4.2.4 nathanw ep = (u_int16_t *)eeprom; 2436 1.4.2.4 nathanw chksum = 0; 2437 1.4.2.4 nathanw for (i = 0; i < 64; i++) 2438 1.4.2.4 nathanw chksum += le16toh(*ep++); 2439 1.4.2.2 nathanw 2440 1.4.2.4 nathanw if (chksum != TRM_NVRAM_CKSUM) { 2441 1.4.2.4 nathanw DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2442 1.4.2.4 nathanw /* 2443 1.4.2.4 nathanw * Checksum error, load default 2444 1.4.2.4 nathanw */ 2445 1.4.2.4 nathanw eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2446 1.4.2.4 nathanw eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2447 1.4.2.4 nathanw eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2448 1.4.2.4 nathanw eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2449 1.4.2.4 nathanw eeprom->subclass = 0x00; 2450 1.4.2.4 nathanw eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2451 1.4.2.4 nathanw eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2452 1.4.2.4 nathanw eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2453 1.4.2.4 nathanw eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2454 1.4.2.4 nathanw eeprom->reserved0 = 0x00; 2455 1.4.2.2 nathanw 2456 1.4.2.4 nathanw for (i = 0, target = eeprom->target; 2457 1.4.2.4 nathanw i < TRM_MAX_TARGETS; 2458 1.4.2.4 nathanw i++, target++) { 2459 1.4.2.4 nathanw target->config0 = 0x77; 2460 1.4.2.4 nathanw target->period = 0x00; 2461 1.4.2.4 nathanw target->config2 = 0x00; 2462 1.4.2.4 nathanw target->config3 = 0x00; 2463 1.4.2.4 nathanw } 2464 1.4.2.2 nathanw 2465 1.4.2.4 nathanw eeprom->scsi_id = 7; 2466 1.4.2.4 nathanw eeprom->channel_cfg = 0x0F; 2467 1.4.2.4 nathanw eeprom->delay_time = 0; 2468 1.4.2.4 nathanw eeprom->max_tag = 4; 2469 1.4.2.4 nathanw eeprom->reserved1 = 0x15; 2470 1.4.2.4 nathanw eeprom->boot_target = 0; 2471 1.4.2.4 nathanw eeprom->boot_lun = 0; 2472 1.4.2.4 nathanw eeprom->reserved2 = 0; 2473 1.4.2.4 nathanw memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2474 1.4.2.4 nathanw 2475 1.4.2.4 nathanw chksum = 0; 2476 1.4.2.4 nathanw ep = (u_int16_t *)eeprom; 2477 1.4.2.4 nathanw for (i = 0; i < 63; i++) 2478 1.4.2.4 nathanw chksum += le16toh(*ep++); 2479 1.4.2.4 nathanw 2480 1.4.2.4 nathanw chksum = TRM_NVRAM_CKSUM - chksum; 2481 1.4.2.4 nathanw eeprom->checksum0 = chksum & 0xFF; 2482 1.4.2.4 nathanw eeprom->checksum1 = chksum >> 8; 2483 1.4.2.4 nathanw 2484 1.4.2.4 nathanw trm_eeprom_write_all(sc, eeprom); 2485 1.4.2.4 nathanw } 2486 1.4.2.2 nathanw } 2487 1.4.2.2 nathanw 2488 1.4.2.2 nathanw /* 2489 1.4.2.4 nathanw * write struct eeprom 128 bytes to seeprom 2490 1.4.2.2 nathanw */ 2491 1.4.2.2 nathanw static void 2492 1.4.2.2 nathanw trm_eeprom_write_all(sc, eeprom) 2493 1.4.2.2 nathanw struct trm_softc *sc; 2494 1.4.2.2 nathanw struct trm_nvram *eeprom; 2495 1.4.2.2 nathanw { 2496 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2497 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2498 1.4.2.2 nathanw u_int8_t *buf = (u_int8_t *)eeprom; 2499 1.4.2.2 nathanw u_int8_t addr; 2500 1.4.2.2 nathanw 2501 1.4.2.2 nathanw /* Enable SEEPROM */ 2502 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2503 1.4.2.2 nathanw bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2504 1.4.2.2 nathanw 2505 1.4.2.2 nathanw /* 2506 1.4.2.2 nathanw * Write enable 2507 1.4.2.2 nathanw */ 2508 1.4.2.2 nathanw trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2509 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2510 1.4.2.4 nathanw trm_eeprom_wait(); 2511 1.4.2.2 nathanw 2512 1.4.2.2 nathanw for (addr = 0; addr < 128; addr++, buf++) 2513 1.4.2.2 nathanw trm_eeprom_set_data(sc, addr, *buf); 2514 1.4.2.2 nathanw 2515 1.4.2.2 nathanw /* 2516 1.4.2.2 nathanw * Write disable 2517 1.4.2.2 nathanw */ 2518 1.4.2.2 nathanw trm_eeprom_write_cmd(sc, 0x04, 0x00); 2519 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2520 1.4.2.4 nathanw trm_eeprom_wait(); 2521 1.4.2.2 nathanw 2522 1.4.2.2 nathanw /* Disable SEEPROM */ 2523 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2524 1.4.2.2 nathanw bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2525 1.4.2.2 nathanw } 2526 1.4.2.2 nathanw 2527 1.4.2.2 nathanw /* 2528 1.4.2.2 nathanw * write one byte to seeprom 2529 1.4.2.2 nathanw */ 2530 1.4.2.2 nathanw static void 2531 1.4.2.2 nathanw trm_eeprom_set_data(sc, addr, data) 2532 1.4.2.2 nathanw struct trm_softc *sc; 2533 1.4.2.2 nathanw u_int8_t addr; 2534 1.4.2.2 nathanw u_int8_t data; 2535 1.4.2.2 nathanw { 2536 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2537 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2538 1.4.2.2 nathanw int i; 2539 1.4.2.2 nathanw u_int8_t send; 2540 1.4.2.2 nathanw 2541 1.4.2.2 nathanw /* 2542 1.4.2.2 nathanw * Send write command & address 2543 1.4.2.2 nathanw */ 2544 1.4.2.2 nathanw trm_eeprom_write_cmd(sc, 0x05, addr); 2545 1.4.2.2 nathanw /* 2546 1.4.2.2 nathanw * Write data 2547 1.4.2.2 nathanw */ 2548 1.4.2.2 nathanw for (i = 0; i < 8; i++, data <<= 1) { 2549 1.4.2.2 nathanw send = NVR_SELECT; 2550 1.4.2.2 nathanw if (data & 0x80) /* Start from bit 7 */ 2551 1.4.2.2 nathanw send |= NVR_BITOUT; 2552 1.4.2.2 nathanw 2553 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2554 1.4.2.4 nathanw trm_eeprom_wait(); 2555 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2556 1.4.2.4 nathanw trm_eeprom_wait(); 2557 1.4.2.2 nathanw } 2558 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2559 1.4.2.4 nathanw trm_eeprom_wait(); 2560 1.4.2.2 nathanw /* 2561 1.4.2.2 nathanw * Disable chip select 2562 1.4.2.2 nathanw */ 2563 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2564 1.4.2.4 nathanw trm_eeprom_wait(); 2565 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2566 1.4.2.4 nathanw trm_eeprom_wait(); 2567 1.4.2.2 nathanw /* 2568 1.4.2.2 nathanw * Wait for write ready 2569 1.4.2.2 nathanw */ 2570 1.4.2.2 nathanw for (;;) { 2571 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2572 1.4.2.2 nathanw NVR_SELECT | NVR_CLOCK); 2573 1.4.2.4 nathanw trm_eeprom_wait(); 2574 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2575 1.4.2.4 nathanw trm_eeprom_wait(); 2576 1.4.2.2 nathanw if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2577 1.4.2.2 nathanw break; 2578 1.4.2.2 nathanw } 2579 1.4.2.2 nathanw /* 2580 1.4.2.2 nathanw * Disable chip select 2581 1.4.2.2 nathanw */ 2582 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2583 1.4.2.2 nathanw } 2584 1.4.2.2 nathanw 2585 1.4.2.2 nathanw /* 2586 1.4.2.4 nathanw * read seeprom 128 bytes to struct eeprom 2587 1.4.2.2 nathanw */ 2588 1.4.2.2 nathanw static void 2589 1.4.2.2 nathanw trm_eeprom_read_all(sc, eeprom) 2590 1.4.2.2 nathanw struct trm_softc *sc; 2591 1.4.2.2 nathanw struct trm_nvram *eeprom; 2592 1.4.2.2 nathanw { 2593 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2594 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2595 1.4.2.2 nathanw u_int8_t *buf = (u_int8_t *)eeprom; 2596 1.4.2.2 nathanw u_int8_t addr; 2597 1.4.2.2 nathanw 2598 1.4.2.2 nathanw /* 2599 1.4.2.2 nathanw * Enable SEEPROM 2600 1.4.2.2 nathanw */ 2601 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2602 1.4.2.2 nathanw bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2603 1.4.2.2 nathanw 2604 1.4.2.4 nathanw for (addr = 0; addr < 128; addr++) 2605 1.4.2.4 nathanw *buf++ = trm_eeprom_get_data(sc, addr); 2606 1.4.2.2 nathanw 2607 1.4.2.2 nathanw /* 2608 1.4.2.2 nathanw * Disable SEEPROM 2609 1.4.2.2 nathanw */ 2610 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2611 1.4.2.2 nathanw bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2612 1.4.2.2 nathanw } 2613 1.4.2.2 nathanw 2614 1.4.2.2 nathanw /* 2615 1.4.2.2 nathanw * read one byte from seeprom 2616 1.4.2.2 nathanw */ 2617 1.4.2.2 nathanw static u_int8_t 2618 1.4.2.2 nathanw trm_eeprom_get_data(sc, addr) 2619 1.4.2.2 nathanw struct trm_softc *sc; 2620 1.4.2.2 nathanw u_int8_t addr; 2621 1.4.2.2 nathanw { 2622 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2623 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2624 1.4.2.2 nathanw int i; 2625 1.4.2.2 nathanw u_int8_t read, data = 0; 2626 1.4.2.2 nathanw 2627 1.4.2.2 nathanw /* 2628 1.4.2.2 nathanw * Send read command & address 2629 1.4.2.2 nathanw */ 2630 1.4.2.2 nathanw trm_eeprom_write_cmd(sc, 0x06, addr); 2631 1.4.2.2 nathanw 2632 1.4.2.2 nathanw for (i = 0; i < 8; i++) { /* Read data */ 2633 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2634 1.4.2.2 nathanw NVR_SELECT | NVR_CLOCK); 2635 1.4.2.4 nathanw trm_eeprom_wait(); 2636 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2637 1.4.2.2 nathanw /* 2638 1.4.2.2 nathanw * Get data bit while falling edge 2639 1.4.2.2 nathanw */ 2640 1.4.2.2 nathanw read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2641 1.4.2.2 nathanw data <<= 1; 2642 1.4.2.2 nathanw if (read & NVR_BITIN) 2643 1.4.2.2 nathanw data |= 1; 2644 1.4.2.2 nathanw 2645 1.4.2.4 nathanw trm_eeprom_wait(); 2646 1.4.2.2 nathanw } 2647 1.4.2.2 nathanw /* 2648 1.4.2.2 nathanw * Disable chip select 2649 1.4.2.2 nathanw */ 2650 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2651 1.4.2.2 nathanw return (data); 2652 1.4.2.2 nathanw } 2653 1.4.2.2 nathanw 2654 1.4.2.2 nathanw /* 2655 1.4.2.2 nathanw * write SB and Op Code into seeprom 2656 1.4.2.2 nathanw */ 2657 1.4.2.2 nathanw static void 2658 1.4.2.2 nathanw trm_eeprom_write_cmd(sc, cmd, addr) 2659 1.4.2.2 nathanw struct trm_softc *sc; 2660 1.4.2.2 nathanw u_int8_t cmd; 2661 1.4.2.2 nathanw u_int8_t addr; 2662 1.4.2.2 nathanw { 2663 1.4.2.2 nathanw bus_space_tag_t iot = sc->sc_iot; 2664 1.4.2.2 nathanw bus_space_handle_t ioh = sc->sc_ioh; 2665 1.4.2.2 nathanw int i; 2666 1.4.2.2 nathanw u_int8_t send; 2667 1.4.2.2 nathanw 2668 1.4.2.2 nathanw /* Program SB+OP code */ 2669 1.4.2.2 nathanw for (i = 0; i < 3; i++, cmd <<= 1) { 2670 1.4.2.2 nathanw send = NVR_SELECT; 2671 1.4.2.2 nathanw if (cmd & 0x04) /* Start from bit 2 */ 2672 1.4.2.2 nathanw send |= NVR_BITOUT; 2673 1.4.2.2 nathanw 2674 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2675 1.4.2.4 nathanw trm_eeprom_wait(); 2676 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2677 1.4.2.4 nathanw trm_eeprom_wait(); 2678 1.4.2.2 nathanw } 2679 1.4.2.2 nathanw 2680 1.4.2.2 nathanw /* Program address */ 2681 1.4.2.2 nathanw for (i = 0; i < 7; i++, addr <<= 1) { 2682 1.4.2.2 nathanw send = NVR_SELECT; 2683 1.4.2.2 nathanw if (addr & 0x40) /* Start from bit 6 */ 2684 1.4.2.2 nathanw send |= NVR_BITOUT; 2685 1.4.2.2 nathanw 2686 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2687 1.4.2.4 nathanw trm_eeprom_wait(); 2688 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2689 1.4.2.4 nathanw trm_eeprom_wait(); 2690 1.4.2.2 nathanw } 2691 1.4.2.2 nathanw bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2692 1.4.2.4 nathanw trm_eeprom_wait(); 2693 1.4.2.2 nathanw } 2694
Indexes created Tue Oct 14 15:09:51 GMT 2025