trm.c revision 1.1
1 /* $NetBSD: trm.c,v 1.1 2001/11/03 17:01:17 tsutsui Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2001 Rui-Xiang Guo 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from 34 * dc395x_trm.c 35 * 36 * Written for NetBSD 1.4.x by 37 * Erich Chen (erich (at) tekram.com.tw) 38 * 39 * Provided by 40 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 41 */ 42 43 #undef TRM_DEBUG 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/buf.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsi_message.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/pci/pcidevs.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/trmreg.h> 66 67 /* 68 * feature of chip set MAX value 69 */ 70 #define TRM_MAX_TARGETS 16 71 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 72 #define TRM_MAX_SRB 32 73 74 /* 75 * Segment Entry 76 */ 77 struct trm_sg_entry { 78 u_int32_t address; 79 u_int32_t length; 80 }; 81 82 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 83 84 /* 85 ********************************************************************** 86 * The SEEPROM structure for TRM_S1040 87 ********************************************************************** 88 */ 89 struct nvram_target { 90 u_int8_t config0; /* Target configuration byte 0 */ 91 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 92 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 93 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 94 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 95 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 96 #define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC) Parity check enable */ 97 u_int8_t period; /* Target period */ 98 u_int8_t config2; /* Target configuration byte 2 */ 99 u_int8_t config3; /* Target configuration byte 3 */ 100 }; 101 102 struct trm_nvram { 103 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 104 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 105 u_int8_t subclass; /* 4 Sub Class */ 106 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 107 u_int8_t device_id[2]; /* 7,8 Device ID */ 108 u_int8_t reserved0; /* 9 Reserved */ 109 struct nvram_target target[TRM_MAX_TARGETS]; 110 /* 10,11,12,13 111 * 14,15,16,17 112 * .... 113 * 70,71,72,73 */ 114 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 115 u_int8_t channel_cfg; /* 75 Channel configuration */ 116 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 117 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 118 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 119 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 120 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 121 u_int8_t delay_time; /* 76 Power on delay time */ 122 u_int8_t max_tag; /* 77 Maximum tags */ 123 u_int8_t reserved1; /* 78 */ 124 u_int8_t boot_target; /* 79 */ 125 u_int8_t boot_lun; /* 80 */ 126 u_int8_t reserved2; /* 81 */ 127 u_int8_t reserved3[44]; /* 82,..125 */ 128 u_int8_t checksum0; /* 126 */ 129 u_int8_t checksum1; /* 127 */ 130 #define TRM_NVRAM_CKSUM 0x1234 131 }; 132 133 /* Nvram Initiater bits definition */ 134 #define MORE2_DRV 0x00000001 135 #define GREATER_1G 0x00000002 136 #define RST_SCSI_BUS 0x00000004 137 #define ACTIVE_NEGATION 0x00000008 138 #define NO_SEEK 0x00000010 139 #define LUN_CHECK 0x00000020 140 141 #define trm_wait_30us() DELAY(30) 142 143 /* 144 *----------------------------------------------------------------------- 145 * SCSI Request Block 146 *----------------------------------------------------------------------- 147 */ 148 struct trm_srb { 149 struct trm_srb *next; 150 struct trm_dcb *dcb; 151 152 struct trm_sg_entry *sgentry; 153 struct trm_sg_entry tempsg; /* Temp sgentry when Request Sense */ 154 /* 155 * the scsipi_xfer for this cmd 156 */ 157 struct scsipi_xfer *xs; 158 bus_dmamap_t dmap; 159 bus_size_t sgoffset; /* Xfer buf offset */ 160 161 u_int32_t buflen; /* Total xfer length */ 162 u_int32_t templen; /* Temp buflen when Request Sense */ 163 u_int32_t sgaddr; /* SGList physical starting address */ 164 165 u_int state; /* SRB State */ 166 #define SRB_FREE 0x0000 167 #define SRB_WAIT 0x0001 168 #define SRB_READY 0x0002 169 #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */ 170 #define SRB_MSGIN 0x0008 171 #define SRB_EXTEND_MSGIN 0x0010 172 #define SRB_COMMAND 0x0020 173 #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */ 174 #define SRB_DISCONNECT 0x0080 175 #define SRB_DATA_XFER 0x0100 176 #define SRB_XFERPAD 0x0200 177 #define SRB_STATUS 0x0400 178 #define SRB_COMPLETED 0x0800 179 #define SRB_ABORT_SENT 0x1000 180 #define SRB_DO_SYNC_NEGO 0x2000 181 #define SRB_DO_WIDE_NEGO 0x4000 182 #define SRB_UNEXPECT_RESEL 0x8000 183 u_int8_t *msg; 184 185 int sgcnt; 186 int sgindex; 187 188 int phase; /* SCSI phase */ 189 int hastat; /* Host Adapter Status */ 190 #define H_STATUS_GOOD 0x00 191 #define H_SEL_TIMEOUT 0x11 192 #define H_OVER_UNDER_RUN 0x12 193 #define H_UNEXP_BUS_FREE 0x13 194 #define H_TARGET_PHASE_F 0x14 195 #define H_INVALID_CCB_OP 0x16 196 #define H_LINK_CCB_BAD 0x17 197 #define H_BAD_TARGET_DIR 0x18 198 #define H_DUPLICATE_CCB 0x19 199 #define H_BAD_CCB_OR_SG 0x1A 200 #define H_ABORT 0xFF 201 int tastat; /* Target SCSI Status Byte */ 202 int flag; /* SRBFlag */ 203 #define DATAOUT 0x0080 204 #define DATAIN 0x0040 205 #define RESIDUAL_VALID 0x0020 206 #define ENABLE_TIMER 0x0010 207 #define RESET_DEV0 0x0004 208 #define ABORT_DEV 0x0002 209 #define AUTO_REQSENSE 0x0001 210 int srbstat; /* SRB Status */ 211 #define SRB_OK 0x01 212 #define ABORTION 0x02 213 #define OVER_RUN 0x04 214 #define UNDER_RUN 0x08 215 #define PARITY_ERROR 0x10 216 #define SRB_ERROR 0x20 217 int tagnum; /* Tag number */ 218 int retry; /* Retry Count */ 219 int msgcnt; 220 221 int cmdlen; /* SCSI command length */ 222 u_int8_t cmd[12]; /* SCSI command */ 223 u_int8_t tempcmd[6]; /* Temp cmd when Request Sense */ 224 225 u_int8_t msgin[6]; 226 u_int8_t msgout[6]; 227 }; 228 229 /* 230 *----------------------------------------------------------------------- 231 * Device Control Block 232 *----------------------------------------------------------------------- 233 */ 234 struct trm_dcb { 235 struct trm_dcb *next; 236 237 struct trm_srb *waitsrb; 238 struct trm_srb *last_waitsrb; 239 240 struct trm_srb *gosrb; 241 struct trm_srb *last_gosrb; 242 243 struct trm_srb *actsrb; 244 245 int gosrb_cnt; 246 u_int maxcmd; /* Max command */ 247 248 int id; /* SCSI Target ID (SCSI Only) */ 249 int lun; /* SCSI Log. Unit (SCSI Only) */ 250 251 u_int8_t tagmask; /* Tag mask */ 252 253 u_int8_t tacfg; /* Target Config */ 254 u_int8_t idmsg; /* Identify Msg */ 255 u_int8_t period; /* Max Period for nego. */ 256 257 u_int8_t synctl; /* Sync control for reg. */ 258 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 259 u_int8_t mode; /* Sync mode ? (1 sync):(0 async) */ 260 #define SYNC_NEGO_ENABLE 0x01 261 #define SYNC_NEGO_DONE 0x02 262 #define WIDE_NEGO_ENABLE 0x04 263 #define WIDE_NEGO_DONE 0x08 264 #define EN_TAG_QUEUING 0x10 265 #define EN_ATN_STOP 0x20 266 #define SYNC_NEGO_OFFSET 15 267 u_int8_t flag; 268 #define ABORT_DEV_ 0x01 269 #define SHOW_MESSAGE_ 0x02 270 u_int8_t type; /* Device Type */ 271 }; 272 273 /* 274 *----------------------------------------------------------------------- 275 * Adapter Control Block 276 *----------------------------------------------------------------------- 277 */ 278 struct trm_softc { 279 struct device sc_dev; 280 281 bus_space_tag_t sc_iot; 282 bus_space_handle_t sc_ioh; 283 bus_dma_tag_t sc_dmat; 284 bus_dmamap_t sc_dmamap; /* Map the control structures */ 285 286 struct trm_dcb *sc_linkdcb; 287 struct trm_dcb *sc_roundcb; 288 289 struct trm_dcb *sc_actdcb; 290 struct trm_dcb *sc_dcb[TRM_MAX_TARGETS][8]; 291 292 struct trm_srb *sc_freesrb; 293 struct trm_srb *sc_tempsrb; 294 struct trm_srb *sc_srb; /* SRB array */ 295 296 struct trm_sg_entry *sc_sglist; 297 298 int maxid; 299 int maxtag; /* Max Tag number */ 300 /* 301 * Link to the generic SCSI driver 302 */ 303 struct scsipi_channel sc_channel; 304 struct scsipi_adapter sc_adapter; 305 306 int sc_id; /* Adapter SCSI Target ID */ 307 308 int devcnt; /* Device Count */ 309 310 int devflag[TRM_MAX_TARGETS][8]; /* flag of initDCB for device */ 311 312 int devscan[TRM_MAX_TARGETS][8]; 313 int devscan_end; 314 int cur_offset; /* Current Sync offset */ 315 316 struct trm_nvram sc_eeprom; 317 int sc_config; 318 #define HCC_WIDE_CARD 0x20 319 #define HCC_SCSI_RESET 0x10 320 #define HCC_PARITY 0x08 321 #define HCC_AUTOTERM 0x04 322 #define HCC_LOW8TERM 0x02 323 #define HCC_UP8TERM 0x01 324 int sc_flag; 325 #define RESET_DEV 0x01 326 #define RESET_DETECT 0x02 327 #define RESET_DONE 0x04 328 }; 329 330 /* 331 * SCSI Status codes not defined in scsi_all.h 332 */ 333 #define SCSI_COND_MET 0x04 /* Condition Met */ 334 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 335 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpect Bus Free */ 336 #define SCSI_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */ 337 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Time out */ 338 339 static void trm_rewait_srb(struct trm_dcb *, struct trm_srb *); 340 static void trm_wait_srb(struct trm_softc *); 341 static void trm_reset_device(struct trm_softc *); 342 static void trm_recover_srb(struct trm_softc *); 343 static int trm_start_scsi(struct trm_softc *, struct trm_dcb *, 344 struct trm_srb *); 345 static int trm_intr(void *); 346 347 static void trm_dataout_phase0(struct trm_softc *, struct trm_srb *, int *); 348 static void trm_datain_phase0(struct trm_softc *, struct trm_srb *, int *); 349 static void trm_command_phase0(struct trm_softc *, struct trm_srb *, int *); 350 static void trm_status_phase0(struct trm_softc *, struct trm_srb *, int *); 351 static void trm_msgout_phase0(struct trm_softc *, struct trm_srb *, int *); 352 static void trm_msgin_phase0(struct trm_softc *, struct trm_srb *, int *); 353 static void trm_dataout_phase1(struct trm_softc *, struct trm_srb *, int *); 354 static void trm_datain_phase1(struct trm_softc *, struct trm_srb *, int *); 355 static void trm_command_phase1(struct trm_softc *, struct trm_srb *, int *); 356 static void trm_status_phase1(struct trm_softc *, struct trm_srb *, int *); 357 static void trm_msgout_phase1(struct trm_softc *, struct trm_srb *, int *); 358 static void trm_msgin_phase1(struct trm_softc *, struct trm_srb *, int *); 359 static void trm_nop0(struct trm_softc *, struct trm_srb *, int *); 360 static void trm_nop1(struct trm_softc *, struct trm_srb *, int *); 361 362 static void trm_set_xfer_rate(struct trm_softc *, struct trm_srb *, 363 struct trm_dcb *); 364 static void trm_dataio_xfer(struct trm_softc *, struct trm_srb *, int); 365 static void trm_disconnect(struct trm_softc *); 366 static void trm_reselect(struct trm_softc *); 367 static void trm_srb_done(struct trm_softc *, struct trm_dcb *, 368 struct trm_srb *); 369 static void trm_doing_srb_done(struct trm_softc *); 370 static void trm_scsi_reset_detect(struct trm_softc *); 371 static void trm_reset_scsi_bus(struct trm_softc *); 372 static void trm_request_sense(struct trm_softc *, struct trm_dcb *, 373 struct trm_srb *); 374 static void trm_msgout_abort(struct trm_softc *, struct trm_srb *); 375 static void trm_timeout(void *); 376 static void trm_reset(struct trm_softc *); 377 static void trm_send_srb(struct scsipi_xfer *, struct trm_softc *, 378 struct trm_srb *); 379 static int trm_init(struct trm_softc *); 380 static void trm_init_adapter(struct trm_softc *); 381 static void trm_init_dcb(struct trm_softc *, struct trm_dcb *, 382 struct scsipi_xfer *); 383 static void trm_link_srb(struct trm_softc *); 384 static void trm_init_sc(struct trm_softc *); 385 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 386 static void trm_release_srb(struct trm_softc *, struct trm_dcb *, 387 struct trm_srb *); 388 void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *); 389 390 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 391 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 392 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 393 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 394 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 395 396 static int trm_probe(struct device *, struct cfdata *, void *); 397 static void trm_attach(struct device *, struct device *, void *); 398 399 struct cfattach trm_ca = { 400 sizeof(struct trm_softc), trm_probe, trm_attach 401 }; 402 403 404 /* 405 * state_v = (void *) trm_scsi_phase0[phase] 406 */ 407 static void *trm_scsi_phase0[] = { 408 trm_dataout_phase0, /* phase:0 */ 409 trm_datain_phase0, /* phase:1 */ 410 trm_command_phase0, /* phase:2 */ 411 trm_status_phase0, /* phase:3 */ 412 trm_nop0, /* phase:4 */ 413 trm_nop1, /* phase:5 */ 414 trm_msgout_phase0, /* phase:6 */ 415 trm_msgin_phase0, /* phase:7 */ 416 }; 417 418 /* 419 * state_v = (void *) trm_scsi_phase1[phase] 420 */ 421 static void *trm_scsi_phase1[] = { 422 trm_dataout_phase1, /* phase:0 */ 423 trm_datain_phase1, /* phase:1 */ 424 trm_command_phase1, /* phase:2 */ 425 trm_status_phase1, /* phase:3 */ 426 trm_nop0, /* phase:4 */ 427 trm_nop1, /* phase:5 */ 428 trm_msgout_phase1, /* phase:6 */ 429 trm_msgin_phase1, /* phase:7 */ 430 }; 431 432 /* real period: */ 433 static const u_int8_t trm_clock_period[] = { 434 13, /* 52 ns 20.0 MB/sec */ 435 18, /* 72 ns 13.3 MB/sec */ 436 25, /* 100 ns 10.0 MB/sec */ 437 31, /* 124 ns 8.0 MB/sec */ 438 37, /* 148 ns 6.6 MB/sec */ 439 43, /* 172 ns 5.7 MB/sec */ 440 50, /* 200 ns 5.0 MB/sec */ 441 62 /* 248 ns 4.0 MB/sec */ 442 }; 443 444 /* 445 * Q back to pending Q 446 */ 447 static void 448 trm_rewait_srb(dcb, srb) 449 struct trm_dcb *dcb; 450 struct trm_srb *srb; 451 { 452 struct trm_srb *psrb1; 453 int s; 454 455 s = splbio(); 456 457 dcb->gosrb_cnt--; 458 psrb1 = dcb->gosrb; 459 if (srb == psrb1) 460 dcb->gosrb = psrb1->next; 461 else { 462 while (srb != psrb1->next) 463 psrb1 = psrb1->next; 464 465 psrb1->next = srb->next; 466 if (srb == dcb->last_gosrb) 467 dcb->last_gosrb = psrb1; 468 } 469 if (dcb->waitsrb) { 470 srb->next = dcb->waitsrb; 471 dcb->waitsrb = srb; 472 } else { 473 srb->next = NULL; 474 dcb->waitsrb = srb; 475 dcb->last_waitsrb = srb; 476 } 477 dcb->tagmask &= ~(1 << srb->tagnum); /* Free TAG number */ 478 479 splx(s); 480 } 481 482 static void 483 trm_wait_srb(sc) 484 struct trm_softc *sc; 485 { 486 struct trm_dcb *ptr, *ptr1; 487 struct trm_srb *srb; 488 int s; 489 490 s = splbio(); 491 492 if (sc->sc_actdcb == NULL && 493 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) == 0) { 494 ptr = sc->sc_roundcb; 495 if (ptr == NULL) { 496 ptr = sc->sc_linkdcb; 497 sc->sc_roundcb = ptr; 498 } 499 for (ptr1 = ptr; ptr1 != NULL;) { 500 sc->sc_roundcb = ptr1->next; 501 if (ptr1->maxcmd <= ptr1->gosrb_cnt || 502 (srb = ptr1->waitsrb) == NULL) { 503 if (sc->sc_roundcb == ptr) 504 break; 505 ptr1 = ptr1->next; 506 } else { 507 if (trm_start_scsi(sc, ptr1, srb) == 0) { 508 /* 509 * If trm_start_scsi return 0 : 510 * current interrupt status is 511 * interrupt enable. It's said that 512 * SCSI processor is unoccupied 513 */ 514 ptr1->gosrb_cnt++; 515 if (ptr1->last_waitsrb == srb) { 516 ptr1->waitsrb = NULL; 517 ptr1->last_waitsrb = NULL; 518 } else 519 ptr1->waitsrb = srb->next; 520 521 srb->next = NULL; 522 if (ptr1->gosrb != NULL) 523 ptr1->last_gosrb->next = srb; 524 else 525 ptr1->gosrb = srb; 526 527 ptr1->last_gosrb = srb; 528 } 529 break; 530 } 531 } 532 } 533 splx(s); 534 } 535 536 static void 537 trm_send_srb(xs, sc, srb) 538 struct scsipi_xfer *xs; 539 struct trm_softc *sc; 540 struct trm_srb *srb; 541 { 542 struct trm_dcb *dcb; 543 int s; 544 545 #ifdef TRM_DEBUG 546 printf("trm_send_srb..........\n"); 547 #endif 548 s = splbio(); 549 550 /* 551 * now get the DCB from upper layer( OS ) 552 */ 553 dcb = srb->dcb; 554 555 if (dcb->maxcmd <= dcb->gosrb_cnt || 556 sc->sc_actdcb != NULL || 557 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV))) { 558 if (dcb->waitsrb != NULL) { 559 dcb->last_waitsrb->next = srb; 560 dcb->last_waitsrb = srb; 561 srb->next = NULL; 562 } else { 563 dcb->waitsrb = srb; 564 dcb->last_waitsrb = srb; 565 } 566 splx(s); 567 return; 568 } 569 if (dcb->waitsrb != NULL) { 570 dcb->last_waitsrb->next = srb; 571 dcb->last_waitsrb = srb; 572 srb->next = NULL; 573 /* srb = GetWaitingSRB(dcb); */ 574 srb = dcb->waitsrb; 575 dcb->waitsrb = srb->next; 576 srb->next = NULL; 577 } 578 if (trm_start_scsi(sc, dcb, srb) == 0) { 579 /* 580 * If trm_start_scsi return 0: current interrupt status 581 * is interrupt enable. It's said that SCSI processor is 582 * unoccupied. 583 */ 584 dcb->gosrb_cnt++; /* stack waiting SRB */ 585 if (dcb->gosrb != NULL) { 586 dcb->last_gosrb->next = srb; 587 dcb->last_gosrb = srb; 588 } else { 589 dcb->gosrb = srb; 590 dcb->last_gosrb = srb; 591 } 592 } else { 593 /* 594 * If trm_start_scsi return 1: current interrupt status 595 * is interrupt disreenable. It's said that SCSI processor 596 * has more one SRB need to do we need reQ back SRB. 597 */ 598 if (dcb->waitsrb != NULL) { 599 srb->next = dcb->waitsrb; 600 dcb->waitsrb = srb; 601 } else { 602 srb->next = NULL; 603 dcb->waitsrb = srb; 604 dcb->last_waitsrb = srb; 605 } 606 } 607 608 splx(s); 609 } 610 611 /* 612 * Called by GENERIC SCSI driver 613 * enqueues a SCSI command 614 */ 615 void 616 trm_scsipi_request(chan, req, arg) 617 struct scsipi_channel *chan; 618 scsipi_adapter_req_t req; 619 void *arg; 620 { 621 bus_space_tag_t iot; 622 bus_space_handle_t ioh; 623 struct trm_softc *sc; 624 struct trm_dcb *dcb = NULL; 625 struct trm_srb *srb; 626 struct scsipi_xfer *xs; 627 int error, i, id, lun, s; 628 629 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 630 iot = sc->sc_iot; 631 ioh = sc->sc_ioh; 632 633 switch (req) { 634 case ADAPTER_REQ_RUN_XFER: 635 xs = arg; 636 id = xs->xs_periph->periph_target; 637 lun = xs->xs_periph->periph_lun; 638 #ifdef TRM_DEBUG 639 printf("trm_scsipi_request.....\n"); 640 printf("%s: id= %d lun= %d\n", sc->sc_dev.dv_xname, id, lun); 641 printf("sc->devscan[id][lun]= %d\n", sc->devscan[id][lun]); 642 #endif 643 if ((id > sc->maxid) || (lun > 7)) { 644 xs->error = XS_DRIVER_STUFFUP; 645 return; 646 } 647 dcb = sc->sc_dcb[id][lun]; 648 if (sc->devscan[id][lun] != 0 && sc->devflag[id][lun] == 0) { 649 /* 650 * Scan SCSI BUS => trm_init_dcb 651 */ 652 if (sc->devcnt < TRM_MAX_TARGETS) { 653 #ifdef TRM_DEBUG 654 printf("trm_init_dcb: dcb=%8x, ", (int) dcb); 655 printf("ID=%2x, LUN=%2x\n", id, lun); 656 #endif 657 sc->devflag[id][lun] = 1; 658 trm_init_dcb(sc, dcb, xs); 659 } else { 660 printf("%s: ", sc->sc_dev.dv_xname); 661 printf("sc->devcnt >= TRM_MAX_TARGETS\n"); 662 xs->error = XS_DRIVER_STUFFUP; 663 return; 664 } 665 } 666 667 if (xs->xs_control & XS_CTL_RESET) { 668 trm_reset(sc); 669 xs->error = XS_NOERROR | XS_RESET; 670 return; 671 } 672 if (xs->xs_status & XS_STS_DONE) { 673 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 674 xs->xs_status &= ~XS_STS_DONE; 675 } 676 xs->error = 0; 677 xs->status = 0; 678 xs->resid = 0; 679 680 s = splbio(); 681 682 /* Get SRB */ 683 srb = sc->sc_freesrb; 684 if (srb != NULL) { 685 sc->sc_freesrb = srb->next; 686 srb->next = NULL; 687 #ifdef TRM_DEBUG 688 printf("srb = %8p sc->sc_freesrb= %8p\n", 689 srb, sc->sc_freesrb); 690 #endif 691 } else { 692 xs->error = XS_RESOURCE_SHORTAGE; 693 scsipi_done(xs); 694 splx(s); 695 return; 696 } 697 /* 698 * XXX BuildSRB(srb ,dcb); XXX 699 */ 700 srb->dcb = dcb; 701 srb->xs = xs; 702 srb->cmdlen = xs->cmdlen; 703 /* 704 * Move layer of CAM command block to layer of SCSI 705 * Request Block for SCSI processor command doing. 706 */ 707 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 708 if (xs->datalen > 0) { 709 #ifdef TRM_DEBUG 710 printf("xs->datalen...\n"); 711 printf("sc->sc_dmat=%x\n", (int) sc->sc_dmat); 712 printf("srb->dmap=%x\n", (int) srb->dmap); 713 printf("xs->data=%x\n", (int) xs->data); 714 printf("xs->datalen=%x\n", (int) xs->datalen); 715 #endif 716 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 717 xs->data, xs->datalen, NULL, 718 (xs->xs_control & XS_CTL_NOSLEEP) ? 719 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) != 0) { 720 printf("%s: DMA transfer map unable to load, " 721 "error = %d\n", sc->sc_dev.dv_xname, error); 722 xs->error = XS_DRIVER_STUFFUP; 723 /* 724 * free SRB 725 */ 726 srb->next = sc->sc_freesrb; 727 sc->sc_freesrb = srb; 728 return; 729 } 730 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 731 srb->dmap->dm_mapsize, 732 (xs->xs_control & XS_CTL_DATA_IN) ? 733 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 734 735 /* Set up the scatter gather list */ 736 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 737 srb->sgentry[i].address = 738 htole32(srb->dmap->dm_segs[i].ds_addr); 739 srb->sgentry[i].length = 740 htole32(srb->dmap->dm_segs[i].ds_len); 741 } 742 srb->buflen = xs->datalen; 743 srb->sgcnt = srb->dmap->dm_nsegs; 744 } else { 745 srb->sgentry[0].address = 0; 746 srb->sgentry[0].length = 0; 747 srb->buflen = 0; 748 srb->sgcnt = 0; 749 } 750 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 751 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 752 753 if (dcb->type != T_SEQUENTIAL) 754 srb->retry = 1; 755 else 756 srb->retry = 0; 757 758 srb->sgindex = 0; 759 srb->hastat = 0; 760 srb->tastat = 0; 761 srb->msgcnt = 0; 762 srb->srbstat = 0; 763 srb->flag = 0; 764 srb->state = 0; 765 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 766 767 trm_send_srb(xs, sc, srb); 768 splx(s); 769 770 if ((xs->xs_control & XS_CTL_POLL) == 0) { 771 int timeout = xs->timeout; 772 timeout = (timeout > 100000) ? 773 timeout / 1000 * hz : timeout * hz / 1000; 774 callout_reset(&xs->xs_callout, timeout, 775 trm_timeout, srb); 776 } else { 777 s = splbio(); 778 do { 779 while (--xs->timeout) { 780 DELAY(1000); 781 if (bus_space_read_2(iot, ioh, 782 TRM_SCSI_STATUS) & SCSIINTERRUPT) 783 break; 784 } 785 if (xs->timeout == 0) { 786 trm_timeout(srb); 787 break; 788 } else 789 trm_intr(sc); 790 } while ((xs->xs_status & XS_STS_DONE) == 0); 791 splx(s); 792 } 793 return; 794 795 case ADAPTER_REQ_GROW_RESOURCES: 796 /* XXX Not supported. */ 797 return; 798 799 case ADAPTER_REQ_SET_XFER_MODE: 800 /* XXX XXX XXX */ 801 return; 802 } 803 } 804 805 static void 806 trm_reset_device(sc) 807 struct trm_softc *sc; 808 { 809 struct trm_dcb *dcb, *pdcb; 810 struct trm_nvram *eeprom; 811 int index; 812 813 dcb = sc->sc_linkdcb; 814 if (dcb == NULL) 815 return; 816 817 pdcb = dcb; 818 do { 819 dcb->mode &= ~(SYNC_NEGO_DONE | WIDE_NEGO_DONE); 820 dcb->synctl = 0; 821 dcb->offset = 0; 822 eeprom = &sc->sc_eeprom; 823 dcb->tacfg = eeprom->target[dcb->id].config0; 824 index = eeprom->target[dcb->id].period & 0x07; 825 dcb->period = trm_clock_period[index]; 826 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && 827 (sc->sc_config & HCC_WIDE_CARD)) 828 dcb->mode |= WIDE_NEGO_ENABLE; 829 830 dcb = dcb->next; 831 } 832 while (pdcb != dcb); 833 } 834 835 static void 836 trm_recover_srb(sc) 837 struct trm_softc *sc; 838 { 839 struct trm_dcb *dcb, *pdcb; 840 struct trm_srb *psrb, *psrb2; 841 int i; 842 843 dcb = sc->sc_linkdcb; 844 if (dcb == NULL) 845 return; 846 847 pdcb = dcb; 848 do { 849 psrb = pdcb->gosrb; 850 for (i = 0; i < pdcb->gosrb_cnt; i++) { 851 psrb2 = psrb; 852 psrb = psrb->next; 853 if (pdcb->waitsrb) { 854 psrb2->next = pdcb->waitsrb; 855 pdcb->waitsrb = psrb2; 856 } else { 857 pdcb->waitsrb = psrb2; 858 pdcb->last_waitsrb = psrb2; 859 psrb2->next = NULL; 860 } 861 } 862 pdcb->gosrb_cnt = 0; 863 pdcb->gosrb = NULL; 864 pdcb->tagmask = 0; 865 pdcb = pdcb->next; 866 } 867 while (pdcb != dcb); 868 } 869 870 /* 871 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 872 */ 873 static void 874 trm_reset(sc) 875 struct trm_softc *sc; 876 { 877 bus_space_tag_t iot = sc->sc_iot; 878 bus_space_handle_t ioh = sc->sc_ioh; 879 int s; 880 881 #ifdef TRM_DEBUG 882 printf("%s: SCSI RESET.........", sc->sc_dev.dv_xname); 883 #endif 884 s = splbio(); 885 886 /* disable SCSI and DMA interrupt */ 887 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 888 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 889 890 trm_reset_scsi_bus(sc); 891 DELAY(500000); 892 893 /* Enable SCSI interrupt */ 894 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 895 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 896 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 897 898 /* Enable DMA interrupt */ 899 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 900 901 /* Clear DMA FIFO */ 902 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 903 904 /* Clear SCSI FIFO */ 905 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 906 907 trm_reset_device(sc); 908 trm_doing_srb_done(sc); 909 sc->sc_actdcb = NULL; 910 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 911 trm_wait_srb(sc); 912 913 splx(s); 914 } 915 916 static void 917 trm_timeout(arg) 918 void *arg; 919 { 920 struct trm_srb *srb = (struct trm_srb *)arg; 921 struct scsipi_xfer *xs = srb->xs; 922 struct scsipi_periph *periph = xs->xs_periph; 923 struct trm_softc *sc; 924 int s; 925 926 if (xs == NULL) 927 printf("trm_timeout called with xs == NULL\n"); 928 929 else { 930 scsipi_printaddr(xs->xs_periph); 931 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 932 } 933 934 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 935 936 s = splbio(); 937 trm_reset_scsi_bus(sc); 938 callout_stop(&xs->xs_callout); 939 splx(s); 940 } 941 942 static int 943 trm_start_scsi(sc, dcb, srb) 944 struct trm_softc *sc; 945 struct trm_dcb *dcb; 946 struct trm_srb *srb; 947 { 948 bus_space_tag_t iot = sc->sc_iot; 949 bus_space_handle_t ioh = sc->sc_ioh; 950 int tagnum; 951 u_int32_t tagmask; 952 u_int8_t scsicmd, idmsg; 953 954 srb->tagnum = 31; 955 956 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 957 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, dcb->id); 958 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 959 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 960 srb->phase = PH_BUS_FREE; /* initial phase */ 961 /* Flush FIFO */ 962 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 963 964 idmsg = dcb->idmsg; 965 966 if ((srb->cmd[0] == INQUIRY) || 967 (srb->cmd[0] == REQUEST_SENSE) || 968 (srb->flag & AUTO_REQSENSE)) { 969 if (((dcb->mode & WIDE_NEGO_ENABLE) && 970 (dcb->mode & WIDE_NEGO_DONE) == 0) || 971 ((dcb->mode & SYNC_NEGO_ENABLE) && 972 (dcb->mode & SYNC_NEGO_DONE) == 0)) { 973 if ((dcb->idmsg & 7) == 0 || srb->cmd[0] != INQUIRY) { 974 scsicmd = SCMD_SEL_ATNSTOP; 975 srb->state = SRB_MSGOUT; 976 goto polling; 977 } 978 } 979 /* Send identify message */ 980 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 981 idmsg & ~MSG_IDENTIFY_DISCFLAG); 982 scsicmd = SCMD_SEL_ATN; 983 srb->state = SRB_START_; 984 } else { /* not inquiry,request sense,auto request sense */ 985 /* Send identify message */ 986 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, idmsg); 987 DELAY(30); 988 scsicmd = SCMD_SEL_ATN; 989 srb->state = SRB_START_; 990 if (dcb->mode & EN_TAG_QUEUING) { 991 /* Send Tag message, get tag id */ 992 tagmask = 1; 993 tagnum = 0; 994 while (tagmask & dcb->tagmask) { 995 tagmask = tagmask << 1; 996 tagnum++; 997 } 998 /* Send Tag id */ 999 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1000 MSG_SIMPLE_Q_TAG); 1001 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, tagnum); 1002 1003 dcb->tagmask |= tagmask; 1004 srb->tagnum = tagnum; 1005 1006 scsicmd = SCMD_SEL_ATN3; 1007 srb->state = SRB_START_; 1008 } 1009 } 1010 polling: 1011 /* 1012 * Send CDB ..command block... 1013 */ 1014 if (srb->flag & AUTO_REQSENSE) { 1015 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, REQUEST_SENSE); 1016 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1017 dcb->idmsg << SCSI_CMD_LUN_SHIFT); 1018 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1019 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1020 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1021 sizeof(struct scsipi_sense_data)); 1022 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1023 } else 1024 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1025 srb->cmd, srb->cmdlen); 1026 1027 if (bus_space_read_2(iot, ioh, TRM_SCSI_STATUS) & SCSIINTERRUPT) { 1028 /* 1029 * If trm_start_scsi return 1: current interrupt status 1030 * is interrupt disreenable. It's said that SCSI processor 1031 * has more one SRB need to do, SCSI processor has been 1032 * occupied by one SRB. 1033 */ 1034 srb->state = SRB_READY; 1035 dcb->tagmask &= ~(1 << srb->tagnum); 1036 return (1); 1037 } else { 1038 /* 1039 * If trm_start_scsi return 0: current interrupt status 1040 * is interrupt enable. It's said that SCSI processor is 1041 * unoccupied. 1042 */ 1043 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1044 sc->sc_actdcb = dcb; 1045 dcb->actsrb = srb; 1046 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1047 DO_DATALATCH | DO_HWRESELECT); 1048 /* it's important for atn stop */ 1049 /* 1050 * SCSI command 1051 */ 1052 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1053 return (0); 1054 } 1055 } 1056 1057 /* 1058 * Catch an interrupt from the adapter 1059 * Process pending device interrupts. 1060 */ 1061 static int 1062 trm_intr(vsc) 1063 void *vsc; 1064 { 1065 bus_space_tag_t iot; 1066 bus_space_handle_t ioh; 1067 struct trm_softc *sc; 1068 struct trm_dcb *dcb; 1069 struct trm_srb *srb; 1070 void (*state_v) (struct trm_softc *, struct trm_srb *, int *); 1071 int phase, intstat, stat = 0; 1072 1073 #ifdef TRM_DEBUG 1074 printf("trm_intr......\n"); 1075 #endif 1076 sc = (struct trm_softc *)vsc; 1077 iot = sc->sc_iot; 1078 ioh = sc->sc_ioh; 1079 1080 if (sc == NULL) 1081 return (0); 1082 1083 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1084 if ((stat & SCSIINTERRUPT) == 0) 1085 return (0); 1086 1087 #ifdef TRM_DEBUG 1088 printf("stat=%2x,", stat); 1089 #endif 1090 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1091 1092 #ifdef TRM_DEBUG 1093 printf("intstat=%2x,", intstat); 1094 #endif 1095 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1096 trm_disconnect(sc); 1097 return (1); 1098 } 1099 if (intstat & INT_RESELECTED) { 1100 trm_reselect(sc); 1101 return (1); 1102 } 1103 if (intstat & INT_SCSIRESET) { 1104 trm_scsi_reset_detect(sc); 1105 return (1); 1106 } 1107 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1108 dcb = sc->sc_actdcb; 1109 srb = dcb->actsrb; 1110 if (dcb != NULL) 1111 if (dcb->flag & ABORT_DEV_) { 1112 srb->msgout[0] = MSG_ABORT; 1113 trm_msgout_abort(sc, srb); 1114 } 1115 /* 1116 * software sequential machine 1117 */ 1118 phase = srb->phase; /* phase: */ 1119 1120 /* 1121 * 62037 or 62137 call trm_scsi_phase0[]... "phase 1122 * entry" handle every phase before start transfer 1123 */ 1124 state_v = (void *)trm_scsi_phase0[phase]; 1125 state_v(sc, srb, &stat); 1126 1127 /* 1128 * if there were any exception occured 1129 * stat will be modify to bus free phase new 1130 * stat transfer out from ... prvious state_v 1131 * 1132 */ 1133 /* phase:0,1,2,3,4,5,6,7 */ 1134 srb->phase = stat & PHASEMASK; 1135 phase = stat & PHASEMASK; 1136 1137 /* 1138 * call trm_scsi_phase1[]... "phase entry" handle every 1139 * phase do transfer 1140 */ 1141 state_v = (void *)trm_scsi_phase1[phase]; 1142 state_v(sc, srb, &stat); 1143 return (1); 1144 } 1145 return (0); 1146 } 1147 1148 static void 1149 trm_msgout_phase0(sc, srb, pstat) 1150 struct trm_softc *sc; 1151 struct trm_srb *srb; 1152 int *pstat; 1153 { 1154 1155 if (srb->state & (SRB_UNEXPECT_RESEL | SRB_ABORT_SENT)) 1156 *pstat = PH_BUS_FREE; /* .. initial phase */ 1157 } 1158 1159 static void 1160 trm_msgout_phase1(sc, srb, pstat) 1161 struct trm_softc *sc; 1162 struct trm_srb *srb; 1163 int *pstat; 1164 { 1165 bus_space_tag_t iot = sc->sc_iot; 1166 bus_space_handle_t ioh = sc->sc_ioh; 1167 struct trm_dcb *dcb; 1168 1169 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1170 dcb = sc->sc_actdcb; 1171 if ((srb->state & SRB_MSGOUT) == 0) { 1172 if (srb->msgcnt > 0) { 1173 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1174 srb->msgout, srb->msgcnt); 1175 srb->msgcnt = 0; 1176 if ((dcb->flag & ABORT_DEV_) && 1177 (srb->msgout[0] == MSG_ABORT)) 1178 srb->state = SRB_ABORT_SENT; 1179 } else { 1180 if ((srb->cmd[0] == INQUIRY) || 1181 (srb->cmd[0] == REQUEST_SENSE) || 1182 (srb->flag & AUTO_REQSENSE)) 1183 if (dcb->mode & SYNC_NEGO_ENABLE) 1184 goto mop1; 1185 1186 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, MSG_ABORT); 1187 } 1188 } else { 1189 mop1: /* message out phase */ 1190 if ((srb->state & SRB_DO_WIDE_NEGO) == 0 && 1191 (dcb->mode & WIDE_NEGO_ENABLE)) { 1192 /* 1193 * WIDE DATA TRANSFER REQUEST code (03h) 1194 */ 1195 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1196 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1197 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1198 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1199 MSG_EXTENDED); /* (01h) */ 1200 1201 /* Message length (02h) */ 1202 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1203 MSG_EXT_WDTR_LEN); 1204 1205 /* wide data xfer (03h) */ 1206 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1207 MSG_EXT_WDTR); 1208 1209 /* width: 0(8bit), 1(16bit) ,2(32bit) */ 1210 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1211 MSG_EXT_WDTR_BUS_16_BIT); 1212 1213 srb->state |= SRB_DO_WIDE_NEGO; 1214 } else if ((srb->state & SRB_DO_SYNC_NEGO) == 0 && 1215 (dcb->mode & SYNC_NEGO_ENABLE)) { 1216 /* 1217 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1218 */ 1219 if ((dcb->mode & WIDE_NEGO_DONE) == 0) 1220 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1221 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1222 1223 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1224 MSG_EXTENDED); /* (01h) */ 1225 1226 /* Message length (03h) */ 1227 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1228 MSG_EXT_SDTR_LEN); 1229 1230 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1231 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1232 MSG_EXT_SDTR); 1233 1234 /* Transfer peeriod factor */ 1235 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, dcb->period); 1236 1237 /* REQ/ACK offset */ 1238 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1239 SYNC_NEGO_OFFSET); 1240 srb->state |= SRB_DO_SYNC_NEGO; 1241 } 1242 } 1243 /* it's important for atn stop */ 1244 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1245 1246 /* 1247 * SCSI cammand 1248 */ 1249 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1250 } 1251 1252 static void 1253 trm_command_phase0(sc, srb, pstat) 1254 struct trm_softc *sc; 1255 struct trm_srb *srb; 1256 int *pstat; 1257 { 1258 1259 } 1260 1261 static void 1262 trm_command_phase1(sc, srb, pstat) 1263 struct trm_softc *sc; 1264 struct trm_srb *srb; 1265 int *pstat; 1266 { 1267 bus_space_tag_t iot = sc->sc_iot; 1268 bus_space_handle_t ioh = sc->sc_ioh; 1269 struct trm_dcb *dcb; 1270 1271 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1272 if (srb->flag & AUTO_REQSENSE) { 1273 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, REQUEST_SENSE); 1274 dcb = sc->sc_actdcb; 1275 /* target id */ 1276 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1277 dcb->idmsg << SCSI_CMD_LUN_SHIFT); 1278 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1279 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1280 /* sizeof(struct scsi_sense_data) */ 1281 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1282 sizeof(struct scsipi_sense_data)); 1283 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1284 } else 1285 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1286 srb->cmd, srb->cmdlen); 1287 1288 srb->state = SRB_COMMAND; 1289 /* it's important for atn stop */ 1290 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1291 1292 /* 1293 * SCSI cammand 1294 */ 1295 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1296 } 1297 1298 static void 1299 trm_dataout_phase0(sc, srb, pstat) 1300 struct trm_softc *sc; 1301 struct trm_srb *srb; 1302 int *pstat; 1303 { 1304 bus_space_tag_t iot = sc->sc_iot; 1305 bus_space_handle_t ioh = sc->sc_ioh; 1306 struct trm_dcb *dcb; 1307 struct trm_sg_entry *sg; 1308 int sgindex; 1309 u_int32_t xferlen, leftcnt = 0; 1310 1311 dcb = srb->dcb; 1312 1313 if ((srb->state & SRB_XFERPAD) == 0) { 1314 if (*pstat & PARITYERROR) 1315 srb->srbstat |= PARITY_ERROR; 1316 1317 if ((*pstat & SCSIXFERDONE) == 0) { 1318 /* 1319 * when data transfer from DMA FIFO to SCSI FIFO 1320 * if there was some data left in SCSI FIFO 1321 */ 1322 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1323 SCSI_FIFOCNT_MASK; 1324 if (dcb->synctl & WIDE_SYNC) 1325 /* 1326 * if WIDE scsi SCSI FIFOCNT unit is word 1327 * so need to * 2 1328 */ 1329 leftcnt <<= 1; 1330 } 1331 /* 1332 * caculate all the residue data that not yet tranfered 1333 * SCSI transfer counter + left in SCSI FIFO data 1334 * 1335 * .....TRM_SCSI_XCNT (24bits) 1336 * The counter always decrement by one for every SCSI 1337 * byte transfer. 1338 * .....TRM_SCSI_FIFOCNT ( 5bits) 1339 * The counter is SCSI FIFO offset counter 1340 */ 1341 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1342 if (leftcnt == 1) { 1343 leftcnt = 0; 1344 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1345 DO_CLRFIFO); 1346 } 1347 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1348 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1349 DMAXFERCOMP) == 0) 1350 ; 1351 1352 srb->buflen = 0; 1353 } else { /* Update SG list */ 1354 /* 1355 * if transfer not yet complete 1356 * there were some data residue in SCSI FIFO or 1357 * SCSI transfer counter not empty 1358 */ 1359 if (srb->buflen != leftcnt) { 1360 /* data that had transferred length */ 1361 xferlen = srb->buflen - leftcnt; 1362 1363 /* next time to be transferred length */ 1364 srb->buflen = leftcnt; 1365 1366 /* 1367 * parsing from last time disconnect sgindex 1368 */ 1369 sg = srb->sgentry + srb->sgindex; 1370 for (sgindex = srb->sgindex; 1371 sgindex < srb->sgcnt; 1372 sgindex++, sg++) { 1373 /* 1374 * find last time which SG transfer 1375 * be disconnect 1376 */ 1377 if (xferlen >= le32toh(sg->length)) 1378 xferlen -= le32toh(sg->length); 1379 else { 1380 /* 1381 * update last time 1382 * disconnected SG list 1383 */ 1384 /* residue data length */ 1385 sg->length = htole32( 1386 le32toh(sg->length) 1387 - xferlen); 1388 /* residue data pointer */ 1389 sg->address = htole32( 1390 le32toh(sg->address) 1391 + xferlen); 1392 srb->sgindex = sgindex; 1393 break; 1394 } 1395 } 1396 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1397 srb->sgoffset, TRM_SG_SIZE, 1398 BUS_DMASYNC_PREWRITE); 1399 } 1400 } 1401 } 1402 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1403 } 1404 1405 static void 1406 trm_dataout_phase1(sc, srb, pstat) 1407 struct trm_softc *sc; 1408 struct trm_srb *srb; 1409 int *pstat; 1410 { 1411 1412 /* 1413 * do prepare befor transfer when data out phase 1414 */ 1415 trm_dataio_xfer(sc, srb, XFERDATAOUT); 1416 } 1417 1418 static void 1419 trm_datain_phase0(sc, srb, pstat) 1420 struct trm_softc *sc; 1421 struct trm_srb *srb; 1422 int *pstat; 1423 { 1424 bus_space_tag_t iot = sc->sc_iot; 1425 bus_space_handle_t ioh = sc->sc_ioh; 1426 struct trm_sg_entry *sg; 1427 int sgindex; 1428 u_int32_t xferlen, leftcnt = 0; 1429 1430 if ((srb->state & SRB_XFERPAD) == 0) { 1431 if (*pstat & PARITYERROR) 1432 srb->srbstat |= PARITY_ERROR; 1433 1434 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1435 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1436 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1437 DMAXFERCOMP) == 0) 1438 ; 1439 1440 srb->buflen = 0; 1441 } else { /* phase changed */ 1442 /* 1443 * parsing the case: 1444 * when a transfer not yet complete 1445 * but be disconnected by uper layer 1446 * if transfer not yet complete 1447 * there were some data residue in SCSI FIFO or 1448 * SCSI transfer counter not empty 1449 */ 1450 if (srb->buflen != leftcnt) { 1451 /* 1452 * data that had transferred length 1453 */ 1454 xferlen = srb->buflen - leftcnt; 1455 1456 /* 1457 * next time to be transferred length 1458 */ 1459 srb->buflen = leftcnt; 1460 1461 /* 1462 * parsing from last time disconnect sgindex 1463 */ 1464 sg = srb->sgentry + srb->sgindex; 1465 for (sgindex = srb->sgindex; 1466 sgindex < srb->sgcnt; 1467 sgindex++, sg++) { 1468 /* 1469 * find last time which SG transfer 1470 * be disconnect 1471 */ 1472 if (xferlen >= le32toh(sg->length)) 1473 xferlen -= le32toh(sg->length); 1474 else { 1475 /* 1476 * update last time 1477 * disconnected SG list 1478 */ 1479 /* residue data length */ 1480 sg->length = htole32( 1481 le32toh(sg->length) 1482 - xferlen); 1483 /* residue data pointer */ 1484 sg->address = htole32( 1485 le32toh(sg->address) 1486 + xferlen); 1487 srb->sgindex = sgindex; 1488 break; 1489 } 1490 } 1491 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1492 srb->sgoffset, TRM_SG_SIZE, 1493 BUS_DMASYNC_PREWRITE); 1494 } 1495 } 1496 } 1497 } 1498 1499 static void 1500 trm_datain_phase1(sc, srb, pstat) 1501 struct trm_softc *sc; 1502 struct trm_srb *srb; 1503 int *pstat; 1504 { 1505 1506 /* 1507 * do prepare befor transfer when data in phase 1508 */ 1509 trm_dataio_xfer(sc, srb, XFERDATAIN); 1510 } 1511 1512 static void 1513 trm_dataio_xfer(sc, srb, iodir) 1514 struct trm_softc *sc; 1515 struct trm_srb *srb; 1516 int iodir; 1517 { 1518 bus_space_tag_t iot = sc->sc_iot; 1519 bus_space_handle_t ioh = sc->sc_ioh; 1520 struct trm_dcb *dcb = srb->dcb; 1521 1522 if (srb->sgindex < srb->sgcnt) { 1523 if (srb->buflen > 0) { 1524 /* 1525 * load what physical address of Scatter/Gather 1526 * list table want to be transfer 1527 */ 1528 srb->state = SRB_DATA_XFER; 1529 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1530 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1531 srb->sgaddr + 1532 srb->sgindex * sizeof(struct trm_sg_entry)); 1533 /* 1534 * load how many bytes in the Scatter/Gather list table 1535 */ 1536 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1537 (srb->sgcnt - srb->sgindex) 1538 * sizeof(struct trm_sg_entry)); 1539 /* 1540 * load total xfer length (24bits) max value 16Mbyte 1541 */ 1542 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1543 /* Start DMA transfer */ 1544 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1545 iodir | SGXFER); 1546 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1547 STARTDMAXFER); 1548 1549 /* Start SCSI transfer */ 1550 /* it's important for atn stop */ 1551 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1552 DO_DATALATCH); 1553 1554 /* 1555 * SCSI cammand 1556 */ 1557 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1558 (iodir == XFERDATAOUT) ? 1559 SCMD_DMA_OUT : SCMD_DMA_IN); 1560 } else { /* xfer pad */ 1561 if (srb->sgcnt) { 1562 srb->hastat = H_OVER_UNDER_RUN; 1563 srb->srbstat |= OVER_RUN; 1564 } 1565 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1566 (dcb->synctl & WIDE_SYNC) ? 2 : 1); 1567 1568 if (iodir == XFERDATAOUT) 1569 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1570 else 1571 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1572 1573 srb->state |= SRB_XFERPAD; 1574 /* it's important for atn stop */ 1575 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1576 DO_DATALATCH); 1577 1578 /* 1579 * SCSI cammand 1580 */ 1581 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1582 (iodir == XFERDATAOUT) ? 1583 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1584 } 1585 } 1586 } 1587 1588 static void 1589 trm_status_phase0(sc, srb, pstat) 1590 struct trm_softc *sc; 1591 struct trm_srb *srb; 1592 int *pstat; 1593 { 1594 bus_space_tag_t iot = sc->sc_iot; 1595 bus_space_handle_t ioh = sc->sc_ioh; 1596 1597 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1598 srb->state = SRB_COMPLETED; 1599 *pstat = PH_BUS_FREE; /* .. initial phase */ 1600 /* it's important for atn stop */ 1601 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1602 1603 /* 1604 * SCSI cammand 1605 */ 1606 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1607 } 1608 1609 static void 1610 trm_status_phase1(sc, srb, pstat) 1611 struct trm_softc *sc; 1612 struct trm_srb *srb; 1613 int *pstat; 1614 { 1615 bus_space_tag_t iot = sc->sc_iot; 1616 bus_space_handle_t ioh = sc->sc_ioh; 1617 1618 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1619 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1620 & SCSI_FIFO_EMPTY) == 0) 1621 bus_space_write_2(iot, ioh, 1622 TRM_SCSI_CONTROL, DO_CLRFIFO); 1623 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1624 & DMA_FIFO_EMPTY) == 0) 1625 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1626 } else { 1627 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1628 & DMA_FIFO_EMPTY) == 0) 1629 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1630 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1631 & SCSI_FIFO_EMPTY) == 0) 1632 bus_space_write_2(iot, ioh, 1633 TRM_SCSI_CONTROL, DO_CLRFIFO); 1634 } 1635 srb->state = SRB_STATUS; 1636 /* it's important for atn stop */ 1637 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1638 1639 /* 1640 * SCSI cammand 1641 */ 1642 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1643 } 1644 1645 static void 1646 trm_msgin_phase0(sc, srb, pstat) 1647 struct trm_softc *sc; 1648 struct trm_srb *srb; 1649 int *pstat; 1650 { 1651 bus_space_tag_t iot = sc->sc_iot; 1652 bus_space_handle_t ioh = sc->sc_ioh; 1653 struct trm_dcb *dcb = sc->sc_actdcb; 1654 struct trm_srb *tempsrb; 1655 int syncxfer, tagid, index; 1656 u_int8_t msgin_code; 1657 1658 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1659 if ((srb->state & SRB_EXTEND_MSGIN) == 0) { 1660 if (msgin_code == MSG_DISCONNECT) { 1661 srb->state = SRB_DISCONNECT; 1662 goto min6; 1663 } else if (msgin_code == MSG_SAVEDATAPOINTER) { 1664 goto min6; 1665 } else if ((msgin_code == MSG_EXTENDED) || 1666 ((msgin_code >= MSG_SIMPLE_Q_TAG) && 1667 (msgin_code <= MSG_ORDERED_Q_TAG))) { 1668 srb->state |= SRB_EXTEND_MSGIN; 1669 /* extended message (01h) */ 1670 srb->msgin[0] = msgin_code; 1671 1672 srb->msgcnt = 1; 1673 /* extended message length (n) */ 1674 srb->msg = &srb->msgin[1]; 1675 1676 goto min6; 1677 } else if (msgin_code == MSG_MESSAGE_REJECT) { 1678 /* Reject message */ 1679 /* do wide nego reject */ 1680 if (dcb->mode & WIDE_NEGO_ENABLE) { 1681 dcb = srb->dcb; 1682 dcb->mode |= WIDE_NEGO_DONE; 1683 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP | 1684 WIDE_NEGO_ENABLE); 1685 srb->state &= ~(SRB_DO_WIDE_NEGO | SRB_MSGIN); 1686 if ((dcb->mode & SYNC_NEGO_ENABLE) && 1687 (dcb->mode & SYNC_NEGO_DONE) == 0) { 1688 /* Set ATN, in case ATN was clear */ 1689 srb->state |= SRB_MSGOUT; 1690 bus_space_write_2(iot, ioh, 1691 TRM_SCSI_CONTROL, DO_SETATN); 1692 } else 1693 /* Clear ATN */ 1694 bus_space_write_2(iot, ioh, 1695 TRM_SCSI_CONTROL, DO_CLRATN); 1696 } else if (dcb->mode & SYNC_NEGO_ENABLE) { 1697 /* do sync nego reject */ 1698 bus_space_write_2(iot, ioh, 1699 TRM_SCSI_CONTROL, DO_CLRATN); 1700 if (srb->state & SRB_DO_SYNC_NEGO) { 1701 dcb = srb->dcb; 1702 dcb->mode &= ~(SYNC_NEGO_ENABLE | 1703 SYNC_NEGO_DONE); 1704 dcb->synctl = 0; 1705 dcb->offset = 0; 1706 goto re_prog; 1707 } 1708 } 1709 goto min6; 1710 } else if (msgin_code == MSG_IGN_WIDE_RESIDUE) { 1711 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1712 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1713 goto min6; 1714 } else { 1715 /* 1716 * Restore data pointer message 1717 * Save data pointer message 1718 * Completion message 1719 * NOP message 1720 */ 1721 goto min6; 1722 } 1723 } else { 1724 /* 1725 * when extend message in:srb->state = SRB_EXTEND_MSGIN 1726 * Parsing incomming extented messages 1727 */ 1728 *srb->msg = msgin_code; 1729 srb->msgcnt++; 1730 srb->msg++; 1731 #ifdef TRM_DEBUG 1732 printf("srb->msgin[0]=%2x\n", srb->msgin[0]); 1733 printf("srb->msgin[1]=%2x\n", srb->msgin[1]); 1734 printf("srb->msgin[2]=%2x\n", srb->msgin[2]); 1735 printf("srb->msgin[3]=%2x\n", srb->msgin[3]); 1736 printf("srb->msgin[4]=%2x\n", srb->msgin[4]); 1737 #endif 1738 if ((srb->msgin[0] >= MSG_SIMPLE_Q_TAG) && 1739 (srb->msgin[0] <= MSG_ORDERED_Q_TAG)) { 1740 /* 1741 * is QUEUE tag message : 1742 * 1743 * byte 0: 1744 * HEAD QUEUE TAG (20h) 1745 * ORDERED QUEUE TAG (21h) 1746 * SIMPLE QUEUE TAG (22h) 1747 * byte 1: 1748 * Queue tag (00h - FFh) 1749 */ 1750 if (srb->msgcnt == 2) { 1751 srb->state = 0; 1752 tagid = srb->msgin[1]; 1753 srb = dcb->gosrb; 1754 tempsrb = dcb->last_gosrb; 1755 if (srb) { 1756 for (;;) { 1757 if (srb->tagnum != tagid) { 1758 if (srb == tempsrb) 1759 goto mingx0; 1760 1761 srb = srb->next; 1762 } else 1763 break; 1764 } 1765 if (dcb->flag & ABORT_DEV_) { 1766 srb->state = SRB_ABORT_SENT; 1767 srb->msgout[0] = MSG_ABORT; 1768 trm_msgout_abort(sc, srb); 1769 } 1770 if ((srb->state & SRB_DISCONNECT) == 0) 1771 goto mingx0; 1772 1773 dcb->actsrb = srb; 1774 srb->state = SRB_DATA_XFER; 1775 } else { 1776 mingx0: 1777 srb = sc->sc_tempsrb; 1778 srb->state = SRB_UNEXPECT_RESEL; 1779 dcb->actsrb = srb; 1780 srb->msgout[0] = MSG_ABORT_TAG; 1781 trm_msgout_abort(sc, srb); 1782 } 1783 } 1784 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1785 (srb->msgin[2] == MSG_EXT_WDTR) && 1786 (srb->msgcnt == 4)) { 1787 /* 1788 * is Wide data xfer Extended message : 1789 * ====================================== 1790 * WIDE DATA TRANSFER REQUEST 1791 * ====================================== 1792 * byte 0 : Extended message (01h) 1793 * byte 1 : Extended message length (02h) 1794 * byte 2 : WIDE DATA TRANSFER code (03h) 1795 * byte 3 : Transfer width exponent 1796 */ 1797 dcb = srb->dcb; 1798 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_WIDE_NEGO); 1799 if ((srb->msgin[1] != MSG_EXT_WDTR_LEN)) { 1800 /* Length is wrong, reject it */ 1801 dcb->mode &= 1802 ~(WIDE_NEGO_ENABLE | WIDE_NEGO_DONE); 1803 srb->msgcnt = 1; 1804 srb->msgin[0] = MSG_MESSAGE_REJECT; 1805 bus_space_write_2(iot, ioh, 1806 TRM_SCSI_CONTROL, DO_SETATN); 1807 goto min6; 1808 } 1809 if (dcb->mode & WIDE_NEGO_ENABLE) { 1810 /* Do wide negoniation */ 1811 if (srb->msgin[3] > MSG_EXT_WDTR_BUS_32_BIT) { 1812 /* reject_msg: */ 1813 dcb->mode &= ~(WIDE_NEGO_ENABLE | 1814 WIDE_NEGO_DONE); 1815 srb->msgcnt = 1; 1816 srb->msgin[0] = MSG_MESSAGE_REJECT; 1817 bus_space_write_2(iot, ioh, 1818 TRM_SCSI_CONTROL, DO_SETATN); 1819 goto min6; 1820 } 1821 if (srb->msgin[3] == MSG_EXT_WDTR_BUS_32_BIT) 1822 /* do 16 bits */ 1823 srb->msgin[3] = MSG_EXT_WDTR_BUS_16_BIT; 1824 else { 1825 if ((dcb->mode & WIDE_NEGO_DONE) == 0) { 1826 srb->state &= 1827 ~(SRB_DO_WIDE_NEGO | 1828 SRB_MSGIN); 1829 dcb->mode |= WIDE_NEGO_DONE; 1830 dcb->mode &= 1831 ~(SYNC_NEGO_DONE | 1832 EN_ATN_STOP | 1833 WIDE_NEGO_ENABLE); 1834 if (srb->msgin[3] != 1835 MSG_EXT_WDTR_BUS_8_BIT) 1836 /* is Wide data xfer */ 1837 dcb->synctl |= 1838 WIDE_SYNC; 1839 } 1840 } 1841 } else 1842 srb->msgin[3] = MSG_EXT_WDTR_BUS_8_BIT; 1843 1844 srb->state |= SRB_MSGOUT; 1845 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1846 DO_SETATN); 1847 goto min6; 1848 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1849 (srb->msgin[2] == MSG_EXT_SDTR) && 1850 (srb->msgcnt == 5)) { 1851 /* 1852 * is 8bit transfer Extended message : 1853 * ================================= 1854 * SYNCHRONOUS DATA TRANSFER REQUEST 1855 * ================================= 1856 * byte 0 : Extended message (01h) 1857 * byte 1 : Extended message length (03) 1858 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1859 * byte 3 : Transfer period factor 1860 * byte 4 : REQ/ACK offset 1861 */ 1862 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_SYNC_NEGO); 1863 if (srb->msgin[1] != MSG_EXT_SDTR_LEN) { 1864 /* reject_msg: */ 1865 srb->msgcnt = 1; 1866 srb->msgin[0] = MSG_MESSAGE_REJECT; 1867 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1868 DO_SETATN); 1869 } else if (srb->msgin[3] == 0 || srb->msgin[4] == 0) { 1870 /* set async */ 1871 dcb = srb->dcb; 1872 /* disable sync & sync nego */ 1873 dcb->mode &= 1874 ~(SYNC_NEGO_ENABLE | SYNC_NEGO_DONE); 1875 dcb->synctl = 0; 1876 dcb->offset = 0; 1877 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1878 (dcb->lun == 0)) { 1879 printf("%s: target %d, Sync period=0 " 1880 "or Sync offset=0 to be " 1881 "asynchronous transfer\n", 1882 sc->sc_dev.dv_xname, dcb->id); 1883 dcb->flag |= SHOW_MESSAGE_; 1884 } 1885 goto re_prog; 1886 } else { /* set sync */ 1887 dcb = srb->dcb; 1888 dcb->mode |= SYNC_NEGO_ENABLE | SYNC_NEGO_DONE; 1889 1890 /* Transfer period factor */ 1891 dcb->period = srb->msgin[3]; 1892 1893 /* REQ/ACK offset */ 1894 dcb->offset = srb->msgin[4]; 1895 for (index = 0; index < 7; index++) 1896 if (srb->msgin[3] <= 1897 trm_clock_period[index]) 1898 break; 1899 1900 dcb->synctl |= (index | ALT_SYNC); 1901 /* 1902 * show negotiation message 1903 */ 1904 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1905 (dcb->lun == 0)) { 1906 syncxfer = 100000 / 1907 (trm_clock_period[index] * 4); 1908 if (dcb->synctl & WIDE_SYNC) { 1909 printf("%s: target %d, " 1910 "16bits Wide transfer\n", 1911 sc->sc_dev.dv_xname, 1912 dcb->id); 1913 syncxfer = syncxfer * 2; 1914 } else 1915 printf("%s: target %d, " 1916 "8bits Narrow transfer\n", 1917 sc->sc_dev.dv_xname, 1918 dcb->id); 1919 1920 printf("%s: target %d, " 1921 "Sync transfer %d.%01d MB/sec, " 1922 "Offset %d\n", sc->sc_dev.dv_xname, 1923 dcb->id, syncxfer / 100, 1924 syncxfer % 100, dcb->offset); 1925 dcb->flag |= SHOW_MESSAGE_; 1926 } 1927 re_prog: 1928 /* 1929 * program SCSI control register 1930 */ 1931 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, 1932 dcb->synctl); 1933 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 1934 dcb->offset); 1935 trm_set_xfer_rate(sc, srb, dcb); 1936 } 1937 } 1938 } 1939 min6: 1940 *pstat = PH_BUS_FREE; /* .. initial phase */ 1941 /* it's important for atn stop */ 1942 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1943 1944 /* 1945 * SCSI cammand 1946 */ 1947 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1948 } 1949 1950 static void 1951 trm_msgin_phase1(sc, srb, pstat) 1952 struct trm_softc *sc; 1953 struct trm_srb *srb; 1954 int *pstat; 1955 { 1956 bus_space_tag_t iot = sc->sc_iot; 1957 bus_space_handle_t ioh = sc->sc_ioh; 1958 1959 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1960 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1961 if ((srb->state & SRB_MSGIN) == 0) { 1962 srb->state &= SRB_DISCONNECT; 1963 srb->state |= SRB_MSGIN; 1964 } 1965 /* it's important for atn stop */ 1966 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1967 1968 /* 1969 * SCSI cammand 1970 */ 1971 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1972 } 1973 1974 static void 1975 trm_nop0(sc, srb, pstat) 1976 struct trm_softc *sc; 1977 struct trm_srb *srb; 1978 int *pstat; 1979 { 1980 1981 } 1982 1983 static void 1984 trm_nop1(sc, srb, pstat) 1985 struct trm_softc *sc; 1986 struct trm_srb *srb; 1987 int *pstat; 1988 { 1989 1990 } 1991 1992 static void 1993 trm_set_xfer_rate(sc, srb, dcb) 1994 struct trm_softc *sc; 1995 struct trm_srb *srb; 1996 struct trm_dcb *dcb; 1997 { 1998 struct trm_dcb *tempdcb; 1999 int i; 2000 2001 /* 2002 * set all lun device's (period, offset) 2003 */ 2004 #ifdef TRM_DEBUG 2005 printf("trm_set_xfer_rate............\n"); 2006 #endif 2007 if ((dcb->idmsg & 0x07) == 0) { 2008 if (sc->devscan_end == 0) 2009 sc->cur_offset = dcb->offset; 2010 else { 2011 tempdcb = sc->sc_linkdcb; 2012 for (i = 0; i < sc->devcnt; i++) { 2013 /* 2014 * different LUN but had same target ID 2015 */ 2016 if (tempdcb->id == dcb->id) { 2017 tempdcb->synctl = dcb->synctl; 2018 tempdcb->offset = dcb->offset; 2019 tempdcb->mode = dcb->mode; 2020 } 2021 tempdcb = tempdcb->next; 2022 } 2023 } 2024 } 2025 } 2026 2027 static void 2028 trm_disconnect(sc) 2029 struct trm_softc *sc; 2030 { 2031 bus_space_tag_t iot = sc->sc_iot; 2032 bus_space_handle_t ioh = sc->sc_ioh; 2033 struct trm_dcb *dcb; 2034 struct trm_srb *srb, *psrb; 2035 int i, s; 2036 2037 #ifdef TRM_DEBUG 2038 printf("trm_disconnect...............\n"); 2039 #endif 2040 s = splbio(); 2041 2042 dcb = sc->sc_actdcb; 2043 if (dcb == NULL) { 2044 DELAY(1000); /* 1 msec */ 2045 2046 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2047 DO_CLRFIFO | DO_HWRESELECT); 2048 return; 2049 } 2050 srb = dcb->actsrb; 2051 sc->sc_actdcb = 0; 2052 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2053 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2054 DO_CLRFIFO | DO_HWRESELECT); 2055 DELAY(100); 2056 if (srb->state & SRB_UNEXPECT_RESEL) { 2057 srb->state = 0; 2058 trm_wait_srb(sc); 2059 } else if (srb->state & SRB_ABORT_SENT) { 2060 dcb->tagmask = 0; 2061 dcb->flag &= ~ABORT_DEV_; 2062 srb = dcb->gosrb; 2063 for (i = 0; i < dcb->gosrb_cnt; i++) { 2064 psrb = srb->next; 2065 srb->next = sc->sc_freesrb; 2066 sc->sc_freesrb = srb; 2067 srb = psrb; 2068 } 2069 dcb->gosrb_cnt = 0; 2070 dcb->gosrb = 0; 2071 trm_wait_srb(sc); 2072 } else { 2073 if ((srb->state & (SRB_START_ | SRB_MSGOUT)) || 2074 (srb->state & (SRB_DISCONNECT | SRB_COMPLETED)) == 0) { 2075 /* Selection time out */ 2076 if (sc->devscan_end) { 2077 srb->state = SRB_READY; 2078 trm_rewait_srb(dcb, srb); 2079 } else { 2080 srb->tastat = SCSI_SEL_TIMEOUT; 2081 goto disc1; 2082 } 2083 } else if (srb->state & SRB_DISCONNECT) { 2084 /* 2085 * SRB_DISCONNECT 2086 */ 2087 trm_wait_srb(sc); 2088 } else if (srb->state & SRB_COMPLETED) { 2089 disc1: 2090 /* 2091 * SRB_COMPLETED 2092 */ 2093 if (dcb->maxcmd > 1) { 2094 /* free tag mask */ 2095 dcb->tagmask &= ~(1 << srb->tagnum); 2096 } 2097 dcb->actsrb = 0; 2098 srb->state = SRB_FREE; 2099 trm_srb_done(sc, dcb, srb); 2100 } 2101 } 2102 splx(s); 2103 } 2104 2105 static void 2106 trm_reselect(sc) 2107 struct trm_softc *sc; 2108 { 2109 bus_space_tag_t iot = sc->sc_iot; 2110 bus_space_handle_t ioh = sc->sc_ioh; 2111 struct trm_dcb *dcb; 2112 struct trm_srb *srb; 2113 int id, lun; 2114 2115 #ifdef TRM_DEBUG 2116 printf("trm_reselect.................\n"); 2117 #endif 2118 dcb = sc->sc_actdcb; 2119 if (dcb != NULL) { /* Arbitration lost but Reselection win */ 2120 srb = dcb->actsrb; 2121 srb->state = SRB_READY; 2122 trm_rewait_srb(dcb, srb); 2123 } 2124 /* Read Reselected Target Id and LUN */ 2125 id = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2126 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2127 dcb = sc->sc_linkdcb; 2128 while (id != dcb->id && lun != dcb->lun) 2129 /* get dcb of the reselect id */ 2130 dcb = dcb->next; 2131 2132 sc->sc_actdcb = dcb; 2133 if (dcb->mode & EN_TAG_QUEUING) { 2134 srb = sc->sc_tempsrb; 2135 dcb->actsrb = srb; 2136 } else { 2137 srb = dcb->actsrb; 2138 if (srb == NULL || (srb->state & SRB_DISCONNECT) == 0) { 2139 /* 2140 * abort command 2141 */ 2142 srb = sc->sc_tempsrb; 2143 srb->state = SRB_UNEXPECT_RESEL; 2144 dcb->actsrb = srb; 2145 srb->msgout[0] = MSG_ABORT; 2146 trm_msgout_abort(sc, srb); 2147 } else { 2148 if (dcb->flag & ABORT_DEV_) { 2149 srb->state = SRB_ABORT_SENT; 2150 srb->msgout[0] = MSG_ABORT; 2151 trm_msgout_abort(sc, srb); 2152 } else 2153 srb->state = SRB_DATA_XFER; 2154 } 2155 } 2156 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2157 /* 2158 * Program HA ID, target ID, period and offset 2159 */ 2160 /* target ID */ 2161 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, id); 2162 2163 /* host ID */ 2164 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2165 2166 /* period */ 2167 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 2168 2169 /* offset */ 2170 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 2171 2172 /* it's important for atn stop */ 2173 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2174 DELAY(30); 2175 /* 2176 * SCSI cammand 2177 */ 2178 /* to rls the /ACK signal */ 2179 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2180 } 2181 2182 /* 2183 * Complete execution of a SCSI command 2184 * Signal completion to the generic SCSI driver 2185 */ 2186 static void 2187 trm_srb_done(sc, dcb, srb) 2188 struct trm_softc *sc; 2189 struct trm_dcb *dcb; 2190 struct trm_srb *srb; 2191 { 2192 struct scsipi_xfer *xs = srb->xs; 2193 struct scsipi_inquiry_data *ptr; 2194 struct trm_dcb *tempdcb; 2195 int i, j, id, lun, s, tastat; 2196 u_int8_t bval; 2197 2198 #ifdef TRM_DEBUG 2199 printf("trm_srb_done..................\n"); 2200 #endif 2201 if ((xs->xs_control & XS_CTL_POLL) == 0) 2202 callout_stop(&xs->xs_callout); 2203 2204 if (xs == NULL) 2205 return; 2206 2207 /* 2208 * target status 2209 */ 2210 tastat = srb->tastat; 2211 2212 if (srb->flag & AUTO_REQSENSE) { 2213 /* 2214 * status of auto request sense 2215 */ 2216 srb->flag &= ~AUTO_REQSENSE; 2217 srb->hastat = 0; 2218 srb->tastat = SCSI_CHECK; 2219 if (tastat == SCSI_CHECK) { 2220 xs->error = XS_TIMEOUT; 2221 goto ckc_e; 2222 } 2223 memcpy(srb->cmd, srb->tempcmd, sizeof(srb->tempcmd)); 2224 2225 srb->buflen = srb->templen; 2226 srb->sgentry[0].address = srb->tempsg.address; 2227 srb->sgentry[0].length = srb->tempsg.length; 2228 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2229 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2230 xs->status = SCSI_CHECK; 2231 goto ckc_e; 2232 } 2233 /* 2234 * target status 2235 */ 2236 if (tastat) 2237 switch (tastat) { 2238 case SCSI_CHECK: 2239 trm_request_sense(sc, dcb, srb); 2240 return; 2241 case SCSI_QUEUE_FULL: 2242 dcb->maxcmd = dcb->gosrb_cnt - 1; 2243 trm_rewait_srb(dcb, srb); 2244 srb->hastat = 0; 2245 srb->tastat = 0; 2246 goto ckc_e; 2247 case SCSI_SEL_TIMEOUT: 2248 srb->hastat = H_SEL_TIMEOUT; 2249 srb->tastat = 0; 2250 xs->error = XS_TIMEOUT; 2251 break; 2252 case SCSI_BUSY: 2253 xs->error = XS_BUSY; 2254 break; 2255 case SCSI_RESV_CONFLICT: 2256 #ifdef TRM_DEBUG 2257 printf("%s: target reserved at ", sc->sc_dev.dv_xname); 2258 printf("%s %d\n", __FILE__, __LINE__); 2259 #endif 2260 xs->error = XS_BUSY; 2261 break; 2262 default: 2263 srb->hastat = 0; 2264 if (srb->retry) { 2265 srb->retry--; 2266 srb->tastat = 0; 2267 srb->sgindex = 0; 2268 if (trm_start_scsi(sc, dcb, srb)) 2269 /* 2270 * If trm_start_scsi return 1 : 2271 * current interrupt status is 2272 * interrupt disreenable. It's said 2273 * that SCSI processor has more one 2274 * SRB need to do. 2275 */ 2276 trm_rewait_srb(dcb, srb); 2277 return; 2278 } else { 2279 #ifdef TRM_DEBUG 2280 printf("%s: driver stuffup at %s %d\n", 2281 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2282 #endif 2283 xs->error = XS_DRIVER_STUFFUP; 2284 break; 2285 } 2286 } 2287 else { 2288 /* 2289 * process initiator status...... 2290 * Adapter (initiator) status 2291 */ 2292 if (srb->hastat & H_OVER_UNDER_RUN) { 2293 srb->tastat = 0; 2294 /* Illegal length (over/under run) */ 2295 xs->error = XS_DRIVER_STUFFUP; 2296 } else if (srb->srbstat & PARITY_ERROR) { 2297 #ifdef TRM_DEBUG 2298 printf("%s: driver stuffup at %s %d\n", 2299 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2300 #endif 2301 /* Driver failed to perform operation */ 2302 xs->error = XS_DRIVER_STUFFUP; 2303 } else { /* No error */ 2304 srb->hastat = 0; 2305 srb->tastat = 0; 2306 xs->error = XS_NOERROR; 2307 /* there is no error, (sense is invalid) */ 2308 } 2309 } 2310 ckc_e: 2311 id = srb->xs->xs_periph->periph_target; 2312 lun = srb->xs->xs_periph->periph_lun; 2313 if (sc->devscan[id][lun]) { 2314 /* 2315 * if SCSI command in "scan devices" duty 2316 */ 2317 if (srb->cmd[0] == TEST_UNIT_READY) { 2318 /* SCSI command phase: test unit ready */ 2319 #ifdef TRM_DEBUG 2320 printf("srb->cmd[0] == TEST_UNIT_READY....\n"); 2321 #endif 2322 } else if (srb->cmd[0] == INQUIRY) { 2323 /* 2324 * SCSI command phase: inquiry scsi device data 2325 * (type,capacity,manufacture.... 2326 */ 2327 if (xs->error == XS_TIMEOUT) 2328 goto NO_DEV; 2329 2330 ptr = (struct scsipi_inquiry_data *)xs->data; 2331 bval = ptr->device & SID_TYPE; 2332 /* 2333 * #define T_NODEVICE 0x1f Unknown or no device type 2334 */ 2335 if (bval == T_NODEVICE) { 2336 NO_DEV: 2337 #ifdef TRM_DEBUG 2338 printf("trm_srb_done NO Device: "); 2339 printf("id= %d ,lun= %d\n", id, lun); 2340 #endif 2341 s = splbio(); 2342 /* 2343 * dcb Q link 2344 * move the head of DCB to temdcb 2345 */ 2346 tempdcb = sc->sc_linkdcb; 2347 2348 /* 2349 * search current DCB for pass link 2350 */ 2351 while (tempdcb->next != dcb) 2352 tempdcb = tempdcb->next; 2353 2354 /* 2355 * when the current DCB been found 2356 * than connect current DCB tail 2357 * to the DCB tail that before current DCB 2358 */ 2359 tempdcb->next = dcb->next; 2360 2361 /* 2362 * if there was only one DCB ,connect his 2363 * tail to his head 2364 */ 2365 if (sc->sc_linkdcb == dcb) 2366 sc->sc_linkdcb = tempdcb->next; 2367 2368 if (sc->sc_roundcb == dcb) 2369 sc->sc_roundcb = tempdcb->next; 2370 2371 /* 2372 * if no device than free this device DCB 2373 * free( dcb, M_DEVBUF); 2374 */ 2375 sc->devcnt--; 2376 #ifdef TRM_DEBUG 2377 printf("sc->devcnt=%d\n", sc->devcnt); 2378 #endif 2379 if (sc->devcnt == 0) { 2380 sc->sc_linkdcb = NULL; 2381 sc->sc_roundcb = NULL; 2382 } 2383 /* no device set scan device flag=0 */ 2384 sc->devscan[id][lun] = 0; 2385 i = 0; 2386 j = 0; 2387 while (i <= sc->maxid) { 2388 while (j < 8) { 2389 if (sc->devscan[i][j] == 1) { 2390 sc->devscan_end = 0; 2391 splx(s); 2392 goto exit; 2393 } else 2394 sc->devscan_end = 1; 2395 2396 j++; 2397 } 2398 j = 0; 2399 i++; 2400 } 2401 splx(s); 2402 } else { 2403 dcb->type = bval; 2404 if (bval == T_DIRECT || bval == T_OPTICAL) { 2405 if ((((ptr->version & 0x07) >= 2) || 2406 ((ptr->response_format & 0x0F) 2407 == 2)) && 2408 (ptr->flags3 & SID_CmdQue) && 2409 (dcb->tacfg & NTC_DO_TAG_QUEUING) && 2410 (dcb->tacfg & NTC_DO_DISCONNECT)) { 2411 dcb->maxcmd = sc->maxtag; 2412 dcb->mode |= EN_TAG_QUEUING; 2413 dcb->tagmask = 0; 2414 } else 2415 dcb->mode |= EN_ATN_STOP; 2416 } 2417 } 2418 /* srb->cmd[0] == INQUIRY */ 2419 } 2420 /* sc->devscan[id][lun] */ 2421 } 2422 exit: 2423 if (xs->datalen > 0) { 2424 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2425 srb->dmap->dm_mapsize, (xs->xs_control & XS_CTL_DATA_IN) ? 2426 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2427 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2428 } 2429 trm_release_srb(sc, dcb, srb); 2430 trm_wait_srb(sc); 2431 xs->xs_status |= XS_STS_DONE; 2432 /* Notify cmd done */ 2433 scsipi_done(xs); 2434 } 2435 2436 static void 2437 trm_release_srb(sc, dcb, srb) 2438 struct trm_softc *sc; 2439 struct trm_dcb *dcb; 2440 struct trm_srb *srb; 2441 { 2442 struct trm_srb *psrb; 2443 int s; 2444 2445 s = splbio(); 2446 if (srb == dcb->gosrb) 2447 dcb->gosrb = srb->next; 2448 else { 2449 psrb = dcb->gosrb; 2450 while (psrb->next != srb) 2451 psrb = psrb->next; 2452 2453 psrb->next = srb->next; 2454 if (srb == dcb->last_gosrb) 2455 dcb->last_gosrb = psrb; 2456 } 2457 srb->next = sc->sc_freesrb; 2458 sc->sc_freesrb = srb; 2459 dcb->gosrb_cnt--; 2460 splx(s); 2461 return; 2462 } 2463 2464 static void 2465 trm_doing_srb_done(sc) 2466 struct trm_softc *sc; 2467 { 2468 struct trm_dcb *dcb, *pdcb; 2469 struct trm_srb *psrb, *psrb2; 2470 struct scsipi_xfer *xs; 2471 int i; 2472 2473 dcb = sc->sc_linkdcb; 2474 if (dcb == NULL) 2475 return; 2476 2477 pdcb = dcb; 2478 do { 2479 psrb = pdcb->gosrb; 2480 for (i = 0; i < pdcb->gosrb_cnt; i++) { 2481 psrb2 = psrb->next; 2482 xs = psrb->xs; 2483 xs->error = XS_TIMEOUT; 2484 /* ReleaseSRB( dcb, srb ); */ 2485 psrb->next = sc->sc_freesrb; 2486 sc->sc_freesrb = psrb; 2487 scsipi_done(xs); 2488 psrb = psrb2; 2489 } 2490 pdcb->gosrb_cnt = 0;; 2491 pdcb->gosrb = NULL; 2492 pdcb->tagmask = 0; 2493 pdcb = pdcb->next; 2494 } 2495 while (pdcb != dcb); 2496 } 2497 2498 static void 2499 trm_reset_scsi_bus(sc) 2500 struct trm_softc *sc; 2501 { 2502 bus_space_tag_t iot = sc->sc_iot; 2503 bus_space_handle_t ioh = sc->sc_ioh; 2504 int s; 2505 2506 s = splbio(); 2507 2508 sc->sc_flag |= RESET_DEV; 2509 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2510 while ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2511 INT_SCSIRESET) == 0) 2512 ; 2513 2514 splx(s); 2515 } 2516 2517 static void 2518 trm_scsi_reset_detect(sc) 2519 struct trm_softc *sc; 2520 { 2521 bus_space_tag_t iot = sc->sc_iot; 2522 bus_space_handle_t ioh = sc->sc_ioh; 2523 int s; 2524 2525 #ifdef TRM_DEBUG 2526 printf("trm_scsi_reset_detect...............\n"); 2527 #endif 2528 DELAY(1000000); /* delay 1 sec */ 2529 2530 s = splbio(); 2531 2532 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2533 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2534 2535 if (sc->sc_flag & RESET_DEV) { 2536 sc->sc_flag |= RESET_DONE; 2537 } else { 2538 sc->sc_flag |= RESET_DETECT; 2539 trm_reset_device(sc); 2540 /* trm_doing_srb_done( sc ); ???? */ 2541 trm_recover_srb(sc); 2542 sc->sc_actdcb = NULL; 2543 sc->sc_flag = 0; 2544 trm_wait_srb(sc); 2545 } 2546 splx(s); 2547 } 2548 2549 static void 2550 trm_request_sense(sc, dcb, srb) 2551 struct trm_softc *sc; 2552 struct trm_dcb *dcb; 2553 struct trm_srb *srb; 2554 { 2555 struct scsipi_xfer *xs = srb->xs; 2556 struct scsipi_sense *ss; 2557 int error, lun = xs->xs_periph->periph_lun; 2558 2559 srb->flag |= AUTO_REQSENSE; 2560 memcpy(srb->tempcmd, srb->cmd, sizeof(srb->tempcmd)); 2561 2562 srb->templen = srb->buflen; 2563 srb->tempsg.address = srb->sgentry[0].address; 2564 srb->tempsg.length = srb->sgentry[0].length; 2565 2566 /* Status of initiator/target */ 2567 srb->hastat = 0; 2568 srb->tastat = 0; 2569 2570 ss = (struct scsipi_sense *)srb->cmd; 2571 ss->opcode = REQUEST_SENSE; 2572 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 2573 ss->unused[0] = ss->unused[1] = 0; 2574 ss->length = sizeof(struct scsipi_sense_data); 2575 ss->control = 0; 2576 2577 srb->buflen = sizeof(struct scsipi_sense_data); 2578 srb->sgcnt = 1; 2579 srb->sgindex = 0; 2580 srb->cmdlen = sizeof(struct scsipi_sense); 2581 2582 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2583 &xs->sense.scsi_sense, srb->buflen, NULL, 2584 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2585 printf("trm_request_sense: can not bus_dmamap_load()\n"); 2586 xs->error = XS_DRIVER_STUFFUP; 2587 return; 2588 } 2589 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2590 srb->buflen, BUS_DMASYNC_PREREAD); 2591 2592 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2593 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2594 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2595 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2596 2597 if (trm_start_scsi(sc, dcb, srb)) 2598 /* 2599 * If trm_start_scsi return 1: current interrupt status 2600 * is interrupt disreenable. It's said that SCSI processor 2601 * has more one SRB need to do. 2602 */ 2603 trm_rewait_srb(dcb, srb); 2604 } 2605 2606 static void 2607 trm_msgout_abort(sc, srb) 2608 struct trm_softc *sc; 2609 struct trm_srb *srb; 2610 { 2611 bus_space_tag_t iot = sc->sc_iot; 2612 bus_space_handle_t ioh = sc->sc_ioh; 2613 2614 srb->msgcnt = 1; 2615 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_SETATN); 2616 srb->dcb->flag &= ~ABORT_DEV_; 2617 } 2618 2619 /* 2620 * initialize the internal structures for a given DCB 2621 */ 2622 static void 2623 trm_init_dcb(sc, dcb, xs) 2624 struct trm_softc *sc; 2625 struct trm_dcb *dcb; 2626 struct scsipi_xfer *xs; 2627 { 2628 struct trm_nvram *eeprom; 2629 struct trm_dcb *tempdcb; 2630 int index, id, lun, s; 2631 2632 id = xs->xs_periph->periph_target; 2633 lun = xs->xs_periph->periph_lun; 2634 2635 s = splbio(); 2636 if (sc->sc_linkdcb == 0) { 2637 sc->sc_linkdcb = dcb; 2638 /* 2639 * RunRobin impersonate the role that let each device had 2640 * good proportion about SCSI command proceeding. 2641 */ 2642 sc->sc_roundcb = dcb; 2643 dcb->next = dcb; 2644 } else { 2645 tempdcb = sc->sc_linkdcb; 2646 /* search the last nod of DCB link */ 2647 while (tempdcb->next != sc->sc_linkdcb) 2648 tempdcb = tempdcb->next; 2649 2650 /* connect current DCB with last DCB tail */ 2651 tempdcb->next = dcb; 2652 /* connect current DCB tail to this DCB Q head */ 2653 dcb->next = sc->sc_linkdcb; 2654 } 2655 splx(s); 2656 2657 sc->devcnt++; 2658 dcb->id = id; 2659 dcb->lun = lun; 2660 dcb->waitsrb = NULL; 2661 dcb->gosrb = NULL; 2662 dcb->gosrb_cnt = 0; 2663 dcb->actsrb = NULL; 2664 dcb->tagmask = 0; 2665 dcb->maxcmd = 1; 2666 dcb->flag = 0; 2667 2668 eeprom = &sc->sc_eeprom; 2669 dcb->tacfg = eeprom->target[id].config0; 2670 /* 2671 * disconnect enable? 2672 */ 2673 dcb->idmsg = MSG_IDENTIFY(lun, dcb->tacfg & NTC_DO_DISCONNECT); 2674 /* 2675 * tag Qing enable? 2676 * wide nego, sync nego enable? 2677 */ 2678 dcb->synctl = 0; 2679 dcb->offset = 0; 2680 index = eeprom->target[id].period & 0x07; 2681 dcb->period = trm_clock_period[index]; 2682 dcb->mode = 0; 2683 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && (sc->sc_config & HCC_WIDE_CARD)) 2684 /* enable wide nego */ 2685 dcb->mode |= WIDE_NEGO_ENABLE; 2686 2687 if ((dcb->tacfg & NTC_DO_SYNC_NEGO) && (lun == 0 || sc->cur_offset > 0)) 2688 /* enable sync nego */ 2689 dcb->mode |= SYNC_NEGO_ENABLE; 2690 } 2691 2692 static void 2693 trm_link_srb(sc) 2694 struct trm_softc *sc; 2695 { 2696 struct trm_srb *srb; 2697 int i; 2698 2699 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 2700 M_DEVBUF, M_NOWAIT); 2701 if (sc->sc_srb == NULL) { 2702 printf("%s: can not allocate SRB\n", sc->sc_dev.dv_xname); 2703 return; 2704 } 2705 memset(sc->sc_srb, 0, sizeof(struct trm_srb) * TRM_MAX_SRB); 2706 2707 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++, srb++) { 2708 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 2709 srb->sgoffset = TRM_SG_SIZE * i; 2710 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 2711 /* 2712 * map all SRB space to SRB_array 2713 */ 2714 if (bus_dmamap_create(sc->sc_dmat, 2715 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 2716 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 2717 printf("%s: unable to create DMA transfer map...\n", 2718 sc->sc_dev.dv_xname); 2719 free(sc->sc_srb, M_DEVBUF); 2720 return; 2721 } 2722 if (i != TRM_MAX_SRB - 1) { 2723 /* 2724 * link all SRB 2725 */ 2726 srb->next = sc->sc_srb + 1; 2727 #ifdef TRM_DEBUG 2728 printf("srb->next = %8x ", (int) (sc->sc_srb + 1)); 2729 #endif 2730 } else { 2731 /* 2732 * load NULL to NextSRB of the last SRB 2733 */ 2734 srb->next = NULL; 2735 } 2736 #ifdef TRM_DEBUG 2737 printf("srb = %8x\n", (int) sc->sc_srb); 2738 #endif 2739 } 2740 return; 2741 } 2742 2743 /* 2744 * initialize the internal structures for a given SCSI host 2745 */ 2746 static void 2747 trm_init_sc(sc) 2748 struct trm_softc *sc; 2749 { 2750 bus_space_tag_t iot = sc->sc_iot; 2751 bus_space_handle_t ioh = sc->sc_ioh; 2752 struct trm_nvram *eeprom; 2753 struct trm_srb tempsrb; 2754 int i, j; 2755 2756 eeprom = &sc->sc_eeprom; 2757 sc->maxid = 7; 2758 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2759 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 2760 sc->sc_config |= HCC_WIDE_CARD; 2761 sc->maxid = 15; 2762 } 2763 if (eeprom->channel_cfg & NAC_POWERON_SCSI_RESET) 2764 sc->sc_config |= HCC_SCSI_RESET; 2765 2766 sc->sc_linkdcb = NULL; 2767 sc->sc_roundcb = NULL; 2768 sc->sc_actdcb = NULL; 2769 sc->sc_id = eeprom->scsi_id; 2770 sc->devcnt = 0; 2771 sc->maxtag = 2 << eeprom->max_tag; 2772 sc->sc_flag = 0; 2773 sc->devscan_end = 0; 2774 /* 2775 * link all device's SRB Q of this adapter 2776 */ 2777 trm_link_srb(sc); 2778 sc->sc_freesrb = sc->sc_srb; 2779 /* 2780 * temp SRB for Q tag used or abord command used 2781 */ 2782 sc->sc_tempsrb = &tempsrb; 2783 /* allocate DCB array for scan device */ 2784 for (i = 0; i <= sc->maxid; i++) 2785 if (sc->sc_id != i) 2786 for (j = 0; j < 8; j++) { 2787 sc->devscan[i][j] = 1; 2788 sc->devflag[i][j] = 0; 2789 sc->sc_dcb[i][j] = 2790 malloc(sizeof(struct trm_dcb), 2791 M_DEVBUF, M_WAITOK); 2792 } 2793 2794 #ifdef TRM_DEBUG 2795 printf("sizeof(struct trm_dcb)= %8x\n", sizeof(struct trm_dcb)); 2796 printf("sizeof(struct trm_softc)= %8x\n", sizeof(struct trm_softc)); 2797 printf("sizeof(struct trm_srb)= %8x\n", sizeof(struct trm_srb)); 2798 #endif 2799 sc->sc_adapter.adapt_dev = &sc->sc_dev; 2800 sc->sc_adapter.adapt_nchannels = 1; 2801 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 2802 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 2803 sc->sc_adapter.adapt_request = trm_scsipi_request; 2804 sc->sc_adapter.adapt_minphys = minphys; 2805 2806 sc->sc_channel.chan_adapter = &sc->sc_adapter; 2807 sc->sc_channel.chan_bustype = &scsi_bustype; 2808 sc->sc_channel.chan_channel = 0; 2809 sc->sc_channel.chan_ntargets = sc->maxid + 1; 2810 sc->sc_channel.chan_nluns = 8; 2811 sc->sc_channel.chan_id = sc->sc_id; 2812 } 2813 2814 /* 2815 * write sc_eeprom 128 bytes to seeprom 2816 */ 2817 static void 2818 trm_eeprom_write_all(sc, eeprom) 2819 struct trm_softc *sc; 2820 struct trm_nvram *eeprom; 2821 { 2822 bus_space_tag_t iot = sc->sc_iot; 2823 bus_space_handle_t ioh = sc->sc_ioh; 2824 u_int8_t *buf = (u_int8_t *)eeprom; 2825 u_int8_t addr; 2826 2827 /* Enable SEEPROM */ 2828 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2829 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2830 2831 /* 2832 * Write enable 2833 */ 2834 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2835 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2836 trm_wait_30us(); 2837 2838 for (addr = 0; addr < 128; addr++, buf++) 2839 trm_eeprom_set_data(sc, addr, *buf); 2840 2841 /* 2842 * Write disable 2843 */ 2844 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2845 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2846 trm_wait_30us(); 2847 2848 /* Disable SEEPROM */ 2849 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2850 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2851 } 2852 2853 /* 2854 * write one byte to seeprom 2855 */ 2856 static void 2857 trm_eeprom_set_data(sc, addr, data) 2858 struct trm_softc *sc; 2859 u_int8_t addr; 2860 u_int8_t data; 2861 { 2862 bus_space_tag_t iot = sc->sc_iot; 2863 bus_space_handle_t ioh = sc->sc_ioh; 2864 int i; 2865 u_int8_t send; 2866 2867 /* 2868 * Send write command & address 2869 */ 2870 trm_eeprom_write_cmd(sc, 0x05, addr); 2871 /* 2872 * Write data 2873 */ 2874 for (i = 0; i < 8; i++, data <<= 1) { 2875 send = NVR_SELECT; 2876 if (data & 0x80) /* Start from bit 7 */ 2877 send |= NVR_BITOUT; 2878 2879 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2880 trm_wait_30us(); 2881 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2882 trm_wait_30us(); 2883 } 2884 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2885 trm_wait_30us(); 2886 /* 2887 * Disable chip select 2888 */ 2889 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2890 trm_wait_30us(); 2891 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2892 trm_wait_30us(); 2893 /* 2894 * Wait for write ready 2895 */ 2896 for (;;) { 2897 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2898 NVR_SELECT | NVR_CLOCK); 2899 trm_wait_30us(); 2900 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2901 trm_wait_30us(); 2902 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2903 break; 2904 } 2905 /* 2906 * Disable chip select 2907 */ 2908 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2909 } 2910 2911 /* 2912 * read seeprom 128 bytes to sc_eeprom 2913 */ 2914 static void 2915 trm_eeprom_read_all(sc, eeprom) 2916 struct trm_softc *sc; 2917 struct trm_nvram *eeprom; 2918 { 2919 bus_space_tag_t iot = sc->sc_iot; 2920 bus_space_handle_t ioh = sc->sc_ioh; 2921 u_int8_t *buf = (u_int8_t *)eeprom; 2922 u_int8_t addr; 2923 2924 /* 2925 * Enable SEEPROM 2926 */ 2927 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2928 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2929 2930 for (addr = 0; addr < 128; addr++, buf++) 2931 *buf = trm_eeprom_get_data(sc, addr); 2932 2933 /* 2934 * Disable SEEPROM 2935 */ 2936 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2937 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2938 } 2939 2940 /* 2941 * read one byte from seeprom 2942 */ 2943 static u_int8_t 2944 trm_eeprom_get_data(sc, addr) 2945 struct trm_softc *sc; 2946 u_int8_t addr; 2947 { 2948 bus_space_tag_t iot = sc->sc_iot; 2949 bus_space_handle_t ioh = sc->sc_ioh; 2950 int i; 2951 u_int8_t read, data = 0; 2952 2953 /* 2954 * Send read command & address 2955 */ 2956 trm_eeprom_write_cmd(sc, 0x06, addr); 2957 2958 for (i = 0; i < 8; i++) { /* Read data */ 2959 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2960 NVR_SELECT | NVR_CLOCK); 2961 trm_wait_30us(); 2962 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2963 /* 2964 * Get data bit while falling edge 2965 */ 2966 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2967 data <<= 1; 2968 if (read & NVR_BITIN) 2969 data |= 1; 2970 2971 trm_wait_30us(); 2972 } 2973 /* 2974 * Disable chip select 2975 */ 2976 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2977 return (data); 2978 } 2979 2980 /* 2981 * write SB and Op Code into seeprom 2982 */ 2983 static void 2984 trm_eeprom_write_cmd(sc, cmd, addr) 2985 struct trm_softc *sc; 2986 u_int8_t cmd; 2987 u_int8_t addr; 2988 { 2989 bus_space_tag_t iot = sc->sc_iot; 2990 bus_space_handle_t ioh = sc->sc_ioh; 2991 int i; 2992 u_int8_t send; 2993 2994 /* Program SB+OP code */ 2995 for (i = 0; i < 3; i++, cmd <<= 1) { 2996 send = NVR_SELECT; 2997 if (cmd & 0x04) /* Start from bit 2 */ 2998 send |= NVR_BITOUT; 2999 3000 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 3001 trm_wait_30us(); 3002 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 3003 trm_wait_30us(); 3004 } 3005 3006 /* Program address */ 3007 for (i = 0; i < 7; i++, addr <<= 1) { 3008 send = NVR_SELECT; 3009 if (addr & 0x40) /* Start from bit 6 */ 3010 send |= NVR_BITOUT; 3011 3012 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 3013 trm_wait_30us(); 3014 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 3015 trm_wait_30us(); 3016 } 3017 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 3018 trm_wait_30us(); 3019 } 3020 3021 /* 3022 * read seeprom 128 bytes to sc_eeprom and check checksum. 3023 * If it is wrong, updated with default value. 3024 */ 3025 static void 3026 trm_check_eeprom(sc, eeprom) 3027 struct trm_softc *sc; 3028 struct trm_nvram *eeprom; 3029 { 3030 struct nvram_target *target; 3031 u_int16_t *ep; 3032 u_int16_t chksum; 3033 int i; 3034 3035 #ifdef TRM_DEBUG 3036 printf("\n trm_check_eeprom......\n"); 3037 #endif 3038 trm_eeprom_read_all(sc, eeprom); 3039 ep = (u_int16_t *)eeprom; 3040 chksum = 0; 3041 for (i = 0; i < 64; i++) 3042 chksum += le16toh(*ep++); 3043 3044 if (chksum != TRM_NVRAM_CKSUM) { 3045 #ifdef TRM_DEBUG 3046 printf("TRM_S1040 EEPROM Check Sum ERROR (load default).\n"); 3047 #endif 3048 /* 3049 * Checksum error, load default 3050 */ 3051 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 3052 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 3053 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 3054 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 3055 eeprom->subclass = 0x00; 3056 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 3057 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 3058 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 3059 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 3060 eeprom->reserved0 = 0x00; 3061 3062 for (i = 0, target = eeprom->target; 3063 i < TRM_MAX_TARGETS; 3064 i++, target++) { 3065 target->config0 = 0x77; 3066 target->period = 0x00; 3067 target->config2 = 0x00; 3068 target->config3 = 0x00; 3069 } 3070 3071 eeprom->scsi_id = 7; 3072 eeprom->channel_cfg = 0x0F; 3073 eeprom->delay_time = 0; 3074 eeprom->max_tag = 4; 3075 eeprom->reserved1 = 0x15; 3076 eeprom->boot_target = 0; 3077 eeprom->boot_lun = 0; 3078 eeprom->reserved2 = 0; 3079 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 3080 3081 chksum = 0; 3082 ep = (u_int16_t *)eeprom; 3083 for (i = 0; i < 63; i++) 3084 chksum += le16toh(*ep++); 3085 3086 chksum = TRM_NVRAM_CKSUM - chksum; 3087 eeprom->checksum0 = chksum & 0xFF; 3088 eeprom->checksum1 = chksum >> 8; 3089 3090 trm_eeprom_write_all(sc, eeprom); 3091 } 3092 } 3093 3094 /* 3095 * initialize the SCSI chip ctrl registers 3096 */ 3097 static void 3098 trm_init_adapter(sc) 3099 struct trm_softc *sc; 3100 { 3101 bus_space_tag_t iot = sc->sc_iot; 3102 bus_space_handle_t ioh = sc->sc_ioh; 3103 u_int8_t bval; 3104 3105 /* program configuration 0 */ 3106 bval = PHASELATCH | INITIATOR | BLOCKRST; 3107 if (sc->sc_config & HCC_PARITY) 3108 bval |= PARITYCHECK; 3109 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 3110 3111 /* program configuration 1 */ 3112 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 3113 ACTIVE_NEG | ACTIVE_NEGPLUS); 3114 3115 /* 250ms selection timeout */ 3116 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 3117 3118 /* Mask all the interrupt */ 3119 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 3120 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 3121 3122 /* Reset SCSI module */ 3123 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 3124 3125 /* program Host ID */ 3126 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 3127 3128 /* set ansynchronous transfer */ 3129 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 3130 3131 /* Trun LED control off */ 3132 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 3133 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 3134 3135 /* DMA config */ 3136 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 3137 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 3138 3139 /* Clear pending interrupt status */ 3140 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 3141 3142 /* Enable SCSI interrupt */ 3143 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 3144 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 3145 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 3146 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 3147 } 3148 3149 /* 3150 * initialize the internal structures for a given SCSI host 3151 */ 3152 static int 3153 trm_init(sc) 3154 struct trm_softc *sc; 3155 { 3156 bus_dma_segment_t seg; 3157 int error, rseg, all_sgsize; 3158 3159 /* 3160 * EEPROM CHECKSUM 3161 */ 3162 trm_check_eeprom(sc, &sc->sc_eeprom); 3163 /* 3164 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 3165 * allocate the space for all SCSI control blocks (SRB) for DMA memory 3166 */ 3167 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 3168 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 3169 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 3170 printf("%s: unable to allocate SCSI REQUEST BLOCKS, " 3171 "error = %d\n", sc->sc_dev.dv_xname, error); 3172 return (-1); 3173 } 3174 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 3175 all_sgsize, (caddr_t *) &sc->sc_sglist, 3176 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 3177 printf("%s: unable to map SCSI REQUEST BLOCKS, " 3178 "error = %d\n", sc->sc_dev.dv_xname, error); 3179 return (-1); 3180 } 3181 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 3182 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 3183 printf("%s: unable to create SRB DMA maps, " 3184 "error = %d\n", sc->sc_dev.dv_xname, error); 3185 return (-1); 3186 } 3187 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 3188 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 3189 printf("%s: unable to load SRB DMA maps, " 3190 "error = %d\n", sc->sc_dev.dv_xname, error); 3191 return (-1); 3192 } 3193 #ifdef TRM_DEBUG 3194 printf("\n\n%s: all_sgsize=%x\n", sc->sc_dev.dv_xname, all_sgsize); 3195 #endif 3196 memset(sc->sc_sglist, 0, all_sgsize); 3197 trm_init_sc(sc); 3198 trm_init_adapter(sc); 3199 trm_reset(sc); 3200 return (0); 3201 } 3202 3203 /* 3204 * attach and init a host adapter 3205 */ 3206 static void 3207 trm_attach(parent, self, aux) 3208 struct device *parent; 3209 struct device *self; 3210 void *aux; 3211 { 3212 struct pci_attach_args *const pa = aux; 3213 struct trm_softc *sc = (void *) self; 3214 bus_space_tag_t iot; /* bus space tag */ 3215 bus_space_handle_t ioh; /* bus space handle */ 3216 pci_intr_handle_t ih; 3217 pcireg_t command; 3218 const char *intrstr; 3219 3220 /* 3221 * These cards do not allow memory mapped accesses 3222 * pa_pc: chipset tag 3223 * pa_tag: pci tag 3224 */ 3225 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3226 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 3227 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 3228 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3229 pci_conf_write(pa->pa_pc, pa->pa_tag, 3230 PCI_COMMAND_STATUS_REG, command); 3231 } 3232 /* 3233 * mask for get correct base address of pci IO port 3234 */ 3235 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 3236 &iot, &ioh, NULL, NULL)) { 3237 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 3238 return; 3239 } 3240 /* 3241 * test checksum of eeprom..& initial "ACB" adapter control block... 3242 */ 3243 sc->sc_iot = iot; 3244 sc->sc_ioh = ioh; 3245 sc->sc_dmat = pa->pa_dmat; 3246 if (trm_init(sc)) { 3247 /* 3248 * Error during initialization! 3249 */ 3250 printf(": Error during initialization\n"); 3251 return; 3252 } 3253 /* 3254 * Now try to attach all the sub-devices 3255 */ 3256 if (sc->sc_config & HCC_WIDE_CARD) 3257 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 3258 "Ultra Wide SCSI Adapter\n"); 3259 else 3260 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 3261 "Ultra SCSI Adapter\n"); 3262 3263 printf("%s: Adapter ID=%d, Max tag number=%d, %d SCBs\n", 3264 sc->sc_dev.dv_xname, sc->sc_id, sc->maxtag, TRM_MAX_SRB); 3265 /* 3266 * Now tell the generic SCSI layer about our bus. 3267 * map and establish interrupt 3268 */ 3269 if (pci_intr_map(pa, &ih)) { 3270 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 3271 return; 3272 } 3273 intrstr = pci_intr_string(pa->pa_pc, ih); 3274 3275 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 3276 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 3277 if (intrstr != NULL) 3278 printf(" at %s", intrstr); 3279 printf("\n"); 3280 return; 3281 } 3282 if (intrstr != NULL) 3283 printf("%s: interrupting at %s\n", 3284 sc->sc_dev.dv_xname, intrstr); 3285 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 3286 } 3287 3288 /* 3289 * match pci device 3290 */ 3291 static int 3292 trm_probe(parent, match, aux) 3293 struct device *parent; 3294 struct cfdata *match; 3295 void *aux; 3296 { 3297 struct pci_attach_args *pa = aux; 3298 3299 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 3300 switch (PCI_PRODUCT(pa->pa_id)) { 3301 case PCI_PRODUCT_TEKRAM2_DC315: 3302 return (1); 3303 } 3304 return (0); 3305 } 3306
Indexes created Tue Sep 23 14:10:03 GMT 2025