trm.c revision 1.10
1 /* $NetBSD: trm.c,v 1.10 2002/04/05 18:27:55 bouyer Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.10 2002/04/05 18:27:55 bouyer Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsi_message.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/trmreg.h> 77 78 /* 79 * feature of chip set MAX value 80 */ 81 #define TRM_MAX_TARGETS 16 82 #define TRM_MAX_LUNS 8 83 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 #define TRM_MAX_SRB 32 /* XXX */ 85 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 #define TRM_MAX_OFFSET 15 87 #define TRM_MAX_PERIOD 125 88 89 /* 90 * Segment Entry 91 */ 92 struct trm_sg_entry { 93 u_int32_t address; 94 u_int32_t length; 95 }; 96 97 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 99 /* 100 ********************************************************************** 101 * The SEEPROM structure for TRM_S1040 102 ********************************************************************** 103 */ 104 struct nvram_target { 105 u_int8_t config0; /* Target configuration byte 0 */ 106 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 u_int8_t period; /* Target period */ 113 u_int8_t config2; /* Target configuration byte 2 */ 114 u_int8_t config3; /* Target configuration byte 3 */ 115 }; 116 117 struct trm_nvram { 118 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 u_int8_t subclass; /* 4 Sub Class */ 121 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 u_int8_t device_id[2]; /* 7,8 Device ID */ 123 u_int8_t reserved0; /* 9 Reserved */ 124 struct nvram_target target[TRM_MAX_TARGETS]; 125 /* 10,11,12,13 126 * 14,15,16,17 127 * .... 128 * 70,71,72,73 */ 129 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 u_int8_t channel_cfg; /* 75 Channel configuration */ 131 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 u_int8_t delay_time; /* 76 Power on delay time */ 137 u_int8_t max_tag; /* 77 Maximum tags */ 138 u_int8_t reserved1; /* 78 */ 139 u_int8_t boot_target; /* 79 */ 140 u_int8_t boot_lun; /* 80 */ 141 u_int8_t reserved2; /* 81 */ 142 u_int8_t reserved3[44]; /* 82,..125 */ 143 u_int8_t checksum0; /* 126 */ 144 u_int8_t checksum1; /* 127 */ 145 #define TRM_NVRAM_CKSUM 0x1234 146 }; 147 148 /* Nvram Initiater bits definition */ 149 #define MORE2_DRV 0x00000001 150 #define GREATER_1G 0x00000002 151 #define RST_SCSI_BUS 0x00000004 152 #define ACTIVE_NEGATION 0x00000008 153 #define NO_SEEK 0x00000010 154 #define LUN_CHECK 0x00000020 155 156 #define trm_eeprom_wait() DELAY(30) 157 158 /* 159 *----------------------------------------------------------------------- 160 * SCSI Request Block 161 *----------------------------------------------------------------------- 162 */ 163 struct trm_srb { 164 TAILQ_ENTRY(trm_srb) next; 165 166 struct trm_sg_entry *sgentry; 167 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 bus_dmamap_t dmap; 169 bus_size_t sgoffset; /* Xfer buf offset */ 170 171 u_int32_t buflen; /* Total xfer length */ 172 u_int32_t sgaddr; /* SGList physical starting address */ 173 174 int sgcnt; 175 int sgindex; 176 177 int hastat; /* Host Adapter Status */ 178 #define H_STATUS_GOOD 0x00 179 #define H_SEL_TIMEOUT 0x11 180 #define H_OVER_UNDER_RUN 0x12 181 #define H_UNEXP_BUS_FREE 0x13 182 #define H_TARGET_PHASE_F 0x14 183 #define H_INVALID_CCB_OP 0x16 184 #define H_LINK_CCB_BAD 0x17 185 #define H_BAD_TARGET_DIR 0x18 186 #define H_DUPLICATE_CCB 0x19 187 #define H_BAD_CCB_OR_SG 0x1A 188 #define H_ABORT 0xFF 189 int tastat; /* Target SCSI Status Byte */ 190 int flag; /* SRBFlag */ 191 #define AUTO_REQSENSE 0x0001 192 #define PARITY_ERROR 0x0002 193 #define SRB_TIMEOUT 0x0004 194 195 int cmdlen; /* SCSI command length */ 196 u_int8_t cmd[12]; /* SCSI command */ 197 198 u_int8_t tag[2]; 199 }; 200 201 /* 202 * some info about each target and lun on the SCSI bus 203 */ 204 struct trm_linfo { 205 int used; /* number of slots in use */ 206 int avail; /* where to start scanning */ 207 int busy; /* lun in use */ 208 struct trm_srb *untagged; 209 struct trm_srb *queued[TRM_MAX_TAG]; 210 }; 211 212 struct trm_tinfo { 213 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 #define SYNC_NEGO_ENABLE 0x0001 215 #define SYNC_NEGO_DOING 0x0002 216 #define SYNC_NEGO_DONE 0x0004 217 #define WIDE_NEGO_ENABLE 0x0008 218 #define WIDE_NEGO_DOING 0x0010 219 #define WIDE_NEGO_DONE 0x0020 220 #define USE_TAG_QUEUING 0x0040 221 #define NO_RESELECT 0x0080 222 struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 224 u_int8_t config0; /* Target Config */ 225 u_int8_t period; /* Max Period for nego. */ 226 u_int8_t synctl; /* Sync control for reg. */ 227 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 }; 229 230 /* 231 *----------------------------------------------------------------------- 232 * Adapter Control Block 233 *----------------------------------------------------------------------- 234 */ 235 struct trm_softc { 236 struct device sc_dev; 237 238 bus_space_tag_t sc_iot; 239 bus_space_handle_t sc_ioh; 240 bus_dma_tag_t sc_dmat; 241 bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 243 struct trm_srb *sc_actsrb; 244 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 246 TAILQ_HEAD(, trm_srb) sc_freesrb, 247 sc_readysrb; 248 struct trm_srb *sc_srb; /* SRB array */ 249 250 struct trm_sg_entry *sc_sglist; 251 252 int sc_maxid; 253 /* 254 * Link to the generic SCSI driver 255 */ 256 struct scsipi_channel sc_channel; 257 struct scsipi_adapter sc_adapter; 258 259 int sc_id; /* Adapter SCSI Target ID */ 260 261 int sc_state; /* SRB State */ 262 #define TRM_IDLE 0 263 #define TRM_WAIT 1 264 #define TRM_READY 2 265 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 #define TRM_MSGIN 4 267 #define TRM_EXTEND_MSGIN 5 268 #define TRM_COMMAND 6 269 #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 #define TRM_DISCONNECTED 8 271 #define TRM_DATA_XFER 9 272 #define TRM_XFERPAD 10 273 #define TRM_STATUS 11 274 #define TRM_COMPLETED 12 275 #define TRM_ABORT_SENT 13 276 #define TRM_UNEXPECT_RESEL 14 277 278 int sc_phase; /* SCSI phase */ 279 int sc_config; 280 #define HCC_WIDE_CARD 0x01 281 #define HCC_SCSI_RESET 0x02 282 #define HCC_PARITY 0x04 283 #define HCC_AUTOTERM 0x08 284 #define HCC_LOW8TERM 0x10 285 #define HCC_UP8TERM 0x20 286 287 int sc_flag; 288 #define RESET_DEV 0x01 289 #define RESET_DETECT 0x02 290 #define RESET_DONE 0x04 291 #define WAIT_TAGMSG 0x08 /* XXX */ 292 293 int sc_msgcnt; 294 295 int resel_target; /* XXX */ 296 int resel_lun; /* XXX */ 297 298 u_int8_t *sc_msg; 299 u_int8_t sc_msgbuf[6]; 300 }; 301 302 /* 303 * SCSI Status codes not defined in scsi_all.h 304 */ 305 #define SCSI_COND_MET 0x04 /* Condition Met */ 306 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 311 static int trm_probe(struct device *, struct cfdata *, void *); 312 static void trm_attach(struct device *, struct device *, void *); 313 314 static int trm_init(struct trm_softc *); 315 316 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 void *); 318 static void trm_update_xfer_mode(struct trm_softc *, int); 319 static void trm_sched(struct trm_softc *); 320 static int trm_select(struct trm_softc *, struct trm_srb *); 321 static void trm_reset(struct trm_softc *); 322 static void trm_timeout(void *); 323 static int trm_intr(void *); 324 325 static void trm_dataout_phase0(struct trm_softc *, int); 326 static void trm_datain_phase0(struct trm_softc *, int); 327 static void trm_status_phase0(struct trm_softc *); 328 static void trm_msgin_phase0(struct trm_softc *); 329 static void trm_command_phase1(struct trm_softc *); 330 static void trm_status_phase1(struct trm_softc *); 331 static void trm_msgout_phase1(struct trm_softc *); 332 static void trm_msgin_phase1(struct trm_softc *); 333 334 static void trm_dataio_xfer(struct trm_softc *, int); 335 static void trm_disconnect(struct trm_softc *); 336 static void trm_reselect(struct trm_softc *); 337 static void trm_done(struct trm_softc *, struct trm_srb *); 338 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 341 static void trm_scsi_reset_detect(struct trm_softc *); 342 static void trm_reset_scsi_bus(struct trm_softc *); 343 344 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 351 struct cfattach trm_ca = { 352 sizeof(struct trm_softc), trm_probe, trm_attach 353 }; 354 355 /* real period: */ 356 static const u_int8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(parent, match, aux) 370 struct device *parent; 371 struct cfdata *match; 372 void *aux; 373 { 374 struct pci_attach_args *pa = aux; 375 376 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 377 switch (PCI_PRODUCT(pa->pa_id)) { 378 case PCI_PRODUCT_TEKRAM2_DC315: 379 return (1); 380 } 381 return (0); 382 } 383 384 /* 385 * attach and init a host adapter 386 */ 387 static void 388 trm_attach(parent, self, aux) 389 struct device *parent; 390 struct device *self; 391 void *aux; 392 { 393 struct pci_attach_args *const pa = aux; 394 struct trm_softc *sc = (struct trm_softc *)self; 395 bus_space_tag_t iot; 396 bus_space_handle_t ioh; 397 pci_intr_handle_t ih; 398 pcireg_t command; 399 const char *intrstr; 400 401 /* 402 * These cards do not allow memory mapped accesses 403 * pa_pc: chipset tag 404 * pa_tag: pci tag 405 */ 406 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 407 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 408 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 409 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 410 pci_conf_write(pa->pa_pc, pa->pa_tag, 411 PCI_COMMAND_STATUS_REG, command); 412 } 413 /* 414 * mask for get correct base address of pci IO port 415 */ 416 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 417 &iot, &ioh, NULL, NULL)) { 418 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 419 return; 420 } 421 /* 422 * test checksum of eeprom.. & initialize softc... 423 */ 424 sc->sc_iot = iot; 425 sc->sc_ioh = ioh; 426 sc->sc_dmat = pa->pa_dmat; 427 428 if (trm_init(sc) != 0) { 429 /* 430 * Error during initialization! 431 */ 432 printf(": Error during initialization\n"); 433 return; 434 } 435 /* 436 * Now try to attach all the sub-devices 437 */ 438 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 439 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 440 "Ultra Wide SCSI Adapter\n"); 441 else 442 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 443 "Ultra SCSI Adapter\n"); 444 445 /* 446 * Now tell the generic SCSI layer about our bus. 447 * map and establish interrupt 448 */ 449 if (pci_intr_map(pa, &ih)) { 450 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 451 return; 452 } 453 intrstr = pci_intr_string(pa->pa_pc, ih); 454 455 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 456 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 457 if (intrstr != NULL) 458 printf(" at %s", intrstr); 459 printf("\n"); 460 return; 461 } 462 if (intrstr != NULL) 463 printf("%s: interrupting at %s\n", 464 sc->sc_dev.dv_xname, intrstr); 465 466 sc->sc_adapter.adapt_dev = &sc->sc_dev; 467 sc->sc_adapter.adapt_nchannels = 1; 468 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 469 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 470 sc->sc_adapter.adapt_request = trm_scsipi_request; 471 sc->sc_adapter.adapt_minphys = minphys; 472 473 sc->sc_channel.chan_adapter = &sc->sc_adapter; 474 sc->sc_channel.chan_bustype = &scsi_bustype; 475 sc->sc_channel.chan_channel = 0; 476 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 477 sc->sc_channel.chan_nluns = 8; 478 sc->sc_channel.chan_id = sc->sc_id; 479 480 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 481 } 482 483 /* 484 * initialize the internal structures for a given SCSI host 485 */ 486 static int 487 trm_init(sc) 488 struct trm_softc *sc; 489 { 490 bus_space_tag_t iot = sc->sc_iot; 491 bus_space_handle_t ioh = sc->sc_ioh; 492 bus_dma_segment_t seg; 493 struct trm_nvram eeprom; 494 struct trm_srb *srb; 495 struct trm_tinfo *ti; 496 struct nvram_target *tconf; 497 int error, rseg, all_sgsize; 498 int i, target; 499 u_int8_t bval; 500 501 DPRINTF(("\n")); 502 503 /* 504 * allocate the space for all SCSI control blocks (SRB) for DMA memory 505 */ 506 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 507 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 508 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 509 printf(": unable to allocate SCSI REQUEST BLOCKS, " 510 "error = %d\n", error); 511 return (1); 512 } 513 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 514 all_sgsize, (caddr_t *) &sc->sc_sglist, 515 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 516 printf(": unable to map SCSI REQUEST BLOCKS, " 517 "error = %d\n", error); 518 return (1); 519 } 520 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 521 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 522 printf(": unable to create SRB DMA maps, " 523 "error = %d\n", error); 524 return (1); 525 } 526 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 527 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 528 printf(": unable to load SRB DMA maps, " 529 "error = %d\n", error); 530 return (1); 531 } 532 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 533 memset(sc->sc_sglist, 0, all_sgsize); 534 535 /* 536 * EEPROM CHECKSUM 537 */ 538 trm_check_eeprom(sc, &eeprom); 539 540 sc->sc_maxid = 7; 541 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 542 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 543 sc->sc_config |= HCC_WIDE_CARD; 544 sc->sc_maxid = 15; 545 } 546 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 547 sc->sc_config |= HCC_SCSI_RESET; 548 549 sc->sc_actsrb = NULL; 550 sc->sc_id = eeprom.scsi_id; 551 sc->sc_flag = 0; 552 553 /* 554 * initialize and link all device's SRB queues of this adapter 555 */ 556 TAILQ_INIT(&sc->sc_freesrb); 557 TAILQ_INIT(&sc->sc_readysrb); 558 559 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 560 M_DEVBUF, M_NOWAIT|M_ZERO); 561 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 562 if (sc->sc_srb == NULL) { 563 printf(": can not allocate SRB\n"); 564 return (1); 565 } 566 567 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 568 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 569 srb->sgoffset = TRM_SG_SIZE * i; 570 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 571 /* 572 * map all SRB space to SRB_array 573 */ 574 if (bus_dmamap_create(sc->sc_dmat, 575 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 576 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 577 printf(": unable to create DMA transfer map...\n"); 578 free(sc->sc_srb, M_DEVBUF); 579 return (1); 580 } 581 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 582 srb++; 583 } 584 585 /* 586 * initialize all target info structures 587 */ 588 for (target = 0; target < TRM_MAX_TARGETS; target++) { 589 ti = &sc->sc_tinfo[target]; 590 ti->synctl = 0; 591 ti->offset = 0; 592 tconf = &eeprom.target[target]; 593 ti->config0 = tconf->config0; 594 ti->period = trm_clock_period[tconf->period & 0x07]; 595 ti->flag = 0; 596 if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 597 (sc->sc_config & HCC_WIDE_CARD) != 0) 598 ti->flag |= WIDE_NEGO_ENABLE; 599 if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 600 ti->flag |= SYNC_NEGO_ENABLE; 601 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 602 #ifdef notyet 603 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 604 ti->flag |= USE_TAG_QUEUING; 605 #endif 606 } else 607 ti->flag |= NO_RESELECT; 608 609 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 610 target, ti->config0, ti->period)); 611 DPRINTF((", flag = 0x%02x\n", ti->flag)); 612 } 613 614 /* program configuration 0 */ 615 bval = PHASELATCH | INITIATOR | BLOCKRST; 616 if ((sc->sc_config & HCC_PARITY) != 0) 617 bval |= PARITYCHECK; 618 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 619 620 /* program configuration 1 */ 621 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 622 ACTIVE_NEG | ACTIVE_NEGPLUS); 623 624 /* 250ms selection timeout */ 625 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 626 627 /* Mask all interrupts */ 628 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 629 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 630 631 /* Reset SCSI module */ 632 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 633 634 /* program Host ID */ 635 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 636 637 /* set asynchronous transfer */ 638 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 639 640 /* Turn LED control off */ 641 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 642 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 643 644 /* DMA config */ 645 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 646 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 647 648 /* Clear pending interrupt status */ 649 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 650 651 /* Enable SCSI interrupt */ 652 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 653 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 654 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 655 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 656 657 trm_reset(sc); 658 659 return (0); 660 } 661 662 /* 663 * enqueues a SCSI command 664 * called by the higher level SCSI driver 665 */ 666 static void 667 trm_scsipi_request(chan, req, arg) 668 struct scsipi_channel *chan; 669 scsipi_adapter_req_t req; 670 void *arg; 671 { 672 bus_space_tag_t iot; 673 bus_space_handle_t ioh; 674 struct trm_softc *sc; 675 struct trm_srb *srb; 676 struct scsipi_xfer *xs; 677 int error, i, target, lun, s; 678 679 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 680 iot = sc->sc_iot; 681 ioh = sc->sc_ioh; 682 683 switch (req) { 684 case ADAPTER_REQ_RUN_XFER: 685 xs = arg; 686 target = xs->xs_periph->periph_target; 687 lun = xs->xs_periph->periph_lun; 688 DPRINTF(("trm_scsipi_request.....\n")); 689 DPRINTF(("target= %d lun= %d\n", target, lun)); 690 if (xs->xs_control & XS_CTL_RESET) { 691 trm_reset(sc); 692 xs->error = XS_NOERROR | XS_RESET; 693 return; 694 } 695 if (xs->xs_status & XS_STS_DONE) { 696 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 697 xs->xs_status &= ~XS_STS_DONE; 698 } 699 700 s = splbio(); 701 702 /* Get SRB */ 703 srb = TAILQ_FIRST(&sc->sc_freesrb); 704 if (srb != NULL) { 705 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 706 } else { 707 xs->error = XS_RESOURCE_SHORTAGE; 708 scsipi_done(xs); 709 splx(s); 710 return; 711 } 712 713 srb->xs = xs; 714 srb->cmdlen = xs->cmdlen; 715 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 716 717 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 718 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 719 xs->data, xs->datalen, NULL, 720 ((xs->xs_control & XS_CTL_NOSLEEP) ? 721 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 722 BUS_DMA_STREAMING | 723 ((xs->xs_control & XS_CTL_DATA_IN) ? 724 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 725 printf("%s: DMA transfer map unable to load, " 726 "error = %d\n", sc->sc_dev.dv_xname, error); 727 xs->error = XS_DRIVER_STUFFUP; 728 /* 729 * free SRB 730 */ 731 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 732 splx(s); 733 return; 734 } 735 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 736 srb->dmap->dm_mapsize, 737 (xs->xs_control & XS_CTL_DATA_IN) ? 738 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 739 740 /* Set up the scatter gather list */ 741 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 742 srb->sgentry[i].address = 743 htole32(srb->dmap->dm_segs[i].ds_addr); 744 srb->sgentry[i].length = 745 htole32(srb->dmap->dm_segs[i].ds_len); 746 } 747 srb->buflen = xs->datalen; 748 srb->sgcnt = srb->dmap->dm_nsegs; 749 } else { 750 srb->sgentry[0].address = 0; 751 srb->sgentry[0].length = 0; 752 srb->buflen = 0; 753 srb->sgcnt = 0; 754 } 755 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 756 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 757 758 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 759 760 srb->sgindex = 0; 761 srb->hastat = 0; 762 srb->tastat = 0; 763 srb->flag = 0; 764 765 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 766 if (sc->sc_actsrb == NULL) 767 trm_sched(sc); 768 splx(s); 769 770 if ((xs->xs_control & XS_CTL_POLL) != 0) { 771 int timeout = xs->timeout; 772 773 s = splbio(); 774 do { 775 while (--timeout) { 776 DELAY(1000); 777 if (bus_space_read_2(iot, ioh, 778 TRM_SCSI_STATUS) & SCSIINTERRUPT) 779 break; 780 } 781 if (timeout == 0) { 782 trm_timeout(srb); 783 break; 784 } else 785 trm_intr(sc); 786 } while ((xs->xs_status & XS_STS_DONE) == 0); 787 splx(s); 788 } 789 return; 790 791 case ADAPTER_REQ_GROW_RESOURCES: 792 /* XXX Not supported. */ 793 return; 794 795 case ADAPTER_REQ_SET_XFER_MODE: 796 { 797 struct trm_tinfo *ti; 798 struct scsipi_xfer_mode *xm; 799 800 xm = arg; 801 ti = &sc->sc_tinfo[xm->xm_target]; 802 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 803 804 #ifdef notyet 805 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 806 ti->flag |= USE_TAG_QUEUING; 807 else 808 #endif 809 ti->flag &= ~USE_TAG_QUEUING; 810 811 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 812 ti->flag |= WIDE_NEGO_ENABLE; 813 ti->flag &= ~WIDE_NEGO_DONE; 814 } 815 816 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 817 ti->flag |= SYNC_NEGO_ENABLE; 818 ti->flag &= ~SYNC_NEGO_DONE; 819 ti->period = trm_clock_period[0]; 820 } 821 822 /* 823 * If we're not going to negotiate, send the 824 * notification now, since it won't happen later. 825 */ 826 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 827 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 828 trm_update_xfer_mode(sc, xm->xm_target); 829 830 return; 831 } 832 } 833 } 834 835 static void 836 trm_update_xfer_mode(sc, target) 837 struct trm_softc *sc; 838 int target; 839 { 840 struct scsipi_xfer_mode xm; 841 struct trm_tinfo *ti; 842 843 ti = &sc->sc_tinfo[target]; 844 xm.xm_target = target; 845 xm.xm_mode = 0; 846 xm.xm_period = 0; 847 xm.xm_offset = 0; 848 849 if ((ti->synctl & WIDE_SYNC) != 0) 850 xm.xm_mode |= PERIPH_CAP_WIDE16; 851 852 if (ti->period > 0) { 853 xm.xm_mode |= PERIPH_CAP_SYNC; 854 xm.xm_period = ti->period; 855 xm.xm_offset = ti->offset; 856 } 857 858 #ifdef notyet 859 if ((ti->flag & USE_TAG_QUEUING) != 0) 860 xm.xm_mode |= PERIPH_CAP_TQING; 861 #endif 862 863 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 864 } 865 866 static void 867 trm_sched(sc) 868 struct trm_softc *sc; 869 { 870 struct trm_srb *srb; 871 struct scsipi_periph *periph; 872 struct trm_tinfo *ti; 873 struct trm_linfo *li; 874 int s, lun, tag; 875 876 DPRINTF(("trm_sched...\n")); 877 878 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 879 periph = srb->xs->xs_periph; 880 ti = &sc->sc_tinfo[periph->periph_target]; 881 lun = periph->periph_lun; 882 883 /* select type of tag for this command */ 884 if ((ti->flag & NO_RESELECT) != 0 || 885 (ti->flag & USE_TAG_QUEUING) == 0 || 886 (srb->flag & AUTO_REQSENSE) != 0 || 887 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 888 tag = 0; 889 else 890 tag = srb->xs->xs_tag_type; 891 #if 0 892 /* XXX use tags for polled commands? */ 893 if (srb->xs->xs_control & XS_CTL_POLL) 894 tag = 0; 895 #endif 896 897 s = splbio(); 898 li = ti->linfo[lun]; 899 if (li == NULL) { 900 /* initialize lun info */ 901 if ((li = malloc(sizeof(*li), M_DEVBUF, 902 M_NOWAIT|M_ZERO)) == NULL) { 903 splx(s); 904 continue; 905 } 906 ti->linfo[lun] = li; 907 } 908 909 if (tag == 0) { 910 /* try to issue this srb as an un-tagged command */ 911 if (li->untagged == NULL) 912 li->untagged = srb; 913 } 914 if (li->untagged != NULL) { 915 tag = 0; 916 if (li->busy != 1 && li->used == 0) { 917 /* we need to issue the untagged command now */ 918 srb = li->untagged; 919 periph = srb->xs->xs_periph; 920 } else { 921 /* not ready yet */ 922 splx(s); 923 continue; 924 } 925 } 926 srb->tag[0] = tag; 927 if (tag != 0) { 928 li->queued[srb->xs->xs_tag_id] = srb; 929 srb->tag[1] = srb->xs->xs_tag_id; 930 li->used++; 931 } 932 933 if (li->untagged != NULL && li->busy != 1) { 934 li->busy = 1; 935 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 936 sc->sc_actsrb = srb; 937 trm_select(sc, srb); 938 splx(s); 939 break; 940 } 941 if (li->untagged == NULL && tag != 0) { 942 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 943 sc->sc_actsrb = srb; 944 trm_select(sc, srb); 945 splx(s); 946 break; 947 } else 948 splx(s); 949 } 950 } 951 952 static int 953 trm_select(sc, srb) 954 struct trm_softc *sc; 955 struct trm_srb *srb; 956 { 957 bus_space_tag_t iot = sc->sc_iot; 958 bus_space_handle_t ioh = sc->sc_ioh; 959 struct scsipi_periph *periph = srb->xs->xs_periph; 960 int target = periph->periph_target; 961 int lun = periph->periph_lun; 962 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 963 u_int8_t scsicmd; 964 965 DPRINTF(("trm_select.....\n")); 966 967 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 968 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 969 trm_timeout, srb); 970 } 971 972 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 973 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 974 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 975 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 976 /* Flush FIFO */ 977 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 978 DELAY(10); 979 980 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 981 982 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 983 984 if (((ti->flag & WIDE_NEGO_ENABLE) && 985 (ti->flag & WIDE_NEGO_DONE) == 0) || 986 ((ti->flag & SYNC_NEGO_ENABLE) && 987 (ti->flag & SYNC_NEGO_DONE) == 0)) { 988 sc->sc_state = TRM_MSGOUT; 989 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 990 MSG_IDENTIFY(lun, 0)); 991 bus_space_write_multi_1(iot, ioh, 992 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 993 /* it's important for atn stop */ 994 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 995 DO_DATALATCH | DO_HWRESELECT); 996 /* SCSI command */ 997 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 998 DPRINTF(("select with SEL_ATNSTOP\n")); 999 return (0); 1000 } 1001 1002 if (srb->tag[0] != 0) { 1003 /* Send identify message */ 1004 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1005 MSG_IDENTIFY(lun, 1)); 1006 /* Send Tag id */ 1007 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1008 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1009 scsicmd = SCMD_SEL_ATN3; 1010 DPRINTF(("select with SEL_ATN3\n")); 1011 } else { 1012 /* Send identify message */ 1013 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1014 MSG_IDENTIFY(lun, 1015 (ti->flag & NO_RESELECT) == 0 && 1016 (srb->flag & AUTO_REQSENSE) == 0 && 1017 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1018 scsicmd = SCMD_SEL_ATN; 1019 DPRINTF(("select with SEL_ATN\n")); 1020 } 1021 sc->sc_state = TRM_START; 1022 1023 /* 1024 * Send CDB ..command block... 1025 */ 1026 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1027 1028 /* 1029 * If trm_select returns 0: current interrupt status 1030 * is interrupt enable. It's said that SCSI processor is 1031 * unoccupied. 1032 */ 1033 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1034 /* SCSI command */ 1035 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1036 return (0); 1037 } 1038 1039 /* 1040 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1041 */ 1042 static void 1043 trm_reset(sc) 1044 struct trm_softc *sc; 1045 { 1046 bus_space_tag_t iot = sc->sc_iot; 1047 bus_space_handle_t ioh = sc->sc_ioh; 1048 int s; 1049 1050 DPRINTF(("trm_reset.........\n")); 1051 1052 s = splbio(); 1053 1054 /* disable SCSI and DMA interrupt */ 1055 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1056 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1057 1058 trm_reset_scsi_bus(sc); 1059 DELAY(100000); 1060 1061 /* Enable SCSI interrupt */ 1062 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1063 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1064 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1065 1066 /* Enable DMA interrupt */ 1067 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1068 1069 /* Clear DMA FIFO */ 1070 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1071 1072 /* Clear SCSI FIFO */ 1073 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1074 1075 sc->sc_actsrb = NULL; 1076 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1077 1078 splx(s); 1079 } 1080 1081 static void 1082 trm_timeout(arg) 1083 void *arg; 1084 { 1085 struct trm_srb *srb = (struct trm_srb *)arg; 1086 struct scsipi_xfer *xs = srb->xs; 1087 struct scsipi_periph *periph = xs->xs_periph; 1088 struct trm_softc *sc; 1089 int s; 1090 1091 if (xs == NULL) 1092 printf("trm_timeout called with xs == NULL\n"); 1093 1094 else { 1095 scsipi_printaddr(xs->xs_periph); 1096 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1097 } 1098 1099 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1100 1101 trm_reset_scsi_bus(sc); 1102 s = splbio(); 1103 srb->flag |= SRB_TIMEOUT; 1104 trm_done(sc, srb); 1105 /* XXX needs more.. */ 1106 splx(s); 1107 } 1108 1109 /* 1110 * Catch an interrupt from the adapter 1111 * Process pending device interrupts. 1112 */ 1113 static int 1114 trm_intr(arg) 1115 void *arg; 1116 { 1117 bus_space_tag_t iot; 1118 bus_space_handle_t ioh; 1119 struct trm_softc *sc; 1120 struct trm_srb *srb; 1121 int intstat, stat; 1122 1123 DPRINTF(("trm_intr......\n")); 1124 sc = (struct trm_softc *)arg; 1125 if (sc == NULL) 1126 return (0); 1127 1128 iot = sc->sc_iot; 1129 ioh = sc->sc_ioh; 1130 1131 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1132 if ((stat & SCSIINTERRUPT) == 0) 1133 return (0); 1134 1135 DPRINTF(("stat = %04x, ", stat)); 1136 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1137 1138 DPRINTF(("intstat=%02x, ", intstat)); 1139 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1140 DPRINTF(("\n")); 1141 trm_disconnect(sc); 1142 return (1); 1143 } 1144 if (intstat & INT_RESELECTED) { 1145 DPRINTF(("\n")); 1146 trm_reselect(sc); 1147 return (1); 1148 } 1149 if (intstat & INT_SCSIRESET) { 1150 DPRINTF(("\n")); 1151 trm_scsi_reset_detect(sc); 1152 return (1); 1153 } 1154 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1155 srb = sc->sc_actsrb; 1156 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1157 sc->sc_phase, sc->sc_state)); 1158 /* 1159 * software sequential machine 1160 */ 1161 1162 /* 1163 * call phase0 functions... "phase entry" handle 1164 * every phase before start transfer 1165 */ 1166 switch (sc->sc_phase) { 1167 case PH_DATA_OUT: 1168 trm_dataout_phase0(sc, stat); 1169 break; 1170 case PH_DATA_IN: 1171 trm_datain_phase0(sc, stat); 1172 break; 1173 case PH_COMMAND: 1174 break; 1175 case PH_STATUS: 1176 trm_status_phase0(sc); 1177 stat = PH_BUS_FREE; 1178 break; 1179 case PH_MSG_OUT: 1180 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1181 sc->sc_state == TRM_ABORT_SENT) 1182 stat = PH_BUS_FREE; 1183 break; 1184 case PH_MSG_IN: 1185 trm_msgin_phase0(sc); 1186 stat = PH_BUS_FREE; 1187 break; 1188 case PH_BUS_FREE: 1189 break; 1190 default: 1191 printf("%s: unexpected phase in trm_intr() phase0\n", 1192 sc->sc_dev.dv_xname); 1193 break; 1194 } 1195 1196 sc->sc_phase = stat & PHASEMASK; 1197 1198 switch (sc->sc_phase) { 1199 case PH_DATA_OUT: 1200 trm_dataio_xfer(sc, XFERDATAOUT); 1201 break; 1202 case PH_DATA_IN: 1203 trm_dataio_xfer(sc, XFERDATAIN); 1204 break; 1205 case PH_COMMAND: 1206 trm_command_phase1(sc); 1207 break; 1208 case PH_STATUS: 1209 trm_status_phase1(sc); 1210 break; 1211 case PH_MSG_OUT: 1212 trm_msgout_phase1(sc); 1213 break; 1214 case PH_MSG_IN: 1215 trm_msgin_phase1(sc); 1216 break; 1217 case PH_BUS_FREE: 1218 break; 1219 default: 1220 printf("%s: unexpected phase in trm_intr() phase1\n", 1221 sc->sc_dev.dv_xname); 1222 break; 1223 } 1224 1225 return (1); 1226 } 1227 return (0); 1228 } 1229 1230 static void 1231 trm_msgout_phase1(sc) 1232 struct trm_softc *sc; 1233 { 1234 bus_space_tag_t iot = sc->sc_iot; 1235 bus_space_handle_t ioh = sc->sc_ioh; 1236 struct trm_srb *srb; 1237 struct scsipi_periph *periph; 1238 struct trm_tinfo *ti; 1239 1240 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1241 1242 srb = sc->sc_actsrb; 1243 1244 /* message out phase */ 1245 if (srb != NULL) { 1246 periph = srb->xs->xs_periph; 1247 ti = &sc->sc_tinfo[periph->periph_target]; 1248 1249 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1250 (ti->flag & WIDE_NEGO_ENABLE)) { 1251 /* send WDTR */ 1252 ti->flag &= ~SYNC_NEGO_DONE; 1253 1254 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1255 sc->sc_msgbuf[1] = MSG_EXTENDED; 1256 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1257 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1258 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1259 sc->sc_msgcnt = 5; 1260 1261 ti->flag |= WIDE_NEGO_DOING; 1262 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1263 (ti->flag & SYNC_NEGO_ENABLE)) { 1264 /* send SDTR */ 1265 int cnt = 0; 1266 1267 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1268 sc->sc_msgbuf[cnt++] = 1269 MSG_IDENTIFY(periph->periph_lun, 0); 1270 1271 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1272 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1273 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1274 sc->sc_msgbuf[cnt++] = ti->period; 1275 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1276 sc->sc_msgcnt = cnt; 1277 ti->flag |= SYNC_NEGO_DOING; 1278 } 1279 } 1280 if (sc->sc_msgcnt == 0) { 1281 sc->sc_msgbuf[0] = MSG_ABORT; 1282 sc->sc_msgcnt = 1; 1283 sc->sc_state = TRM_ABORT_SENT; 1284 } 1285 1286 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1287 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1288 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1289 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1290 1291 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1292 sc->sc_msgbuf, sc->sc_msgcnt); 1293 sc->sc_msgcnt = 0; 1294 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1295 1296 /* it's important for atn stop */ 1297 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1298 1299 /* 1300 * SCSI command 1301 */ 1302 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1303 } 1304 1305 static void 1306 trm_command_phase1(sc) 1307 struct trm_softc *sc; 1308 { 1309 bus_space_tag_t iot = sc->sc_iot; 1310 bus_space_handle_t ioh = sc->sc_ioh; 1311 struct trm_srb *srb; 1312 1313 srb = sc->sc_actsrb; 1314 if (srb == NULL) { 1315 DPRINTF(("trm_command_phase1: no active srb\n")); 1316 return; 1317 } 1318 1319 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1320 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1321 1322 sc->sc_state = TRM_COMMAND; 1323 /* it's important for atn stop */ 1324 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1325 1326 /* 1327 * SCSI command 1328 */ 1329 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1330 } 1331 1332 static void 1333 trm_dataout_phase0(sc, stat) 1334 struct trm_softc *sc; 1335 int stat; 1336 { 1337 bus_space_tag_t iot = sc->sc_iot; 1338 bus_space_handle_t ioh = sc->sc_ioh; 1339 struct trm_srb *srb; 1340 struct scsipi_periph *periph; 1341 struct trm_tinfo *ti; 1342 struct trm_sg_entry *sg; 1343 int sgindex; 1344 u_int32_t xferlen, leftcnt = 0; 1345 1346 if (sc->sc_state == TRM_XFERPAD) 1347 return; 1348 1349 srb = sc->sc_actsrb; 1350 if (srb == NULL) { 1351 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1352 return; 1353 } 1354 periph = srb->xs->xs_periph; 1355 ti = &sc->sc_tinfo[periph->periph_target]; 1356 1357 if ((stat & PARITYERROR) != 0) 1358 srb->flag |= PARITY_ERROR; 1359 1360 if ((stat & SCSIXFERDONE) == 0) { 1361 /* 1362 * when data transfer from DMA FIFO to SCSI FIFO 1363 * if there was some data left in SCSI FIFO 1364 */ 1365 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1366 SCSI_FIFOCNT_MASK; 1367 if (ti->synctl & WIDE_SYNC) 1368 /* 1369 * if WIDE scsi SCSI FIFOCNT unit is word 1370 * so need to * 2 1371 */ 1372 leftcnt <<= 1; 1373 } 1374 /* 1375 * calculate all the residue data that was not yet transferred 1376 * SCSI transfer counter + left in SCSI FIFO data 1377 * 1378 * .....TRM_SCSI_XCNT (24bits) 1379 * The counter always decrements by one for every SCSI 1380 * byte transfer. 1381 * .....TRM_SCSI_FIFOCNT ( 5bits) 1382 * The counter is SCSI FIFO offset counter 1383 */ 1384 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1385 if (leftcnt == 1) { 1386 leftcnt = 0; 1387 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1388 } 1389 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1390 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1391 DMAXFERCOMP) == 0) 1392 ; /* XXX needs timeout */ 1393 1394 srb->buflen = 0; 1395 } else { 1396 /* Update SG list */ 1397 1398 /* 1399 * if transfer not yet complete 1400 * there were some data residue in SCSI FIFO or 1401 * SCSI transfer counter not empty 1402 */ 1403 if (srb->buflen != leftcnt) { 1404 /* data that had transferred length */ 1405 xferlen = srb->buflen - leftcnt; 1406 1407 /* next time to be transferred length */ 1408 srb->buflen = leftcnt; 1409 1410 /* 1411 * parsing from last time disconnect sgindex 1412 */ 1413 sg = srb->sgentry + srb->sgindex; 1414 for (sgindex = srb->sgindex; 1415 sgindex < srb->sgcnt; 1416 sgindex++, sg++) { 1417 /* 1418 * find last time which SG transfer 1419 * be disconnect 1420 */ 1421 if (xferlen >= le32toh(sg->length)) 1422 xferlen -= le32toh(sg->length); 1423 else { 1424 /* 1425 * update last time 1426 * disconnected SG list 1427 */ 1428 /* residue data length */ 1429 sg->length = 1430 htole32(le32toh(sg->length) 1431 - xferlen); 1432 /* residue data pointer */ 1433 sg->address = 1434 htole32(le32toh(sg->address) 1435 + xferlen); 1436 srb->sgindex = sgindex; 1437 break; 1438 } 1439 } 1440 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1441 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1442 } 1443 } 1444 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1445 } 1446 1447 static void 1448 trm_datain_phase0(sc, stat) 1449 struct trm_softc *sc; 1450 int stat; 1451 { 1452 bus_space_tag_t iot = sc->sc_iot; 1453 bus_space_handle_t ioh = sc->sc_ioh; 1454 struct trm_srb *srb; 1455 struct trm_sg_entry *sg; 1456 int sgindex; 1457 u_int32_t xferlen, leftcnt = 0; 1458 1459 if (sc->sc_state == TRM_XFERPAD) 1460 return; 1461 1462 srb = sc->sc_actsrb; 1463 if (srb == NULL) { 1464 DPRINTF(("trm_datain_phase0: no active srb\n")); 1465 return; 1466 } 1467 1468 if (stat & PARITYERROR) 1469 srb->flag |= PARITY_ERROR; 1470 1471 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1472 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1473 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1474 DMAXFERCOMP) == 0) 1475 ; /* XXX needs timeout */ 1476 1477 srb->buflen = 0; 1478 } else { /* phase changed */ 1479 /* 1480 * parsing the case: 1481 * when a transfer not yet complete 1482 * but be disconnected by upper layer 1483 * if transfer not yet complete 1484 * there were some data residue in SCSI FIFO or 1485 * SCSI transfer counter not empty 1486 */ 1487 if (srb->buflen != leftcnt) { 1488 /* 1489 * data that had transferred length 1490 */ 1491 xferlen = srb->buflen - leftcnt; 1492 1493 /* 1494 * next time to be transferred length 1495 */ 1496 srb->buflen = leftcnt; 1497 1498 /* 1499 * parsing from last time disconnect sgindex 1500 */ 1501 sg = srb->sgentry + srb->sgindex; 1502 for (sgindex = srb->sgindex; 1503 sgindex < srb->sgcnt; 1504 sgindex++, sg++) { 1505 /* 1506 * find last time which SG transfer 1507 * be disconnect 1508 */ 1509 if (xferlen >= le32toh(sg->length)) 1510 xferlen -= le32toh(sg->length); 1511 else { 1512 /* 1513 * update last time 1514 * disconnected SG list 1515 */ 1516 /* residue data length */ 1517 sg->length = 1518 htole32(le32toh(sg->length) 1519 - xferlen); 1520 /* residue data pointer */ 1521 sg->address = 1522 htole32(le32toh(sg->address) 1523 + xferlen); 1524 srb->sgindex = sgindex; 1525 break; 1526 } 1527 } 1528 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1529 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1530 } 1531 } 1532 } 1533 1534 static void 1535 trm_dataio_xfer(sc, iodir) 1536 struct trm_softc *sc; 1537 int iodir; 1538 { 1539 bus_space_tag_t iot = sc->sc_iot; 1540 bus_space_handle_t ioh = sc->sc_ioh; 1541 struct trm_srb *srb; 1542 struct scsipi_periph *periph; 1543 struct trm_tinfo *ti; 1544 1545 srb = sc->sc_actsrb; 1546 if (srb == NULL) { 1547 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1548 return; 1549 } 1550 periph = srb->xs->xs_periph; 1551 ti = &sc->sc_tinfo[periph->periph_target]; 1552 1553 if (srb->sgindex < srb->sgcnt) { 1554 if (srb->buflen > 0) { 1555 /* 1556 * load what physical address of Scatter/Gather 1557 * list table want to be transfer 1558 */ 1559 sc->sc_state = TRM_DATA_XFER; 1560 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1561 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1562 srb->sgaddr + 1563 srb->sgindex * sizeof(struct trm_sg_entry)); 1564 /* 1565 * load how many bytes in the Scatter/Gather list table 1566 */ 1567 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1568 (srb->sgcnt - srb->sgindex) 1569 * sizeof(struct trm_sg_entry)); 1570 /* 1571 * load total xfer length (24bits) max value 16Mbyte 1572 */ 1573 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1574 /* Start DMA transfer */ 1575 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1576 iodir | SGXFER); 1577 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1578 STARTDMAXFER); 1579 1580 /* Start SCSI transfer */ 1581 /* it's important for atn stop */ 1582 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1583 DO_DATALATCH); 1584 1585 /* 1586 * SCSI command 1587 */ 1588 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1589 (iodir == XFERDATAOUT) ? 1590 SCMD_DMA_OUT : SCMD_DMA_IN); 1591 } else { /* xfer pad */ 1592 if (srb->sgcnt) { 1593 srb->hastat = H_OVER_UNDER_RUN; 1594 } 1595 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1596 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1597 1598 if (iodir == XFERDATAOUT) 1599 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1600 else 1601 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1602 1603 sc->sc_state = TRM_XFERPAD; 1604 /* it's important for atn stop */ 1605 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1606 DO_DATALATCH); 1607 1608 /* 1609 * SCSI command 1610 */ 1611 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1612 (iodir == XFERDATAOUT) ? 1613 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1614 } 1615 } 1616 } 1617 1618 static void 1619 trm_status_phase0(sc) 1620 struct trm_softc *sc; 1621 { 1622 bus_space_tag_t iot = sc->sc_iot; 1623 bus_space_handle_t ioh = sc->sc_ioh; 1624 struct trm_srb *srb; 1625 1626 srb = sc->sc_actsrb; 1627 if (srb == NULL) { 1628 DPRINTF(("trm_status_phase0: no active srb\n")); 1629 return; 1630 } 1631 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1632 sc->sc_state = TRM_COMPLETED; 1633 /* it's important for atn stop */ 1634 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1635 1636 /* 1637 * SCSI command 1638 */ 1639 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1640 } 1641 1642 static void 1643 trm_status_phase1(sc) 1644 struct trm_softc *sc; 1645 { 1646 bus_space_tag_t iot = sc->sc_iot; 1647 bus_space_handle_t ioh = sc->sc_ioh; 1648 1649 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1650 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1651 & SCSI_FIFO_EMPTY) == 0) 1652 bus_space_write_2(iot, ioh, 1653 TRM_SCSI_CONTROL, DO_CLRFIFO); 1654 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1655 & DMA_FIFO_EMPTY) == 0) 1656 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1657 } else { 1658 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1659 & DMA_FIFO_EMPTY) == 0) 1660 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1661 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1662 & SCSI_FIFO_EMPTY) == 0) 1663 bus_space_write_2(iot, ioh, 1664 TRM_SCSI_CONTROL, DO_CLRFIFO); 1665 } 1666 sc->sc_state = TRM_STATUS; 1667 /* it's important for atn stop */ 1668 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1669 1670 /* 1671 * SCSI command 1672 */ 1673 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1674 } 1675 1676 static void 1677 trm_msgin_phase0(sc) 1678 struct trm_softc *sc; 1679 { 1680 bus_space_tag_t iot = sc->sc_iot; 1681 bus_space_handle_t ioh = sc->sc_ioh; 1682 struct trm_srb *srb; 1683 struct scsipi_periph *periph; 1684 struct trm_tinfo *ti; 1685 int index; 1686 u_int8_t msgin_code; 1687 1688 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1689 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1690 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1691 switch (msgin_code) { 1692 case MSG_DISCONNECT: 1693 sc->sc_state = TRM_DISCONNECTED; 1694 break; 1695 1696 case MSG_SAVEDATAPOINTER: 1697 break; 1698 1699 case MSG_EXTENDED: 1700 case MSG_SIMPLE_Q_TAG: 1701 case MSG_HEAD_OF_Q_TAG: 1702 case MSG_ORDERED_Q_TAG: 1703 sc->sc_state = TRM_EXTEND_MSGIN; 1704 /* extended message (01h) */ 1705 sc->sc_msgbuf[0] = msgin_code; 1706 1707 sc->sc_msgcnt = 1; 1708 /* extended message length (n) */ 1709 sc->sc_msg = &sc->sc_msgbuf[1]; 1710 1711 break; 1712 case MSG_MESSAGE_REJECT: 1713 /* Reject message */ 1714 srb = sc->sc_actsrb; 1715 if (srb == NULL) { 1716 DPRINTF(("trm_msgin_phase0: " 1717 " message reject without actsrb\n")); 1718 break; 1719 } 1720 periph = srb->xs->xs_periph; 1721 ti = &sc->sc_tinfo[periph->periph_target]; 1722 1723 if (ti->flag & WIDE_NEGO_ENABLE) { 1724 /* do wide nego reject */ 1725 ti->flag |= WIDE_NEGO_DONE; 1726 ti->flag &= 1727 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1728 if ((ti->flag & SYNC_NEGO_ENABLE) && 1729 (ti->flag & SYNC_NEGO_DONE) == 0) { 1730 /* Set ATN, in case ATN was clear */ 1731 sc->sc_state = TRM_MSGOUT; 1732 bus_space_write_2(iot, ioh, 1733 TRM_SCSI_CONTROL, DO_SETATN); 1734 } else 1735 /* Clear ATN */ 1736 bus_space_write_2(iot, ioh, 1737 TRM_SCSI_CONTROL, DO_CLRATN); 1738 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1739 /* do sync nego reject */ 1740 bus_space_write_2(iot, ioh, 1741 TRM_SCSI_CONTROL, DO_CLRATN); 1742 if (ti->flag & SYNC_NEGO_DOING) { 1743 ti->flag &=~(SYNC_NEGO_ENABLE | 1744 SYNC_NEGO_DONE); 1745 ti->synctl = 0; 1746 ti->offset = 0; 1747 bus_space_write_1(iot, ioh, 1748 TRM_SCSI_SYNC, ti->synctl); 1749 bus_space_write_1(iot, ioh, 1750 TRM_SCSI_OFFSET, ti->offset); 1751 } 1752 } 1753 break; 1754 1755 case MSG_IGN_WIDE_RESIDUE: 1756 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1757 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1758 break; 1759 1760 default: 1761 /* 1762 * Restore data pointer message 1763 * Save data pointer message 1764 * Completion message 1765 * NOP message 1766 */ 1767 break; 1768 } 1769 } else { 1770 /* 1771 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1772 * Parsing incoming extented messages 1773 */ 1774 *sc->sc_msg++ = msgin_code; 1775 sc->sc_msgcnt++; 1776 1777 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1778 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1779 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1780 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1781 1782 switch (sc->sc_msgbuf[0]) { 1783 case MSG_SIMPLE_Q_TAG: 1784 case MSG_HEAD_OF_Q_TAG: 1785 case MSG_ORDERED_Q_TAG: 1786 /* 1787 * is QUEUE tag message : 1788 * 1789 * byte 0: 1790 * HEAD QUEUE TAG (20h) 1791 * ORDERED QUEUE TAG (21h) 1792 * SIMPLE QUEUE TAG (22h) 1793 * byte 1: 1794 * Queue tag (00h - FFh) 1795 */ 1796 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1797 /* XXX XXX XXX */ 1798 struct trm_linfo *li; 1799 int tagid; 1800 1801 sc->sc_flag &= ~WAIT_TAGMSG; 1802 tagid = sc->sc_msgbuf[1]; 1803 ti = &sc->sc_tinfo[sc->resel_target]; 1804 li = ti->linfo[sc->resel_lun]; 1805 srb = li->queued[tagid]; 1806 if (srb != NULL) { 1807 sc->sc_actsrb = srb; 1808 sc->sc_state = TRM_DATA_XFER; 1809 break; 1810 } else { 1811 printf("%s: invalid tag id\n", 1812 sc->sc_dev.dv_xname); 1813 } 1814 1815 sc->sc_state = TRM_UNEXPECT_RESEL; 1816 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1817 sc->sc_msgcnt = 1; 1818 bus_space_write_2(iot, ioh, 1819 TRM_SCSI_CONTROL, DO_SETATN); 1820 } else 1821 sc->sc_state = TRM_IDLE; 1822 break; 1823 1824 case MSG_EXTENDED: 1825 srb = sc->sc_actsrb; 1826 if (srb == NULL) { 1827 DPRINTF(("trm_msgin_phase0: " 1828 "extended message without actsrb\n")); 1829 break; 1830 } 1831 periph = srb->xs->xs_periph; 1832 ti = &sc->sc_tinfo[periph->periph_target]; 1833 1834 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1835 sc->sc_msgcnt == 4) { 1836 /* 1837 * is Wide data xfer Extended message : 1838 * ====================================== 1839 * WIDE DATA TRANSFER REQUEST 1840 * ====================================== 1841 * byte 0 : Extended message (01h) 1842 * byte 1 : Extended message length (02h) 1843 * byte 2 : WIDE DATA TRANSFER code (03h) 1844 * byte 3 : Transfer width exponent 1845 */ 1846 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1847 /* Length is wrong, reject it */ 1848 ti->flag &= ~(WIDE_NEGO_ENABLE | 1849 WIDE_NEGO_DONE); 1850 sc->sc_state = TRM_MSGOUT; 1851 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1852 sc->sc_msgcnt = 1; 1853 bus_space_write_2(iot, ioh, 1854 TRM_SCSI_CONTROL, DO_SETATN); 1855 break; 1856 } 1857 1858 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1859 sc->sc_msgbuf[3] = 1860 MSG_EXT_WDTR_BUS_8_BIT; 1861 1862 if (sc->sc_msgbuf[3] > 1863 MSG_EXT_WDTR_BUS_32_BIT) { 1864 /* reject_msg: */ 1865 ti->flag &= ~(WIDE_NEGO_ENABLE | 1866 WIDE_NEGO_DONE); 1867 sc->sc_state = TRM_MSGOUT; 1868 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1869 sc->sc_msgcnt = 1; 1870 bus_space_write_2(iot, ioh, 1871 TRM_SCSI_CONTROL, DO_SETATN); 1872 break; 1873 } 1874 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1875 /* do 16 bits */ 1876 sc->sc_msgbuf[3] = 1877 MSG_EXT_WDTR_BUS_16_BIT; 1878 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1879 ti->flag |= WIDE_NEGO_DONE; 1880 ti->flag &= ~(SYNC_NEGO_DONE | 1881 WIDE_NEGO_ENABLE); 1882 if (sc->sc_msgbuf[3] != 1883 MSG_EXT_WDTR_BUS_8_BIT) 1884 /* is Wide data xfer */ 1885 ti->synctl |= WIDE_SYNC; 1886 trm_update_xfer_mode(sc, 1887 periph->periph_target); 1888 } 1889 1890 sc->sc_state = TRM_MSGOUT; 1891 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1892 DO_SETATN); 1893 break; 1894 1895 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1896 sc->sc_msgcnt == 5) { 1897 /* 1898 * is 8bit transfer Extended message : 1899 * ================================= 1900 * SYNCHRONOUS DATA TRANSFER REQUEST 1901 * ================================= 1902 * byte 0 : Extended message (01h) 1903 * byte 1 : Extended message length (03) 1904 * byte 2 : SYNC DATA TRANSFER code (01h) 1905 * byte 3 : Transfer period factor 1906 * byte 4 : REQ/ACK offset 1907 */ 1908 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1909 /* reject_msg */ 1910 sc->sc_state = TRM_MSGOUT; 1911 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1912 sc->sc_msgcnt = 1; 1913 bus_space_write_2(iot, ioh, 1914 TRM_SCSI_CONTROL, DO_SETATN); 1915 break; 1916 } 1917 1918 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1919 ti->flag &= 1920 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1921 ti->flag |= SYNC_NEGO_DONE; 1922 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1923 sc->sc_msgbuf[3] = 0; 1924 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1925 sc->sc_msgbuf[4] = 1926 TRM_MAX_OFFSET; 1927 1928 if (sc->sc_msgbuf[3] == 0 || 1929 sc->sc_msgbuf[4] == 0) { 1930 /* set async */ 1931 ti->synctl = 0; 1932 ti->offset = 0; 1933 } else { 1934 /* set sync */ 1935 /* Transfer period factor */ 1936 ti->period = sc->sc_msgbuf[3]; 1937 /* REQ/ACK offset */ 1938 ti->offset = sc->sc_msgbuf[4]; 1939 for (index = 0; 1940 index < NPERIOD; 1941 index++) 1942 if (ti->period <= 1943 trm_clock_period[ 1944 index]) 1945 break; 1946 1947 ti->synctl |= ALT_SYNC | index; 1948 } 1949 /* 1950 * program SCSI control register 1951 */ 1952 bus_space_write_1(iot, ioh, 1953 TRM_SCSI_SYNC, ti->synctl); 1954 bus_space_write_1(iot, ioh, 1955 TRM_SCSI_OFFSET, ti->offset); 1956 trm_update_xfer_mode(sc, 1957 periph->periph_target); 1958 } 1959 sc->sc_state = TRM_IDLE; 1960 } 1961 break; 1962 default: 1963 break; 1964 } 1965 } 1966 1967 /* it's important for atn stop */ 1968 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1969 1970 /* 1971 * SCSI command 1972 */ 1973 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1974 } 1975 1976 static void 1977 trm_msgin_phase1(sc) 1978 struct trm_softc *sc; 1979 { 1980 bus_space_tag_t iot = sc->sc_iot; 1981 bus_space_handle_t ioh = sc->sc_ioh; 1982 1983 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1984 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1985 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1986 sc->sc_state = TRM_MSGIN; 1987 } 1988 1989 /* it's important for atn stop */ 1990 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1991 1992 /* 1993 * SCSI command 1994 */ 1995 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1996 } 1997 1998 static void 1999 trm_disconnect(sc) 2000 struct trm_softc *sc; 2001 { 2002 bus_space_tag_t iot = sc->sc_iot; 2003 bus_space_handle_t ioh = sc->sc_ioh; 2004 struct trm_srb *srb; 2005 int s; 2006 2007 s = splbio(); 2008 2009 srb = sc->sc_actsrb; 2010 DPRINTF(("trm_disconnect...............\n")); 2011 2012 if (srb == NULL) { 2013 DPRINTF(("trm_disconnect: no active srb\n")); 2014 DELAY(1000); /* 1 msec */ 2015 2016 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2017 DO_CLRFIFO | DO_HWRESELECT); 2018 return; 2019 } 2020 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2021 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2022 DO_CLRFIFO | DO_HWRESELECT); 2023 DELAY(100); 2024 2025 switch (sc->sc_state) { 2026 case TRM_UNEXPECT_RESEL: 2027 sc->sc_state = TRM_IDLE; 2028 break; 2029 2030 case TRM_ABORT_SENT: 2031 goto finish; 2032 2033 case TRM_START: 2034 case TRM_MSGOUT: 2035 { 2036 /* Selection time out - discard all LUNs if empty */ 2037 struct scsipi_periph *periph; 2038 struct trm_tinfo *ti; 2039 struct trm_linfo *li; 2040 int lun; 2041 2042 DPRINTF(("selection timeout\n")); 2043 2044 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2045 2046 periph = srb->xs->xs_periph; 2047 ti = &sc->sc_tinfo[periph->periph_target]; 2048 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2049 li = ti->linfo[lun]; 2050 if (li != NULL && 2051 li->untagged == NULL && li->used == 0) { 2052 ti->linfo[lun] = NULL; 2053 free(li, M_DEVBUF); 2054 } 2055 } 2056 } 2057 goto finish; 2058 2059 case TRM_DISCONNECTED: 2060 sc->sc_actsrb = NULL; 2061 sc->sc_state = TRM_IDLE; 2062 goto sched; 2063 2064 case TRM_COMPLETED: 2065 goto finish; 2066 } 2067 2068 out: 2069 splx(s); 2070 return; 2071 2072 finish: 2073 sc->sc_state = TRM_IDLE; 2074 trm_done(sc, srb); 2075 goto out; 2076 2077 sched: 2078 trm_sched(sc); 2079 goto out; 2080 } 2081 2082 static void 2083 trm_reselect(sc) 2084 struct trm_softc *sc; 2085 { 2086 bus_space_tag_t iot = sc->sc_iot; 2087 bus_space_handle_t ioh = sc->sc_ioh; 2088 struct trm_tinfo *ti; 2089 struct trm_linfo *li; 2090 int target, lun; 2091 2092 DPRINTF(("trm_reselect.................\n")); 2093 2094 if (sc->sc_actsrb != NULL) { 2095 /* arbitration lost but reselection win */ 2096 sc->sc_state = TRM_READY; 2097 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2098 ti = &sc->sc_tinfo[target]; 2099 } else { 2100 /* Read Reselected Target Id and LUN */ 2101 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2102 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2103 ti = &sc->sc_tinfo[target]; 2104 li = ti->linfo[lun]; 2105 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2106 2107 /* 2108 * Check to see if we are running an un-tagged command. 2109 * Otherwise ack the IDENTIFY and wait for a tag message. 2110 */ 2111 if (li != NULL) { 2112 if (li->untagged != NULL && li->busy) { 2113 sc->sc_actsrb = li->untagged; 2114 sc->sc_state = TRM_DATA_XFER; 2115 } else { 2116 sc->resel_target = target; 2117 sc->resel_lun = lun; 2118 /* XXX XXX XXX */ 2119 sc->sc_flag |= WAIT_TAGMSG; 2120 } 2121 } 2122 2123 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2124 sc->sc_actsrb == NULL) { 2125 printf("%s: reselect from target %d lun %d " 2126 "without nexus; sending abort\n", 2127 sc->sc_dev.dv_xname, target, lun); 2128 sc->sc_state = TRM_UNEXPECT_RESEL; 2129 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2130 sc->sc_msgcnt = 1; 2131 bus_space_write_2(iot, ioh, 2132 TRM_SCSI_CONTROL, DO_SETATN); 2133 } 2134 } 2135 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2136 /* 2137 * Program HA ID, target ID, period and offset 2138 */ 2139 /* target ID */ 2140 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2141 2142 /* host ID */ 2143 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2144 2145 /* period */ 2146 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2147 2148 /* offset */ 2149 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2150 2151 /* it's important for atn stop */ 2152 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2153 /* 2154 * SCSI command 2155 */ 2156 /* to rls the /ACK signal */ 2157 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2158 } 2159 2160 /* 2161 * Complete execution of a SCSI command 2162 * Signal completion to the generic SCSI driver 2163 */ 2164 static void 2165 trm_done(sc, srb) 2166 struct trm_softc *sc; 2167 struct trm_srb *srb; 2168 { 2169 struct scsipi_xfer *xs = srb->xs; 2170 2171 DPRINTF(("trm_done..................\n")); 2172 2173 if (xs == NULL) 2174 return; 2175 2176 if ((xs->xs_control & XS_CTL_POLL) == 0) 2177 callout_stop(&xs->xs_callout); 2178 2179 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2180 srb->flag & AUTO_REQSENSE) { 2181 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2182 srb->dmap->dm_mapsize, 2183 ((xs->xs_control & XS_CTL_DATA_IN) || 2184 (srb->flag & AUTO_REQSENSE)) ? 2185 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2186 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2187 } 2188 2189 /* 2190 * target status 2191 */ 2192 xs->status = srb->tastat; 2193 2194 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2195 2196 switch (xs->status) { 2197 case SCSI_OK: 2198 /* 2199 * process initiator status...... 2200 * Adapter (initiator) status 2201 */ 2202 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2203 printf("%s: over/under run error\n", 2204 sc->sc_dev.dv_xname); 2205 srb->tastat = 0; 2206 /* Illegal length (over/under run) */ 2207 xs->error = XS_DRIVER_STUFFUP; 2208 } else if ((srb->flag & PARITY_ERROR) != 0) { 2209 printf("%s: parity error\n", 2210 sc->sc_dev.dv_xname); 2211 /* Driver failed to perform operation */ 2212 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2213 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2214 xs->resid = srb->buflen; 2215 xs->error = XS_TIMEOUT; 2216 } else { 2217 /* No error */ 2218 xs->resid = srb->buflen; 2219 srb->hastat = 0; 2220 if (srb->flag & AUTO_REQSENSE) { 2221 /* there is no error, (sense is invalid) */ 2222 xs->error = XS_SENSE; 2223 } else { 2224 srb->tastat = 0; 2225 xs->error = XS_NOERROR; 2226 } 2227 } 2228 break; 2229 2230 case SCSI_CHECK: 2231 if ((srb->flag & AUTO_REQSENSE) != 0 || 2232 trm_request_sense(sc, srb) != 0) { 2233 printf("%s: request sense failed\n", 2234 sc->sc_dev.dv_xname); 2235 xs->error = XS_DRIVER_STUFFUP; 2236 break; 2237 } 2238 xs->error = XS_SENSE; 2239 return; 2240 2241 case SCSI_SEL_TIMEOUT: 2242 srb->hastat = H_SEL_TIMEOUT; 2243 srb->tastat = 0; 2244 xs->error = XS_SELTIMEOUT; 2245 break; 2246 2247 case SCSI_QUEUE_FULL: 2248 case SCSI_BUSY: 2249 xs->error = XS_BUSY; 2250 break; 2251 2252 case SCSI_RESV_CONFLICT: 2253 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2254 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2255 xs->error = XS_BUSY; 2256 break; 2257 2258 default: 2259 srb->hastat = 0; 2260 printf("%s: trm_done(): unknown status = %02x\n", 2261 sc->sc_dev.dv_xname, xs->status); 2262 xs->error = XS_DRIVER_STUFFUP; 2263 break; 2264 } 2265 2266 trm_dequeue(sc, srb); 2267 if (srb == sc->sc_actsrb) { 2268 sc->sc_actsrb = NULL; 2269 trm_sched(sc); 2270 } 2271 2272 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2273 2274 /* Notify cmd done */ 2275 scsipi_done(xs); 2276 } 2277 2278 static int 2279 trm_request_sense(sc, srb) 2280 struct trm_softc *sc; 2281 struct trm_srb *srb; 2282 { 2283 struct scsipi_xfer *xs; 2284 struct scsipi_periph *periph; 2285 struct trm_tinfo *ti; 2286 struct trm_linfo *li; 2287 struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2288 int error; 2289 2290 DPRINTF(("trm_request_sense...\n")); 2291 2292 xs = srb->xs; 2293 periph = xs->xs_periph; 2294 2295 srb->flag |= AUTO_REQSENSE; 2296 2297 /* Status of initiator/target */ 2298 srb->hastat = 0; 2299 srb->tastat = 0; 2300 2301 ss->opcode = REQUEST_SENSE; 2302 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2303 ss->unused[0] = ss->unused[1] = 0; 2304 ss->length = sizeof(struct scsipi_sense_data); 2305 ss->control = 0; 2306 2307 srb->buflen = sizeof(struct scsipi_sense_data); 2308 srb->sgcnt = 1; 2309 srb->sgindex = 0; 2310 srb->cmdlen = sizeof(struct scsipi_sense); 2311 2312 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2313 &xs->sense.scsi_sense, srb->buflen, NULL, 2314 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2315 return error; 2316 } 2317 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2318 srb->buflen, BUS_DMASYNC_PREREAD); 2319 2320 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2321 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2322 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2323 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2324 2325 ti = &sc->sc_tinfo[periph->periph_target]; 2326 li = ti->linfo[periph->periph_lun]; 2327 if (li->busy > 0) 2328 li->busy = 0; 2329 trm_dequeue(sc, srb); 2330 li->untagged = srb; /* must be executed first to fix C/A */ 2331 li->busy = 2; 2332 2333 if (srb == sc->sc_actsrb) 2334 trm_select(sc, srb); 2335 else { 2336 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2337 if (sc->sc_actsrb == NULL) 2338 trm_sched(sc); 2339 } 2340 return 0; 2341 } 2342 2343 static void 2344 trm_dequeue(sc, srb) 2345 struct trm_softc *sc; 2346 struct trm_srb *srb; 2347 { 2348 struct scsipi_periph *periph; 2349 struct trm_tinfo *ti; 2350 struct trm_linfo *li; 2351 2352 periph = srb->xs->xs_periph; 2353 ti = &sc->sc_tinfo[periph->periph_target]; 2354 li = ti->linfo[periph->periph_lun]; 2355 2356 if (li->untagged == srb) { 2357 li->busy = 0; 2358 li->untagged = NULL; 2359 } 2360 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2361 li->queued[srb->tag[1]] = NULL; 2362 li->used--; 2363 } 2364 } 2365 2366 static void 2367 trm_reset_scsi_bus(sc) 2368 struct trm_softc *sc; 2369 { 2370 bus_space_tag_t iot = sc->sc_iot; 2371 bus_space_handle_t ioh = sc->sc_ioh; 2372 int timeout, s; 2373 2374 DPRINTF(("trm_reset_scsi_bus.........\n")); 2375 2376 s = splbio(); 2377 2378 sc->sc_flag |= RESET_DEV; 2379 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2380 for (timeout = 20000; timeout >= 0; timeout--) { 2381 DELAY(1); 2382 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2383 INT_SCSIRESET) == 0) 2384 break; 2385 } 2386 if (timeout == 0) 2387 printf(": scsibus reset timeout\n"); 2388 2389 splx(s); 2390 } 2391 2392 static void 2393 trm_scsi_reset_detect(sc) 2394 struct trm_softc *sc; 2395 { 2396 bus_space_tag_t iot = sc->sc_iot; 2397 bus_space_handle_t ioh = sc->sc_ioh; 2398 int s; 2399 2400 DPRINTF(("trm_scsi_reset_detect...............\n")); 2401 DELAY(1000000); /* delay 1 sec */ 2402 2403 s = splbio(); 2404 2405 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2406 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2407 2408 if (sc->sc_flag & RESET_DEV) { 2409 sc->sc_flag |= RESET_DONE; 2410 } else { 2411 sc->sc_flag |= RESET_DETECT; 2412 sc->sc_actsrb = NULL; 2413 sc->sc_flag = 0; 2414 trm_sched(sc); 2415 } 2416 splx(s); 2417 } 2418 2419 /* 2420 * read seeprom 128 bytes to struct eeprom and check checksum. 2421 * If it is wrong, update with default value. 2422 */ 2423 static void 2424 trm_check_eeprom(sc, eeprom) 2425 struct trm_softc *sc; 2426 struct trm_nvram *eeprom; 2427 { 2428 struct nvram_target *target; 2429 u_int16_t *ep; 2430 u_int16_t chksum; 2431 int i; 2432 2433 DPRINTF(("trm_check_eeprom......\n")); 2434 trm_eeprom_read_all(sc, eeprom); 2435 ep = (u_int16_t *)eeprom; 2436 chksum = 0; 2437 for (i = 0; i < 64; i++) 2438 chksum += le16toh(*ep++); 2439 2440 if (chksum != TRM_NVRAM_CKSUM) { 2441 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2442 /* 2443 * Checksum error, load default 2444 */ 2445 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2446 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2447 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2448 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2449 eeprom->subclass = 0x00; 2450 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2451 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2452 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2453 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2454 eeprom->reserved0 = 0x00; 2455 2456 for (i = 0, target = eeprom->target; 2457 i < TRM_MAX_TARGETS; 2458 i++, target++) { 2459 target->config0 = 0x77; 2460 target->period = 0x00; 2461 target->config2 = 0x00; 2462 target->config3 = 0x00; 2463 } 2464 2465 eeprom->scsi_id = 7; 2466 eeprom->channel_cfg = 0x0F; 2467 eeprom->delay_time = 0; 2468 eeprom->max_tag = 4; 2469 eeprom->reserved1 = 0x15; 2470 eeprom->boot_target = 0; 2471 eeprom->boot_lun = 0; 2472 eeprom->reserved2 = 0; 2473 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2474 2475 chksum = 0; 2476 ep = (u_int16_t *)eeprom; 2477 for (i = 0; i < 63; i++) 2478 chksum += le16toh(*ep++); 2479 2480 chksum = TRM_NVRAM_CKSUM - chksum; 2481 eeprom->checksum0 = chksum & 0xFF; 2482 eeprom->checksum1 = chksum >> 8; 2483 2484 trm_eeprom_write_all(sc, eeprom); 2485 } 2486 } 2487 2488 /* 2489 * write struct eeprom 128 bytes to seeprom 2490 */ 2491 static void 2492 trm_eeprom_write_all(sc, eeprom) 2493 struct trm_softc *sc; 2494 struct trm_nvram *eeprom; 2495 { 2496 bus_space_tag_t iot = sc->sc_iot; 2497 bus_space_handle_t ioh = sc->sc_ioh; 2498 u_int8_t *buf = (u_int8_t *)eeprom; 2499 u_int8_t addr; 2500 2501 /* Enable SEEPROM */ 2502 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2503 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2504 2505 /* 2506 * Write enable 2507 */ 2508 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2509 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2510 trm_eeprom_wait(); 2511 2512 for (addr = 0; addr < 128; addr++, buf++) 2513 trm_eeprom_set_data(sc, addr, *buf); 2514 2515 /* 2516 * Write disable 2517 */ 2518 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2519 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2520 trm_eeprom_wait(); 2521 2522 /* Disable SEEPROM */ 2523 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2524 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2525 } 2526 2527 /* 2528 * write one byte to seeprom 2529 */ 2530 static void 2531 trm_eeprom_set_data(sc, addr, data) 2532 struct trm_softc *sc; 2533 u_int8_t addr; 2534 u_int8_t data; 2535 { 2536 bus_space_tag_t iot = sc->sc_iot; 2537 bus_space_handle_t ioh = sc->sc_ioh; 2538 int i; 2539 u_int8_t send; 2540 2541 /* 2542 * Send write command & address 2543 */ 2544 trm_eeprom_write_cmd(sc, 0x05, addr); 2545 /* 2546 * Write data 2547 */ 2548 for (i = 0; i < 8; i++, data <<= 1) { 2549 send = NVR_SELECT; 2550 if (data & 0x80) /* Start from bit 7 */ 2551 send |= NVR_BITOUT; 2552 2553 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2554 trm_eeprom_wait(); 2555 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2556 trm_eeprom_wait(); 2557 } 2558 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2559 trm_eeprom_wait(); 2560 /* 2561 * Disable chip select 2562 */ 2563 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2564 trm_eeprom_wait(); 2565 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2566 trm_eeprom_wait(); 2567 /* 2568 * Wait for write ready 2569 */ 2570 for (;;) { 2571 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2572 NVR_SELECT | NVR_CLOCK); 2573 trm_eeprom_wait(); 2574 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2575 trm_eeprom_wait(); 2576 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2577 break; 2578 } 2579 /* 2580 * Disable chip select 2581 */ 2582 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2583 } 2584 2585 /* 2586 * read seeprom 128 bytes to struct eeprom 2587 */ 2588 static void 2589 trm_eeprom_read_all(sc, eeprom) 2590 struct trm_softc *sc; 2591 struct trm_nvram *eeprom; 2592 { 2593 bus_space_tag_t iot = sc->sc_iot; 2594 bus_space_handle_t ioh = sc->sc_ioh; 2595 u_int8_t *buf = (u_int8_t *)eeprom; 2596 u_int8_t addr; 2597 2598 /* 2599 * Enable SEEPROM 2600 */ 2601 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2602 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2603 2604 for (addr = 0; addr < 128; addr++) 2605 *buf++ = trm_eeprom_get_data(sc, addr); 2606 2607 /* 2608 * Disable SEEPROM 2609 */ 2610 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2611 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2612 } 2613 2614 /* 2615 * read one byte from seeprom 2616 */ 2617 static u_int8_t 2618 trm_eeprom_get_data(sc, addr) 2619 struct trm_softc *sc; 2620 u_int8_t addr; 2621 { 2622 bus_space_tag_t iot = sc->sc_iot; 2623 bus_space_handle_t ioh = sc->sc_ioh; 2624 int i; 2625 u_int8_t read, data = 0; 2626 2627 /* 2628 * Send read command & address 2629 */ 2630 trm_eeprom_write_cmd(sc, 0x06, addr); 2631 2632 for (i = 0; i < 8; i++) { /* Read data */ 2633 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2634 NVR_SELECT | NVR_CLOCK); 2635 trm_eeprom_wait(); 2636 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2637 /* 2638 * Get data bit while falling edge 2639 */ 2640 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2641 data <<= 1; 2642 if (read & NVR_BITIN) 2643 data |= 1; 2644 2645 trm_eeprom_wait(); 2646 } 2647 /* 2648 * Disable chip select 2649 */ 2650 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2651 return (data); 2652 } 2653 2654 /* 2655 * write SB and Op Code into seeprom 2656 */ 2657 static void 2658 trm_eeprom_write_cmd(sc, cmd, addr) 2659 struct trm_softc *sc; 2660 u_int8_t cmd; 2661 u_int8_t addr; 2662 { 2663 bus_space_tag_t iot = sc->sc_iot; 2664 bus_space_handle_t ioh = sc->sc_ioh; 2665 int i; 2666 u_int8_t send; 2667 2668 /* Program SB+OP code */ 2669 for (i = 0; i < 3; i++, cmd <<= 1) { 2670 send = NVR_SELECT; 2671 if (cmd & 0x04) /* Start from bit 2 */ 2672 send |= NVR_BITOUT; 2673 2674 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2675 trm_eeprom_wait(); 2676 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2677 trm_eeprom_wait(); 2678 } 2679 2680 /* Program address */ 2681 for (i = 0; i < 7; i++, addr <<= 1) { 2682 send = NVR_SELECT; 2683 if (addr & 0x40) /* Start from bit 6 */ 2684 send |= NVR_BITOUT; 2685 2686 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2687 trm_eeprom_wait(); 2688 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2689 trm_eeprom_wait(); 2690 } 2691 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2692 trm_eeprom_wait(); 2693 } 2694
Indexes created Tue Sep 23 23:09:58 GMT 2025