trm.c revision 1.12
1 /* $NetBSD: trm.c,v 1.12 2002/09/30 20:38:04 thorpej Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.12 2002/09/30 20:38:04 thorpej Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsi_message.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/trmreg.h> 77 78 /* 79 * feature of chip set MAX value 80 */ 81 #define TRM_MAX_TARGETS 16 82 #define TRM_MAX_LUNS 8 83 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 #define TRM_MAX_SRB 32 /* XXX */ 85 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 #define TRM_MAX_OFFSET 15 87 #define TRM_MAX_PERIOD 125 88 89 /* 90 * Segment Entry 91 */ 92 struct trm_sg_entry { 93 u_int32_t address; 94 u_int32_t length; 95 }; 96 97 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 99 /* 100 ********************************************************************** 101 * The SEEPROM structure for TRM_S1040 102 ********************************************************************** 103 */ 104 struct nvram_target { 105 u_int8_t config0; /* Target configuration byte 0 */ 106 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 u_int8_t period; /* Target period */ 113 u_int8_t config2; /* Target configuration byte 2 */ 114 u_int8_t config3; /* Target configuration byte 3 */ 115 }; 116 117 struct trm_nvram { 118 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 u_int8_t subclass; /* 4 Sub Class */ 121 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 u_int8_t device_id[2]; /* 7,8 Device ID */ 123 u_int8_t reserved0; /* 9 Reserved */ 124 struct nvram_target target[TRM_MAX_TARGETS]; 125 /* 10,11,12,13 126 * 14,15,16,17 127 * .... 128 * 70,71,72,73 */ 129 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 u_int8_t channel_cfg; /* 75 Channel configuration */ 131 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 u_int8_t delay_time; /* 76 Power on delay time */ 137 u_int8_t max_tag; /* 77 Maximum tags */ 138 u_int8_t reserved1; /* 78 */ 139 u_int8_t boot_target; /* 79 */ 140 u_int8_t boot_lun; /* 80 */ 141 u_int8_t reserved2; /* 81 */ 142 u_int8_t reserved3[44]; /* 82,..125 */ 143 u_int8_t checksum0; /* 126 */ 144 u_int8_t checksum1; /* 127 */ 145 #define TRM_NVRAM_CKSUM 0x1234 146 }; 147 148 /* Nvram Initiater bits definition */ 149 #define MORE2_DRV 0x00000001 150 #define GREATER_1G 0x00000002 151 #define RST_SCSI_BUS 0x00000004 152 #define ACTIVE_NEGATION 0x00000008 153 #define NO_SEEK 0x00000010 154 #define LUN_CHECK 0x00000020 155 156 #define trm_eeprom_wait() DELAY(30) 157 158 /* 159 *----------------------------------------------------------------------- 160 * SCSI Request Block 161 *----------------------------------------------------------------------- 162 */ 163 struct trm_srb { 164 TAILQ_ENTRY(trm_srb) next; 165 166 struct trm_sg_entry *sgentry; 167 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 bus_dmamap_t dmap; 169 bus_size_t sgoffset; /* Xfer buf offset */ 170 171 u_int32_t buflen; /* Total xfer length */ 172 u_int32_t sgaddr; /* SGList physical starting address */ 173 174 int sgcnt; 175 int sgindex; 176 177 int hastat; /* Host Adapter Status */ 178 #define H_STATUS_GOOD 0x00 179 #define H_SEL_TIMEOUT 0x11 180 #define H_OVER_UNDER_RUN 0x12 181 #define H_UNEXP_BUS_FREE 0x13 182 #define H_TARGET_PHASE_F 0x14 183 #define H_INVALID_CCB_OP 0x16 184 #define H_LINK_CCB_BAD 0x17 185 #define H_BAD_TARGET_DIR 0x18 186 #define H_DUPLICATE_CCB 0x19 187 #define H_BAD_CCB_OR_SG 0x1A 188 #define H_ABORT 0xFF 189 int tastat; /* Target SCSI Status Byte */ 190 int flag; /* SRBFlag */ 191 #define AUTO_REQSENSE 0x0001 192 #define PARITY_ERROR 0x0002 193 #define SRB_TIMEOUT 0x0004 194 195 int cmdlen; /* SCSI command length */ 196 u_int8_t cmd[12]; /* SCSI command */ 197 198 u_int8_t tag[2]; 199 }; 200 201 /* 202 * some info about each target and lun on the SCSI bus 203 */ 204 struct trm_linfo { 205 int used; /* number of slots in use */ 206 int avail; /* where to start scanning */ 207 int busy; /* lun in use */ 208 struct trm_srb *untagged; 209 struct trm_srb *queued[TRM_MAX_TAG]; 210 }; 211 212 struct trm_tinfo { 213 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 #define SYNC_NEGO_ENABLE 0x0001 215 #define SYNC_NEGO_DOING 0x0002 216 #define SYNC_NEGO_DONE 0x0004 217 #define WIDE_NEGO_ENABLE 0x0008 218 #define WIDE_NEGO_DOING 0x0010 219 #define WIDE_NEGO_DONE 0x0020 220 #define USE_TAG_QUEUING 0x0040 221 #define NO_RESELECT 0x0080 222 struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 224 u_int8_t config0; /* Target Config */ 225 u_int8_t period; /* Max Period for nego. */ 226 u_int8_t synctl; /* Sync control for reg. */ 227 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 }; 229 230 /* 231 *----------------------------------------------------------------------- 232 * Adapter Control Block 233 *----------------------------------------------------------------------- 234 */ 235 struct trm_softc { 236 struct device sc_dev; 237 238 bus_space_tag_t sc_iot; 239 bus_space_handle_t sc_ioh; 240 bus_dma_tag_t sc_dmat; 241 bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 243 struct trm_srb *sc_actsrb; 244 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 246 TAILQ_HEAD(, trm_srb) sc_freesrb, 247 sc_readysrb; 248 struct trm_srb *sc_srb; /* SRB array */ 249 250 struct trm_sg_entry *sc_sglist; 251 252 int sc_maxid; 253 /* 254 * Link to the generic SCSI driver 255 */ 256 struct scsipi_channel sc_channel; 257 struct scsipi_adapter sc_adapter; 258 259 int sc_id; /* Adapter SCSI Target ID */ 260 261 int sc_state; /* SRB State */ 262 #define TRM_IDLE 0 263 #define TRM_WAIT 1 264 #define TRM_READY 2 265 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 #define TRM_MSGIN 4 267 #define TRM_EXTEND_MSGIN 5 268 #define TRM_COMMAND 6 269 #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 #define TRM_DISCONNECTED 8 271 #define TRM_DATA_XFER 9 272 #define TRM_XFERPAD 10 273 #define TRM_STATUS 11 274 #define TRM_COMPLETED 12 275 #define TRM_ABORT_SENT 13 276 #define TRM_UNEXPECT_RESEL 14 277 278 int sc_phase; /* SCSI phase */ 279 int sc_config; 280 #define HCC_WIDE_CARD 0x01 281 #define HCC_SCSI_RESET 0x02 282 #define HCC_PARITY 0x04 283 #define HCC_AUTOTERM 0x08 284 #define HCC_LOW8TERM 0x10 285 #define HCC_UP8TERM 0x20 286 287 int sc_flag; 288 #define RESET_DEV 0x01 289 #define RESET_DETECT 0x02 290 #define RESET_DONE 0x04 291 #define WAIT_TAGMSG 0x08 /* XXX */ 292 293 int sc_msgcnt; 294 295 int resel_target; /* XXX */ 296 int resel_lun; /* XXX */ 297 298 u_int8_t *sc_msg; 299 u_int8_t sc_msgbuf[6]; 300 }; 301 302 /* 303 * SCSI Status codes not defined in scsi_all.h 304 */ 305 #define SCSI_COND_MET 0x04 /* Condition Met */ 306 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 311 static int trm_probe(struct device *, struct cfdata *, void *); 312 static void trm_attach(struct device *, struct device *, void *); 313 314 static int trm_init(struct trm_softc *); 315 316 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 void *); 318 static void trm_update_xfer_mode(struct trm_softc *, int); 319 static void trm_sched(struct trm_softc *); 320 static int trm_select(struct trm_softc *, struct trm_srb *); 321 static void trm_reset(struct trm_softc *); 322 static void trm_timeout(void *); 323 static int trm_intr(void *); 324 325 static void trm_dataout_phase0(struct trm_softc *, int); 326 static void trm_datain_phase0(struct trm_softc *, int); 327 static void trm_status_phase0(struct trm_softc *); 328 static void trm_msgin_phase0(struct trm_softc *); 329 static void trm_command_phase1(struct trm_softc *); 330 static void trm_status_phase1(struct trm_softc *); 331 static void trm_msgout_phase1(struct trm_softc *); 332 static void trm_msgin_phase1(struct trm_softc *); 333 334 static void trm_dataio_xfer(struct trm_softc *, int); 335 static void trm_disconnect(struct trm_softc *); 336 static void trm_reselect(struct trm_softc *); 337 static void trm_done(struct trm_softc *, struct trm_srb *); 338 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 341 static void trm_scsi_reset_detect(struct trm_softc *); 342 static void trm_reset_scsi_bus(struct trm_softc *); 343 344 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 351 CFATTACH_DECL(trm, sizeof(struct trm_softc), 352 trm_probe, trm_attach, NULL, NULL) 353 354 /* real period: */ 355 static const u_int8_t trm_clock_period[] = { 356 12, /* 48 ns 20.0 MB/sec */ 357 18, /* 72 ns 13.3 MB/sec */ 358 25, /* 100 ns 10.0 MB/sec */ 359 31, /* 124 ns 8.0 MB/sec */ 360 37, /* 148 ns 6.6 MB/sec */ 361 43, /* 172 ns 5.7 MB/sec */ 362 50, /* 200 ns 5.0 MB/sec */ 363 62 /* 248 ns 4.0 MB/sec */ 364 }; 365 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 366 367 static int 368 trm_probe(parent, match, aux) 369 struct device *parent; 370 struct cfdata *match; 371 void *aux; 372 { 373 struct pci_attach_args *pa = aux; 374 375 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 376 switch (PCI_PRODUCT(pa->pa_id)) { 377 case PCI_PRODUCT_TEKRAM2_DC315: 378 return (1); 379 } 380 return (0); 381 } 382 383 /* 384 * attach and init a host adapter 385 */ 386 static void 387 trm_attach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pci_attach_args *const pa = aux; 393 struct trm_softc *sc = (struct trm_softc *)self; 394 bus_space_tag_t iot; 395 bus_space_handle_t ioh; 396 pci_intr_handle_t ih; 397 pcireg_t command; 398 const char *intrstr; 399 400 /* 401 * These cards do not allow memory mapped accesses 402 * pa_pc: chipset tag 403 * pa_tag: pci tag 404 */ 405 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 406 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 407 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 408 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 409 pci_conf_write(pa->pa_pc, pa->pa_tag, 410 PCI_COMMAND_STATUS_REG, command); 411 } 412 /* 413 * mask for get correct base address of pci IO port 414 */ 415 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 416 &iot, &ioh, NULL, NULL)) { 417 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 418 return; 419 } 420 /* 421 * test checksum of eeprom.. & initialize softc... 422 */ 423 sc->sc_iot = iot; 424 sc->sc_ioh = ioh; 425 sc->sc_dmat = pa->pa_dmat; 426 427 if (trm_init(sc) != 0) { 428 /* 429 * Error during initialization! 430 */ 431 printf(": Error during initialization\n"); 432 return; 433 } 434 /* 435 * Now try to attach all the sub-devices 436 */ 437 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 438 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 439 "Ultra Wide SCSI Adapter\n"); 440 else 441 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 442 "Ultra SCSI Adapter\n"); 443 444 /* 445 * Now tell the generic SCSI layer about our bus. 446 * map and establish interrupt 447 */ 448 if (pci_intr_map(pa, &ih)) { 449 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 450 return; 451 } 452 intrstr = pci_intr_string(pa->pa_pc, ih); 453 454 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 455 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 456 if (intrstr != NULL) 457 printf(" at %s", intrstr); 458 printf("\n"); 459 return; 460 } 461 if (intrstr != NULL) 462 printf("%s: interrupting at %s\n", 463 sc->sc_dev.dv_xname, intrstr); 464 465 sc->sc_adapter.adapt_dev = &sc->sc_dev; 466 sc->sc_adapter.adapt_nchannels = 1; 467 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 468 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 469 sc->sc_adapter.adapt_request = trm_scsipi_request; 470 sc->sc_adapter.adapt_minphys = minphys; 471 472 sc->sc_channel.chan_adapter = &sc->sc_adapter; 473 sc->sc_channel.chan_bustype = &scsi_bustype; 474 sc->sc_channel.chan_channel = 0; 475 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 476 sc->sc_channel.chan_nluns = 8; 477 sc->sc_channel.chan_id = sc->sc_id; 478 479 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 480 } 481 482 /* 483 * initialize the internal structures for a given SCSI host 484 */ 485 static int 486 trm_init(sc) 487 struct trm_softc *sc; 488 { 489 bus_space_tag_t iot = sc->sc_iot; 490 bus_space_handle_t ioh = sc->sc_ioh; 491 bus_dma_segment_t seg; 492 struct trm_nvram eeprom; 493 struct trm_srb *srb; 494 struct trm_tinfo *ti; 495 struct nvram_target *tconf; 496 int error, rseg, all_sgsize; 497 int i, target; 498 u_int8_t bval; 499 500 DPRINTF(("\n")); 501 502 /* 503 * allocate the space for all SCSI control blocks (SRB) for DMA memory 504 */ 505 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 506 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 507 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 508 printf(": unable to allocate SCSI REQUEST BLOCKS, " 509 "error = %d\n", error); 510 return (1); 511 } 512 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 513 all_sgsize, (caddr_t *) &sc->sc_sglist, 514 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 515 printf(": unable to map SCSI REQUEST BLOCKS, " 516 "error = %d\n", error); 517 return (1); 518 } 519 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 520 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 521 printf(": unable to create SRB DMA maps, " 522 "error = %d\n", error); 523 return (1); 524 } 525 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 526 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 527 printf(": unable to load SRB DMA maps, " 528 "error = %d\n", error); 529 return (1); 530 } 531 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 532 memset(sc->sc_sglist, 0, all_sgsize); 533 534 /* 535 * EEPROM CHECKSUM 536 */ 537 trm_check_eeprom(sc, &eeprom); 538 539 sc->sc_maxid = 7; 540 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 541 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 542 sc->sc_config |= HCC_WIDE_CARD; 543 sc->sc_maxid = 15; 544 } 545 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 546 sc->sc_config |= HCC_SCSI_RESET; 547 548 sc->sc_actsrb = NULL; 549 sc->sc_id = eeprom.scsi_id; 550 sc->sc_flag = 0; 551 552 /* 553 * initialize and link all device's SRB queues of this adapter 554 */ 555 TAILQ_INIT(&sc->sc_freesrb); 556 TAILQ_INIT(&sc->sc_readysrb); 557 558 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 559 M_DEVBUF, M_NOWAIT|M_ZERO); 560 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 561 if (sc->sc_srb == NULL) { 562 printf(": can not allocate SRB\n"); 563 return (1); 564 } 565 566 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 567 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 568 srb->sgoffset = TRM_SG_SIZE * i; 569 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 570 /* 571 * map all SRB space to SRB_array 572 */ 573 if (bus_dmamap_create(sc->sc_dmat, 574 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 575 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 576 printf(": unable to create DMA transfer map...\n"); 577 free(sc->sc_srb, M_DEVBUF); 578 return (1); 579 } 580 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 581 srb++; 582 } 583 584 /* 585 * initialize all target info structures 586 */ 587 for (target = 0; target < TRM_MAX_TARGETS; target++) { 588 ti = &sc->sc_tinfo[target]; 589 ti->synctl = 0; 590 ti->offset = 0; 591 tconf = &eeprom.target[target]; 592 ti->config0 = tconf->config0; 593 ti->period = trm_clock_period[tconf->period & 0x07]; 594 ti->flag = 0; 595 if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 596 (sc->sc_config & HCC_WIDE_CARD) != 0) 597 ti->flag |= WIDE_NEGO_ENABLE; 598 if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 599 ti->flag |= SYNC_NEGO_ENABLE; 600 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 601 #ifdef notyet 602 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 603 ti->flag |= USE_TAG_QUEUING; 604 #endif 605 } else 606 ti->flag |= NO_RESELECT; 607 608 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 609 target, ti->config0, ti->period)); 610 DPRINTF((", flag = 0x%02x\n", ti->flag)); 611 } 612 613 /* program configuration 0 */ 614 bval = PHASELATCH | INITIATOR | BLOCKRST; 615 if ((sc->sc_config & HCC_PARITY) != 0) 616 bval |= PARITYCHECK; 617 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 618 619 /* program configuration 1 */ 620 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 621 ACTIVE_NEG | ACTIVE_NEGPLUS); 622 623 /* 250ms selection timeout */ 624 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 625 626 /* Mask all interrupts */ 627 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 628 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 629 630 /* Reset SCSI module */ 631 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 632 633 /* program Host ID */ 634 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 635 636 /* set asynchronous transfer */ 637 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 638 639 /* Turn LED control off */ 640 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 641 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 642 643 /* DMA config */ 644 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 645 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 646 647 /* Clear pending interrupt status */ 648 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 649 650 /* Enable SCSI interrupt */ 651 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 652 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 653 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 654 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 655 656 trm_reset(sc); 657 658 return (0); 659 } 660 661 /* 662 * enqueues a SCSI command 663 * called by the higher level SCSI driver 664 */ 665 static void 666 trm_scsipi_request(chan, req, arg) 667 struct scsipi_channel *chan; 668 scsipi_adapter_req_t req; 669 void *arg; 670 { 671 bus_space_tag_t iot; 672 bus_space_handle_t ioh; 673 struct trm_softc *sc; 674 struct trm_srb *srb; 675 struct scsipi_xfer *xs; 676 int error, i, target, lun, s; 677 678 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 679 iot = sc->sc_iot; 680 ioh = sc->sc_ioh; 681 682 switch (req) { 683 case ADAPTER_REQ_RUN_XFER: 684 xs = arg; 685 target = xs->xs_periph->periph_target; 686 lun = xs->xs_periph->periph_lun; 687 DPRINTF(("trm_scsipi_request.....\n")); 688 DPRINTF(("target= %d lun= %d\n", target, lun)); 689 if (xs->xs_control & XS_CTL_RESET) { 690 trm_reset(sc); 691 xs->error = XS_NOERROR | XS_RESET; 692 return; 693 } 694 if (xs->xs_status & XS_STS_DONE) { 695 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 696 xs->xs_status &= ~XS_STS_DONE; 697 } 698 699 s = splbio(); 700 701 /* Get SRB */ 702 srb = TAILQ_FIRST(&sc->sc_freesrb); 703 if (srb != NULL) { 704 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 705 } else { 706 xs->error = XS_RESOURCE_SHORTAGE; 707 scsipi_done(xs); 708 splx(s); 709 return; 710 } 711 712 srb->xs = xs; 713 srb->cmdlen = xs->cmdlen; 714 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 715 716 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 717 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 718 xs->data, xs->datalen, NULL, 719 ((xs->xs_control & XS_CTL_NOSLEEP) ? 720 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 721 BUS_DMA_STREAMING | 722 ((xs->xs_control & XS_CTL_DATA_IN) ? 723 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 724 printf("%s: DMA transfer map unable to load, " 725 "error = %d\n", sc->sc_dev.dv_xname, error); 726 xs->error = XS_DRIVER_STUFFUP; 727 /* 728 * free SRB 729 */ 730 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 731 splx(s); 732 return; 733 } 734 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 735 srb->dmap->dm_mapsize, 736 (xs->xs_control & XS_CTL_DATA_IN) ? 737 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 738 739 /* Set up the scatter gather list */ 740 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 741 srb->sgentry[i].address = 742 htole32(srb->dmap->dm_segs[i].ds_addr); 743 srb->sgentry[i].length = 744 htole32(srb->dmap->dm_segs[i].ds_len); 745 } 746 srb->buflen = xs->datalen; 747 srb->sgcnt = srb->dmap->dm_nsegs; 748 } else { 749 srb->sgentry[0].address = 0; 750 srb->sgentry[0].length = 0; 751 srb->buflen = 0; 752 srb->sgcnt = 0; 753 } 754 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 755 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 756 757 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 758 759 srb->sgindex = 0; 760 srb->hastat = 0; 761 srb->tastat = 0; 762 srb->flag = 0; 763 764 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 765 if (sc->sc_actsrb == NULL) 766 trm_sched(sc); 767 splx(s); 768 769 if ((xs->xs_control & XS_CTL_POLL) != 0) { 770 int timeout = xs->timeout; 771 772 s = splbio(); 773 do { 774 while (--timeout) { 775 DELAY(1000); 776 if (bus_space_read_2(iot, ioh, 777 TRM_SCSI_STATUS) & SCSIINTERRUPT) 778 break; 779 } 780 if (timeout == 0) { 781 trm_timeout(srb); 782 break; 783 } else 784 trm_intr(sc); 785 } while ((xs->xs_status & XS_STS_DONE) == 0); 786 splx(s); 787 } 788 return; 789 790 case ADAPTER_REQ_GROW_RESOURCES: 791 /* XXX Not supported. */ 792 return; 793 794 case ADAPTER_REQ_SET_XFER_MODE: 795 { 796 struct trm_tinfo *ti; 797 struct scsipi_xfer_mode *xm; 798 799 xm = arg; 800 ti = &sc->sc_tinfo[xm->xm_target]; 801 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 802 803 #ifdef notyet 804 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 805 ti->flag |= USE_TAG_QUEUING; 806 else 807 #endif 808 ti->flag &= ~USE_TAG_QUEUING; 809 810 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 811 ti->flag |= WIDE_NEGO_ENABLE; 812 ti->flag &= ~WIDE_NEGO_DONE; 813 } 814 815 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 816 ti->flag |= SYNC_NEGO_ENABLE; 817 ti->flag &= ~SYNC_NEGO_DONE; 818 ti->period = trm_clock_period[0]; 819 } 820 821 /* 822 * If we're not going to negotiate, send the 823 * notification now, since it won't happen later. 824 */ 825 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 826 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 827 trm_update_xfer_mode(sc, xm->xm_target); 828 829 return; 830 } 831 } 832 } 833 834 static void 835 trm_update_xfer_mode(sc, target) 836 struct trm_softc *sc; 837 int target; 838 { 839 struct scsipi_xfer_mode xm; 840 struct trm_tinfo *ti; 841 842 ti = &sc->sc_tinfo[target]; 843 xm.xm_target = target; 844 xm.xm_mode = 0; 845 xm.xm_period = 0; 846 xm.xm_offset = 0; 847 848 if ((ti->synctl & WIDE_SYNC) != 0) 849 xm.xm_mode |= PERIPH_CAP_WIDE16; 850 851 if (ti->period > 0) { 852 xm.xm_mode |= PERIPH_CAP_SYNC; 853 xm.xm_period = ti->period; 854 xm.xm_offset = ti->offset; 855 } 856 857 #ifdef notyet 858 if ((ti->flag & USE_TAG_QUEUING) != 0) 859 xm.xm_mode |= PERIPH_CAP_TQING; 860 #endif 861 862 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 863 } 864 865 static void 866 trm_sched(sc) 867 struct trm_softc *sc; 868 { 869 struct trm_srb *srb; 870 struct scsipi_periph *periph; 871 struct trm_tinfo *ti; 872 struct trm_linfo *li; 873 int s, lun, tag; 874 875 DPRINTF(("trm_sched...\n")); 876 877 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 878 periph = srb->xs->xs_periph; 879 ti = &sc->sc_tinfo[periph->periph_target]; 880 lun = periph->periph_lun; 881 882 /* select type of tag for this command */ 883 if ((ti->flag & NO_RESELECT) != 0 || 884 (ti->flag & USE_TAG_QUEUING) == 0 || 885 (srb->flag & AUTO_REQSENSE) != 0 || 886 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 887 tag = 0; 888 else 889 tag = srb->xs->xs_tag_type; 890 #if 0 891 /* XXX use tags for polled commands? */ 892 if (srb->xs->xs_control & XS_CTL_POLL) 893 tag = 0; 894 #endif 895 896 s = splbio(); 897 li = ti->linfo[lun]; 898 if (li == NULL) { 899 /* initialize lun info */ 900 if ((li = malloc(sizeof(*li), M_DEVBUF, 901 M_NOWAIT|M_ZERO)) == NULL) { 902 splx(s); 903 continue; 904 } 905 ti->linfo[lun] = li; 906 } 907 908 if (tag == 0) { 909 /* try to issue this srb as an un-tagged command */ 910 if (li->untagged == NULL) 911 li->untagged = srb; 912 } 913 if (li->untagged != NULL) { 914 tag = 0; 915 if (li->busy != 1 && li->used == 0) { 916 /* we need to issue the untagged command now */ 917 srb = li->untagged; 918 periph = srb->xs->xs_periph; 919 } else { 920 /* not ready yet */ 921 splx(s); 922 continue; 923 } 924 } 925 srb->tag[0] = tag; 926 if (tag != 0) { 927 li->queued[srb->xs->xs_tag_id] = srb; 928 srb->tag[1] = srb->xs->xs_tag_id; 929 li->used++; 930 } 931 932 if (li->untagged != NULL && li->busy != 1) { 933 li->busy = 1; 934 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 935 sc->sc_actsrb = srb; 936 trm_select(sc, srb); 937 splx(s); 938 break; 939 } 940 if (li->untagged == NULL && tag != 0) { 941 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 942 sc->sc_actsrb = srb; 943 trm_select(sc, srb); 944 splx(s); 945 break; 946 } else 947 splx(s); 948 } 949 } 950 951 static int 952 trm_select(sc, srb) 953 struct trm_softc *sc; 954 struct trm_srb *srb; 955 { 956 bus_space_tag_t iot = sc->sc_iot; 957 bus_space_handle_t ioh = sc->sc_ioh; 958 struct scsipi_periph *periph = srb->xs->xs_periph; 959 int target = periph->periph_target; 960 int lun = periph->periph_lun; 961 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 962 u_int8_t scsicmd; 963 964 DPRINTF(("trm_select.....\n")); 965 966 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 967 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 968 trm_timeout, srb); 969 } 970 971 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 972 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 973 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 974 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 975 /* Flush FIFO */ 976 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 977 DELAY(10); 978 979 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 980 981 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 982 983 if (((ti->flag & WIDE_NEGO_ENABLE) && 984 (ti->flag & WIDE_NEGO_DONE) == 0) || 985 ((ti->flag & SYNC_NEGO_ENABLE) && 986 (ti->flag & SYNC_NEGO_DONE) == 0)) { 987 sc->sc_state = TRM_MSGOUT; 988 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 989 MSG_IDENTIFY(lun, 0)); 990 bus_space_write_multi_1(iot, ioh, 991 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 992 /* it's important for atn stop */ 993 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 994 DO_DATALATCH | DO_HWRESELECT); 995 /* SCSI command */ 996 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 997 DPRINTF(("select with SEL_ATNSTOP\n")); 998 return (0); 999 } 1000 1001 if (srb->tag[0] != 0) { 1002 /* Send identify message */ 1003 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1004 MSG_IDENTIFY(lun, 1)); 1005 /* Send Tag id */ 1006 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1007 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1008 scsicmd = SCMD_SEL_ATN3; 1009 DPRINTF(("select with SEL_ATN3\n")); 1010 } else { 1011 /* Send identify message */ 1012 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1013 MSG_IDENTIFY(lun, 1014 (ti->flag & NO_RESELECT) == 0 && 1015 (srb->flag & AUTO_REQSENSE) == 0 && 1016 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1017 scsicmd = SCMD_SEL_ATN; 1018 DPRINTF(("select with SEL_ATN\n")); 1019 } 1020 sc->sc_state = TRM_START; 1021 1022 /* 1023 * Send CDB ..command block... 1024 */ 1025 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1026 1027 /* 1028 * If trm_select returns 0: current interrupt status 1029 * is interrupt enable. It's said that SCSI processor is 1030 * unoccupied. 1031 */ 1032 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1033 /* SCSI command */ 1034 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1035 return (0); 1036 } 1037 1038 /* 1039 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1040 */ 1041 static void 1042 trm_reset(sc) 1043 struct trm_softc *sc; 1044 { 1045 bus_space_tag_t iot = sc->sc_iot; 1046 bus_space_handle_t ioh = sc->sc_ioh; 1047 int s; 1048 1049 DPRINTF(("trm_reset.........\n")); 1050 1051 s = splbio(); 1052 1053 /* disable SCSI and DMA interrupt */ 1054 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1055 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1056 1057 trm_reset_scsi_bus(sc); 1058 DELAY(100000); 1059 1060 /* Enable SCSI interrupt */ 1061 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1062 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1063 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1064 1065 /* Enable DMA interrupt */ 1066 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1067 1068 /* Clear DMA FIFO */ 1069 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1070 1071 /* Clear SCSI FIFO */ 1072 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1073 1074 sc->sc_actsrb = NULL; 1075 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1076 1077 splx(s); 1078 } 1079 1080 static void 1081 trm_timeout(arg) 1082 void *arg; 1083 { 1084 struct trm_srb *srb = (struct trm_srb *)arg; 1085 struct scsipi_xfer *xs = srb->xs; 1086 struct scsipi_periph *periph = xs->xs_periph; 1087 struct trm_softc *sc; 1088 int s; 1089 1090 if (xs == NULL) 1091 printf("trm_timeout called with xs == NULL\n"); 1092 1093 else { 1094 scsipi_printaddr(xs->xs_periph); 1095 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1096 } 1097 1098 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1099 1100 trm_reset_scsi_bus(sc); 1101 s = splbio(); 1102 srb->flag |= SRB_TIMEOUT; 1103 trm_done(sc, srb); 1104 /* XXX needs more.. */ 1105 splx(s); 1106 } 1107 1108 /* 1109 * Catch an interrupt from the adapter 1110 * Process pending device interrupts. 1111 */ 1112 static int 1113 trm_intr(arg) 1114 void *arg; 1115 { 1116 bus_space_tag_t iot; 1117 bus_space_handle_t ioh; 1118 struct trm_softc *sc; 1119 struct trm_srb *srb; 1120 int intstat, stat; 1121 1122 DPRINTF(("trm_intr......\n")); 1123 sc = (struct trm_softc *)arg; 1124 if (sc == NULL) 1125 return (0); 1126 1127 iot = sc->sc_iot; 1128 ioh = sc->sc_ioh; 1129 1130 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1131 if ((stat & SCSIINTERRUPT) == 0) 1132 return (0); 1133 1134 DPRINTF(("stat = %04x, ", stat)); 1135 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1136 1137 DPRINTF(("intstat=%02x, ", intstat)); 1138 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1139 DPRINTF(("\n")); 1140 trm_disconnect(sc); 1141 return (1); 1142 } 1143 if (intstat & INT_RESELECTED) { 1144 DPRINTF(("\n")); 1145 trm_reselect(sc); 1146 return (1); 1147 } 1148 if (intstat & INT_SCSIRESET) { 1149 DPRINTF(("\n")); 1150 trm_scsi_reset_detect(sc); 1151 return (1); 1152 } 1153 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1154 srb = sc->sc_actsrb; 1155 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1156 sc->sc_phase, sc->sc_state)); 1157 /* 1158 * software sequential machine 1159 */ 1160 1161 /* 1162 * call phase0 functions... "phase entry" handle 1163 * every phase before start transfer 1164 */ 1165 switch (sc->sc_phase) { 1166 case PH_DATA_OUT: 1167 trm_dataout_phase0(sc, stat); 1168 break; 1169 case PH_DATA_IN: 1170 trm_datain_phase0(sc, stat); 1171 break; 1172 case PH_COMMAND: 1173 break; 1174 case PH_STATUS: 1175 trm_status_phase0(sc); 1176 stat = PH_BUS_FREE; 1177 break; 1178 case PH_MSG_OUT: 1179 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1180 sc->sc_state == TRM_ABORT_SENT) 1181 stat = PH_BUS_FREE; 1182 break; 1183 case PH_MSG_IN: 1184 trm_msgin_phase0(sc); 1185 stat = PH_BUS_FREE; 1186 break; 1187 case PH_BUS_FREE: 1188 break; 1189 default: 1190 printf("%s: unexpected phase in trm_intr() phase0\n", 1191 sc->sc_dev.dv_xname); 1192 break; 1193 } 1194 1195 sc->sc_phase = stat & PHASEMASK; 1196 1197 switch (sc->sc_phase) { 1198 case PH_DATA_OUT: 1199 trm_dataio_xfer(sc, XFERDATAOUT); 1200 break; 1201 case PH_DATA_IN: 1202 trm_dataio_xfer(sc, XFERDATAIN); 1203 break; 1204 case PH_COMMAND: 1205 trm_command_phase1(sc); 1206 break; 1207 case PH_STATUS: 1208 trm_status_phase1(sc); 1209 break; 1210 case PH_MSG_OUT: 1211 trm_msgout_phase1(sc); 1212 break; 1213 case PH_MSG_IN: 1214 trm_msgin_phase1(sc); 1215 break; 1216 case PH_BUS_FREE: 1217 break; 1218 default: 1219 printf("%s: unexpected phase in trm_intr() phase1\n", 1220 sc->sc_dev.dv_xname); 1221 break; 1222 } 1223 1224 return (1); 1225 } 1226 return (0); 1227 } 1228 1229 static void 1230 trm_msgout_phase1(sc) 1231 struct trm_softc *sc; 1232 { 1233 bus_space_tag_t iot = sc->sc_iot; 1234 bus_space_handle_t ioh = sc->sc_ioh; 1235 struct trm_srb *srb; 1236 struct scsipi_periph *periph; 1237 struct trm_tinfo *ti; 1238 1239 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1240 1241 srb = sc->sc_actsrb; 1242 1243 /* message out phase */ 1244 if (srb != NULL) { 1245 periph = srb->xs->xs_periph; 1246 ti = &sc->sc_tinfo[periph->periph_target]; 1247 1248 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1249 (ti->flag & WIDE_NEGO_ENABLE)) { 1250 /* send WDTR */ 1251 ti->flag &= ~SYNC_NEGO_DONE; 1252 1253 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1254 sc->sc_msgbuf[1] = MSG_EXTENDED; 1255 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1256 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1257 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1258 sc->sc_msgcnt = 5; 1259 1260 ti->flag |= WIDE_NEGO_DOING; 1261 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1262 (ti->flag & SYNC_NEGO_ENABLE)) { 1263 /* send SDTR */ 1264 int cnt = 0; 1265 1266 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1267 sc->sc_msgbuf[cnt++] = 1268 MSG_IDENTIFY(periph->periph_lun, 0); 1269 1270 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1271 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1272 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1273 sc->sc_msgbuf[cnt++] = ti->period; 1274 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1275 sc->sc_msgcnt = cnt; 1276 ti->flag |= SYNC_NEGO_DOING; 1277 } 1278 } 1279 if (sc->sc_msgcnt == 0) { 1280 sc->sc_msgbuf[0] = MSG_ABORT; 1281 sc->sc_msgcnt = 1; 1282 sc->sc_state = TRM_ABORT_SENT; 1283 } 1284 1285 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1286 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1287 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1288 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1289 1290 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1291 sc->sc_msgbuf, sc->sc_msgcnt); 1292 sc->sc_msgcnt = 0; 1293 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1294 1295 /* it's important for atn stop */ 1296 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1297 1298 /* 1299 * SCSI command 1300 */ 1301 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1302 } 1303 1304 static void 1305 trm_command_phase1(sc) 1306 struct trm_softc *sc; 1307 { 1308 bus_space_tag_t iot = sc->sc_iot; 1309 bus_space_handle_t ioh = sc->sc_ioh; 1310 struct trm_srb *srb; 1311 1312 srb = sc->sc_actsrb; 1313 if (srb == NULL) { 1314 DPRINTF(("trm_command_phase1: no active srb\n")); 1315 return; 1316 } 1317 1318 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1319 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1320 1321 sc->sc_state = TRM_COMMAND; 1322 /* it's important for atn stop */ 1323 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1324 1325 /* 1326 * SCSI command 1327 */ 1328 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1329 } 1330 1331 static void 1332 trm_dataout_phase0(sc, stat) 1333 struct trm_softc *sc; 1334 int stat; 1335 { 1336 bus_space_tag_t iot = sc->sc_iot; 1337 bus_space_handle_t ioh = sc->sc_ioh; 1338 struct trm_srb *srb; 1339 struct scsipi_periph *periph; 1340 struct trm_tinfo *ti; 1341 struct trm_sg_entry *sg; 1342 int sgindex; 1343 u_int32_t xferlen, leftcnt = 0; 1344 1345 if (sc->sc_state == TRM_XFERPAD) 1346 return; 1347 1348 srb = sc->sc_actsrb; 1349 if (srb == NULL) { 1350 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1351 return; 1352 } 1353 periph = srb->xs->xs_periph; 1354 ti = &sc->sc_tinfo[periph->periph_target]; 1355 1356 if ((stat & PARITYERROR) != 0) 1357 srb->flag |= PARITY_ERROR; 1358 1359 if ((stat & SCSIXFERDONE) == 0) { 1360 /* 1361 * when data transfer from DMA FIFO to SCSI FIFO 1362 * if there was some data left in SCSI FIFO 1363 */ 1364 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1365 SCSI_FIFOCNT_MASK; 1366 if (ti->synctl & WIDE_SYNC) 1367 /* 1368 * if WIDE scsi SCSI FIFOCNT unit is word 1369 * so need to * 2 1370 */ 1371 leftcnt <<= 1; 1372 } 1373 /* 1374 * calculate all the residue data that was not yet transferred 1375 * SCSI transfer counter + left in SCSI FIFO data 1376 * 1377 * .....TRM_SCSI_XCNT (24bits) 1378 * The counter always decrements by one for every SCSI 1379 * byte transfer. 1380 * .....TRM_SCSI_FIFOCNT ( 5bits) 1381 * The counter is SCSI FIFO offset counter 1382 */ 1383 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1384 if (leftcnt == 1) { 1385 leftcnt = 0; 1386 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1387 } 1388 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1389 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1390 DMAXFERCOMP) == 0) 1391 ; /* XXX needs timeout */ 1392 1393 srb->buflen = 0; 1394 } else { 1395 /* Update SG list */ 1396 1397 /* 1398 * if transfer not yet complete 1399 * there were some data residue in SCSI FIFO or 1400 * SCSI transfer counter not empty 1401 */ 1402 if (srb->buflen != leftcnt) { 1403 /* data that had transferred length */ 1404 xferlen = srb->buflen - leftcnt; 1405 1406 /* next time to be transferred length */ 1407 srb->buflen = leftcnt; 1408 1409 /* 1410 * parsing from last time disconnect sgindex 1411 */ 1412 sg = srb->sgentry + srb->sgindex; 1413 for (sgindex = srb->sgindex; 1414 sgindex < srb->sgcnt; 1415 sgindex++, sg++) { 1416 /* 1417 * find last time which SG transfer 1418 * be disconnect 1419 */ 1420 if (xferlen >= le32toh(sg->length)) 1421 xferlen -= le32toh(sg->length); 1422 else { 1423 /* 1424 * update last time 1425 * disconnected SG list 1426 */ 1427 /* residue data length */ 1428 sg->length = 1429 htole32(le32toh(sg->length) 1430 - xferlen); 1431 /* residue data pointer */ 1432 sg->address = 1433 htole32(le32toh(sg->address) 1434 + xferlen); 1435 srb->sgindex = sgindex; 1436 break; 1437 } 1438 } 1439 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1440 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1441 } 1442 } 1443 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1444 } 1445 1446 static void 1447 trm_datain_phase0(sc, stat) 1448 struct trm_softc *sc; 1449 int stat; 1450 { 1451 bus_space_tag_t iot = sc->sc_iot; 1452 bus_space_handle_t ioh = sc->sc_ioh; 1453 struct trm_srb *srb; 1454 struct trm_sg_entry *sg; 1455 int sgindex; 1456 u_int32_t xferlen, leftcnt = 0; 1457 1458 if (sc->sc_state == TRM_XFERPAD) 1459 return; 1460 1461 srb = sc->sc_actsrb; 1462 if (srb == NULL) { 1463 DPRINTF(("trm_datain_phase0: no active srb\n")); 1464 return; 1465 } 1466 1467 if (stat & PARITYERROR) 1468 srb->flag |= PARITY_ERROR; 1469 1470 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1471 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1472 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1473 DMAXFERCOMP) == 0) 1474 ; /* XXX needs timeout */ 1475 1476 srb->buflen = 0; 1477 } else { /* phase changed */ 1478 /* 1479 * parsing the case: 1480 * when a transfer not yet complete 1481 * but be disconnected by upper layer 1482 * if transfer not yet complete 1483 * there were some data residue in SCSI FIFO or 1484 * SCSI transfer counter not empty 1485 */ 1486 if (srb->buflen != leftcnt) { 1487 /* 1488 * data that had transferred length 1489 */ 1490 xferlen = srb->buflen - leftcnt; 1491 1492 /* 1493 * next time to be transferred length 1494 */ 1495 srb->buflen = leftcnt; 1496 1497 /* 1498 * parsing from last time disconnect sgindex 1499 */ 1500 sg = srb->sgentry + srb->sgindex; 1501 for (sgindex = srb->sgindex; 1502 sgindex < srb->sgcnt; 1503 sgindex++, sg++) { 1504 /* 1505 * find last time which SG transfer 1506 * be disconnect 1507 */ 1508 if (xferlen >= le32toh(sg->length)) 1509 xferlen -= le32toh(sg->length); 1510 else { 1511 /* 1512 * update last time 1513 * disconnected SG list 1514 */ 1515 /* residue data length */ 1516 sg->length = 1517 htole32(le32toh(sg->length) 1518 - xferlen); 1519 /* residue data pointer */ 1520 sg->address = 1521 htole32(le32toh(sg->address) 1522 + xferlen); 1523 srb->sgindex = sgindex; 1524 break; 1525 } 1526 } 1527 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1528 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1529 } 1530 } 1531 } 1532 1533 static void 1534 trm_dataio_xfer(sc, iodir) 1535 struct trm_softc *sc; 1536 int iodir; 1537 { 1538 bus_space_tag_t iot = sc->sc_iot; 1539 bus_space_handle_t ioh = sc->sc_ioh; 1540 struct trm_srb *srb; 1541 struct scsipi_periph *periph; 1542 struct trm_tinfo *ti; 1543 1544 srb = sc->sc_actsrb; 1545 if (srb == NULL) { 1546 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1547 return; 1548 } 1549 periph = srb->xs->xs_periph; 1550 ti = &sc->sc_tinfo[periph->periph_target]; 1551 1552 if (srb->sgindex < srb->sgcnt) { 1553 if (srb->buflen > 0) { 1554 /* 1555 * load what physical address of Scatter/Gather 1556 * list table want to be transfer 1557 */ 1558 sc->sc_state = TRM_DATA_XFER; 1559 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1560 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1561 srb->sgaddr + 1562 srb->sgindex * sizeof(struct trm_sg_entry)); 1563 /* 1564 * load how many bytes in the Scatter/Gather list table 1565 */ 1566 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1567 (srb->sgcnt - srb->sgindex) 1568 * sizeof(struct trm_sg_entry)); 1569 /* 1570 * load total xfer length (24bits) max value 16Mbyte 1571 */ 1572 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1573 /* Start DMA transfer */ 1574 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1575 iodir | SGXFER); 1576 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1577 STARTDMAXFER); 1578 1579 /* Start SCSI transfer */ 1580 /* it's important for atn stop */ 1581 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1582 DO_DATALATCH); 1583 1584 /* 1585 * SCSI command 1586 */ 1587 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1588 (iodir == XFERDATAOUT) ? 1589 SCMD_DMA_OUT : SCMD_DMA_IN); 1590 } else { /* xfer pad */ 1591 if (srb->sgcnt) { 1592 srb->hastat = H_OVER_UNDER_RUN; 1593 } 1594 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1595 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1596 1597 if (iodir == XFERDATAOUT) 1598 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1599 else 1600 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1601 1602 sc->sc_state = TRM_XFERPAD; 1603 /* it's important for atn stop */ 1604 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1605 DO_DATALATCH); 1606 1607 /* 1608 * SCSI command 1609 */ 1610 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1611 (iodir == XFERDATAOUT) ? 1612 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1613 } 1614 } 1615 } 1616 1617 static void 1618 trm_status_phase0(sc) 1619 struct trm_softc *sc; 1620 { 1621 bus_space_tag_t iot = sc->sc_iot; 1622 bus_space_handle_t ioh = sc->sc_ioh; 1623 struct trm_srb *srb; 1624 1625 srb = sc->sc_actsrb; 1626 if (srb == NULL) { 1627 DPRINTF(("trm_status_phase0: no active srb\n")); 1628 return; 1629 } 1630 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1631 sc->sc_state = TRM_COMPLETED; 1632 /* it's important for atn stop */ 1633 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1634 1635 /* 1636 * SCSI command 1637 */ 1638 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1639 } 1640 1641 static void 1642 trm_status_phase1(sc) 1643 struct trm_softc *sc; 1644 { 1645 bus_space_tag_t iot = sc->sc_iot; 1646 bus_space_handle_t ioh = sc->sc_ioh; 1647 1648 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1649 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1650 & SCSI_FIFO_EMPTY) == 0) 1651 bus_space_write_2(iot, ioh, 1652 TRM_SCSI_CONTROL, DO_CLRFIFO); 1653 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1654 & DMA_FIFO_EMPTY) == 0) 1655 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1656 } else { 1657 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1658 & DMA_FIFO_EMPTY) == 0) 1659 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1660 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1661 & SCSI_FIFO_EMPTY) == 0) 1662 bus_space_write_2(iot, ioh, 1663 TRM_SCSI_CONTROL, DO_CLRFIFO); 1664 } 1665 sc->sc_state = TRM_STATUS; 1666 /* it's important for atn stop */ 1667 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1668 1669 /* 1670 * SCSI command 1671 */ 1672 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1673 } 1674 1675 static void 1676 trm_msgin_phase0(sc) 1677 struct trm_softc *sc; 1678 { 1679 bus_space_tag_t iot = sc->sc_iot; 1680 bus_space_handle_t ioh = sc->sc_ioh; 1681 struct trm_srb *srb; 1682 struct scsipi_periph *periph; 1683 struct trm_tinfo *ti; 1684 int index; 1685 u_int8_t msgin_code; 1686 1687 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1688 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1689 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1690 switch (msgin_code) { 1691 case MSG_DISCONNECT: 1692 sc->sc_state = TRM_DISCONNECTED; 1693 break; 1694 1695 case MSG_SAVEDATAPOINTER: 1696 break; 1697 1698 case MSG_EXTENDED: 1699 case MSG_SIMPLE_Q_TAG: 1700 case MSG_HEAD_OF_Q_TAG: 1701 case MSG_ORDERED_Q_TAG: 1702 sc->sc_state = TRM_EXTEND_MSGIN; 1703 /* extended message (01h) */ 1704 sc->sc_msgbuf[0] = msgin_code; 1705 1706 sc->sc_msgcnt = 1; 1707 /* extended message length (n) */ 1708 sc->sc_msg = &sc->sc_msgbuf[1]; 1709 1710 break; 1711 case MSG_MESSAGE_REJECT: 1712 /* Reject message */ 1713 srb = sc->sc_actsrb; 1714 if (srb == NULL) { 1715 DPRINTF(("trm_msgin_phase0: " 1716 " message reject without actsrb\n")); 1717 break; 1718 } 1719 periph = srb->xs->xs_periph; 1720 ti = &sc->sc_tinfo[periph->periph_target]; 1721 1722 if (ti->flag & WIDE_NEGO_ENABLE) { 1723 /* do wide nego reject */ 1724 ti->flag |= WIDE_NEGO_DONE; 1725 ti->flag &= 1726 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1727 if ((ti->flag & SYNC_NEGO_ENABLE) && 1728 (ti->flag & SYNC_NEGO_DONE) == 0) { 1729 /* Set ATN, in case ATN was clear */ 1730 sc->sc_state = TRM_MSGOUT; 1731 bus_space_write_2(iot, ioh, 1732 TRM_SCSI_CONTROL, DO_SETATN); 1733 } else 1734 /* Clear ATN */ 1735 bus_space_write_2(iot, ioh, 1736 TRM_SCSI_CONTROL, DO_CLRATN); 1737 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1738 /* do sync nego reject */ 1739 bus_space_write_2(iot, ioh, 1740 TRM_SCSI_CONTROL, DO_CLRATN); 1741 if (ti->flag & SYNC_NEGO_DOING) { 1742 ti->flag &=~(SYNC_NEGO_ENABLE | 1743 SYNC_NEGO_DONE); 1744 ti->synctl = 0; 1745 ti->offset = 0; 1746 bus_space_write_1(iot, ioh, 1747 TRM_SCSI_SYNC, ti->synctl); 1748 bus_space_write_1(iot, ioh, 1749 TRM_SCSI_OFFSET, ti->offset); 1750 } 1751 } 1752 break; 1753 1754 case MSG_IGN_WIDE_RESIDUE: 1755 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1756 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1757 break; 1758 1759 default: 1760 /* 1761 * Restore data pointer message 1762 * Save data pointer message 1763 * Completion message 1764 * NOP message 1765 */ 1766 break; 1767 } 1768 } else { 1769 /* 1770 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1771 * Parsing incoming extented messages 1772 */ 1773 *sc->sc_msg++ = msgin_code; 1774 sc->sc_msgcnt++; 1775 1776 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1777 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1778 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1779 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1780 1781 switch (sc->sc_msgbuf[0]) { 1782 case MSG_SIMPLE_Q_TAG: 1783 case MSG_HEAD_OF_Q_TAG: 1784 case MSG_ORDERED_Q_TAG: 1785 /* 1786 * is QUEUE tag message : 1787 * 1788 * byte 0: 1789 * HEAD QUEUE TAG (20h) 1790 * ORDERED QUEUE TAG (21h) 1791 * SIMPLE QUEUE TAG (22h) 1792 * byte 1: 1793 * Queue tag (00h - FFh) 1794 */ 1795 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1796 /* XXX XXX XXX */ 1797 struct trm_linfo *li; 1798 int tagid; 1799 1800 sc->sc_flag &= ~WAIT_TAGMSG; 1801 tagid = sc->sc_msgbuf[1]; 1802 ti = &sc->sc_tinfo[sc->resel_target]; 1803 li = ti->linfo[sc->resel_lun]; 1804 srb = li->queued[tagid]; 1805 if (srb != NULL) { 1806 sc->sc_actsrb = srb; 1807 sc->sc_state = TRM_DATA_XFER; 1808 break; 1809 } else { 1810 printf("%s: invalid tag id\n", 1811 sc->sc_dev.dv_xname); 1812 } 1813 1814 sc->sc_state = TRM_UNEXPECT_RESEL; 1815 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1816 sc->sc_msgcnt = 1; 1817 bus_space_write_2(iot, ioh, 1818 TRM_SCSI_CONTROL, DO_SETATN); 1819 } else 1820 sc->sc_state = TRM_IDLE; 1821 break; 1822 1823 case MSG_EXTENDED: 1824 srb = sc->sc_actsrb; 1825 if (srb == NULL) { 1826 DPRINTF(("trm_msgin_phase0: " 1827 "extended message without actsrb\n")); 1828 break; 1829 } 1830 periph = srb->xs->xs_periph; 1831 ti = &sc->sc_tinfo[periph->periph_target]; 1832 1833 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1834 sc->sc_msgcnt == 4) { 1835 /* 1836 * is Wide data xfer Extended message : 1837 * ====================================== 1838 * WIDE DATA TRANSFER REQUEST 1839 * ====================================== 1840 * byte 0 : Extended message (01h) 1841 * byte 1 : Extended message length (02h) 1842 * byte 2 : WIDE DATA TRANSFER code (03h) 1843 * byte 3 : Transfer width exponent 1844 */ 1845 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1846 /* Length is wrong, reject it */ 1847 ti->flag &= ~(WIDE_NEGO_ENABLE | 1848 WIDE_NEGO_DONE); 1849 sc->sc_state = TRM_MSGOUT; 1850 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1851 sc->sc_msgcnt = 1; 1852 bus_space_write_2(iot, ioh, 1853 TRM_SCSI_CONTROL, DO_SETATN); 1854 break; 1855 } 1856 1857 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1858 sc->sc_msgbuf[3] = 1859 MSG_EXT_WDTR_BUS_8_BIT; 1860 1861 if (sc->sc_msgbuf[3] > 1862 MSG_EXT_WDTR_BUS_32_BIT) { 1863 /* reject_msg: */ 1864 ti->flag &= ~(WIDE_NEGO_ENABLE | 1865 WIDE_NEGO_DONE); 1866 sc->sc_state = TRM_MSGOUT; 1867 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1868 sc->sc_msgcnt = 1; 1869 bus_space_write_2(iot, ioh, 1870 TRM_SCSI_CONTROL, DO_SETATN); 1871 break; 1872 } 1873 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1874 /* do 16 bits */ 1875 sc->sc_msgbuf[3] = 1876 MSG_EXT_WDTR_BUS_16_BIT; 1877 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1878 ti->flag |= WIDE_NEGO_DONE; 1879 ti->flag &= ~(SYNC_NEGO_DONE | 1880 WIDE_NEGO_ENABLE); 1881 if (sc->sc_msgbuf[3] != 1882 MSG_EXT_WDTR_BUS_8_BIT) 1883 /* is Wide data xfer */ 1884 ti->synctl |= WIDE_SYNC; 1885 trm_update_xfer_mode(sc, 1886 periph->periph_target); 1887 } 1888 1889 sc->sc_state = TRM_MSGOUT; 1890 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1891 DO_SETATN); 1892 break; 1893 1894 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1895 sc->sc_msgcnt == 5) { 1896 /* 1897 * is 8bit transfer Extended message : 1898 * ================================= 1899 * SYNCHRONOUS DATA TRANSFER REQUEST 1900 * ================================= 1901 * byte 0 : Extended message (01h) 1902 * byte 1 : Extended message length (03) 1903 * byte 2 : SYNC DATA TRANSFER code (01h) 1904 * byte 3 : Transfer period factor 1905 * byte 4 : REQ/ACK offset 1906 */ 1907 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1908 /* reject_msg */ 1909 sc->sc_state = TRM_MSGOUT; 1910 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1911 sc->sc_msgcnt = 1; 1912 bus_space_write_2(iot, ioh, 1913 TRM_SCSI_CONTROL, DO_SETATN); 1914 break; 1915 } 1916 1917 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1918 ti->flag &= 1919 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1920 ti->flag |= SYNC_NEGO_DONE; 1921 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1922 sc->sc_msgbuf[3] = 0; 1923 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1924 sc->sc_msgbuf[4] = 1925 TRM_MAX_OFFSET; 1926 1927 if (sc->sc_msgbuf[3] == 0 || 1928 sc->sc_msgbuf[4] == 0) { 1929 /* set async */ 1930 ti->synctl = 0; 1931 ti->offset = 0; 1932 } else { 1933 /* set sync */ 1934 /* Transfer period factor */ 1935 ti->period = sc->sc_msgbuf[3]; 1936 /* REQ/ACK offset */ 1937 ti->offset = sc->sc_msgbuf[4]; 1938 for (index = 0; 1939 index < NPERIOD; 1940 index++) 1941 if (ti->period <= 1942 trm_clock_period[ 1943 index]) 1944 break; 1945 1946 ti->synctl |= ALT_SYNC | index; 1947 } 1948 /* 1949 * program SCSI control register 1950 */ 1951 bus_space_write_1(iot, ioh, 1952 TRM_SCSI_SYNC, ti->synctl); 1953 bus_space_write_1(iot, ioh, 1954 TRM_SCSI_OFFSET, ti->offset); 1955 trm_update_xfer_mode(sc, 1956 periph->periph_target); 1957 } 1958 sc->sc_state = TRM_IDLE; 1959 } 1960 break; 1961 default: 1962 break; 1963 } 1964 } 1965 1966 /* it's important for atn stop */ 1967 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1968 1969 /* 1970 * SCSI command 1971 */ 1972 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1973 } 1974 1975 static void 1976 trm_msgin_phase1(sc) 1977 struct trm_softc *sc; 1978 { 1979 bus_space_tag_t iot = sc->sc_iot; 1980 bus_space_handle_t ioh = sc->sc_ioh; 1981 1982 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1983 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1984 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1985 sc->sc_state = TRM_MSGIN; 1986 } 1987 1988 /* it's important for atn stop */ 1989 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1990 1991 /* 1992 * SCSI command 1993 */ 1994 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1995 } 1996 1997 static void 1998 trm_disconnect(sc) 1999 struct trm_softc *sc; 2000 { 2001 bus_space_tag_t iot = sc->sc_iot; 2002 bus_space_handle_t ioh = sc->sc_ioh; 2003 struct trm_srb *srb; 2004 int s; 2005 2006 s = splbio(); 2007 2008 srb = sc->sc_actsrb; 2009 DPRINTF(("trm_disconnect...............\n")); 2010 2011 if (srb == NULL) { 2012 DPRINTF(("trm_disconnect: no active srb\n")); 2013 DELAY(1000); /* 1 msec */ 2014 2015 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2016 DO_CLRFIFO | DO_HWRESELECT); 2017 return; 2018 } 2019 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2020 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2021 DO_CLRFIFO | DO_HWRESELECT); 2022 DELAY(100); 2023 2024 switch (sc->sc_state) { 2025 case TRM_UNEXPECT_RESEL: 2026 sc->sc_state = TRM_IDLE; 2027 break; 2028 2029 case TRM_ABORT_SENT: 2030 goto finish; 2031 2032 case TRM_START: 2033 case TRM_MSGOUT: 2034 { 2035 /* Selection time out - discard all LUNs if empty */ 2036 struct scsipi_periph *periph; 2037 struct trm_tinfo *ti; 2038 struct trm_linfo *li; 2039 int lun; 2040 2041 DPRINTF(("selection timeout\n")); 2042 2043 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2044 2045 periph = srb->xs->xs_periph; 2046 ti = &sc->sc_tinfo[periph->periph_target]; 2047 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2048 li = ti->linfo[lun]; 2049 if (li != NULL && 2050 li->untagged == NULL && li->used == 0) { 2051 ti->linfo[lun] = NULL; 2052 free(li, M_DEVBUF); 2053 } 2054 } 2055 } 2056 goto finish; 2057 2058 case TRM_DISCONNECTED: 2059 sc->sc_actsrb = NULL; 2060 sc->sc_state = TRM_IDLE; 2061 goto sched; 2062 2063 case TRM_COMPLETED: 2064 goto finish; 2065 } 2066 2067 out: 2068 splx(s); 2069 return; 2070 2071 finish: 2072 sc->sc_state = TRM_IDLE; 2073 trm_done(sc, srb); 2074 goto out; 2075 2076 sched: 2077 trm_sched(sc); 2078 goto out; 2079 } 2080 2081 static void 2082 trm_reselect(sc) 2083 struct trm_softc *sc; 2084 { 2085 bus_space_tag_t iot = sc->sc_iot; 2086 bus_space_handle_t ioh = sc->sc_ioh; 2087 struct trm_tinfo *ti; 2088 struct trm_linfo *li; 2089 int target, lun; 2090 2091 DPRINTF(("trm_reselect.................\n")); 2092 2093 if (sc->sc_actsrb != NULL) { 2094 /* arbitration lost but reselection win */ 2095 sc->sc_state = TRM_READY; 2096 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2097 ti = &sc->sc_tinfo[target]; 2098 } else { 2099 /* Read Reselected Target Id and LUN */ 2100 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2101 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2102 ti = &sc->sc_tinfo[target]; 2103 li = ti->linfo[lun]; 2104 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2105 2106 /* 2107 * Check to see if we are running an un-tagged command. 2108 * Otherwise ack the IDENTIFY and wait for a tag message. 2109 */ 2110 if (li != NULL) { 2111 if (li->untagged != NULL && li->busy) { 2112 sc->sc_actsrb = li->untagged; 2113 sc->sc_state = TRM_DATA_XFER; 2114 } else { 2115 sc->resel_target = target; 2116 sc->resel_lun = lun; 2117 /* XXX XXX XXX */ 2118 sc->sc_flag |= WAIT_TAGMSG; 2119 } 2120 } 2121 2122 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2123 sc->sc_actsrb == NULL) { 2124 printf("%s: reselect from target %d lun %d " 2125 "without nexus; sending abort\n", 2126 sc->sc_dev.dv_xname, target, lun); 2127 sc->sc_state = TRM_UNEXPECT_RESEL; 2128 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2129 sc->sc_msgcnt = 1; 2130 bus_space_write_2(iot, ioh, 2131 TRM_SCSI_CONTROL, DO_SETATN); 2132 } 2133 } 2134 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2135 /* 2136 * Program HA ID, target ID, period and offset 2137 */ 2138 /* target ID */ 2139 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2140 2141 /* host ID */ 2142 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2143 2144 /* period */ 2145 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2146 2147 /* offset */ 2148 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2149 2150 /* it's important for atn stop */ 2151 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2152 /* 2153 * SCSI command 2154 */ 2155 /* to rls the /ACK signal */ 2156 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2157 } 2158 2159 /* 2160 * Complete execution of a SCSI command 2161 * Signal completion to the generic SCSI driver 2162 */ 2163 static void 2164 trm_done(sc, srb) 2165 struct trm_softc *sc; 2166 struct trm_srb *srb; 2167 { 2168 struct scsipi_xfer *xs = srb->xs; 2169 2170 DPRINTF(("trm_done..................\n")); 2171 2172 if (xs == NULL) 2173 return; 2174 2175 if ((xs->xs_control & XS_CTL_POLL) == 0) 2176 callout_stop(&xs->xs_callout); 2177 2178 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2179 srb->flag & AUTO_REQSENSE) { 2180 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2181 srb->dmap->dm_mapsize, 2182 ((xs->xs_control & XS_CTL_DATA_IN) || 2183 (srb->flag & AUTO_REQSENSE)) ? 2184 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2185 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2186 } 2187 2188 /* 2189 * target status 2190 */ 2191 xs->status = srb->tastat; 2192 2193 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2194 2195 switch (xs->status) { 2196 case SCSI_OK: 2197 /* 2198 * process initiator status...... 2199 * Adapter (initiator) status 2200 */ 2201 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2202 printf("%s: over/under run error\n", 2203 sc->sc_dev.dv_xname); 2204 srb->tastat = 0; 2205 /* Illegal length (over/under run) */ 2206 xs->error = XS_DRIVER_STUFFUP; 2207 } else if ((srb->flag & PARITY_ERROR) != 0) { 2208 printf("%s: parity error\n", 2209 sc->sc_dev.dv_xname); 2210 /* Driver failed to perform operation */ 2211 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2212 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2213 xs->resid = srb->buflen; 2214 xs->error = XS_TIMEOUT; 2215 } else { 2216 /* No error */ 2217 xs->resid = srb->buflen; 2218 srb->hastat = 0; 2219 if (srb->flag & AUTO_REQSENSE) { 2220 /* there is no error, (sense is invalid) */ 2221 xs->error = XS_SENSE; 2222 } else { 2223 srb->tastat = 0; 2224 xs->error = XS_NOERROR; 2225 } 2226 } 2227 break; 2228 2229 case SCSI_CHECK: 2230 if ((srb->flag & AUTO_REQSENSE) != 0 || 2231 trm_request_sense(sc, srb) != 0) { 2232 printf("%s: request sense failed\n", 2233 sc->sc_dev.dv_xname); 2234 xs->error = XS_DRIVER_STUFFUP; 2235 break; 2236 } 2237 xs->error = XS_SENSE; 2238 return; 2239 2240 case SCSI_SEL_TIMEOUT: 2241 srb->hastat = H_SEL_TIMEOUT; 2242 srb->tastat = 0; 2243 xs->error = XS_SELTIMEOUT; 2244 break; 2245 2246 case SCSI_QUEUE_FULL: 2247 case SCSI_BUSY: 2248 xs->error = XS_BUSY; 2249 break; 2250 2251 case SCSI_RESV_CONFLICT: 2252 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2253 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2254 xs->error = XS_BUSY; 2255 break; 2256 2257 default: 2258 srb->hastat = 0; 2259 printf("%s: trm_done(): unknown status = %02x\n", 2260 sc->sc_dev.dv_xname, xs->status); 2261 xs->error = XS_DRIVER_STUFFUP; 2262 break; 2263 } 2264 2265 trm_dequeue(sc, srb); 2266 if (srb == sc->sc_actsrb) { 2267 sc->sc_actsrb = NULL; 2268 trm_sched(sc); 2269 } 2270 2271 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2272 2273 /* Notify cmd done */ 2274 scsipi_done(xs); 2275 } 2276 2277 static int 2278 trm_request_sense(sc, srb) 2279 struct trm_softc *sc; 2280 struct trm_srb *srb; 2281 { 2282 struct scsipi_xfer *xs; 2283 struct scsipi_periph *periph; 2284 struct trm_tinfo *ti; 2285 struct trm_linfo *li; 2286 struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2287 int error; 2288 2289 DPRINTF(("trm_request_sense...\n")); 2290 2291 xs = srb->xs; 2292 periph = xs->xs_periph; 2293 2294 srb->flag |= AUTO_REQSENSE; 2295 2296 /* Status of initiator/target */ 2297 srb->hastat = 0; 2298 srb->tastat = 0; 2299 2300 ss->opcode = REQUEST_SENSE; 2301 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2302 ss->unused[0] = ss->unused[1] = 0; 2303 ss->length = sizeof(struct scsipi_sense_data); 2304 ss->control = 0; 2305 2306 srb->buflen = sizeof(struct scsipi_sense_data); 2307 srb->sgcnt = 1; 2308 srb->sgindex = 0; 2309 srb->cmdlen = sizeof(struct scsipi_sense); 2310 2311 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2312 &xs->sense.scsi_sense, srb->buflen, NULL, 2313 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2314 return error; 2315 } 2316 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2317 srb->buflen, BUS_DMASYNC_PREREAD); 2318 2319 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2320 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2321 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2322 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2323 2324 ti = &sc->sc_tinfo[periph->periph_target]; 2325 li = ti->linfo[periph->periph_lun]; 2326 if (li->busy > 0) 2327 li->busy = 0; 2328 trm_dequeue(sc, srb); 2329 li->untagged = srb; /* must be executed first to fix C/A */ 2330 li->busy = 2; 2331 2332 if (srb == sc->sc_actsrb) 2333 trm_select(sc, srb); 2334 else { 2335 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2336 if (sc->sc_actsrb == NULL) 2337 trm_sched(sc); 2338 } 2339 return 0; 2340 } 2341 2342 static void 2343 trm_dequeue(sc, srb) 2344 struct trm_softc *sc; 2345 struct trm_srb *srb; 2346 { 2347 struct scsipi_periph *periph; 2348 struct trm_tinfo *ti; 2349 struct trm_linfo *li; 2350 2351 periph = srb->xs->xs_periph; 2352 ti = &sc->sc_tinfo[periph->periph_target]; 2353 li = ti->linfo[periph->periph_lun]; 2354 2355 if (li->untagged == srb) { 2356 li->busy = 0; 2357 li->untagged = NULL; 2358 } 2359 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2360 li->queued[srb->tag[1]] = NULL; 2361 li->used--; 2362 } 2363 } 2364 2365 static void 2366 trm_reset_scsi_bus(sc) 2367 struct trm_softc *sc; 2368 { 2369 bus_space_tag_t iot = sc->sc_iot; 2370 bus_space_handle_t ioh = sc->sc_ioh; 2371 int timeout, s; 2372 2373 DPRINTF(("trm_reset_scsi_bus.........\n")); 2374 2375 s = splbio(); 2376 2377 sc->sc_flag |= RESET_DEV; 2378 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2379 for (timeout = 20000; timeout >= 0; timeout--) { 2380 DELAY(1); 2381 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2382 INT_SCSIRESET) == 0) 2383 break; 2384 } 2385 if (timeout == 0) 2386 printf(": scsibus reset timeout\n"); 2387 2388 splx(s); 2389 } 2390 2391 static void 2392 trm_scsi_reset_detect(sc) 2393 struct trm_softc *sc; 2394 { 2395 bus_space_tag_t iot = sc->sc_iot; 2396 bus_space_handle_t ioh = sc->sc_ioh; 2397 int s; 2398 2399 DPRINTF(("trm_scsi_reset_detect...............\n")); 2400 DELAY(1000000); /* delay 1 sec */ 2401 2402 s = splbio(); 2403 2404 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2405 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2406 2407 if (sc->sc_flag & RESET_DEV) { 2408 sc->sc_flag |= RESET_DONE; 2409 } else { 2410 sc->sc_flag |= RESET_DETECT; 2411 sc->sc_actsrb = NULL; 2412 sc->sc_flag = 0; 2413 trm_sched(sc); 2414 } 2415 splx(s); 2416 } 2417 2418 /* 2419 * read seeprom 128 bytes to struct eeprom and check checksum. 2420 * If it is wrong, update with default value. 2421 */ 2422 static void 2423 trm_check_eeprom(sc, eeprom) 2424 struct trm_softc *sc; 2425 struct trm_nvram *eeprom; 2426 { 2427 struct nvram_target *target; 2428 u_int16_t *ep; 2429 u_int16_t chksum; 2430 int i; 2431 2432 DPRINTF(("trm_check_eeprom......\n")); 2433 trm_eeprom_read_all(sc, eeprom); 2434 ep = (u_int16_t *)eeprom; 2435 chksum = 0; 2436 for (i = 0; i < 64; i++) 2437 chksum += le16toh(*ep++); 2438 2439 if (chksum != TRM_NVRAM_CKSUM) { 2440 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2441 /* 2442 * Checksum error, load default 2443 */ 2444 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2445 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2446 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2447 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2448 eeprom->subclass = 0x00; 2449 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2450 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2451 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2452 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2453 eeprom->reserved0 = 0x00; 2454 2455 for (i = 0, target = eeprom->target; 2456 i < TRM_MAX_TARGETS; 2457 i++, target++) { 2458 target->config0 = 0x77; 2459 target->period = 0x00; 2460 target->config2 = 0x00; 2461 target->config3 = 0x00; 2462 } 2463 2464 eeprom->scsi_id = 7; 2465 eeprom->channel_cfg = 0x0F; 2466 eeprom->delay_time = 0; 2467 eeprom->max_tag = 4; 2468 eeprom->reserved1 = 0x15; 2469 eeprom->boot_target = 0; 2470 eeprom->boot_lun = 0; 2471 eeprom->reserved2 = 0; 2472 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2473 2474 chksum = 0; 2475 ep = (u_int16_t *)eeprom; 2476 for (i = 0; i < 63; i++) 2477 chksum += le16toh(*ep++); 2478 2479 chksum = TRM_NVRAM_CKSUM - chksum; 2480 eeprom->checksum0 = chksum & 0xFF; 2481 eeprom->checksum1 = chksum >> 8; 2482 2483 trm_eeprom_write_all(sc, eeprom); 2484 } 2485 } 2486 2487 /* 2488 * write struct eeprom 128 bytes to seeprom 2489 */ 2490 static void 2491 trm_eeprom_write_all(sc, eeprom) 2492 struct trm_softc *sc; 2493 struct trm_nvram *eeprom; 2494 { 2495 bus_space_tag_t iot = sc->sc_iot; 2496 bus_space_handle_t ioh = sc->sc_ioh; 2497 u_int8_t *buf = (u_int8_t *)eeprom; 2498 u_int8_t addr; 2499 2500 /* Enable SEEPROM */ 2501 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2502 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2503 2504 /* 2505 * Write enable 2506 */ 2507 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2508 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2509 trm_eeprom_wait(); 2510 2511 for (addr = 0; addr < 128; addr++, buf++) 2512 trm_eeprom_set_data(sc, addr, *buf); 2513 2514 /* 2515 * Write disable 2516 */ 2517 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2518 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2519 trm_eeprom_wait(); 2520 2521 /* Disable SEEPROM */ 2522 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2523 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2524 } 2525 2526 /* 2527 * write one byte to seeprom 2528 */ 2529 static void 2530 trm_eeprom_set_data(sc, addr, data) 2531 struct trm_softc *sc; 2532 u_int8_t addr; 2533 u_int8_t data; 2534 { 2535 bus_space_tag_t iot = sc->sc_iot; 2536 bus_space_handle_t ioh = sc->sc_ioh; 2537 int i; 2538 u_int8_t send; 2539 2540 /* 2541 * Send write command & address 2542 */ 2543 trm_eeprom_write_cmd(sc, 0x05, addr); 2544 /* 2545 * Write data 2546 */ 2547 for (i = 0; i < 8; i++, data <<= 1) { 2548 send = NVR_SELECT; 2549 if (data & 0x80) /* Start from bit 7 */ 2550 send |= NVR_BITOUT; 2551 2552 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2553 trm_eeprom_wait(); 2554 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2555 trm_eeprom_wait(); 2556 } 2557 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2558 trm_eeprom_wait(); 2559 /* 2560 * Disable chip select 2561 */ 2562 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2563 trm_eeprom_wait(); 2564 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2565 trm_eeprom_wait(); 2566 /* 2567 * Wait for write ready 2568 */ 2569 for (;;) { 2570 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2571 NVR_SELECT | NVR_CLOCK); 2572 trm_eeprom_wait(); 2573 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2574 trm_eeprom_wait(); 2575 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2576 break; 2577 } 2578 /* 2579 * Disable chip select 2580 */ 2581 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2582 } 2583 2584 /* 2585 * read seeprom 128 bytes to struct eeprom 2586 */ 2587 static void 2588 trm_eeprom_read_all(sc, eeprom) 2589 struct trm_softc *sc; 2590 struct trm_nvram *eeprom; 2591 { 2592 bus_space_tag_t iot = sc->sc_iot; 2593 bus_space_handle_t ioh = sc->sc_ioh; 2594 u_int8_t *buf = (u_int8_t *)eeprom; 2595 u_int8_t addr; 2596 2597 /* 2598 * Enable SEEPROM 2599 */ 2600 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2601 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2602 2603 for (addr = 0; addr < 128; addr++) 2604 *buf++ = trm_eeprom_get_data(sc, addr); 2605 2606 /* 2607 * Disable SEEPROM 2608 */ 2609 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2610 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2611 } 2612 2613 /* 2614 * read one byte from seeprom 2615 */ 2616 static u_int8_t 2617 trm_eeprom_get_data(sc, addr) 2618 struct trm_softc *sc; 2619 u_int8_t addr; 2620 { 2621 bus_space_tag_t iot = sc->sc_iot; 2622 bus_space_handle_t ioh = sc->sc_ioh; 2623 int i; 2624 u_int8_t read, data = 0; 2625 2626 /* 2627 * Send read command & address 2628 */ 2629 trm_eeprom_write_cmd(sc, 0x06, addr); 2630 2631 for (i = 0; i < 8; i++) { /* Read data */ 2632 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2633 NVR_SELECT | NVR_CLOCK); 2634 trm_eeprom_wait(); 2635 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2636 /* 2637 * Get data bit while falling edge 2638 */ 2639 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2640 data <<= 1; 2641 if (read & NVR_BITIN) 2642 data |= 1; 2643 2644 trm_eeprom_wait(); 2645 } 2646 /* 2647 * Disable chip select 2648 */ 2649 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2650 return (data); 2651 } 2652 2653 /* 2654 * write SB and Op Code into seeprom 2655 */ 2656 static void 2657 trm_eeprom_write_cmd(sc, cmd, addr) 2658 struct trm_softc *sc; 2659 u_int8_t cmd; 2660 u_int8_t addr; 2661 { 2662 bus_space_tag_t iot = sc->sc_iot; 2663 bus_space_handle_t ioh = sc->sc_ioh; 2664 int i; 2665 u_int8_t send; 2666 2667 /* Program SB+OP code */ 2668 for (i = 0; i < 3; i++, cmd <<= 1) { 2669 send = NVR_SELECT; 2670 if (cmd & 0x04) /* Start from bit 2 */ 2671 send |= NVR_BITOUT; 2672 2673 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2674 trm_eeprom_wait(); 2675 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2676 trm_eeprom_wait(); 2677 } 2678 2679 /* Program address */ 2680 for (i = 0; i < 7; i++, addr <<= 1) { 2681 send = NVR_SELECT; 2682 if (addr & 0x40) /* Start from bit 6 */ 2683 send |= NVR_BITOUT; 2684 2685 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2686 trm_eeprom_wait(); 2687 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2688 trm_eeprom_wait(); 2689 } 2690 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2691 trm_eeprom_wait(); 2692 } 2693
Indexes created Tue Sep 23 22:09:46 GMT 2025