trm.c revision 1.14.4.1
1 /* $NetBSD: trm.c,v 1.14.4.1 2005/04/16 14:50:03 tron Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.14.4.1 2005/04/16 14:50:03 tron Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsi_message.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/trmreg.h> 77 78 /* 79 * feature of chip set MAX value 80 */ 81 #define TRM_MAX_TARGETS 16 82 #define TRM_MAX_LUNS 8 83 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 #define TRM_MAX_SRB 32 /* XXX */ 85 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 #define TRM_MAX_OFFSET 15 87 #define TRM_MAX_PERIOD 125 88 89 /* 90 * Segment Entry 91 */ 92 struct trm_sg_entry { 93 u_int32_t address; 94 u_int32_t length; 95 }; 96 97 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 99 /* 100 ********************************************************************** 101 * The SEEPROM structure for TRM_S1040 102 ********************************************************************** 103 */ 104 struct nvram_target { 105 u_int8_t config0; /* Target configuration byte 0 */ 106 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 u_int8_t period; /* Target period */ 113 u_int8_t config2; /* Target configuration byte 2 */ 114 u_int8_t config3; /* Target configuration byte 3 */ 115 }; 116 117 struct trm_nvram { 118 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 u_int8_t subclass; /* 4 Sub Class */ 121 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 u_int8_t device_id[2]; /* 7,8 Device ID */ 123 u_int8_t reserved0; /* 9 Reserved */ 124 struct nvram_target target[TRM_MAX_TARGETS]; 125 /* 10,11,12,13 126 * 14,15,16,17 127 * .... 128 * 70,71,72,73 */ 129 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 u_int8_t channel_cfg; /* 75 Channel configuration */ 131 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 u_int8_t delay_time; /* 76 Power on delay time */ 137 u_int8_t max_tag; /* 77 Maximum tags */ 138 u_int8_t reserved1; /* 78 */ 139 u_int8_t boot_target; /* 79 */ 140 u_int8_t boot_lun; /* 80 */ 141 u_int8_t reserved2; /* 81 */ 142 u_int8_t reserved3[44]; /* 82,..125 */ 143 u_int8_t checksum0; /* 126 */ 144 u_int8_t checksum1; /* 127 */ 145 #define TRM_NVRAM_CKSUM 0x1234 146 }; 147 148 /* Nvram Initiater bits definition */ 149 #define MORE2_DRV 0x00000001 150 #define GREATER_1G 0x00000002 151 #define RST_SCSI_BUS 0x00000004 152 #define ACTIVE_NEGATION 0x00000008 153 #define NO_SEEK 0x00000010 154 #define LUN_CHECK 0x00000020 155 156 #define trm_eeprom_wait() DELAY(30) 157 158 /* 159 *----------------------------------------------------------------------- 160 * SCSI Request Block 161 *----------------------------------------------------------------------- 162 */ 163 struct trm_srb { 164 TAILQ_ENTRY(trm_srb) next; 165 166 struct trm_sg_entry *sgentry; 167 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 bus_dmamap_t dmap; 169 bus_size_t sgoffset; /* Xfer buf offset */ 170 171 u_int32_t buflen; /* Total xfer length */ 172 u_int32_t sgaddr; /* SGList physical starting address */ 173 174 int sgcnt; 175 int sgindex; 176 177 int hastat; /* Host Adapter Status */ 178 #define H_STATUS_GOOD 0x00 179 #define H_SEL_TIMEOUT 0x11 180 #define H_OVER_UNDER_RUN 0x12 181 #define H_UNEXP_BUS_FREE 0x13 182 #define H_TARGET_PHASE_F 0x14 183 #define H_INVALID_CCB_OP 0x16 184 #define H_LINK_CCB_BAD 0x17 185 #define H_BAD_TARGET_DIR 0x18 186 #define H_DUPLICATE_CCB 0x19 187 #define H_BAD_CCB_OR_SG 0x1A 188 #define H_ABORT 0xFF 189 int tastat; /* Target SCSI Status Byte */ 190 int flag; /* SRBFlag */ 191 #define AUTO_REQSENSE 0x0001 192 #define PARITY_ERROR 0x0002 193 #define SRB_TIMEOUT 0x0004 194 195 int cmdlen; /* SCSI command length */ 196 u_int8_t cmd[12]; /* SCSI command */ 197 198 u_int8_t tag[2]; 199 }; 200 201 /* 202 * some info about each target and lun on the SCSI bus 203 */ 204 struct trm_linfo { 205 int used; /* number of slots in use */ 206 int avail; /* where to start scanning */ 207 int busy; /* lun in use */ 208 struct trm_srb *untagged; 209 struct trm_srb *queued[TRM_MAX_TAG]; 210 }; 211 212 struct trm_tinfo { 213 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 #define SYNC_NEGO_ENABLE 0x0001 215 #define SYNC_NEGO_DOING 0x0002 216 #define SYNC_NEGO_DONE 0x0004 217 #define WIDE_NEGO_ENABLE 0x0008 218 #define WIDE_NEGO_DOING 0x0010 219 #define WIDE_NEGO_DONE 0x0020 220 #define USE_TAG_QUEUING 0x0040 221 #define NO_RESELECT 0x0080 222 struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 224 u_int8_t config0; /* Target Config */ 225 u_int8_t period; /* Max Period for nego. */ 226 u_int8_t synctl; /* Sync control for reg. */ 227 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 }; 229 230 /* 231 *----------------------------------------------------------------------- 232 * Adapter Control Block 233 *----------------------------------------------------------------------- 234 */ 235 struct trm_softc { 236 struct device sc_dev; 237 238 bus_space_tag_t sc_iot; 239 bus_space_handle_t sc_ioh; 240 bus_dma_tag_t sc_dmat; 241 bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 243 struct trm_srb *sc_actsrb; 244 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 246 TAILQ_HEAD(, trm_srb) sc_freesrb, 247 sc_readysrb; 248 struct trm_srb *sc_srb; /* SRB array */ 249 250 struct trm_sg_entry *sc_sglist; 251 252 int sc_maxid; 253 /* 254 * Link to the generic SCSI driver 255 */ 256 struct scsipi_channel sc_channel; 257 struct scsipi_adapter sc_adapter; 258 259 int sc_id; /* Adapter SCSI Target ID */ 260 261 int sc_state; /* SRB State */ 262 #define TRM_IDLE 0 263 #define TRM_WAIT 1 264 #define TRM_READY 2 265 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 #define TRM_MSGIN 4 267 #define TRM_EXTEND_MSGIN 5 268 #define TRM_COMMAND 6 269 #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 #define TRM_DISCONNECTED 8 271 #define TRM_DATA_XFER 9 272 #define TRM_XFERPAD 10 273 #define TRM_STATUS 11 274 #define TRM_COMPLETED 12 275 #define TRM_ABORT_SENT 13 276 #define TRM_UNEXPECT_RESEL 14 277 278 int sc_phase; /* SCSI phase */ 279 int sc_config; 280 #define HCC_WIDE_CARD 0x01 281 #define HCC_SCSI_RESET 0x02 282 #define HCC_PARITY 0x04 283 #define HCC_AUTOTERM 0x08 284 #define HCC_LOW8TERM 0x10 285 #define HCC_UP8TERM 0x20 286 287 int sc_flag; 288 #define RESET_DEV 0x01 289 #define RESET_DETECT 0x02 290 #define RESET_DONE 0x04 291 #define WAIT_TAGMSG 0x08 /* XXX */ 292 293 int sc_msgcnt; 294 295 int resel_target; /* XXX */ 296 int resel_lun; /* XXX */ 297 298 u_int8_t *sc_msg; 299 u_int8_t sc_msgbuf[6]; 300 }; 301 302 /* 303 * SCSI Status codes not defined in scsi_all.h 304 */ 305 #define SCSI_COND_MET 0x04 /* Condition Met */ 306 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 311 static int trm_probe(struct device *, struct cfdata *, void *); 312 static void trm_attach(struct device *, struct device *, void *); 313 314 static int trm_init(struct trm_softc *); 315 316 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 void *); 318 static void trm_update_xfer_mode(struct trm_softc *, int); 319 static void trm_sched(struct trm_softc *); 320 static int trm_select(struct trm_softc *, struct trm_srb *); 321 static void trm_reset(struct trm_softc *); 322 static void trm_timeout(void *); 323 static int trm_intr(void *); 324 325 static void trm_dataout_phase0(struct trm_softc *, int); 326 static void trm_datain_phase0(struct trm_softc *, int); 327 static void trm_status_phase0(struct trm_softc *); 328 static void trm_msgin_phase0(struct trm_softc *); 329 static void trm_command_phase1(struct trm_softc *); 330 static void trm_status_phase1(struct trm_softc *); 331 static void trm_msgout_phase1(struct trm_softc *); 332 static void trm_msgin_phase1(struct trm_softc *); 333 334 static void trm_dataio_xfer(struct trm_softc *, int); 335 static void trm_disconnect(struct trm_softc *); 336 static void trm_reselect(struct trm_softc *); 337 static void trm_done(struct trm_softc *, struct trm_srb *); 338 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 341 static void trm_scsi_reset_detect(struct trm_softc *); 342 static void trm_reset_scsi_bus(struct trm_softc *); 343 344 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 351 CFATTACH_DECL(trm, sizeof(struct trm_softc), 352 trm_probe, trm_attach, NULL, NULL); 353 354 /* real period: */ 355 static const u_int8_t trm_clock_period[] = { 356 12, /* 48 ns 20.0 MB/sec */ 357 18, /* 72 ns 13.3 MB/sec */ 358 25, /* 100 ns 10.0 MB/sec */ 359 31, /* 124 ns 8.0 MB/sec */ 360 37, /* 148 ns 6.6 MB/sec */ 361 43, /* 172 ns 5.7 MB/sec */ 362 50, /* 200 ns 5.0 MB/sec */ 363 62 /* 248 ns 4.0 MB/sec */ 364 }; 365 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 366 367 static int 368 trm_probe(parent, match, aux) 369 struct device *parent; 370 struct cfdata *match; 371 void *aux; 372 { 373 struct pci_attach_args *pa = aux; 374 375 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 376 switch (PCI_PRODUCT(pa->pa_id)) { 377 case PCI_PRODUCT_TEKRAM2_DC315: 378 return (1); 379 } 380 return (0); 381 } 382 383 /* 384 * attach and init a host adapter 385 */ 386 static void 387 trm_attach(parent, self, aux) 388 struct device *parent; 389 struct device *self; 390 void *aux; 391 { 392 struct pci_attach_args *const pa = aux; 393 struct trm_softc *sc = (struct trm_softc *)self; 394 bus_space_tag_t iot; 395 bus_space_handle_t ioh; 396 pci_intr_handle_t ih; 397 pcireg_t command; 398 const char *intrstr; 399 400 /* 401 * These cards do not allow memory mapped accesses 402 * pa_pc: chipset tag 403 * pa_tag: pci tag 404 */ 405 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 406 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 407 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 408 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 409 pci_conf_write(pa->pa_pc, pa->pa_tag, 410 PCI_COMMAND_STATUS_REG, command); 411 } 412 /* 413 * mask for get correct base address of pci IO port 414 */ 415 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 416 &iot, &ioh, NULL, NULL)) { 417 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 418 return; 419 } 420 /* 421 * test checksum of eeprom.. & initialize softc... 422 */ 423 sc->sc_iot = iot; 424 sc->sc_ioh = ioh; 425 sc->sc_dmat = pa->pa_dmat; 426 427 if (trm_init(sc) != 0) { 428 /* 429 * Error during initialization! 430 */ 431 printf(": Error during initialization\n"); 432 return; 433 } 434 /* 435 * Now try to attach all the sub-devices 436 */ 437 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 438 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 439 "Ultra Wide SCSI Adapter\n"); 440 else 441 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 442 "Ultra SCSI Adapter\n"); 443 444 /* 445 * Now tell the generic SCSI layer about our bus. 446 * map and establish interrupt 447 */ 448 if (pci_intr_map(pa, &ih)) { 449 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 450 return; 451 } 452 intrstr = pci_intr_string(pa->pa_pc, ih); 453 454 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 455 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 456 if (intrstr != NULL) 457 printf(" at %s", intrstr); 458 printf("\n"); 459 return; 460 } 461 if (intrstr != NULL) 462 printf("%s: interrupting at %s\n", 463 sc->sc_dev.dv_xname, intrstr); 464 465 sc->sc_adapter.adapt_dev = &sc->sc_dev; 466 sc->sc_adapter.adapt_nchannels = 1; 467 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 468 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 469 sc->sc_adapter.adapt_request = trm_scsipi_request; 470 sc->sc_adapter.adapt_minphys = minphys; 471 472 sc->sc_channel.chan_adapter = &sc->sc_adapter; 473 sc->sc_channel.chan_bustype = &scsi_bustype; 474 sc->sc_channel.chan_channel = 0; 475 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 476 sc->sc_channel.chan_nluns = 8; 477 sc->sc_channel.chan_id = sc->sc_id; 478 479 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 480 } 481 482 /* 483 * initialize the internal structures for a given SCSI host 484 */ 485 static int 486 trm_init(sc) 487 struct trm_softc *sc; 488 { 489 bus_space_tag_t iot = sc->sc_iot; 490 bus_space_handle_t ioh = sc->sc_ioh; 491 bus_dma_segment_t seg; 492 struct trm_nvram eeprom; 493 struct trm_srb *srb; 494 struct trm_tinfo *ti; 495 struct nvram_target *tconf; 496 int error, rseg, all_sgsize; 497 int i, target; 498 u_int8_t bval; 499 500 DPRINTF(("\n")); 501 502 /* 503 * allocate the space for all SCSI control blocks (SRB) for DMA memory 504 */ 505 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 506 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 507 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 508 printf(": unable to allocate SCSI REQUEST BLOCKS, " 509 "error = %d\n", error); 510 return (1); 511 } 512 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 513 all_sgsize, (caddr_t *) &sc->sc_sglist, 514 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 515 printf(": unable to map SCSI REQUEST BLOCKS, " 516 "error = %d\n", error); 517 return (1); 518 } 519 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 520 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 521 printf(": unable to create SRB DMA maps, " 522 "error = %d\n", error); 523 return (1); 524 } 525 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 526 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 527 printf(": unable to load SRB DMA maps, " 528 "error = %d\n", error); 529 return (1); 530 } 531 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 532 memset(sc->sc_sglist, 0, all_sgsize); 533 534 /* 535 * EEPROM CHECKSUM 536 */ 537 trm_check_eeprom(sc, &eeprom); 538 539 sc->sc_maxid = 7; 540 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 541 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 542 sc->sc_config |= HCC_WIDE_CARD; 543 sc->sc_maxid = 15; 544 } 545 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 546 sc->sc_config |= HCC_SCSI_RESET; 547 548 sc->sc_actsrb = NULL; 549 sc->sc_id = eeprom.scsi_id; 550 sc->sc_flag = 0; 551 552 /* 553 * initialize and link all device's SRB queues of this adapter 554 */ 555 TAILQ_INIT(&sc->sc_freesrb); 556 TAILQ_INIT(&sc->sc_readysrb); 557 558 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 559 M_DEVBUF, M_NOWAIT|M_ZERO); 560 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 561 if (sc->sc_srb == NULL) { 562 printf(": can not allocate SRB\n"); 563 return (1); 564 } 565 566 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 567 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 568 srb->sgoffset = TRM_SG_SIZE * i; 569 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 570 /* 571 * map all SRB space to SRB_array 572 */ 573 if (bus_dmamap_create(sc->sc_dmat, 574 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 575 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 576 printf(": unable to create DMA transfer map...\n"); 577 free(sc->sc_srb, M_DEVBUF); 578 return (1); 579 } 580 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 581 srb++; 582 } 583 584 /* 585 * initialize all target info structures 586 */ 587 for (target = 0; target < TRM_MAX_TARGETS; target++) { 588 ti = &sc->sc_tinfo[target]; 589 ti->synctl = 0; 590 ti->offset = 0; 591 tconf = &eeprom.target[target]; 592 ti->config0 = tconf->config0; 593 ti->period = trm_clock_period[tconf->period & 0x07]; 594 ti->flag = 0; 595 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 596 #ifdef notyet 597 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 598 ti->flag |= USE_TAG_QUEUING; 599 #endif 600 } else 601 ti->flag |= NO_RESELECT; 602 603 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 604 target, ti->config0, ti->period)); 605 DPRINTF((", flag = 0x%02x\n", ti->flag)); 606 } 607 608 /* program configuration 0 */ 609 bval = PHASELATCH | INITIATOR | BLOCKRST; 610 if ((sc->sc_config & HCC_PARITY) != 0) 611 bval |= PARITYCHECK; 612 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 613 614 /* program configuration 1 */ 615 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 616 ACTIVE_NEG | ACTIVE_NEGPLUS); 617 618 /* 250ms selection timeout */ 619 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 620 621 /* Mask all interrupts */ 622 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 623 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 624 625 /* Reset SCSI module */ 626 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 627 628 /* program Host ID */ 629 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 630 631 /* set asynchronous transfer */ 632 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 633 634 /* Turn LED control off */ 635 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 636 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 637 638 /* DMA config */ 639 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 640 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 641 642 /* Clear pending interrupt status */ 643 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 644 645 /* Enable SCSI interrupt */ 646 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 647 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 648 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 649 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 650 651 trm_reset(sc); 652 653 return (0); 654 } 655 656 /* 657 * enqueues a SCSI command 658 * called by the higher level SCSI driver 659 */ 660 static void 661 trm_scsipi_request(chan, req, arg) 662 struct scsipi_channel *chan; 663 scsipi_adapter_req_t req; 664 void *arg; 665 { 666 bus_space_tag_t iot; 667 bus_space_handle_t ioh; 668 struct trm_softc *sc; 669 struct trm_srb *srb; 670 struct scsipi_xfer *xs; 671 int error, i, target, lun, s; 672 673 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 674 iot = sc->sc_iot; 675 ioh = sc->sc_ioh; 676 677 switch (req) { 678 case ADAPTER_REQ_RUN_XFER: 679 xs = arg; 680 target = xs->xs_periph->periph_target; 681 lun = xs->xs_periph->periph_lun; 682 DPRINTF(("trm_scsipi_request.....\n")); 683 DPRINTF(("target= %d lun= %d\n", target, lun)); 684 if (xs->xs_control & XS_CTL_RESET) { 685 trm_reset(sc); 686 xs->error = XS_NOERROR | XS_RESET; 687 return; 688 } 689 if (xs->xs_status & XS_STS_DONE) { 690 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 691 xs->xs_status &= ~XS_STS_DONE; 692 } 693 694 s = splbio(); 695 696 /* Get SRB */ 697 srb = TAILQ_FIRST(&sc->sc_freesrb); 698 if (srb != NULL) { 699 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 700 } else { 701 xs->error = XS_RESOURCE_SHORTAGE; 702 scsipi_done(xs); 703 splx(s); 704 return; 705 } 706 707 srb->xs = xs; 708 srb->cmdlen = xs->cmdlen; 709 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 710 711 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 712 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 713 xs->data, xs->datalen, NULL, 714 ((xs->xs_control & XS_CTL_NOSLEEP) ? 715 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 716 BUS_DMA_STREAMING | 717 ((xs->xs_control & XS_CTL_DATA_IN) ? 718 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 719 printf("%s: DMA transfer map unable to load, " 720 "error = %d\n", sc->sc_dev.dv_xname, error); 721 xs->error = XS_DRIVER_STUFFUP; 722 /* 723 * free SRB 724 */ 725 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 726 splx(s); 727 return; 728 } 729 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 730 srb->dmap->dm_mapsize, 731 (xs->xs_control & XS_CTL_DATA_IN) ? 732 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 733 734 /* Set up the scatter gather list */ 735 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 736 srb->sgentry[i].address = 737 htole32(srb->dmap->dm_segs[i].ds_addr); 738 srb->sgentry[i].length = 739 htole32(srb->dmap->dm_segs[i].ds_len); 740 } 741 srb->buflen = xs->datalen; 742 srb->sgcnt = srb->dmap->dm_nsegs; 743 } else { 744 srb->sgentry[0].address = 0; 745 srb->sgentry[0].length = 0; 746 srb->buflen = 0; 747 srb->sgcnt = 0; 748 } 749 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 750 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 751 752 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 753 754 srb->sgindex = 0; 755 srb->hastat = 0; 756 srb->tastat = 0; 757 srb->flag = 0; 758 759 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 760 if (sc->sc_actsrb == NULL) 761 trm_sched(sc); 762 splx(s); 763 764 if ((xs->xs_control & XS_CTL_POLL) != 0) { 765 int timeout = xs->timeout; 766 767 s = splbio(); 768 do { 769 while (--timeout) { 770 DELAY(1000); 771 if (bus_space_read_2(iot, ioh, 772 TRM_SCSI_STATUS) & SCSIINTERRUPT) 773 break; 774 } 775 if (timeout == 0) { 776 trm_timeout(srb); 777 break; 778 } else 779 trm_intr(sc); 780 } while ((xs->xs_status & XS_STS_DONE) == 0); 781 splx(s); 782 } 783 return; 784 785 case ADAPTER_REQ_GROW_RESOURCES: 786 /* XXX Not supported. */ 787 return; 788 789 case ADAPTER_REQ_SET_XFER_MODE: 790 { 791 struct trm_tinfo *ti; 792 struct scsipi_xfer_mode *xm; 793 794 xm = arg; 795 ti = &sc->sc_tinfo[xm->xm_target]; 796 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 797 798 #ifdef notyet 799 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 800 ti->flag |= USE_TAG_QUEUING; 801 else 802 #endif 803 ti->flag &= ~USE_TAG_QUEUING; 804 805 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 806 (sc->sc_config & HCC_WIDE_CARD) != 0 && 807 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 808 ti->flag |= WIDE_NEGO_ENABLE; 809 ti->flag &= ~WIDE_NEGO_DONE; 810 } 811 812 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 813 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 814 ti->flag |= SYNC_NEGO_ENABLE; 815 ti->flag &= ~SYNC_NEGO_DONE; 816 ti->period = trm_clock_period[0]; 817 } 818 819 /* 820 * If we're not going to negotiate, send the 821 * notification now, since it won't happen later. 822 */ 823 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 824 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 825 trm_update_xfer_mode(sc, xm->xm_target); 826 827 return; 828 } 829 } 830 } 831 832 static void 833 trm_update_xfer_mode(sc, target) 834 struct trm_softc *sc; 835 int target; 836 { 837 struct scsipi_xfer_mode xm; 838 struct trm_tinfo *ti; 839 840 ti = &sc->sc_tinfo[target]; 841 xm.xm_target = target; 842 xm.xm_mode = 0; 843 xm.xm_period = 0; 844 xm.xm_offset = 0; 845 846 if ((ti->synctl & WIDE_SYNC) != 0) 847 xm.xm_mode |= PERIPH_CAP_WIDE16; 848 849 if (ti->period > 0) { 850 xm.xm_mode |= PERIPH_CAP_SYNC; 851 xm.xm_period = ti->period; 852 xm.xm_offset = ti->offset; 853 } 854 855 #ifdef notyet 856 if ((ti->flag & USE_TAG_QUEUING) != 0) 857 xm.xm_mode |= PERIPH_CAP_TQING; 858 #endif 859 860 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 861 } 862 863 static void 864 trm_sched(sc) 865 struct trm_softc *sc; 866 { 867 struct trm_srb *srb; 868 struct scsipi_periph *periph; 869 struct trm_tinfo *ti; 870 struct trm_linfo *li; 871 int s, lun, tag; 872 873 DPRINTF(("trm_sched...\n")); 874 875 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 876 periph = srb->xs->xs_periph; 877 ti = &sc->sc_tinfo[periph->periph_target]; 878 lun = periph->periph_lun; 879 880 /* select type of tag for this command */ 881 if ((ti->flag & NO_RESELECT) != 0 || 882 (ti->flag & USE_TAG_QUEUING) == 0 || 883 (srb->flag & AUTO_REQSENSE) != 0 || 884 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 885 tag = 0; 886 else 887 tag = srb->xs->xs_tag_type; 888 #if 0 889 /* XXX use tags for polled commands? */ 890 if (srb->xs->xs_control & XS_CTL_POLL) 891 tag = 0; 892 #endif 893 894 s = splbio(); 895 li = ti->linfo[lun]; 896 if (li == NULL) { 897 /* initialize lun info */ 898 if ((li = malloc(sizeof(*li), M_DEVBUF, 899 M_NOWAIT|M_ZERO)) == NULL) { 900 splx(s); 901 continue; 902 } 903 ti->linfo[lun] = li; 904 } 905 906 if (tag == 0) { 907 /* try to issue this srb as an un-tagged command */ 908 if (li->untagged == NULL) 909 li->untagged = srb; 910 } 911 if (li->untagged != NULL) { 912 tag = 0; 913 if (li->busy != 1 && li->used == 0) { 914 /* we need to issue the untagged command now */ 915 srb = li->untagged; 916 periph = srb->xs->xs_periph; 917 } else { 918 /* not ready yet */ 919 splx(s); 920 continue; 921 } 922 } 923 srb->tag[0] = tag; 924 if (tag != 0) { 925 li->queued[srb->xs->xs_tag_id] = srb; 926 srb->tag[1] = srb->xs->xs_tag_id; 927 li->used++; 928 } 929 930 if (li->untagged != NULL && li->busy != 1) { 931 li->busy = 1; 932 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 933 sc->sc_actsrb = srb; 934 trm_select(sc, srb); 935 splx(s); 936 break; 937 } 938 if (li->untagged == NULL && tag != 0) { 939 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 940 sc->sc_actsrb = srb; 941 trm_select(sc, srb); 942 splx(s); 943 break; 944 } else 945 splx(s); 946 } 947 } 948 949 static int 950 trm_select(sc, srb) 951 struct trm_softc *sc; 952 struct trm_srb *srb; 953 { 954 bus_space_tag_t iot = sc->sc_iot; 955 bus_space_handle_t ioh = sc->sc_ioh; 956 struct scsipi_periph *periph = srb->xs->xs_periph; 957 int target = periph->periph_target; 958 int lun = periph->periph_lun; 959 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 960 u_int8_t scsicmd; 961 962 DPRINTF(("trm_select.....\n")); 963 964 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 965 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 966 trm_timeout, srb); 967 } 968 969 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 970 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 971 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 972 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 973 /* Flush FIFO */ 974 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 975 DELAY(10); 976 977 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 978 979 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 980 981 if (((ti->flag & WIDE_NEGO_ENABLE) && 982 (ti->flag & WIDE_NEGO_DONE) == 0) || 983 ((ti->flag & SYNC_NEGO_ENABLE) && 984 (ti->flag & SYNC_NEGO_DONE) == 0)) { 985 sc->sc_state = TRM_MSGOUT; 986 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 987 MSG_IDENTIFY(lun, 0)); 988 bus_space_write_multi_1(iot, ioh, 989 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 990 /* it's important for atn stop */ 991 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 992 DO_DATALATCH | DO_HWRESELECT); 993 /* SCSI command */ 994 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 995 DPRINTF(("select with SEL_ATNSTOP\n")); 996 return (0); 997 } 998 999 if (srb->tag[0] != 0) { 1000 /* Send identify message */ 1001 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1002 MSG_IDENTIFY(lun, 1)); 1003 /* Send Tag id */ 1004 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 1005 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 1006 scsicmd = SCMD_SEL_ATN3; 1007 DPRINTF(("select with SEL_ATN3\n")); 1008 } else { 1009 /* Send identify message */ 1010 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1011 MSG_IDENTIFY(lun, 1012 (ti->flag & NO_RESELECT) == 0 && 1013 (srb->flag & AUTO_REQSENSE) == 0 && 1014 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1015 scsicmd = SCMD_SEL_ATN; 1016 DPRINTF(("select with SEL_ATN\n")); 1017 } 1018 sc->sc_state = TRM_START; 1019 1020 /* 1021 * Send CDB ..command block... 1022 */ 1023 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1024 1025 /* 1026 * If trm_select returns 0: current interrupt status 1027 * is interrupt enable. It's said that SCSI processor is 1028 * unoccupied. 1029 */ 1030 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1031 /* SCSI command */ 1032 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1033 return (0); 1034 } 1035 1036 /* 1037 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1038 */ 1039 static void 1040 trm_reset(sc) 1041 struct trm_softc *sc; 1042 { 1043 bus_space_tag_t iot = sc->sc_iot; 1044 bus_space_handle_t ioh = sc->sc_ioh; 1045 int s; 1046 1047 DPRINTF(("trm_reset.........\n")); 1048 1049 s = splbio(); 1050 1051 /* disable SCSI and DMA interrupt */ 1052 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1053 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1054 1055 trm_reset_scsi_bus(sc); 1056 DELAY(100000); 1057 1058 /* Enable SCSI interrupt */ 1059 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1060 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1061 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1062 1063 /* Enable DMA interrupt */ 1064 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1065 1066 /* Clear DMA FIFO */ 1067 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1068 1069 /* Clear SCSI FIFO */ 1070 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1071 1072 sc->sc_actsrb = NULL; 1073 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1074 1075 splx(s); 1076 } 1077 1078 static void 1079 trm_timeout(arg) 1080 void *arg; 1081 { 1082 struct trm_srb *srb = (struct trm_srb *)arg; 1083 struct scsipi_xfer *xs = srb->xs; 1084 struct scsipi_periph *periph = xs->xs_periph; 1085 struct trm_softc *sc; 1086 int s; 1087 1088 if (xs == NULL) 1089 printf("trm_timeout called with xs == NULL\n"); 1090 1091 else { 1092 scsipi_printaddr(xs->xs_periph); 1093 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1094 } 1095 1096 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1097 1098 trm_reset_scsi_bus(sc); 1099 s = splbio(); 1100 srb->flag |= SRB_TIMEOUT; 1101 trm_done(sc, srb); 1102 /* XXX needs more.. */ 1103 splx(s); 1104 } 1105 1106 /* 1107 * Catch an interrupt from the adapter 1108 * Process pending device interrupts. 1109 */ 1110 static int 1111 trm_intr(arg) 1112 void *arg; 1113 { 1114 bus_space_tag_t iot; 1115 bus_space_handle_t ioh; 1116 struct trm_softc *sc; 1117 int intstat, stat; 1118 1119 DPRINTF(("trm_intr......\n")); 1120 sc = (struct trm_softc *)arg; 1121 if (sc == NULL) 1122 return (0); 1123 1124 iot = sc->sc_iot; 1125 ioh = sc->sc_ioh; 1126 1127 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1128 if ((stat & SCSIINTERRUPT) == 0) 1129 return (0); 1130 1131 DPRINTF(("stat = %04x, ", stat)); 1132 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1133 1134 DPRINTF(("intstat=%02x, ", intstat)); 1135 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1136 DPRINTF(("\n")); 1137 trm_disconnect(sc); 1138 return (1); 1139 } 1140 if (intstat & INT_RESELECTED) { 1141 DPRINTF(("\n")); 1142 trm_reselect(sc); 1143 return (1); 1144 } 1145 if (intstat & INT_SCSIRESET) { 1146 DPRINTF(("\n")); 1147 trm_scsi_reset_detect(sc); 1148 return (1); 1149 } 1150 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1151 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1152 sc->sc_phase, sc->sc_state)); 1153 /* 1154 * software sequential machine 1155 */ 1156 1157 /* 1158 * call phase0 functions... "phase entry" handle 1159 * every phase before start transfer 1160 */ 1161 switch (sc->sc_phase) { 1162 case PH_DATA_OUT: 1163 trm_dataout_phase0(sc, stat); 1164 break; 1165 case PH_DATA_IN: 1166 trm_datain_phase0(sc, stat); 1167 break; 1168 case PH_COMMAND: 1169 break; 1170 case PH_STATUS: 1171 trm_status_phase0(sc); 1172 stat = PH_BUS_FREE; 1173 break; 1174 case PH_MSG_OUT: 1175 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1176 sc->sc_state == TRM_ABORT_SENT) 1177 stat = PH_BUS_FREE; 1178 break; 1179 case PH_MSG_IN: 1180 trm_msgin_phase0(sc); 1181 stat = PH_BUS_FREE; 1182 break; 1183 case PH_BUS_FREE: 1184 break; 1185 default: 1186 printf("%s: unexpected phase in trm_intr() phase0\n", 1187 sc->sc_dev.dv_xname); 1188 break; 1189 } 1190 1191 sc->sc_phase = stat & PHASEMASK; 1192 1193 switch (sc->sc_phase) { 1194 case PH_DATA_OUT: 1195 trm_dataio_xfer(sc, XFERDATAOUT); 1196 break; 1197 case PH_DATA_IN: 1198 trm_dataio_xfer(sc, XFERDATAIN); 1199 break; 1200 case PH_COMMAND: 1201 trm_command_phase1(sc); 1202 break; 1203 case PH_STATUS: 1204 trm_status_phase1(sc); 1205 break; 1206 case PH_MSG_OUT: 1207 trm_msgout_phase1(sc); 1208 break; 1209 case PH_MSG_IN: 1210 trm_msgin_phase1(sc); 1211 break; 1212 case PH_BUS_FREE: 1213 break; 1214 default: 1215 printf("%s: unexpected phase in trm_intr() phase1\n", 1216 sc->sc_dev.dv_xname); 1217 break; 1218 } 1219 1220 return (1); 1221 } 1222 return (0); 1223 } 1224 1225 static void 1226 trm_msgout_phase1(sc) 1227 struct trm_softc *sc; 1228 { 1229 bus_space_tag_t iot = sc->sc_iot; 1230 bus_space_handle_t ioh = sc->sc_ioh; 1231 struct trm_srb *srb; 1232 struct scsipi_periph *periph; 1233 struct trm_tinfo *ti; 1234 1235 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1236 1237 srb = sc->sc_actsrb; 1238 1239 /* message out phase */ 1240 if (srb != NULL) { 1241 periph = srb->xs->xs_periph; 1242 ti = &sc->sc_tinfo[periph->periph_target]; 1243 1244 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1245 (ti->flag & WIDE_NEGO_ENABLE)) { 1246 /* send WDTR */ 1247 ti->flag &= ~SYNC_NEGO_DONE; 1248 1249 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1250 sc->sc_msgbuf[1] = MSG_EXTENDED; 1251 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1252 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1253 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1254 sc->sc_msgcnt = 5; 1255 1256 ti->flag |= WIDE_NEGO_DOING; 1257 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1258 (ti->flag & SYNC_NEGO_ENABLE)) { 1259 /* send SDTR */ 1260 int cnt = 0; 1261 1262 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1263 sc->sc_msgbuf[cnt++] = 1264 MSG_IDENTIFY(periph->periph_lun, 0); 1265 1266 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1267 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1268 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1269 sc->sc_msgbuf[cnt++] = ti->period; 1270 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1271 sc->sc_msgcnt = cnt; 1272 ti->flag |= SYNC_NEGO_DOING; 1273 } 1274 } 1275 if (sc->sc_msgcnt == 0) { 1276 sc->sc_msgbuf[0] = MSG_ABORT; 1277 sc->sc_msgcnt = 1; 1278 sc->sc_state = TRM_ABORT_SENT; 1279 } 1280 1281 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1282 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1283 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1284 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1285 1286 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1287 sc->sc_msgbuf, sc->sc_msgcnt); 1288 sc->sc_msgcnt = 0; 1289 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1290 1291 /* it's important for atn stop */ 1292 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1293 1294 /* 1295 * SCSI command 1296 */ 1297 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1298 } 1299 1300 static void 1301 trm_command_phase1(sc) 1302 struct trm_softc *sc; 1303 { 1304 bus_space_tag_t iot = sc->sc_iot; 1305 bus_space_handle_t ioh = sc->sc_ioh; 1306 struct trm_srb *srb; 1307 1308 srb = sc->sc_actsrb; 1309 if (srb == NULL) { 1310 DPRINTF(("trm_command_phase1: no active srb\n")); 1311 return; 1312 } 1313 1314 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1315 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1316 1317 sc->sc_state = TRM_COMMAND; 1318 /* it's important for atn stop */ 1319 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1320 1321 /* 1322 * SCSI command 1323 */ 1324 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1325 } 1326 1327 static void 1328 trm_dataout_phase0(sc, stat) 1329 struct trm_softc *sc; 1330 int stat; 1331 { 1332 bus_space_tag_t iot = sc->sc_iot; 1333 bus_space_handle_t ioh = sc->sc_ioh; 1334 struct trm_srb *srb; 1335 struct scsipi_periph *periph; 1336 struct trm_tinfo *ti; 1337 struct trm_sg_entry *sg; 1338 int sgindex; 1339 u_int32_t xferlen, leftcnt = 0; 1340 1341 if (sc->sc_state == TRM_XFERPAD) 1342 return; 1343 1344 srb = sc->sc_actsrb; 1345 if (srb == NULL) { 1346 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1347 return; 1348 } 1349 periph = srb->xs->xs_periph; 1350 ti = &sc->sc_tinfo[periph->periph_target]; 1351 1352 if ((stat & PARITYERROR) != 0) 1353 srb->flag |= PARITY_ERROR; 1354 1355 if ((stat & SCSIXFERDONE) == 0) { 1356 /* 1357 * when data transfer from DMA FIFO to SCSI FIFO 1358 * if there was some data left in SCSI FIFO 1359 */ 1360 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1361 SCSI_FIFOCNT_MASK; 1362 if (ti->synctl & WIDE_SYNC) 1363 /* 1364 * if WIDE scsi SCSI FIFOCNT unit is word 1365 * so need to * 2 1366 */ 1367 leftcnt <<= 1; 1368 } 1369 /* 1370 * calculate all the residue data that was not yet transferred 1371 * SCSI transfer counter + left in SCSI FIFO data 1372 * 1373 * .....TRM_SCSI_XCNT (24bits) 1374 * The counter always decrements by one for every SCSI 1375 * byte transfer. 1376 * .....TRM_SCSI_FIFOCNT ( 5bits) 1377 * The counter is SCSI FIFO offset counter 1378 */ 1379 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1380 if (leftcnt == 1) { 1381 leftcnt = 0; 1382 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1383 } 1384 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1385 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1386 DMAXFERCOMP) == 0) 1387 ; /* XXX needs timeout */ 1388 1389 srb->buflen = 0; 1390 } else { 1391 /* Update SG list */ 1392 1393 /* 1394 * if transfer not yet complete 1395 * there were some data residue in SCSI FIFO or 1396 * SCSI transfer counter not empty 1397 */ 1398 if (srb->buflen != leftcnt) { 1399 /* data that had transferred length */ 1400 xferlen = srb->buflen - leftcnt; 1401 1402 /* next time to be transferred length */ 1403 srb->buflen = leftcnt; 1404 1405 /* 1406 * parsing from last time disconnect sgindex 1407 */ 1408 sg = srb->sgentry + srb->sgindex; 1409 for (sgindex = srb->sgindex; 1410 sgindex < srb->sgcnt; 1411 sgindex++, sg++) { 1412 /* 1413 * find last time which SG transfer 1414 * be disconnect 1415 */ 1416 if (xferlen >= le32toh(sg->length)) 1417 xferlen -= le32toh(sg->length); 1418 else { 1419 /* 1420 * update last time 1421 * disconnected SG list 1422 */ 1423 /* residue data length */ 1424 sg->length = 1425 htole32(le32toh(sg->length) 1426 - xferlen); 1427 /* residue data pointer */ 1428 sg->address = 1429 htole32(le32toh(sg->address) 1430 + xferlen); 1431 srb->sgindex = sgindex; 1432 break; 1433 } 1434 } 1435 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1436 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1437 } 1438 } 1439 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1440 } 1441 1442 static void 1443 trm_datain_phase0(sc, stat) 1444 struct trm_softc *sc; 1445 int stat; 1446 { 1447 bus_space_tag_t iot = sc->sc_iot; 1448 bus_space_handle_t ioh = sc->sc_ioh; 1449 struct trm_srb *srb; 1450 struct trm_sg_entry *sg; 1451 int sgindex; 1452 u_int32_t xferlen, leftcnt = 0; 1453 1454 if (sc->sc_state == TRM_XFERPAD) 1455 return; 1456 1457 srb = sc->sc_actsrb; 1458 if (srb == NULL) { 1459 DPRINTF(("trm_datain_phase0: no active srb\n")); 1460 return; 1461 } 1462 1463 if (stat & PARITYERROR) 1464 srb->flag |= PARITY_ERROR; 1465 1466 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1467 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1468 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1469 DMAXFERCOMP) == 0) 1470 ; /* XXX needs timeout */ 1471 1472 srb->buflen = 0; 1473 } else { /* phase changed */ 1474 /* 1475 * parsing the case: 1476 * when a transfer not yet complete 1477 * but be disconnected by upper layer 1478 * if transfer not yet complete 1479 * there were some data residue in SCSI FIFO or 1480 * SCSI transfer counter not empty 1481 */ 1482 if (srb->buflen != leftcnt) { 1483 /* 1484 * data that had transferred length 1485 */ 1486 xferlen = srb->buflen - leftcnt; 1487 1488 /* 1489 * next time to be transferred length 1490 */ 1491 srb->buflen = leftcnt; 1492 1493 /* 1494 * parsing from last time disconnect sgindex 1495 */ 1496 sg = srb->sgentry + srb->sgindex; 1497 for (sgindex = srb->sgindex; 1498 sgindex < srb->sgcnt; 1499 sgindex++, sg++) { 1500 /* 1501 * find last time which SG transfer 1502 * be disconnect 1503 */ 1504 if (xferlen >= le32toh(sg->length)) 1505 xferlen -= le32toh(sg->length); 1506 else { 1507 /* 1508 * update last time 1509 * disconnected SG list 1510 */ 1511 /* residue data length */ 1512 sg->length = 1513 htole32(le32toh(sg->length) 1514 - xferlen); 1515 /* residue data pointer */ 1516 sg->address = 1517 htole32(le32toh(sg->address) 1518 + xferlen); 1519 srb->sgindex = sgindex; 1520 break; 1521 } 1522 } 1523 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1524 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1525 } 1526 } 1527 } 1528 1529 static void 1530 trm_dataio_xfer(sc, iodir) 1531 struct trm_softc *sc; 1532 int iodir; 1533 { 1534 bus_space_tag_t iot = sc->sc_iot; 1535 bus_space_handle_t ioh = sc->sc_ioh; 1536 struct trm_srb *srb; 1537 struct scsipi_periph *periph; 1538 struct trm_tinfo *ti; 1539 1540 srb = sc->sc_actsrb; 1541 if (srb == NULL) { 1542 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1543 return; 1544 } 1545 periph = srb->xs->xs_periph; 1546 ti = &sc->sc_tinfo[periph->periph_target]; 1547 1548 if (srb->sgindex < srb->sgcnt) { 1549 if (srb->buflen > 0) { 1550 /* 1551 * load what physical address of Scatter/Gather 1552 * list table want to be transfer 1553 */ 1554 sc->sc_state = TRM_DATA_XFER; 1555 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1556 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1557 srb->sgaddr + 1558 srb->sgindex * sizeof(struct trm_sg_entry)); 1559 /* 1560 * load how many bytes in the Scatter/Gather list table 1561 */ 1562 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1563 (srb->sgcnt - srb->sgindex) 1564 * sizeof(struct trm_sg_entry)); 1565 /* 1566 * load total xfer length (24bits) max value 16Mbyte 1567 */ 1568 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1569 /* Start DMA transfer */ 1570 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1571 iodir | SGXFER); 1572 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1573 STARTDMAXFER); 1574 1575 /* Start SCSI transfer */ 1576 /* it's important for atn stop */ 1577 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1578 DO_DATALATCH); 1579 1580 /* 1581 * SCSI command 1582 */ 1583 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1584 (iodir == XFERDATAOUT) ? 1585 SCMD_DMA_OUT : SCMD_DMA_IN); 1586 } else { /* xfer pad */ 1587 if (srb->sgcnt) { 1588 srb->hastat = H_OVER_UNDER_RUN; 1589 } 1590 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1591 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1592 1593 if (iodir == XFERDATAOUT) 1594 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1595 else 1596 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1597 1598 sc->sc_state = TRM_XFERPAD; 1599 /* it's important for atn stop */ 1600 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1601 DO_DATALATCH); 1602 1603 /* 1604 * SCSI command 1605 */ 1606 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1607 (iodir == XFERDATAOUT) ? 1608 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1609 } 1610 } 1611 } 1612 1613 static void 1614 trm_status_phase0(sc) 1615 struct trm_softc *sc; 1616 { 1617 bus_space_tag_t iot = sc->sc_iot; 1618 bus_space_handle_t ioh = sc->sc_ioh; 1619 struct trm_srb *srb; 1620 1621 srb = sc->sc_actsrb; 1622 if (srb == NULL) { 1623 DPRINTF(("trm_status_phase0: no active srb\n")); 1624 return; 1625 } 1626 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1627 sc->sc_state = TRM_COMPLETED; 1628 /* it's important for atn stop */ 1629 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1630 1631 /* 1632 * SCSI command 1633 */ 1634 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1635 } 1636 1637 static void 1638 trm_status_phase1(sc) 1639 struct trm_softc *sc; 1640 { 1641 bus_space_tag_t iot = sc->sc_iot; 1642 bus_space_handle_t ioh = sc->sc_ioh; 1643 1644 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1645 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1646 & SCSI_FIFO_EMPTY) == 0) 1647 bus_space_write_2(iot, ioh, 1648 TRM_SCSI_CONTROL, DO_CLRFIFO); 1649 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1650 & DMA_FIFO_EMPTY) == 0) 1651 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1652 } else { 1653 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1654 & DMA_FIFO_EMPTY) == 0) 1655 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1656 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1657 & SCSI_FIFO_EMPTY) == 0) 1658 bus_space_write_2(iot, ioh, 1659 TRM_SCSI_CONTROL, DO_CLRFIFO); 1660 } 1661 sc->sc_state = TRM_STATUS; 1662 /* it's important for atn stop */ 1663 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1664 1665 /* 1666 * SCSI command 1667 */ 1668 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1669 } 1670 1671 static void 1672 trm_msgin_phase0(sc) 1673 struct trm_softc *sc; 1674 { 1675 bus_space_tag_t iot = sc->sc_iot; 1676 bus_space_handle_t ioh = sc->sc_ioh; 1677 struct trm_srb *srb; 1678 struct scsipi_periph *periph; 1679 struct trm_tinfo *ti; 1680 int index; 1681 u_int8_t msgin_code; 1682 1683 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1684 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1685 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1686 switch (msgin_code) { 1687 case MSG_DISCONNECT: 1688 sc->sc_state = TRM_DISCONNECTED; 1689 break; 1690 1691 case MSG_SAVEDATAPOINTER: 1692 break; 1693 1694 case MSG_EXTENDED: 1695 case MSG_SIMPLE_Q_TAG: 1696 case MSG_HEAD_OF_Q_TAG: 1697 case MSG_ORDERED_Q_TAG: 1698 sc->sc_state = TRM_EXTEND_MSGIN; 1699 /* extended message (01h) */ 1700 sc->sc_msgbuf[0] = msgin_code; 1701 1702 sc->sc_msgcnt = 1; 1703 /* extended message length (n) */ 1704 sc->sc_msg = &sc->sc_msgbuf[1]; 1705 1706 break; 1707 case MSG_MESSAGE_REJECT: 1708 /* Reject message */ 1709 srb = sc->sc_actsrb; 1710 if (srb == NULL) { 1711 DPRINTF(("trm_msgin_phase0: " 1712 " message reject without actsrb\n")); 1713 break; 1714 } 1715 periph = srb->xs->xs_periph; 1716 ti = &sc->sc_tinfo[periph->periph_target]; 1717 1718 if (ti->flag & WIDE_NEGO_ENABLE) { 1719 /* do wide nego reject */ 1720 ti->flag |= WIDE_NEGO_DONE; 1721 ti->flag &= 1722 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1723 if ((ti->flag & SYNC_NEGO_ENABLE) && 1724 (ti->flag & SYNC_NEGO_DONE) == 0) { 1725 /* Set ATN, in case ATN was clear */ 1726 sc->sc_state = TRM_MSGOUT; 1727 bus_space_write_2(iot, ioh, 1728 TRM_SCSI_CONTROL, DO_SETATN); 1729 } else 1730 /* Clear ATN */ 1731 bus_space_write_2(iot, ioh, 1732 TRM_SCSI_CONTROL, DO_CLRATN); 1733 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1734 /* do sync nego reject */ 1735 bus_space_write_2(iot, ioh, 1736 TRM_SCSI_CONTROL, DO_CLRATN); 1737 if (ti->flag & SYNC_NEGO_DOING) { 1738 ti->flag &=~(SYNC_NEGO_ENABLE | 1739 SYNC_NEGO_DONE); 1740 ti->synctl = 0; 1741 ti->offset = 0; 1742 bus_space_write_1(iot, ioh, 1743 TRM_SCSI_SYNC, ti->synctl); 1744 bus_space_write_1(iot, ioh, 1745 TRM_SCSI_OFFSET, ti->offset); 1746 } 1747 } 1748 break; 1749 1750 case MSG_IGN_WIDE_RESIDUE: 1751 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1752 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1753 break; 1754 1755 default: 1756 /* 1757 * Restore data pointer message 1758 * Save data pointer message 1759 * Completion message 1760 * NOP message 1761 */ 1762 break; 1763 } 1764 } else { 1765 /* 1766 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1767 * Parsing incoming extented messages 1768 */ 1769 *sc->sc_msg++ = msgin_code; 1770 sc->sc_msgcnt++; 1771 1772 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1773 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1774 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1775 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1776 1777 switch (sc->sc_msgbuf[0]) { 1778 case MSG_SIMPLE_Q_TAG: 1779 case MSG_HEAD_OF_Q_TAG: 1780 case MSG_ORDERED_Q_TAG: 1781 /* 1782 * is QUEUE tag message : 1783 * 1784 * byte 0: 1785 * HEAD QUEUE TAG (20h) 1786 * ORDERED QUEUE TAG (21h) 1787 * SIMPLE QUEUE TAG (22h) 1788 * byte 1: 1789 * Queue tag (00h - FFh) 1790 */ 1791 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1792 /* XXX XXX XXX */ 1793 struct trm_linfo *li; 1794 int tagid; 1795 1796 sc->sc_flag &= ~WAIT_TAGMSG; 1797 tagid = sc->sc_msgbuf[1]; 1798 ti = &sc->sc_tinfo[sc->resel_target]; 1799 li = ti->linfo[sc->resel_lun]; 1800 srb = li->queued[tagid]; 1801 if (srb != NULL) { 1802 sc->sc_actsrb = srb; 1803 sc->sc_state = TRM_DATA_XFER; 1804 break; 1805 } else { 1806 printf("%s: invalid tag id\n", 1807 sc->sc_dev.dv_xname); 1808 } 1809 1810 sc->sc_state = TRM_UNEXPECT_RESEL; 1811 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1812 sc->sc_msgcnt = 1; 1813 bus_space_write_2(iot, ioh, 1814 TRM_SCSI_CONTROL, DO_SETATN); 1815 } else 1816 sc->sc_state = TRM_IDLE; 1817 break; 1818 1819 case MSG_EXTENDED: 1820 srb = sc->sc_actsrb; 1821 if (srb == NULL) { 1822 DPRINTF(("trm_msgin_phase0: " 1823 "extended message without actsrb\n")); 1824 break; 1825 } 1826 periph = srb->xs->xs_periph; 1827 ti = &sc->sc_tinfo[periph->periph_target]; 1828 1829 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1830 sc->sc_msgcnt == 4) { 1831 /* 1832 * is Wide data xfer Extended message : 1833 * ====================================== 1834 * WIDE DATA TRANSFER REQUEST 1835 * ====================================== 1836 * byte 0 : Extended message (01h) 1837 * byte 1 : Extended message length (02h) 1838 * byte 2 : WIDE DATA TRANSFER code (03h) 1839 * byte 3 : Transfer width exponent 1840 */ 1841 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1842 /* Length is wrong, reject it */ 1843 ti->flag &= ~(WIDE_NEGO_ENABLE | 1844 WIDE_NEGO_DONE); 1845 sc->sc_state = TRM_MSGOUT; 1846 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1847 sc->sc_msgcnt = 1; 1848 bus_space_write_2(iot, ioh, 1849 TRM_SCSI_CONTROL, DO_SETATN); 1850 break; 1851 } 1852 1853 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1854 sc->sc_msgbuf[3] = 1855 MSG_EXT_WDTR_BUS_8_BIT; 1856 1857 if (sc->sc_msgbuf[3] > 1858 MSG_EXT_WDTR_BUS_32_BIT) { 1859 /* reject_msg: */ 1860 ti->flag &= ~(WIDE_NEGO_ENABLE | 1861 WIDE_NEGO_DONE); 1862 sc->sc_state = TRM_MSGOUT; 1863 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1864 sc->sc_msgcnt = 1; 1865 bus_space_write_2(iot, ioh, 1866 TRM_SCSI_CONTROL, DO_SETATN); 1867 break; 1868 } 1869 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1870 /* do 16 bits */ 1871 sc->sc_msgbuf[3] = 1872 MSG_EXT_WDTR_BUS_16_BIT; 1873 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1874 ti->flag |= WIDE_NEGO_DONE; 1875 ti->flag &= ~(SYNC_NEGO_DONE | 1876 WIDE_NEGO_ENABLE); 1877 if (sc->sc_msgbuf[3] != 1878 MSG_EXT_WDTR_BUS_8_BIT) 1879 /* is Wide data xfer */ 1880 ti->synctl |= WIDE_SYNC; 1881 trm_update_xfer_mode(sc, 1882 periph->periph_target); 1883 } 1884 1885 sc->sc_state = TRM_MSGOUT; 1886 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1887 DO_SETATN); 1888 break; 1889 1890 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1891 sc->sc_msgcnt == 5) { 1892 /* 1893 * is 8bit transfer Extended message : 1894 * ================================= 1895 * SYNCHRONOUS DATA TRANSFER REQUEST 1896 * ================================= 1897 * byte 0 : Extended message (01h) 1898 * byte 1 : Extended message length (03) 1899 * byte 2 : SYNC DATA TRANSFER code (01h) 1900 * byte 3 : Transfer period factor 1901 * byte 4 : REQ/ACK offset 1902 */ 1903 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1904 /* reject_msg */ 1905 sc->sc_state = TRM_MSGOUT; 1906 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1907 sc->sc_msgcnt = 1; 1908 bus_space_write_2(iot, ioh, 1909 TRM_SCSI_CONTROL, DO_SETATN); 1910 break; 1911 } 1912 1913 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1914 ti->flag &= 1915 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1916 ti->flag |= SYNC_NEGO_DONE; 1917 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1918 sc->sc_msgbuf[3] = 0; 1919 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1920 sc->sc_msgbuf[4] = 1921 TRM_MAX_OFFSET; 1922 1923 if (sc->sc_msgbuf[3] == 0 || 1924 sc->sc_msgbuf[4] == 0) { 1925 /* set async */ 1926 ti->synctl = 0; 1927 ti->offset = 0; 1928 } else { 1929 /* set sync */ 1930 /* Transfer period factor */ 1931 ti->period = sc->sc_msgbuf[3]; 1932 /* REQ/ACK offset */ 1933 ti->offset = sc->sc_msgbuf[4]; 1934 for (index = 0; 1935 index < NPERIOD; 1936 index++) 1937 if (ti->period <= 1938 trm_clock_period[ 1939 index]) 1940 break; 1941 1942 ti->synctl |= ALT_SYNC | index; 1943 } 1944 /* 1945 * program SCSI control register 1946 */ 1947 bus_space_write_1(iot, ioh, 1948 TRM_SCSI_SYNC, ti->synctl); 1949 bus_space_write_1(iot, ioh, 1950 TRM_SCSI_OFFSET, ti->offset); 1951 trm_update_xfer_mode(sc, 1952 periph->periph_target); 1953 } 1954 sc->sc_state = TRM_IDLE; 1955 } 1956 break; 1957 default: 1958 break; 1959 } 1960 } 1961 1962 /* it's important for atn stop */ 1963 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1964 1965 /* 1966 * SCSI command 1967 */ 1968 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1969 } 1970 1971 static void 1972 trm_msgin_phase1(sc) 1973 struct trm_softc *sc; 1974 { 1975 bus_space_tag_t iot = sc->sc_iot; 1976 bus_space_handle_t ioh = sc->sc_ioh; 1977 1978 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1979 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1980 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1981 sc->sc_state = TRM_MSGIN; 1982 } 1983 1984 /* it's important for atn stop */ 1985 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1986 1987 /* 1988 * SCSI command 1989 */ 1990 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1991 } 1992 1993 static void 1994 trm_disconnect(sc) 1995 struct trm_softc *sc; 1996 { 1997 bus_space_tag_t iot = sc->sc_iot; 1998 bus_space_handle_t ioh = sc->sc_ioh; 1999 struct trm_srb *srb; 2000 int s; 2001 2002 s = splbio(); 2003 2004 srb = sc->sc_actsrb; 2005 DPRINTF(("trm_disconnect...............\n")); 2006 2007 if (srb == NULL) { 2008 DPRINTF(("trm_disconnect: no active srb\n")); 2009 DELAY(1000); /* 1 msec */ 2010 2011 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2012 DO_CLRFIFO | DO_HWRESELECT); 2013 return; 2014 } 2015 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2016 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2017 DO_CLRFIFO | DO_HWRESELECT); 2018 DELAY(100); 2019 2020 switch (sc->sc_state) { 2021 case TRM_UNEXPECT_RESEL: 2022 sc->sc_state = TRM_IDLE; 2023 break; 2024 2025 case TRM_ABORT_SENT: 2026 goto finish; 2027 2028 case TRM_START: 2029 case TRM_MSGOUT: 2030 { 2031 /* Selection time out - discard all LUNs if empty */ 2032 struct scsipi_periph *periph; 2033 struct trm_tinfo *ti; 2034 struct trm_linfo *li; 2035 int lun; 2036 2037 DPRINTF(("selection timeout\n")); 2038 2039 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2040 2041 periph = srb->xs->xs_periph; 2042 ti = &sc->sc_tinfo[periph->periph_target]; 2043 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2044 li = ti->linfo[lun]; 2045 if (li != NULL && 2046 li->untagged == NULL && li->used == 0) { 2047 ti->linfo[lun] = NULL; 2048 free(li, M_DEVBUF); 2049 } 2050 } 2051 } 2052 goto finish; 2053 2054 case TRM_DISCONNECTED: 2055 sc->sc_actsrb = NULL; 2056 sc->sc_state = TRM_IDLE; 2057 goto sched; 2058 2059 case TRM_COMPLETED: 2060 goto finish; 2061 } 2062 2063 out: 2064 splx(s); 2065 return; 2066 2067 finish: 2068 sc->sc_state = TRM_IDLE; 2069 trm_done(sc, srb); 2070 goto out; 2071 2072 sched: 2073 trm_sched(sc); 2074 goto out; 2075 } 2076 2077 static void 2078 trm_reselect(sc) 2079 struct trm_softc *sc; 2080 { 2081 bus_space_tag_t iot = sc->sc_iot; 2082 bus_space_handle_t ioh = sc->sc_ioh; 2083 struct trm_tinfo *ti; 2084 struct trm_linfo *li; 2085 int target, lun; 2086 2087 DPRINTF(("trm_reselect.................\n")); 2088 2089 if (sc->sc_actsrb != NULL) { 2090 /* arbitration lost but reselection win */ 2091 sc->sc_state = TRM_READY; 2092 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2093 ti = &sc->sc_tinfo[target]; 2094 } else { 2095 /* Read Reselected Target Id and LUN */ 2096 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2097 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2098 ti = &sc->sc_tinfo[target]; 2099 li = ti->linfo[lun]; 2100 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2101 2102 /* 2103 * Check to see if we are running an un-tagged command. 2104 * Otherwise ack the IDENTIFY and wait for a tag message. 2105 */ 2106 if (li != NULL) { 2107 if (li->untagged != NULL && li->busy) { 2108 sc->sc_actsrb = li->untagged; 2109 sc->sc_state = TRM_DATA_XFER; 2110 } else { 2111 sc->resel_target = target; 2112 sc->resel_lun = lun; 2113 /* XXX XXX XXX */ 2114 sc->sc_flag |= WAIT_TAGMSG; 2115 } 2116 } 2117 2118 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2119 sc->sc_actsrb == NULL) { 2120 printf("%s: reselect from target %d lun %d " 2121 "without nexus; sending abort\n", 2122 sc->sc_dev.dv_xname, target, lun); 2123 sc->sc_state = TRM_UNEXPECT_RESEL; 2124 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2125 sc->sc_msgcnt = 1; 2126 bus_space_write_2(iot, ioh, 2127 TRM_SCSI_CONTROL, DO_SETATN); 2128 } 2129 } 2130 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2131 /* 2132 * Program HA ID, target ID, period and offset 2133 */ 2134 /* target ID */ 2135 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2136 2137 /* host ID */ 2138 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2139 2140 /* period */ 2141 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2142 2143 /* offset */ 2144 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2145 2146 /* it's important for atn stop */ 2147 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2148 /* 2149 * SCSI command 2150 */ 2151 /* to rls the /ACK signal */ 2152 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2153 } 2154 2155 /* 2156 * Complete execution of a SCSI command 2157 * Signal completion to the generic SCSI driver 2158 */ 2159 static void 2160 trm_done(sc, srb) 2161 struct trm_softc *sc; 2162 struct trm_srb *srb; 2163 { 2164 struct scsipi_xfer *xs = srb->xs; 2165 2166 DPRINTF(("trm_done..................\n")); 2167 2168 if (xs == NULL) 2169 return; 2170 2171 if ((xs->xs_control & XS_CTL_POLL) == 0) 2172 callout_stop(&xs->xs_callout); 2173 2174 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2175 srb->flag & AUTO_REQSENSE) { 2176 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2177 srb->dmap->dm_mapsize, 2178 ((xs->xs_control & XS_CTL_DATA_IN) || 2179 (srb->flag & AUTO_REQSENSE)) ? 2180 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2181 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2182 } 2183 2184 /* 2185 * target status 2186 */ 2187 xs->status = srb->tastat; 2188 2189 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2190 2191 switch (xs->status) { 2192 case SCSI_OK: 2193 /* 2194 * process initiator status...... 2195 * Adapter (initiator) status 2196 */ 2197 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2198 printf("%s: over/under run error\n", 2199 sc->sc_dev.dv_xname); 2200 srb->tastat = 0; 2201 /* Illegal length (over/under run) */ 2202 xs->error = XS_DRIVER_STUFFUP; 2203 } else if ((srb->flag & PARITY_ERROR) != 0) { 2204 printf("%s: parity error\n", 2205 sc->sc_dev.dv_xname); 2206 /* Driver failed to perform operation */ 2207 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2208 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2209 xs->resid = srb->buflen; 2210 xs->error = XS_TIMEOUT; 2211 } else { 2212 /* No error */ 2213 xs->resid = srb->buflen; 2214 srb->hastat = 0; 2215 if (srb->flag & AUTO_REQSENSE) { 2216 /* there is no error, (sense is invalid) */ 2217 xs->error = XS_SENSE; 2218 } else { 2219 srb->tastat = 0; 2220 xs->error = XS_NOERROR; 2221 } 2222 } 2223 break; 2224 2225 case SCSI_CHECK: 2226 if ((srb->flag & AUTO_REQSENSE) != 0 || 2227 trm_request_sense(sc, srb) != 0) { 2228 printf("%s: request sense failed\n", 2229 sc->sc_dev.dv_xname); 2230 xs->error = XS_DRIVER_STUFFUP; 2231 break; 2232 } 2233 xs->error = XS_SENSE; 2234 return; 2235 2236 case SCSI_SEL_TIMEOUT: 2237 srb->hastat = H_SEL_TIMEOUT; 2238 srb->tastat = 0; 2239 xs->error = XS_SELTIMEOUT; 2240 break; 2241 2242 case SCSI_QUEUE_FULL: 2243 case SCSI_BUSY: 2244 xs->error = XS_BUSY; 2245 break; 2246 2247 case SCSI_RESV_CONFLICT: 2248 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2249 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2250 xs->error = XS_BUSY; 2251 break; 2252 2253 default: 2254 srb->hastat = 0; 2255 printf("%s: trm_done(): unknown status = %02x\n", 2256 sc->sc_dev.dv_xname, xs->status); 2257 xs->error = XS_DRIVER_STUFFUP; 2258 break; 2259 } 2260 2261 trm_dequeue(sc, srb); 2262 if (srb == sc->sc_actsrb) { 2263 sc->sc_actsrb = NULL; 2264 trm_sched(sc); 2265 } 2266 2267 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2268 2269 /* Notify cmd done */ 2270 scsipi_done(xs); 2271 } 2272 2273 static int 2274 trm_request_sense(sc, srb) 2275 struct trm_softc *sc; 2276 struct trm_srb *srb; 2277 { 2278 struct scsipi_xfer *xs; 2279 struct scsipi_periph *periph; 2280 struct trm_tinfo *ti; 2281 struct trm_linfo *li; 2282 struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2283 int error; 2284 2285 DPRINTF(("trm_request_sense...\n")); 2286 2287 xs = srb->xs; 2288 periph = xs->xs_periph; 2289 2290 srb->flag |= AUTO_REQSENSE; 2291 2292 /* Status of initiator/target */ 2293 srb->hastat = 0; 2294 srb->tastat = 0; 2295 2296 ss->opcode = REQUEST_SENSE; 2297 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2298 ss->unused[0] = ss->unused[1] = 0; 2299 ss->length = sizeof(struct scsipi_sense_data); 2300 ss->control = 0; 2301 2302 srb->buflen = sizeof(struct scsipi_sense_data); 2303 srb->sgcnt = 1; 2304 srb->sgindex = 0; 2305 srb->cmdlen = sizeof(struct scsipi_sense); 2306 2307 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2308 &xs->sense.scsi_sense, srb->buflen, NULL, 2309 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2310 return error; 2311 } 2312 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2313 srb->buflen, BUS_DMASYNC_PREREAD); 2314 2315 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2316 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2317 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2318 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2319 2320 ti = &sc->sc_tinfo[periph->periph_target]; 2321 li = ti->linfo[periph->periph_lun]; 2322 if (li->busy > 0) 2323 li->busy = 0; 2324 trm_dequeue(sc, srb); 2325 li->untagged = srb; /* must be executed first to fix C/A */ 2326 li->busy = 2; 2327 2328 if (srb == sc->sc_actsrb) 2329 trm_select(sc, srb); 2330 else { 2331 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2332 if (sc->sc_actsrb == NULL) 2333 trm_sched(sc); 2334 } 2335 return 0; 2336 } 2337 2338 static void 2339 trm_dequeue(sc, srb) 2340 struct trm_softc *sc; 2341 struct trm_srb *srb; 2342 { 2343 struct scsipi_periph *periph; 2344 struct trm_tinfo *ti; 2345 struct trm_linfo *li; 2346 2347 periph = srb->xs->xs_periph; 2348 ti = &sc->sc_tinfo[periph->periph_target]; 2349 li = ti->linfo[periph->periph_lun]; 2350 2351 if (li->untagged == srb) { 2352 li->busy = 0; 2353 li->untagged = NULL; 2354 } 2355 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2356 li->queued[srb->tag[1]] = NULL; 2357 li->used--; 2358 } 2359 } 2360 2361 static void 2362 trm_reset_scsi_bus(sc) 2363 struct trm_softc *sc; 2364 { 2365 bus_space_tag_t iot = sc->sc_iot; 2366 bus_space_handle_t ioh = sc->sc_ioh; 2367 int timeout, s; 2368 2369 DPRINTF(("trm_reset_scsi_bus.........\n")); 2370 2371 s = splbio(); 2372 2373 sc->sc_flag |= RESET_DEV; 2374 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2375 for (timeout = 20000; timeout >= 0; timeout--) { 2376 DELAY(1); 2377 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2378 INT_SCSIRESET) == 0) 2379 break; 2380 } 2381 if (timeout == 0) 2382 printf(": scsibus reset timeout\n"); 2383 2384 splx(s); 2385 } 2386 2387 static void 2388 trm_scsi_reset_detect(sc) 2389 struct trm_softc *sc; 2390 { 2391 bus_space_tag_t iot = sc->sc_iot; 2392 bus_space_handle_t ioh = sc->sc_ioh; 2393 int s; 2394 2395 DPRINTF(("trm_scsi_reset_detect...............\n")); 2396 DELAY(1000000); /* delay 1 sec */ 2397 2398 s = splbio(); 2399 2400 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2401 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2402 2403 if (sc->sc_flag & RESET_DEV) { 2404 sc->sc_flag |= RESET_DONE; 2405 } else { 2406 sc->sc_flag |= RESET_DETECT; 2407 sc->sc_actsrb = NULL; 2408 sc->sc_flag = 0; 2409 trm_sched(sc); 2410 } 2411 splx(s); 2412 } 2413 2414 /* 2415 * read seeprom 128 bytes to struct eeprom and check checksum. 2416 * If it is wrong, update with default value. 2417 */ 2418 static void 2419 trm_check_eeprom(sc, eeprom) 2420 struct trm_softc *sc; 2421 struct trm_nvram *eeprom; 2422 { 2423 struct nvram_target *target; 2424 u_int16_t *ep; 2425 u_int16_t chksum; 2426 int i; 2427 2428 DPRINTF(("trm_check_eeprom......\n")); 2429 trm_eeprom_read_all(sc, eeprom); 2430 ep = (u_int16_t *)eeprom; 2431 chksum = 0; 2432 for (i = 0; i < 64; i++) 2433 chksum += le16toh(*ep++); 2434 2435 if (chksum != TRM_NVRAM_CKSUM) { 2436 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2437 /* 2438 * Checksum error, load default 2439 */ 2440 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2441 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2442 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2443 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2444 eeprom->subclass = 0x00; 2445 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2446 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2447 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2448 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2449 eeprom->reserved0 = 0x00; 2450 2451 for (i = 0, target = eeprom->target; 2452 i < TRM_MAX_TARGETS; 2453 i++, target++) { 2454 target->config0 = 0x77; 2455 target->period = 0x00; 2456 target->config2 = 0x00; 2457 target->config3 = 0x00; 2458 } 2459 2460 eeprom->scsi_id = 7; 2461 eeprom->channel_cfg = 0x0F; 2462 eeprom->delay_time = 0; 2463 eeprom->max_tag = 4; 2464 eeprom->reserved1 = 0x15; 2465 eeprom->boot_target = 0; 2466 eeprom->boot_lun = 0; 2467 eeprom->reserved2 = 0; 2468 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2469 2470 chksum = 0; 2471 ep = (u_int16_t *)eeprom; 2472 for (i = 0; i < 63; i++) 2473 chksum += le16toh(*ep++); 2474 2475 chksum = TRM_NVRAM_CKSUM - chksum; 2476 eeprom->checksum0 = chksum & 0xFF; 2477 eeprom->checksum1 = chksum >> 8; 2478 2479 trm_eeprom_write_all(sc, eeprom); 2480 } 2481 } 2482 2483 /* 2484 * write struct eeprom 128 bytes to seeprom 2485 */ 2486 static void 2487 trm_eeprom_write_all(sc, eeprom) 2488 struct trm_softc *sc; 2489 struct trm_nvram *eeprom; 2490 { 2491 bus_space_tag_t iot = sc->sc_iot; 2492 bus_space_handle_t ioh = sc->sc_ioh; 2493 u_int8_t *buf = (u_int8_t *)eeprom; 2494 u_int8_t addr; 2495 2496 /* Enable SEEPROM */ 2497 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2498 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2499 2500 /* 2501 * Write enable 2502 */ 2503 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2504 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2505 trm_eeprom_wait(); 2506 2507 for (addr = 0; addr < 128; addr++, buf++) 2508 trm_eeprom_set_data(sc, addr, *buf); 2509 2510 /* 2511 * Write disable 2512 */ 2513 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2514 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2515 trm_eeprom_wait(); 2516 2517 /* Disable SEEPROM */ 2518 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2519 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2520 } 2521 2522 /* 2523 * write one byte to seeprom 2524 */ 2525 static void 2526 trm_eeprom_set_data(sc, addr, data) 2527 struct trm_softc *sc; 2528 u_int8_t addr; 2529 u_int8_t data; 2530 { 2531 bus_space_tag_t iot = sc->sc_iot; 2532 bus_space_handle_t ioh = sc->sc_ioh; 2533 int i; 2534 u_int8_t send; 2535 2536 /* 2537 * Send write command & address 2538 */ 2539 trm_eeprom_write_cmd(sc, 0x05, addr); 2540 /* 2541 * Write data 2542 */ 2543 for (i = 0; i < 8; i++, data <<= 1) { 2544 send = NVR_SELECT; 2545 if (data & 0x80) /* Start from bit 7 */ 2546 send |= NVR_BITOUT; 2547 2548 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2549 trm_eeprom_wait(); 2550 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2551 trm_eeprom_wait(); 2552 } 2553 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2554 trm_eeprom_wait(); 2555 /* 2556 * Disable chip select 2557 */ 2558 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2559 trm_eeprom_wait(); 2560 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2561 trm_eeprom_wait(); 2562 /* 2563 * Wait for write ready 2564 */ 2565 for (;;) { 2566 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2567 NVR_SELECT | NVR_CLOCK); 2568 trm_eeprom_wait(); 2569 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2570 trm_eeprom_wait(); 2571 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2572 break; 2573 } 2574 /* 2575 * Disable chip select 2576 */ 2577 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2578 } 2579 2580 /* 2581 * read seeprom 128 bytes to struct eeprom 2582 */ 2583 static void 2584 trm_eeprom_read_all(sc, eeprom) 2585 struct trm_softc *sc; 2586 struct trm_nvram *eeprom; 2587 { 2588 bus_space_tag_t iot = sc->sc_iot; 2589 bus_space_handle_t ioh = sc->sc_ioh; 2590 u_int8_t *buf = (u_int8_t *)eeprom; 2591 u_int8_t addr; 2592 2593 /* 2594 * Enable SEEPROM 2595 */ 2596 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2597 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2598 2599 for (addr = 0; addr < 128; addr++) 2600 *buf++ = trm_eeprom_get_data(sc, addr); 2601 2602 /* 2603 * Disable SEEPROM 2604 */ 2605 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2606 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2607 } 2608 2609 /* 2610 * read one byte from seeprom 2611 */ 2612 static u_int8_t 2613 trm_eeprom_get_data(sc, addr) 2614 struct trm_softc *sc; 2615 u_int8_t addr; 2616 { 2617 bus_space_tag_t iot = sc->sc_iot; 2618 bus_space_handle_t ioh = sc->sc_ioh; 2619 int i; 2620 u_int8_t read, data = 0; 2621 2622 /* 2623 * Send read command & address 2624 */ 2625 trm_eeprom_write_cmd(sc, 0x06, addr); 2626 2627 for (i = 0; i < 8; i++) { /* Read data */ 2628 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2629 NVR_SELECT | NVR_CLOCK); 2630 trm_eeprom_wait(); 2631 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2632 /* 2633 * Get data bit while falling edge 2634 */ 2635 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2636 data <<= 1; 2637 if (read & NVR_BITIN) 2638 data |= 1; 2639 2640 trm_eeprom_wait(); 2641 } 2642 /* 2643 * Disable chip select 2644 */ 2645 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2646 return (data); 2647 } 2648 2649 /* 2650 * write SB and Op Code into seeprom 2651 */ 2652 static void 2653 trm_eeprom_write_cmd(sc, cmd, addr) 2654 struct trm_softc *sc; 2655 u_int8_t cmd; 2656 u_int8_t addr; 2657 { 2658 bus_space_tag_t iot = sc->sc_iot; 2659 bus_space_handle_t ioh = sc->sc_ioh; 2660 int i; 2661 u_int8_t send; 2662 2663 /* Program SB+OP code */ 2664 for (i = 0; i < 3; i++, cmd <<= 1) { 2665 send = NVR_SELECT; 2666 if (cmd & 0x04) /* Start from bit 2 */ 2667 send |= NVR_BITOUT; 2668 2669 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2670 trm_eeprom_wait(); 2671 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2672 trm_eeprom_wait(); 2673 } 2674 2675 /* Program address */ 2676 for (i = 0; i < 7; i++, addr <<= 1) { 2677 send = NVR_SELECT; 2678 if (addr & 0x40) /* Start from bit 6 */ 2679 send |= NVR_BITOUT; 2680 2681 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2682 trm_eeprom_wait(); 2683 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2684 trm_eeprom_wait(); 2685 } 2686 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2687 trm_eeprom_wait(); 2688 } 2689
Indexes created Mon Oct 13 21:09:55 GMT 2025