trm.c revision 1.15
1 /* $NetBSD: trm.c,v 1.15 2004/09/25 11:58:19 tsutsui Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.15 2004/09/25 11:58:19 tsutsui Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_all.h> 69 #include <dev/scsipi/scsi_message.h> 70 #include <dev/scsipi/scsipi_all.h> 71 #include <dev/scsipi/scsiconf.h> 72 73 #include <dev/pci/pcidevs.h> 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 #include <dev/pci/trmreg.h> 77 78 /* 79 * feature of chip set MAX value 80 */ 81 #define TRM_MAX_TARGETS 16 82 #define TRM_MAX_LUNS 8 83 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 84 #define TRM_MAX_SRB 32 /* XXX */ 85 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 86 #define TRM_MAX_OFFSET 15 87 #define TRM_MAX_PERIOD 125 88 89 /* 90 * Segment Entry 91 */ 92 struct trm_sg_entry { 93 u_int32_t address; 94 u_int32_t length; 95 }; 96 97 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 98 99 /* 100 ********************************************************************** 101 * The SEEPROM structure for TRM_S1040 102 ********************************************************************** 103 */ 104 struct nvram_target { 105 u_int8_t config0; /* Target configuration byte 0 */ 106 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 107 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 108 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 109 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 110 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 111 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 112 u_int8_t period; /* Target period */ 113 u_int8_t config2; /* Target configuration byte 2 */ 114 u_int8_t config3; /* Target configuration byte 3 */ 115 }; 116 117 struct trm_nvram { 118 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 119 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 120 u_int8_t subclass; /* 4 Sub Class */ 121 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 122 u_int8_t device_id[2]; /* 7,8 Device ID */ 123 u_int8_t reserved0; /* 9 Reserved */ 124 struct nvram_target target[TRM_MAX_TARGETS]; 125 /* 10,11,12,13 126 * 14,15,16,17 127 * .... 128 * 70,71,72,73 */ 129 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 130 u_int8_t channel_cfg; /* 75 Channel configuration */ 131 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 132 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 133 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 134 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 135 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 136 u_int8_t delay_time; /* 76 Power on delay time */ 137 u_int8_t max_tag; /* 77 Maximum tags */ 138 u_int8_t reserved1; /* 78 */ 139 u_int8_t boot_target; /* 79 */ 140 u_int8_t boot_lun; /* 80 */ 141 u_int8_t reserved2; /* 81 */ 142 u_int8_t reserved3[44]; /* 82,..125 */ 143 u_int8_t checksum0; /* 126 */ 144 u_int8_t checksum1; /* 127 */ 145 #define TRM_NVRAM_CKSUM 0x1234 146 }; 147 148 /* Nvram Initiater bits definition */ 149 #define MORE2_DRV 0x00000001 150 #define GREATER_1G 0x00000002 151 #define RST_SCSI_BUS 0x00000004 152 #define ACTIVE_NEGATION 0x00000008 153 #define NO_SEEK 0x00000010 154 #define LUN_CHECK 0x00000020 155 156 #define trm_eeprom_wait() DELAY(30) 157 158 /* 159 *----------------------------------------------------------------------- 160 * SCSI Request Block 161 *----------------------------------------------------------------------- 162 */ 163 struct trm_srb { 164 TAILQ_ENTRY(trm_srb) next; 165 166 struct trm_sg_entry *sgentry; 167 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 168 bus_dmamap_t dmap; 169 bus_size_t sgoffset; /* Xfer buf offset */ 170 171 u_int32_t buflen; /* Total xfer length */ 172 u_int32_t sgaddr; /* SGList physical starting address */ 173 174 int sgcnt; 175 int sgindex; 176 177 int hastat; /* Host Adapter Status */ 178 #define H_STATUS_GOOD 0x00 179 #define H_SEL_TIMEOUT 0x11 180 #define H_OVER_UNDER_RUN 0x12 181 #define H_UNEXP_BUS_FREE 0x13 182 #define H_TARGET_PHASE_F 0x14 183 #define H_INVALID_CCB_OP 0x16 184 #define H_LINK_CCB_BAD 0x17 185 #define H_BAD_TARGET_DIR 0x18 186 #define H_DUPLICATE_CCB 0x19 187 #define H_BAD_CCB_OR_SG 0x1A 188 #define H_ABORT 0xFF 189 int tastat; /* Target SCSI Status Byte */ 190 int flag; /* SRBFlag */ 191 #define AUTO_REQSENSE 0x0001 192 #define PARITY_ERROR 0x0002 193 #define SRB_TIMEOUT 0x0004 194 195 int cmdlen; /* SCSI command length */ 196 u_int8_t cmd[12]; /* SCSI command */ 197 198 u_int8_t tag[2]; 199 }; 200 201 /* 202 * some info about each target and lun on the SCSI bus 203 */ 204 struct trm_linfo { 205 int used; /* number of slots in use */ 206 int avail; /* where to start scanning */ 207 int busy; /* lun in use */ 208 struct trm_srb *untagged; 209 struct trm_srb *queued[TRM_MAX_TAG]; 210 }; 211 212 struct trm_tinfo { 213 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 214 #define SYNC_NEGO_ENABLE 0x0001 215 #define SYNC_NEGO_DOING 0x0002 216 #define SYNC_NEGO_DONE 0x0004 217 #define WIDE_NEGO_ENABLE 0x0008 218 #define WIDE_NEGO_DOING 0x0010 219 #define WIDE_NEGO_DONE 0x0020 220 #define USE_TAG_QUEUING 0x0040 221 #define NO_RESELECT 0x0080 222 struct trm_linfo *linfo[TRM_MAX_LUNS]; 223 224 u_int8_t config0; /* Target Config */ 225 u_int8_t period; /* Max Period for nego. */ 226 u_int8_t synctl; /* Sync control for reg. */ 227 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 228 }; 229 230 /* 231 *----------------------------------------------------------------------- 232 * Adapter Control Block 233 *----------------------------------------------------------------------- 234 */ 235 struct trm_softc { 236 struct device sc_dev; 237 238 bus_space_tag_t sc_iot; 239 bus_space_handle_t sc_ioh; 240 bus_dma_tag_t sc_dmat; 241 bus_dmamap_t sc_dmamap; /* Map the control structures */ 242 243 struct trm_srb *sc_actsrb; 244 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 245 246 TAILQ_HEAD(, trm_srb) sc_freesrb, 247 sc_readysrb; 248 struct trm_srb *sc_srb; /* SRB array */ 249 250 struct trm_sg_entry *sc_sglist; 251 252 int sc_maxid; 253 /* 254 * Link to the generic SCSI driver 255 */ 256 struct scsipi_channel sc_channel; 257 struct scsipi_adapter sc_adapter; 258 259 int sc_id; /* Adapter SCSI Target ID */ 260 261 int sc_state; /* SRB State */ 262 #define TRM_IDLE 0 263 #define TRM_WAIT 1 264 #define TRM_READY 2 265 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 266 #define TRM_MSGIN 4 267 #define TRM_EXTEND_MSGIN 5 268 #define TRM_COMMAND 6 269 #define TRM_START 7 /* arbitration+msg_out+command_out */ 270 #define TRM_DISCONNECTED 8 271 #define TRM_DATA_XFER 9 272 #define TRM_XFERPAD 10 273 #define TRM_STATUS 11 274 #define TRM_COMPLETED 12 275 #define TRM_ABORT_SENT 13 276 #define TRM_UNEXPECT_RESEL 14 277 278 int sc_phase; /* SCSI phase */ 279 int sc_config; 280 #define HCC_WIDE_CARD 0x01 281 #define HCC_SCSI_RESET 0x02 282 #define HCC_PARITY 0x04 283 #define HCC_AUTOTERM 0x08 284 #define HCC_LOW8TERM 0x10 285 #define HCC_UP8TERM 0x20 286 287 int sc_flag; 288 #define RESET_DEV 0x01 289 #define RESET_DETECT 0x02 290 #define RESET_DONE 0x04 291 #define WAIT_TAGMSG 0x08 /* XXX */ 292 293 int sc_msgcnt; 294 295 int resel_target; /* XXX */ 296 int resel_lun; /* XXX */ 297 298 u_int8_t *sc_msg; 299 u_int8_t sc_msgbuf[6]; 300 }; 301 302 /* 303 * SCSI Status codes not defined in scsi_all.h 304 */ 305 #define SCSI_COND_MET 0x04 /* Condition Met */ 306 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 307 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 308 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 309 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 310 311 static int trm_probe(struct device *, struct cfdata *, void *); 312 static void trm_attach(struct device *, struct device *, void *); 313 314 static int trm_init(struct trm_softc *); 315 316 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 317 void *); 318 static void trm_update_xfer_mode(struct trm_softc *, int); 319 static void trm_sched(struct trm_softc *); 320 static int trm_select(struct trm_softc *, struct trm_srb *); 321 static void trm_reset(struct trm_softc *); 322 static void trm_timeout(void *); 323 static int trm_intr(void *); 324 325 static void trm_dataout_phase0(struct trm_softc *, int); 326 static void trm_datain_phase0(struct trm_softc *, int); 327 static void trm_status_phase0(struct trm_softc *); 328 static void trm_msgin_phase0(struct trm_softc *); 329 static void trm_command_phase1(struct trm_softc *); 330 static void trm_status_phase1(struct trm_softc *); 331 static void trm_msgout_phase1(struct trm_softc *); 332 static void trm_msgin_phase1(struct trm_softc *); 333 334 static void trm_dataio_xfer(struct trm_softc *, int); 335 static void trm_disconnect(struct trm_softc *); 336 static void trm_reselect(struct trm_softc *); 337 static void trm_done(struct trm_softc *, struct trm_srb *); 338 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 339 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 340 341 static void trm_scsi_reset_detect(struct trm_softc *); 342 static void trm_reset_scsi_bus(struct trm_softc *); 343 344 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 345 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 348 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 349 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 350 351 CFATTACH_DECL(trm, sizeof(struct trm_softc), 352 trm_probe, trm_attach, NULL, NULL); 353 354 /* real period: */ 355 static const u_int8_t trm_clock_period[] = { 356 12, /* 48 ns 20.0 MB/sec */ 357 18, /* 72 ns 13.3 MB/sec */ 358 25, /* 100 ns 10.0 MB/sec */ 359 31, /* 124 ns 8.0 MB/sec */ 360 37, /* 148 ns 6.6 MB/sec */ 361 43, /* 172 ns 5.7 MB/sec */ 362 50, /* 200 ns 5.0 MB/sec */ 363 62 /* 248 ns 4.0 MB/sec */ 364 }; 365 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 366 367 static int 368 trm_probe(struct device *parent, struct cfdata *match, void *aux) 369 { 370 struct pci_attach_args *pa = aux; 371 372 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 373 switch (PCI_PRODUCT(pa->pa_id)) { 374 case PCI_PRODUCT_TEKRAM2_DC315: 375 return (1); 376 } 377 return (0); 378 } 379 380 /* 381 * attach and init a host adapter 382 */ 383 static void 384 trm_attach(struct device *parent, struct device *self, void *aux) 385 { 386 struct pci_attach_args *const pa = aux; 387 struct trm_softc *sc = (struct trm_softc *)self; 388 bus_space_tag_t iot; 389 bus_space_handle_t ioh; 390 pci_intr_handle_t ih; 391 pcireg_t command; 392 const char *intrstr; 393 394 /* 395 * These cards do not allow memory mapped accesses 396 * pa_pc: chipset tag 397 * pa_tag: pci tag 398 */ 399 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 400 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 401 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 402 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 403 pci_conf_write(pa->pa_pc, pa->pa_tag, 404 PCI_COMMAND_STATUS_REG, command); 405 } 406 /* 407 * mask for get correct base address of pci IO port 408 */ 409 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 410 &iot, &ioh, NULL, NULL)) { 411 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 412 return; 413 } 414 /* 415 * test checksum of eeprom.. & initialize softc... 416 */ 417 sc->sc_iot = iot; 418 sc->sc_ioh = ioh; 419 sc->sc_dmat = pa->pa_dmat; 420 421 if (trm_init(sc) != 0) { 422 /* 423 * Error during initialization! 424 */ 425 printf(": Error during initialization\n"); 426 return; 427 } 428 /* 429 * Now try to attach all the sub-devices 430 */ 431 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 432 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 433 "Ultra Wide SCSI Adapter\n"); 434 else 435 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 436 "Ultra SCSI Adapter\n"); 437 438 /* 439 * Now tell the generic SCSI layer about our bus. 440 * map and establish interrupt 441 */ 442 if (pci_intr_map(pa, &ih)) { 443 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 444 return; 445 } 446 intrstr = pci_intr_string(pa->pa_pc, ih); 447 448 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 449 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 450 if (intrstr != NULL) 451 printf(" at %s", intrstr); 452 printf("\n"); 453 return; 454 } 455 if (intrstr != NULL) 456 printf("%s: interrupting at %s\n", 457 sc->sc_dev.dv_xname, intrstr); 458 459 sc->sc_adapter.adapt_dev = &sc->sc_dev; 460 sc->sc_adapter.adapt_nchannels = 1; 461 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 462 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 463 sc->sc_adapter.adapt_request = trm_scsipi_request; 464 sc->sc_adapter.adapt_minphys = minphys; 465 466 sc->sc_channel.chan_adapter = &sc->sc_adapter; 467 sc->sc_channel.chan_bustype = &scsi_bustype; 468 sc->sc_channel.chan_channel = 0; 469 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 470 sc->sc_channel.chan_nluns = 8; 471 sc->sc_channel.chan_id = sc->sc_id; 472 473 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 474 } 475 476 /* 477 * initialize the internal structures for a given SCSI host 478 */ 479 static int 480 trm_init(struct trm_softc *sc) 481 { 482 bus_space_tag_t iot = sc->sc_iot; 483 bus_space_handle_t ioh = sc->sc_ioh; 484 bus_dma_segment_t seg; 485 struct trm_nvram eeprom; 486 struct trm_srb *srb; 487 struct trm_tinfo *ti; 488 struct nvram_target *tconf; 489 int error, rseg, all_sgsize; 490 int i, target; 491 u_int8_t bval; 492 493 DPRINTF(("\n")); 494 495 /* 496 * allocate the space for all SCSI control blocks (SRB) for DMA memory 497 */ 498 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 499 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 500 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 501 printf(": unable to allocate SCSI REQUEST BLOCKS, " 502 "error = %d\n", error); 503 return (1); 504 } 505 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 506 all_sgsize, (caddr_t *) &sc->sc_sglist, 507 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 508 printf(": unable to map SCSI REQUEST BLOCKS, " 509 "error = %d\n", error); 510 return (1); 511 } 512 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 513 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 514 printf(": unable to create SRB DMA maps, " 515 "error = %d\n", error); 516 return (1); 517 } 518 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 519 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 520 printf(": unable to load SRB DMA maps, " 521 "error = %d\n", error); 522 return (1); 523 } 524 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 525 memset(sc->sc_sglist, 0, all_sgsize); 526 527 /* 528 * EEPROM CHECKSUM 529 */ 530 trm_check_eeprom(sc, &eeprom); 531 532 sc->sc_maxid = 7; 533 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 534 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 535 sc->sc_config |= HCC_WIDE_CARD; 536 sc->sc_maxid = 15; 537 } 538 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 539 sc->sc_config |= HCC_SCSI_RESET; 540 541 sc->sc_actsrb = NULL; 542 sc->sc_id = eeprom.scsi_id; 543 sc->sc_flag = 0; 544 545 /* 546 * initialize and link all device's SRB queues of this adapter 547 */ 548 TAILQ_INIT(&sc->sc_freesrb); 549 TAILQ_INIT(&sc->sc_readysrb); 550 551 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 552 M_DEVBUF, M_NOWAIT|M_ZERO); 553 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 554 if (sc->sc_srb == NULL) { 555 printf(": can not allocate SRB\n"); 556 return (1); 557 } 558 559 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 560 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 561 srb->sgoffset = TRM_SG_SIZE * i; 562 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 563 /* 564 * map all SRB space to SRB_array 565 */ 566 if (bus_dmamap_create(sc->sc_dmat, 567 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 568 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 569 printf(": unable to create DMA transfer map...\n"); 570 free(sc->sc_srb, M_DEVBUF); 571 return (1); 572 } 573 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 574 srb++; 575 } 576 577 /* 578 * initialize all target info structures 579 */ 580 for (target = 0; target < TRM_MAX_TARGETS; target++) { 581 ti = &sc->sc_tinfo[target]; 582 ti->synctl = 0; 583 ti->offset = 0; 584 tconf = &eeprom.target[target]; 585 ti->config0 = tconf->config0; 586 ti->period = trm_clock_period[tconf->period & 0x07]; 587 ti->flag = 0; 588 if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 589 (sc->sc_config & HCC_WIDE_CARD) != 0) 590 ti->flag |= WIDE_NEGO_ENABLE; 591 if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 592 ti->flag |= SYNC_NEGO_ENABLE; 593 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 594 #ifdef notyet 595 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 596 ti->flag |= USE_TAG_QUEUING; 597 #endif 598 } else 599 ti->flag |= NO_RESELECT; 600 601 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 602 target, ti->config0, ti->period)); 603 DPRINTF((", flag = 0x%02x\n", ti->flag)); 604 } 605 606 /* program configuration 0 */ 607 bval = PHASELATCH | INITIATOR | BLOCKRST; 608 if ((sc->sc_config & HCC_PARITY) != 0) 609 bval |= PARITYCHECK; 610 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 611 612 /* program configuration 1 */ 613 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 614 ACTIVE_NEG | ACTIVE_NEGPLUS); 615 616 /* 250ms selection timeout */ 617 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 618 619 /* Mask all interrupts */ 620 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 621 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 622 623 /* Reset SCSI module */ 624 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 625 626 /* program Host ID */ 627 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 628 629 /* set asynchronous transfer */ 630 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 631 632 /* Turn LED control off */ 633 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 634 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 635 636 /* DMA config */ 637 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 638 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 639 640 /* Clear pending interrupt status */ 641 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 642 643 /* Enable SCSI interrupt */ 644 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 645 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 646 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 647 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 648 649 trm_reset(sc); 650 651 return (0); 652 } 653 654 /* 655 * enqueues a SCSI command 656 * called by the higher level SCSI driver 657 */ 658 static void 659 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 660 void *arg) 661 { 662 bus_space_tag_t iot; 663 bus_space_handle_t ioh; 664 struct trm_softc *sc; 665 struct trm_srb *srb; 666 struct scsipi_xfer *xs; 667 int error, i, target, lun, s; 668 669 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 670 iot = sc->sc_iot; 671 ioh = sc->sc_ioh; 672 673 switch (req) { 674 case ADAPTER_REQ_RUN_XFER: 675 xs = arg; 676 target = xs->xs_periph->periph_target; 677 lun = xs->xs_periph->periph_lun; 678 DPRINTF(("trm_scsipi_request.....\n")); 679 DPRINTF(("target= %d lun= %d\n", target, lun)); 680 if (xs->xs_control & XS_CTL_RESET) { 681 trm_reset(sc); 682 xs->error = XS_NOERROR | XS_RESET; 683 return; 684 } 685 if (xs->xs_status & XS_STS_DONE) { 686 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 687 xs->xs_status &= ~XS_STS_DONE; 688 } 689 690 s = splbio(); 691 692 /* Get SRB */ 693 srb = TAILQ_FIRST(&sc->sc_freesrb); 694 if (srb != NULL) { 695 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 696 } else { 697 xs->error = XS_RESOURCE_SHORTAGE; 698 scsipi_done(xs); 699 splx(s); 700 return; 701 } 702 703 srb->xs = xs; 704 srb->cmdlen = xs->cmdlen; 705 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 706 707 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 708 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 709 xs->data, xs->datalen, NULL, 710 ((xs->xs_control & XS_CTL_NOSLEEP) ? 711 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 712 BUS_DMA_STREAMING | 713 ((xs->xs_control & XS_CTL_DATA_IN) ? 714 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 715 printf("%s: DMA transfer map unable to load, " 716 "error = %d\n", sc->sc_dev.dv_xname, error); 717 xs->error = XS_DRIVER_STUFFUP; 718 /* 719 * free SRB 720 */ 721 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 722 splx(s); 723 return; 724 } 725 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 726 srb->dmap->dm_mapsize, 727 (xs->xs_control & XS_CTL_DATA_IN) ? 728 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 729 730 /* Set up the scatter gather list */ 731 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 732 srb->sgentry[i].address = 733 htole32(srb->dmap->dm_segs[i].ds_addr); 734 srb->sgentry[i].length = 735 htole32(srb->dmap->dm_segs[i].ds_len); 736 } 737 srb->buflen = xs->datalen; 738 srb->sgcnt = srb->dmap->dm_nsegs; 739 } else { 740 srb->sgentry[0].address = 0; 741 srb->sgentry[0].length = 0; 742 srb->buflen = 0; 743 srb->sgcnt = 0; 744 } 745 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 746 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 747 748 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 749 750 srb->sgindex = 0; 751 srb->hastat = 0; 752 srb->tastat = 0; 753 srb->flag = 0; 754 755 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 756 if (sc->sc_actsrb == NULL) 757 trm_sched(sc); 758 splx(s); 759 760 if ((xs->xs_control & XS_CTL_POLL) != 0) { 761 int timeout = xs->timeout; 762 763 s = splbio(); 764 do { 765 while (--timeout) { 766 DELAY(1000); 767 if (bus_space_read_2(iot, ioh, 768 TRM_SCSI_STATUS) & SCSIINTERRUPT) 769 break; 770 } 771 if (timeout == 0) { 772 trm_timeout(srb); 773 break; 774 } else 775 trm_intr(sc); 776 } while ((xs->xs_status & XS_STS_DONE) == 0); 777 splx(s); 778 } 779 return; 780 781 case ADAPTER_REQ_GROW_RESOURCES: 782 /* XXX Not supported. */ 783 return; 784 785 case ADAPTER_REQ_SET_XFER_MODE: 786 { 787 struct trm_tinfo *ti; 788 struct scsipi_xfer_mode *xm; 789 790 xm = arg; 791 ti = &sc->sc_tinfo[xm->xm_target]; 792 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 793 794 #ifdef notyet 795 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 796 ti->flag |= USE_TAG_QUEUING; 797 else 798 #endif 799 ti->flag &= ~USE_TAG_QUEUING; 800 801 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 802 ti->flag |= WIDE_NEGO_ENABLE; 803 ti->flag &= ~WIDE_NEGO_DONE; 804 } 805 806 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 807 ti->flag |= SYNC_NEGO_ENABLE; 808 ti->flag &= ~SYNC_NEGO_DONE; 809 ti->period = trm_clock_period[0]; 810 } 811 812 /* 813 * If we're not going to negotiate, send the 814 * notification now, since it won't happen later. 815 */ 816 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 817 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 818 trm_update_xfer_mode(sc, xm->xm_target); 819 820 return; 821 } 822 } 823 } 824 825 static void 826 trm_update_xfer_mode(struct trm_softc *sc, int target) 827 { 828 struct scsipi_xfer_mode xm; 829 struct trm_tinfo *ti; 830 831 ti = &sc->sc_tinfo[target]; 832 xm.xm_target = target; 833 xm.xm_mode = 0; 834 xm.xm_period = 0; 835 xm.xm_offset = 0; 836 837 if ((ti->synctl & WIDE_SYNC) != 0) 838 xm.xm_mode |= PERIPH_CAP_WIDE16; 839 840 if (ti->period > 0) { 841 xm.xm_mode |= PERIPH_CAP_SYNC; 842 xm.xm_period = ti->period; 843 xm.xm_offset = ti->offset; 844 } 845 846 #ifdef notyet 847 if ((ti->flag & USE_TAG_QUEUING) != 0) 848 xm.xm_mode |= PERIPH_CAP_TQING; 849 #endif 850 851 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 852 } 853 854 static void 855 trm_sched(struct trm_softc *sc) 856 { 857 struct trm_srb *srb; 858 struct scsipi_periph *periph; 859 struct trm_tinfo *ti; 860 struct trm_linfo *li; 861 int s, lun, tag; 862 863 DPRINTF(("trm_sched...\n")); 864 865 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 866 periph = srb->xs->xs_periph; 867 ti = &sc->sc_tinfo[periph->periph_target]; 868 lun = periph->periph_lun; 869 870 /* select type of tag for this command */ 871 if ((ti->flag & NO_RESELECT) != 0 || 872 (ti->flag & USE_TAG_QUEUING) == 0 || 873 (srb->flag & AUTO_REQSENSE) != 0 || 874 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 875 tag = 0; 876 else 877 tag = srb->xs->xs_tag_type; 878 #if 0 879 /* XXX use tags for polled commands? */ 880 if (srb->xs->xs_control & XS_CTL_POLL) 881 tag = 0; 882 #endif 883 884 s = splbio(); 885 li = ti->linfo[lun]; 886 if (li == NULL) { 887 /* initialize lun info */ 888 if ((li = malloc(sizeof(*li), M_DEVBUF, 889 M_NOWAIT|M_ZERO)) == NULL) { 890 splx(s); 891 continue; 892 } 893 ti->linfo[lun] = li; 894 } 895 896 if (tag == 0) { 897 /* try to issue this srb as an un-tagged command */ 898 if (li->untagged == NULL) 899 li->untagged = srb; 900 } 901 if (li->untagged != NULL) { 902 tag = 0; 903 if (li->busy != 1 && li->used == 0) { 904 /* we need to issue the untagged command now */ 905 srb = li->untagged; 906 periph = srb->xs->xs_periph; 907 } else { 908 /* not ready yet */ 909 splx(s); 910 continue; 911 } 912 } 913 srb->tag[0] = tag; 914 if (tag != 0) { 915 li->queued[srb->xs->xs_tag_id] = srb; 916 srb->tag[1] = srb->xs->xs_tag_id; 917 li->used++; 918 } 919 920 if (li->untagged != NULL && li->busy != 1) { 921 li->busy = 1; 922 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 923 sc->sc_actsrb = srb; 924 trm_select(sc, srb); 925 splx(s); 926 break; 927 } 928 if (li->untagged == NULL && tag != 0) { 929 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 930 sc->sc_actsrb = srb; 931 trm_select(sc, srb); 932 splx(s); 933 break; 934 } else 935 splx(s); 936 } 937 } 938 939 static int 940 trm_select(struct trm_softc *sc, struct trm_srb *srb) 941 { 942 bus_space_tag_t iot = sc->sc_iot; 943 bus_space_handle_t ioh = sc->sc_ioh; 944 struct scsipi_periph *periph = srb->xs->xs_periph; 945 int target = periph->periph_target; 946 int lun = periph->periph_lun; 947 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 948 u_int8_t scsicmd; 949 950 DPRINTF(("trm_select.....\n")); 951 952 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 953 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 954 trm_timeout, srb); 955 } 956 957 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 958 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 959 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 960 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 961 /* Flush FIFO */ 962 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 963 DELAY(10); 964 965 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 966 967 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 968 969 if (((ti->flag & WIDE_NEGO_ENABLE) && 970 (ti->flag & WIDE_NEGO_DONE) == 0) || 971 ((ti->flag & SYNC_NEGO_ENABLE) && 972 (ti->flag & SYNC_NEGO_DONE) == 0)) { 973 sc->sc_state = TRM_MSGOUT; 974 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 975 MSG_IDENTIFY(lun, 0)); 976 bus_space_write_multi_1(iot, ioh, 977 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 978 /* it's important for atn stop */ 979 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 980 DO_DATALATCH | DO_HWRESELECT); 981 /* SCSI command */ 982 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 983 DPRINTF(("select with SEL_ATNSTOP\n")); 984 return (0); 985 } 986 987 if (srb->tag[0] != 0) { 988 /* Send identify message */ 989 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 990 MSG_IDENTIFY(lun, 1)); 991 /* Send Tag id */ 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 993 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 994 scsicmd = SCMD_SEL_ATN3; 995 DPRINTF(("select with SEL_ATN3\n")); 996 } else { 997 /* Send identify message */ 998 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 999 MSG_IDENTIFY(lun, 1000 (ti->flag & NO_RESELECT) == 0 && 1001 (srb->flag & AUTO_REQSENSE) == 0 && 1002 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1003 scsicmd = SCMD_SEL_ATN; 1004 DPRINTF(("select with SEL_ATN\n")); 1005 } 1006 sc->sc_state = TRM_START; 1007 1008 /* 1009 * Send CDB ..command block... 1010 */ 1011 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1012 1013 /* 1014 * If trm_select returns 0: current interrupt status 1015 * is interrupt enable. It's said that SCSI processor is 1016 * unoccupied. 1017 */ 1018 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1019 /* SCSI command */ 1020 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1021 return (0); 1022 } 1023 1024 /* 1025 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1026 */ 1027 static void 1028 trm_reset(struct trm_softc *sc) 1029 { 1030 bus_space_tag_t iot = sc->sc_iot; 1031 bus_space_handle_t ioh = sc->sc_ioh; 1032 int s; 1033 1034 DPRINTF(("trm_reset.........\n")); 1035 1036 s = splbio(); 1037 1038 /* disable SCSI and DMA interrupt */ 1039 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1040 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1041 1042 trm_reset_scsi_bus(sc); 1043 DELAY(100000); 1044 1045 /* Enable SCSI interrupt */ 1046 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1047 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1048 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1049 1050 /* Enable DMA interrupt */ 1051 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1052 1053 /* Clear DMA FIFO */ 1054 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1055 1056 /* Clear SCSI FIFO */ 1057 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1058 1059 sc->sc_actsrb = NULL; 1060 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1061 1062 splx(s); 1063 } 1064 1065 static void 1066 trm_timeout(void *arg) 1067 { 1068 struct trm_srb *srb = (struct trm_srb *)arg; 1069 struct scsipi_xfer *xs = srb->xs; 1070 struct scsipi_periph *periph = xs->xs_periph; 1071 struct trm_softc *sc; 1072 int s; 1073 1074 if (xs == NULL) 1075 printf("trm_timeout called with xs == NULL\n"); 1076 1077 else { 1078 scsipi_printaddr(xs->xs_periph); 1079 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1080 } 1081 1082 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1083 1084 trm_reset_scsi_bus(sc); 1085 s = splbio(); 1086 srb->flag |= SRB_TIMEOUT; 1087 trm_done(sc, srb); 1088 /* XXX needs more.. */ 1089 splx(s); 1090 } 1091 1092 /* 1093 * Catch an interrupt from the adapter 1094 * Process pending device interrupts. 1095 */ 1096 static int 1097 trm_intr(void *arg) 1098 { 1099 bus_space_tag_t iot; 1100 bus_space_handle_t ioh; 1101 struct trm_softc *sc; 1102 int intstat, stat; 1103 1104 DPRINTF(("trm_intr......\n")); 1105 sc = (struct trm_softc *)arg; 1106 if (sc == NULL) 1107 return (0); 1108 1109 iot = sc->sc_iot; 1110 ioh = sc->sc_ioh; 1111 1112 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1113 if ((stat & SCSIINTERRUPT) == 0) 1114 return (0); 1115 1116 DPRINTF(("stat = %04x, ", stat)); 1117 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1118 1119 DPRINTF(("intstat=%02x, ", intstat)); 1120 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1121 DPRINTF(("\n")); 1122 trm_disconnect(sc); 1123 return (1); 1124 } 1125 if (intstat & INT_RESELECTED) { 1126 DPRINTF(("\n")); 1127 trm_reselect(sc); 1128 return (1); 1129 } 1130 if (intstat & INT_SCSIRESET) { 1131 DPRINTF(("\n")); 1132 trm_scsi_reset_detect(sc); 1133 return (1); 1134 } 1135 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1136 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1137 sc->sc_phase, sc->sc_state)); 1138 /* 1139 * software sequential machine 1140 */ 1141 1142 /* 1143 * call phase0 functions... "phase entry" handle 1144 * every phase before start transfer 1145 */ 1146 switch (sc->sc_phase) { 1147 case PH_DATA_OUT: 1148 trm_dataout_phase0(sc, stat); 1149 break; 1150 case PH_DATA_IN: 1151 trm_datain_phase0(sc, stat); 1152 break; 1153 case PH_COMMAND: 1154 break; 1155 case PH_STATUS: 1156 trm_status_phase0(sc); 1157 stat = PH_BUS_FREE; 1158 break; 1159 case PH_MSG_OUT: 1160 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1161 sc->sc_state == TRM_ABORT_SENT) 1162 stat = PH_BUS_FREE; 1163 break; 1164 case PH_MSG_IN: 1165 trm_msgin_phase0(sc); 1166 stat = PH_BUS_FREE; 1167 break; 1168 case PH_BUS_FREE: 1169 break; 1170 default: 1171 printf("%s: unexpected phase in trm_intr() phase0\n", 1172 sc->sc_dev.dv_xname); 1173 break; 1174 } 1175 1176 sc->sc_phase = stat & PHASEMASK; 1177 1178 switch (sc->sc_phase) { 1179 case PH_DATA_OUT: 1180 trm_dataio_xfer(sc, XFERDATAOUT); 1181 break; 1182 case PH_DATA_IN: 1183 trm_dataio_xfer(sc, XFERDATAIN); 1184 break; 1185 case PH_COMMAND: 1186 trm_command_phase1(sc); 1187 break; 1188 case PH_STATUS: 1189 trm_status_phase1(sc); 1190 break; 1191 case PH_MSG_OUT: 1192 trm_msgout_phase1(sc); 1193 break; 1194 case PH_MSG_IN: 1195 trm_msgin_phase1(sc); 1196 break; 1197 case PH_BUS_FREE: 1198 break; 1199 default: 1200 printf("%s: unexpected phase in trm_intr() phase1\n", 1201 sc->sc_dev.dv_xname); 1202 break; 1203 } 1204 1205 return (1); 1206 } 1207 return (0); 1208 } 1209 1210 static void 1211 trm_msgout_phase1(struct trm_softc *sc) 1212 { 1213 bus_space_tag_t iot = sc->sc_iot; 1214 bus_space_handle_t ioh = sc->sc_ioh; 1215 struct trm_srb *srb; 1216 struct scsipi_periph *periph; 1217 struct trm_tinfo *ti; 1218 1219 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1220 1221 srb = sc->sc_actsrb; 1222 1223 /* message out phase */ 1224 if (srb != NULL) { 1225 periph = srb->xs->xs_periph; 1226 ti = &sc->sc_tinfo[periph->periph_target]; 1227 1228 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1229 (ti->flag & WIDE_NEGO_ENABLE)) { 1230 /* send WDTR */ 1231 ti->flag &= ~SYNC_NEGO_DONE; 1232 1233 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1234 sc->sc_msgbuf[1] = MSG_EXTENDED; 1235 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1236 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1237 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1238 sc->sc_msgcnt = 5; 1239 1240 ti->flag |= WIDE_NEGO_DOING; 1241 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1242 (ti->flag & SYNC_NEGO_ENABLE)) { 1243 /* send SDTR */ 1244 int cnt = 0; 1245 1246 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1247 sc->sc_msgbuf[cnt++] = 1248 MSG_IDENTIFY(periph->periph_lun, 0); 1249 1250 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1251 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1252 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1253 sc->sc_msgbuf[cnt++] = ti->period; 1254 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1255 sc->sc_msgcnt = cnt; 1256 ti->flag |= SYNC_NEGO_DOING; 1257 } 1258 } 1259 if (sc->sc_msgcnt == 0) { 1260 sc->sc_msgbuf[0] = MSG_ABORT; 1261 sc->sc_msgcnt = 1; 1262 sc->sc_state = TRM_ABORT_SENT; 1263 } 1264 1265 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1266 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1267 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1268 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1269 1270 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1271 sc->sc_msgbuf, sc->sc_msgcnt); 1272 sc->sc_msgcnt = 0; 1273 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1274 1275 /* it's important for atn stop */ 1276 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1277 1278 /* 1279 * SCSI command 1280 */ 1281 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1282 } 1283 1284 static void 1285 trm_command_phase1(struct trm_softc *sc) 1286 { 1287 bus_space_tag_t iot = sc->sc_iot; 1288 bus_space_handle_t ioh = sc->sc_ioh; 1289 struct trm_srb *srb; 1290 1291 srb = sc->sc_actsrb; 1292 if (srb == NULL) { 1293 DPRINTF(("trm_command_phase1: no active srb\n")); 1294 return; 1295 } 1296 1297 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1298 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1299 1300 sc->sc_state = TRM_COMMAND; 1301 /* it's important for atn stop */ 1302 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1303 1304 /* 1305 * SCSI command 1306 */ 1307 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1308 } 1309 1310 static void 1311 trm_dataout_phase0(struct trm_softc *sc, int stat) 1312 { 1313 bus_space_tag_t iot = sc->sc_iot; 1314 bus_space_handle_t ioh = sc->sc_ioh; 1315 struct trm_srb *srb; 1316 struct scsipi_periph *periph; 1317 struct trm_tinfo *ti; 1318 struct trm_sg_entry *sg; 1319 int sgindex; 1320 u_int32_t xferlen, leftcnt = 0; 1321 1322 if (sc->sc_state == TRM_XFERPAD) 1323 return; 1324 1325 srb = sc->sc_actsrb; 1326 if (srb == NULL) { 1327 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1328 return; 1329 } 1330 periph = srb->xs->xs_periph; 1331 ti = &sc->sc_tinfo[periph->periph_target]; 1332 1333 if ((stat & PARITYERROR) != 0) 1334 srb->flag |= PARITY_ERROR; 1335 1336 if ((stat & SCSIXFERDONE) == 0) { 1337 /* 1338 * when data transfer from DMA FIFO to SCSI FIFO 1339 * if there was some data left in SCSI FIFO 1340 */ 1341 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1342 SCSI_FIFOCNT_MASK; 1343 if (ti->synctl & WIDE_SYNC) 1344 /* 1345 * if WIDE scsi SCSI FIFOCNT unit is word 1346 * so need to * 2 1347 */ 1348 leftcnt <<= 1; 1349 } 1350 /* 1351 * calculate all the residue data that was not yet transferred 1352 * SCSI transfer counter + left in SCSI FIFO data 1353 * 1354 * .....TRM_SCSI_XCNT (24bits) 1355 * The counter always decrements by one for every SCSI 1356 * byte transfer. 1357 * .....TRM_SCSI_FIFOCNT ( 5bits) 1358 * The counter is SCSI FIFO offset counter 1359 */ 1360 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1361 if (leftcnt == 1) { 1362 leftcnt = 0; 1363 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1364 } 1365 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1366 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1367 DMAXFERCOMP) == 0) 1368 ; /* XXX needs timeout */ 1369 1370 srb->buflen = 0; 1371 } else { 1372 /* Update SG list */ 1373 1374 /* 1375 * if transfer not yet complete 1376 * there were some data residue in SCSI FIFO or 1377 * SCSI transfer counter not empty 1378 */ 1379 if (srb->buflen != leftcnt) { 1380 /* data that had transferred length */ 1381 xferlen = srb->buflen - leftcnt; 1382 1383 /* next time to be transferred length */ 1384 srb->buflen = leftcnt; 1385 1386 /* 1387 * parsing from last time disconnect sgindex 1388 */ 1389 sg = srb->sgentry + srb->sgindex; 1390 for (sgindex = srb->sgindex; 1391 sgindex < srb->sgcnt; 1392 sgindex++, sg++) { 1393 /* 1394 * find last time which SG transfer 1395 * be disconnect 1396 */ 1397 if (xferlen >= le32toh(sg->length)) 1398 xferlen -= le32toh(sg->length); 1399 else { 1400 /* 1401 * update last time 1402 * disconnected SG list 1403 */ 1404 /* residue data length */ 1405 sg->length = 1406 htole32(le32toh(sg->length) 1407 - xferlen); 1408 /* residue data pointer */ 1409 sg->address = 1410 htole32(le32toh(sg->address) 1411 + xferlen); 1412 srb->sgindex = sgindex; 1413 break; 1414 } 1415 } 1416 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1417 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1418 } 1419 } 1420 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1421 } 1422 1423 static void 1424 trm_datain_phase0(struct trm_softc *sc, int stat) 1425 { 1426 bus_space_tag_t iot = sc->sc_iot; 1427 bus_space_handle_t ioh = sc->sc_ioh; 1428 struct trm_srb *srb; 1429 struct trm_sg_entry *sg; 1430 int sgindex; 1431 u_int32_t xferlen, leftcnt = 0; 1432 1433 if (sc->sc_state == TRM_XFERPAD) 1434 return; 1435 1436 srb = sc->sc_actsrb; 1437 if (srb == NULL) { 1438 DPRINTF(("trm_datain_phase0: no active srb\n")); 1439 return; 1440 } 1441 1442 if (stat & PARITYERROR) 1443 srb->flag |= PARITY_ERROR; 1444 1445 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1446 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1447 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1448 DMAXFERCOMP) == 0) 1449 ; /* XXX needs timeout */ 1450 1451 srb->buflen = 0; 1452 } else { /* phase changed */ 1453 /* 1454 * parsing the case: 1455 * when a transfer not yet complete 1456 * but be disconnected by upper layer 1457 * if transfer not yet complete 1458 * there were some data residue in SCSI FIFO or 1459 * SCSI transfer counter not empty 1460 */ 1461 if (srb->buflen != leftcnt) { 1462 /* 1463 * data that had transferred length 1464 */ 1465 xferlen = srb->buflen - leftcnt; 1466 1467 /* 1468 * next time to be transferred length 1469 */ 1470 srb->buflen = leftcnt; 1471 1472 /* 1473 * parsing from last time disconnect sgindex 1474 */ 1475 sg = srb->sgentry + srb->sgindex; 1476 for (sgindex = srb->sgindex; 1477 sgindex < srb->sgcnt; 1478 sgindex++, sg++) { 1479 /* 1480 * find last time which SG transfer 1481 * be disconnect 1482 */ 1483 if (xferlen >= le32toh(sg->length)) 1484 xferlen -= le32toh(sg->length); 1485 else { 1486 /* 1487 * update last time 1488 * disconnected SG list 1489 */ 1490 /* residue data length */ 1491 sg->length = 1492 htole32(le32toh(sg->length) 1493 - xferlen); 1494 /* residue data pointer */ 1495 sg->address = 1496 htole32(le32toh(sg->address) 1497 + xferlen); 1498 srb->sgindex = sgindex; 1499 break; 1500 } 1501 } 1502 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1503 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1504 } 1505 } 1506 } 1507 1508 static void 1509 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1510 { 1511 bus_space_tag_t iot = sc->sc_iot; 1512 bus_space_handle_t ioh = sc->sc_ioh; 1513 struct trm_srb *srb; 1514 struct scsipi_periph *periph; 1515 struct trm_tinfo *ti; 1516 1517 srb = sc->sc_actsrb; 1518 if (srb == NULL) { 1519 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1520 return; 1521 } 1522 periph = srb->xs->xs_periph; 1523 ti = &sc->sc_tinfo[periph->periph_target]; 1524 1525 if (srb->sgindex < srb->sgcnt) { 1526 if (srb->buflen > 0) { 1527 /* 1528 * load what physical address of Scatter/Gather 1529 * list table want to be transfer 1530 */ 1531 sc->sc_state = TRM_DATA_XFER; 1532 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1533 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1534 srb->sgaddr + 1535 srb->sgindex * sizeof(struct trm_sg_entry)); 1536 /* 1537 * load how many bytes in the Scatter/Gather list table 1538 */ 1539 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1540 (srb->sgcnt - srb->sgindex) 1541 * sizeof(struct trm_sg_entry)); 1542 /* 1543 * load total xfer length (24bits) max value 16Mbyte 1544 */ 1545 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1546 /* Start DMA transfer */ 1547 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1548 iodir | SGXFER); 1549 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1550 STARTDMAXFER); 1551 1552 /* Start SCSI transfer */ 1553 /* it's important for atn stop */ 1554 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1555 DO_DATALATCH); 1556 1557 /* 1558 * SCSI command 1559 */ 1560 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1561 (iodir == XFERDATAOUT) ? 1562 SCMD_DMA_OUT : SCMD_DMA_IN); 1563 } else { /* xfer pad */ 1564 if (srb->sgcnt) { 1565 srb->hastat = H_OVER_UNDER_RUN; 1566 } 1567 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1568 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1569 1570 if (iodir == XFERDATAOUT) 1571 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1572 else 1573 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1574 1575 sc->sc_state = TRM_XFERPAD; 1576 /* it's important for atn stop */ 1577 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1578 DO_DATALATCH); 1579 1580 /* 1581 * SCSI command 1582 */ 1583 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1584 (iodir == XFERDATAOUT) ? 1585 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1586 } 1587 } 1588 } 1589 1590 static void 1591 trm_status_phase0(struct trm_softc *sc) 1592 { 1593 bus_space_tag_t iot = sc->sc_iot; 1594 bus_space_handle_t ioh = sc->sc_ioh; 1595 struct trm_srb *srb; 1596 1597 srb = sc->sc_actsrb; 1598 if (srb == NULL) { 1599 DPRINTF(("trm_status_phase0: no active srb\n")); 1600 return; 1601 } 1602 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1603 sc->sc_state = TRM_COMPLETED; 1604 /* it's important for atn stop */ 1605 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1606 1607 /* 1608 * SCSI command 1609 */ 1610 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1611 } 1612 1613 static void 1614 trm_status_phase1(struct trm_softc *sc) 1615 { 1616 bus_space_tag_t iot = sc->sc_iot; 1617 bus_space_handle_t ioh = sc->sc_ioh; 1618 1619 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1620 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1621 & SCSI_FIFO_EMPTY) == 0) 1622 bus_space_write_2(iot, ioh, 1623 TRM_SCSI_CONTROL, DO_CLRFIFO); 1624 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1625 & DMA_FIFO_EMPTY) == 0) 1626 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1627 } else { 1628 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1629 & DMA_FIFO_EMPTY) == 0) 1630 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1631 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1632 & SCSI_FIFO_EMPTY) == 0) 1633 bus_space_write_2(iot, ioh, 1634 TRM_SCSI_CONTROL, DO_CLRFIFO); 1635 } 1636 sc->sc_state = TRM_STATUS; 1637 /* it's important for atn stop */ 1638 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1639 1640 /* 1641 * SCSI command 1642 */ 1643 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1644 } 1645 1646 static void 1647 trm_msgin_phase0(struct trm_softc *sc) 1648 { 1649 bus_space_tag_t iot = sc->sc_iot; 1650 bus_space_handle_t ioh = sc->sc_ioh; 1651 struct trm_srb *srb; 1652 struct scsipi_periph *periph; 1653 struct trm_tinfo *ti; 1654 int index; 1655 u_int8_t msgin_code; 1656 1657 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1658 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1659 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1660 switch (msgin_code) { 1661 case MSG_DISCONNECT: 1662 sc->sc_state = TRM_DISCONNECTED; 1663 break; 1664 1665 case MSG_SAVEDATAPOINTER: 1666 break; 1667 1668 case MSG_EXTENDED: 1669 case MSG_SIMPLE_Q_TAG: 1670 case MSG_HEAD_OF_Q_TAG: 1671 case MSG_ORDERED_Q_TAG: 1672 sc->sc_state = TRM_EXTEND_MSGIN; 1673 /* extended message (01h) */ 1674 sc->sc_msgbuf[0] = msgin_code; 1675 1676 sc->sc_msgcnt = 1; 1677 /* extended message length (n) */ 1678 sc->sc_msg = &sc->sc_msgbuf[1]; 1679 1680 break; 1681 case MSG_MESSAGE_REJECT: 1682 /* Reject message */ 1683 srb = sc->sc_actsrb; 1684 if (srb == NULL) { 1685 DPRINTF(("trm_msgin_phase0: " 1686 " message reject without actsrb\n")); 1687 break; 1688 } 1689 periph = srb->xs->xs_periph; 1690 ti = &sc->sc_tinfo[periph->periph_target]; 1691 1692 if (ti->flag & WIDE_NEGO_ENABLE) { 1693 /* do wide nego reject */ 1694 ti->flag |= WIDE_NEGO_DONE; 1695 ti->flag &= 1696 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1697 if ((ti->flag & SYNC_NEGO_ENABLE) && 1698 (ti->flag & SYNC_NEGO_DONE) == 0) { 1699 /* Set ATN, in case ATN was clear */ 1700 sc->sc_state = TRM_MSGOUT; 1701 bus_space_write_2(iot, ioh, 1702 TRM_SCSI_CONTROL, DO_SETATN); 1703 } else 1704 /* Clear ATN */ 1705 bus_space_write_2(iot, ioh, 1706 TRM_SCSI_CONTROL, DO_CLRATN); 1707 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1708 /* do sync nego reject */ 1709 bus_space_write_2(iot, ioh, 1710 TRM_SCSI_CONTROL, DO_CLRATN); 1711 if (ti->flag & SYNC_NEGO_DOING) { 1712 ti->flag &=~(SYNC_NEGO_ENABLE | 1713 SYNC_NEGO_DONE); 1714 ti->synctl = 0; 1715 ti->offset = 0; 1716 bus_space_write_1(iot, ioh, 1717 TRM_SCSI_SYNC, ti->synctl); 1718 bus_space_write_1(iot, ioh, 1719 TRM_SCSI_OFFSET, ti->offset); 1720 } 1721 } 1722 break; 1723 1724 case MSG_IGN_WIDE_RESIDUE: 1725 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1726 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1727 break; 1728 1729 default: 1730 /* 1731 * Restore data pointer message 1732 * Save data pointer message 1733 * Completion message 1734 * NOP message 1735 */ 1736 break; 1737 } 1738 } else { 1739 /* 1740 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1741 * Parsing incoming extented messages 1742 */ 1743 *sc->sc_msg++ = msgin_code; 1744 sc->sc_msgcnt++; 1745 1746 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1747 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1748 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1749 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1750 1751 switch (sc->sc_msgbuf[0]) { 1752 case MSG_SIMPLE_Q_TAG: 1753 case MSG_HEAD_OF_Q_TAG: 1754 case MSG_ORDERED_Q_TAG: 1755 /* 1756 * is QUEUE tag message : 1757 * 1758 * byte 0: 1759 * HEAD QUEUE TAG (20h) 1760 * ORDERED QUEUE TAG (21h) 1761 * SIMPLE QUEUE TAG (22h) 1762 * byte 1: 1763 * Queue tag (00h - FFh) 1764 */ 1765 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1766 /* XXX XXX XXX */ 1767 struct trm_linfo *li; 1768 int tagid; 1769 1770 sc->sc_flag &= ~WAIT_TAGMSG; 1771 tagid = sc->sc_msgbuf[1]; 1772 ti = &sc->sc_tinfo[sc->resel_target]; 1773 li = ti->linfo[sc->resel_lun]; 1774 srb = li->queued[tagid]; 1775 if (srb != NULL) { 1776 sc->sc_actsrb = srb; 1777 sc->sc_state = TRM_DATA_XFER; 1778 break; 1779 } else { 1780 printf("%s: invalid tag id\n", 1781 sc->sc_dev.dv_xname); 1782 } 1783 1784 sc->sc_state = TRM_UNEXPECT_RESEL; 1785 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1786 sc->sc_msgcnt = 1; 1787 bus_space_write_2(iot, ioh, 1788 TRM_SCSI_CONTROL, DO_SETATN); 1789 } else 1790 sc->sc_state = TRM_IDLE; 1791 break; 1792 1793 case MSG_EXTENDED: 1794 srb = sc->sc_actsrb; 1795 if (srb == NULL) { 1796 DPRINTF(("trm_msgin_phase0: " 1797 "extended message without actsrb\n")); 1798 break; 1799 } 1800 periph = srb->xs->xs_periph; 1801 ti = &sc->sc_tinfo[periph->periph_target]; 1802 1803 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1804 sc->sc_msgcnt == 4) { 1805 /* 1806 * is Wide data xfer Extended message : 1807 * ====================================== 1808 * WIDE DATA TRANSFER REQUEST 1809 * ====================================== 1810 * byte 0 : Extended message (01h) 1811 * byte 1 : Extended message length (02h) 1812 * byte 2 : WIDE DATA TRANSFER code (03h) 1813 * byte 3 : Transfer width exponent 1814 */ 1815 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1816 /* Length is wrong, reject it */ 1817 ti->flag &= ~(WIDE_NEGO_ENABLE | 1818 WIDE_NEGO_DONE); 1819 sc->sc_state = TRM_MSGOUT; 1820 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1821 sc->sc_msgcnt = 1; 1822 bus_space_write_2(iot, ioh, 1823 TRM_SCSI_CONTROL, DO_SETATN); 1824 break; 1825 } 1826 1827 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1828 sc->sc_msgbuf[3] = 1829 MSG_EXT_WDTR_BUS_8_BIT; 1830 1831 if (sc->sc_msgbuf[3] > 1832 MSG_EXT_WDTR_BUS_32_BIT) { 1833 /* reject_msg: */ 1834 ti->flag &= ~(WIDE_NEGO_ENABLE | 1835 WIDE_NEGO_DONE); 1836 sc->sc_state = TRM_MSGOUT; 1837 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1838 sc->sc_msgcnt = 1; 1839 bus_space_write_2(iot, ioh, 1840 TRM_SCSI_CONTROL, DO_SETATN); 1841 break; 1842 } 1843 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1844 /* do 16 bits */ 1845 sc->sc_msgbuf[3] = 1846 MSG_EXT_WDTR_BUS_16_BIT; 1847 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1848 ti->flag |= WIDE_NEGO_DONE; 1849 ti->flag &= ~(SYNC_NEGO_DONE | 1850 WIDE_NEGO_ENABLE); 1851 if (sc->sc_msgbuf[3] != 1852 MSG_EXT_WDTR_BUS_8_BIT) 1853 /* is Wide data xfer */ 1854 ti->synctl |= WIDE_SYNC; 1855 trm_update_xfer_mode(sc, 1856 periph->periph_target); 1857 } 1858 1859 sc->sc_state = TRM_MSGOUT; 1860 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1861 DO_SETATN); 1862 break; 1863 1864 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1865 sc->sc_msgcnt == 5) { 1866 /* 1867 * is 8bit transfer Extended message : 1868 * ================================= 1869 * SYNCHRONOUS DATA TRANSFER REQUEST 1870 * ================================= 1871 * byte 0 : Extended message (01h) 1872 * byte 1 : Extended message length (03) 1873 * byte 2 : SYNC DATA TRANSFER code (01h) 1874 * byte 3 : Transfer period factor 1875 * byte 4 : REQ/ACK offset 1876 */ 1877 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1878 /* reject_msg */ 1879 sc->sc_state = TRM_MSGOUT; 1880 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1881 sc->sc_msgcnt = 1; 1882 bus_space_write_2(iot, ioh, 1883 TRM_SCSI_CONTROL, DO_SETATN); 1884 break; 1885 } 1886 1887 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1888 ti->flag &= 1889 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1890 ti->flag |= SYNC_NEGO_DONE; 1891 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1892 sc->sc_msgbuf[3] = 0; 1893 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1894 sc->sc_msgbuf[4] = 1895 TRM_MAX_OFFSET; 1896 1897 if (sc->sc_msgbuf[3] == 0 || 1898 sc->sc_msgbuf[4] == 0) { 1899 /* set async */ 1900 ti->synctl = 0; 1901 ti->offset = 0; 1902 } else { 1903 /* set sync */ 1904 /* Transfer period factor */ 1905 ti->period = sc->sc_msgbuf[3]; 1906 /* REQ/ACK offset */ 1907 ti->offset = sc->sc_msgbuf[4]; 1908 for (index = 0; 1909 index < NPERIOD; 1910 index++) 1911 if (ti->period <= 1912 trm_clock_period[ 1913 index]) 1914 break; 1915 1916 ti->synctl |= ALT_SYNC | index; 1917 } 1918 /* 1919 * program SCSI control register 1920 */ 1921 bus_space_write_1(iot, ioh, 1922 TRM_SCSI_SYNC, ti->synctl); 1923 bus_space_write_1(iot, ioh, 1924 TRM_SCSI_OFFSET, ti->offset); 1925 trm_update_xfer_mode(sc, 1926 periph->periph_target); 1927 } 1928 sc->sc_state = TRM_IDLE; 1929 } 1930 break; 1931 default: 1932 break; 1933 } 1934 } 1935 1936 /* it's important for atn stop */ 1937 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1938 1939 /* 1940 * SCSI command 1941 */ 1942 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1943 } 1944 1945 static void 1946 trm_msgin_phase1(struct trm_softc *sc) 1947 { 1948 bus_space_tag_t iot = sc->sc_iot; 1949 bus_space_handle_t ioh = sc->sc_ioh; 1950 1951 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1952 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1953 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1954 sc->sc_state = TRM_MSGIN; 1955 } 1956 1957 /* it's important for atn stop */ 1958 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1959 1960 /* 1961 * SCSI command 1962 */ 1963 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1964 } 1965 1966 static void 1967 trm_disconnect(struct trm_softc *sc) 1968 { 1969 bus_space_tag_t iot = sc->sc_iot; 1970 bus_space_handle_t ioh = sc->sc_ioh; 1971 struct trm_srb *srb; 1972 int s; 1973 1974 s = splbio(); 1975 1976 srb = sc->sc_actsrb; 1977 DPRINTF(("trm_disconnect...............\n")); 1978 1979 if (srb == NULL) { 1980 DPRINTF(("trm_disconnect: no active srb\n")); 1981 DELAY(1000); /* 1 msec */ 1982 1983 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1984 DO_CLRFIFO | DO_HWRESELECT); 1985 return; 1986 } 1987 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1988 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1989 DO_CLRFIFO | DO_HWRESELECT); 1990 DELAY(100); 1991 1992 switch (sc->sc_state) { 1993 case TRM_UNEXPECT_RESEL: 1994 sc->sc_state = TRM_IDLE; 1995 break; 1996 1997 case TRM_ABORT_SENT: 1998 goto finish; 1999 2000 case TRM_START: 2001 case TRM_MSGOUT: 2002 { 2003 /* Selection time out - discard all LUNs if empty */ 2004 struct scsipi_periph *periph; 2005 struct trm_tinfo *ti; 2006 struct trm_linfo *li; 2007 int lun; 2008 2009 DPRINTF(("selection timeout\n")); 2010 2011 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2012 2013 periph = srb->xs->xs_periph; 2014 ti = &sc->sc_tinfo[periph->periph_target]; 2015 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2016 li = ti->linfo[lun]; 2017 if (li != NULL && 2018 li->untagged == NULL && li->used == 0) { 2019 ti->linfo[lun] = NULL; 2020 free(li, M_DEVBUF); 2021 } 2022 } 2023 } 2024 goto finish; 2025 2026 case TRM_DISCONNECTED: 2027 sc->sc_actsrb = NULL; 2028 sc->sc_state = TRM_IDLE; 2029 goto sched; 2030 2031 case TRM_COMPLETED: 2032 goto finish; 2033 } 2034 2035 out: 2036 splx(s); 2037 return; 2038 2039 finish: 2040 sc->sc_state = TRM_IDLE; 2041 trm_done(sc, srb); 2042 goto out; 2043 2044 sched: 2045 trm_sched(sc); 2046 goto out; 2047 } 2048 2049 static void 2050 trm_reselect(struct trm_softc *sc) 2051 { 2052 bus_space_tag_t iot = sc->sc_iot; 2053 bus_space_handle_t ioh = sc->sc_ioh; 2054 struct trm_tinfo *ti; 2055 struct trm_linfo *li; 2056 int target, lun; 2057 2058 DPRINTF(("trm_reselect.................\n")); 2059 2060 if (sc->sc_actsrb != NULL) { 2061 /* arbitration lost but reselection win */ 2062 sc->sc_state = TRM_READY; 2063 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2064 ti = &sc->sc_tinfo[target]; 2065 } else { 2066 /* Read Reselected Target Id and LUN */ 2067 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2068 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2069 ti = &sc->sc_tinfo[target]; 2070 li = ti->linfo[lun]; 2071 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2072 2073 /* 2074 * Check to see if we are running an un-tagged command. 2075 * Otherwise ack the IDENTIFY and wait for a tag message. 2076 */ 2077 if (li != NULL) { 2078 if (li->untagged != NULL && li->busy) { 2079 sc->sc_actsrb = li->untagged; 2080 sc->sc_state = TRM_DATA_XFER; 2081 } else { 2082 sc->resel_target = target; 2083 sc->resel_lun = lun; 2084 /* XXX XXX XXX */ 2085 sc->sc_flag |= WAIT_TAGMSG; 2086 } 2087 } 2088 2089 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2090 sc->sc_actsrb == NULL) { 2091 printf("%s: reselect from target %d lun %d " 2092 "without nexus; sending abort\n", 2093 sc->sc_dev.dv_xname, target, lun); 2094 sc->sc_state = TRM_UNEXPECT_RESEL; 2095 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2096 sc->sc_msgcnt = 1; 2097 bus_space_write_2(iot, ioh, 2098 TRM_SCSI_CONTROL, DO_SETATN); 2099 } 2100 } 2101 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2102 /* 2103 * Program HA ID, target ID, period and offset 2104 */ 2105 /* target ID */ 2106 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2107 2108 /* host ID */ 2109 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2110 2111 /* period */ 2112 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2113 2114 /* offset */ 2115 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2116 2117 /* it's important for atn stop */ 2118 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2119 /* 2120 * SCSI command 2121 */ 2122 /* to rls the /ACK signal */ 2123 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2124 } 2125 2126 /* 2127 * Complete execution of a SCSI command 2128 * Signal completion to the generic SCSI driver 2129 */ 2130 static void 2131 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2132 { 2133 struct scsipi_xfer *xs = srb->xs; 2134 2135 DPRINTF(("trm_done..................\n")); 2136 2137 if (xs == NULL) 2138 return; 2139 2140 if ((xs->xs_control & XS_CTL_POLL) == 0) 2141 callout_stop(&xs->xs_callout); 2142 2143 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2144 srb->flag & AUTO_REQSENSE) { 2145 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2146 srb->dmap->dm_mapsize, 2147 ((xs->xs_control & XS_CTL_DATA_IN) || 2148 (srb->flag & AUTO_REQSENSE)) ? 2149 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2150 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2151 } 2152 2153 /* 2154 * target status 2155 */ 2156 xs->status = srb->tastat; 2157 2158 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2159 2160 switch (xs->status) { 2161 case SCSI_OK: 2162 /* 2163 * process initiator status...... 2164 * Adapter (initiator) status 2165 */ 2166 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2167 printf("%s: over/under run error\n", 2168 sc->sc_dev.dv_xname); 2169 srb->tastat = 0; 2170 /* Illegal length (over/under run) */ 2171 xs->error = XS_DRIVER_STUFFUP; 2172 } else if ((srb->flag & PARITY_ERROR) != 0) { 2173 printf("%s: parity error\n", 2174 sc->sc_dev.dv_xname); 2175 /* Driver failed to perform operation */ 2176 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2177 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2178 xs->resid = srb->buflen; 2179 xs->error = XS_TIMEOUT; 2180 } else { 2181 /* No error */ 2182 xs->resid = srb->buflen; 2183 srb->hastat = 0; 2184 if (srb->flag & AUTO_REQSENSE) { 2185 /* there is no error, (sense is invalid) */ 2186 xs->error = XS_SENSE; 2187 } else { 2188 srb->tastat = 0; 2189 xs->error = XS_NOERROR; 2190 } 2191 } 2192 break; 2193 2194 case SCSI_CHECK: 2195 if ((srb->flag & AUTO_REQSENSE) != 0 || 2196 trm_request_sense(sc, srb) != 0) { 2197 printf("%s: request sense failed\n", 2198 sc->sc_dev.dv_xname); 2199 xs->error = XS_DRIVER_STUFFUP; 2200 break; 2201 } 2202 xs->error = XS_SENSE; 2203 return; 2204 2205 case SCSI_SEL_TIMEOUT: 2206 srb->hastat = H_SEL_TIMEOUT; 2207 srb->tastat = 0; 2208 xs->error = XS_SELTIMEOUT; 2209 break; 2210 2211 case SCSI_QUEUE_FULL: 2212 case SCSI_BUSY: 2213 xs->error = XS_BUSY; 2214 break; 2215 2216 case SCSI_RESV_CONFLICT: 2217 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2218 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2219 xs->error = XS_BUSY; 2220 break; 2221 2222 default: 2223 srb->hastat = 0; 2224 printf("%s: trm_done(): unknown status = %02x\n", 2225 sc->sc_dev.dv_xname, xs->status); 2226 xs->error = XS_DRIVER_STUFFUP; 2227 break; 2228 } 2229 2230 trm_dequeue(sc, srb); 2231 if (srb == sc->sc_actsrb) { 2232 sc->sc_actsrb = NULL; 2233 trm_sched(sc); 2234 } 2235 2236 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2237 2238 /* Notify cmd done */ 2239 scsipi_done(xs); 2240 } 2241 2242 static int 2243 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2244 { 2245 struct scsipi_xfer *xs; 2246 struct scsipi_periph *periph; 2247 struct trm_tinfo *ti; 2248 struct trm_linfo *li; 2249 struct scsipi_sense *ss = (struct scsipi_sense *)srb->cmd; 2250 int error; 2251 2252 DPRINTF(("trm_request_sense...\n")); 2253 2254 xs = srb->xs; 2255 periph = xs->xs_periph; 2256 2257 srb->flag |= AUTO_REQSENSE; 2258 2259 /* Status of initiator/target */ 2260 srb->hastat = 0; 2261 srb->tastat = 0; 2262 2263 ss->opcode = REQUEST_SENSE; 2264 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2265 ss->unused[0] = ss->unused[1] = 0; 2266 ss->length = sizeof(struct scsipi_sense_data); 2267 ss->control = 0; 2268 2269 srb->buflen = sizeof(struct scsipi_sense_data); 2270 srb->sgcnt = 1; 2271 srb->sgindex = 0; 2272 srb->cmdlen = sizeof(struct scsipi_sense); 2273 2274 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2275 &xs->sense.scsi_sense, srb->buflen, NULL, 2276 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2277 return error; 2278 } 2279 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2280 srb->buflen, BUS_DMASYNC_PREREAD); 2281 2282 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2283 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2284 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2285 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2286 2287 ti = &sc->sc_tinfo[periph->periph_target]; 2288 li = ti->linfo[periph->periph_lun]; 2289 if (li->busy > 0) 2290 li->busy = 0; 2291 trm_dequeue(sc, srb); 2292 li->untagged = srb; /* must be executed first to fix C/A */ 2293 li->busy = 2; 2294 2295 if (srb == sc->sc_actsrb) 2296 trm_select(sc, srb); 2297 else { 2298 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2299 if (sc->sc_actsrb == NULL) 2300 trm_sched(sc); 2301 } 2302 return 0; 2303 } 2304 2305 static void 2306 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2307 { 2308 struct scsipi_periph *periph; 2309 struct trm_tinfo *ti; 2310 struct trm_linfo *li; 2311 2312 periph = srb->xs->xs_periph; 2313 ti = &sc->sc_tinfo[periph->periph_target]; 2314 li = ti->linfo[periph->periph_lun]; 2315 2316 if (li->untagged == srb) { 2317 li->busy = 0; 2318 li->untagged = NULL; 2319 } 2320 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2321 li->queued[srb->tag[1]] = NULL; 2322 li->used--; 2323 } 2324 } 2325 2326 static void 2327 trm_reset_scsi_bus(struct trm_softc *sc) 2328 { 2329 bus_space_tag_t iot = sc->sc_iot; 2330 bus_space_handle_t ioh = sc->sc_ioh; 2331 int timeout, s; 2332 2333 DPRINTF(("trm_reset_scsi_bus.........\n")); 2334 2335 s = splbio(); 2336 2337 sc->sc_flag |= RESET_DEV; 2338 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2339 for (timeout = 20000; timeout >= 0; timeout--) { 2340 DELAY(1); 2341 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2342 INT_SCSIRESET) == 0) 2343 break; 2344 } 2345 if (timeout == 0) 2346 printf(": scsibus reset timeout\n"); 2347 2348 splx(s); 2349 } 2350 2351 static void 2352 trm_scsi_reset_detect(struct trm_softc *sc) 2353 { 2354 bus_space_tag_t iot = sc->sc_iot; 2355 bus_space_handle_t ioh = sc->sc_ioh; 2356 int s; 2357 2358 DPRINTF(("trm_scsi_reset_detect...............\n")); 2359 DELAY(1000000); /* delay 1 sec */ 2360 2361 s = splbio(); 2362 2363 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2364 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2365 2366 if (sc->sc_flag & RESET_DEV) { 2367 sc->sc_flag |= RESET_DONE; 2368 } else { 2369 sc->sc_flag |= RESET_DETECT; 2370 sc->sc_actsrb = NULL; 2371 sc->sc_flag = 0; 2372 trm_sched(sc); 2373 } 2374 splx(s); 2375 } 2376 2377 /* 2378 * read seeprom 128 bytes to struct eeprom and check checksum. 2379 * If it is wrong, update with default value. 2380 */ 2381 static void 2382 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2383 { 2384 struct nvram_target *target; 2385 u_int16_t *ep; 2386 u_int16_t chksum; 2387 int i; 2388 2389 DPRINTF(("trm_check_eeprom......\n")); 2390 trm_eeprom_read_all(sc, eeprom); 2391 ep = (u_int16_t *)eeprom; 2392 chksum = 0; 2393 for (i = 0; i < 64; i++) 2394 chksum += le16toh(*ep++); 2395 2396 if (chksum != TRM_NVRAM_CKSUM) { 2397 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2398 /* 2399 * Checksum error, load default 2400 */ 2401 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2402 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2403 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2404 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2405 eeprom->subclass = 0x00; 2406 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2407 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2408 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2409 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2410 eeprom->reserved0 = 0x00; 2411 2412 for (i = 0, target = eeprom->target; 2413 i < TRM_MAX_TARGETS; 2414 i++, target++) { 2415 target->config0 = 0x77; 2416 target->period = 0x00; 2417 target->config2 = 0x00; 2418 target->config3 = 0x00; 2419 } 2420 2421 eeprom->scsi_id = 7; 2422 eeprom->channel_cfg = 0x0F; 2423 eeprom->delay_time = 0; 2424 eeprom->max_tag = 4; 2425 eeprom->reserved1 = 0x15; 2426 eeprom->boot_target = 0; 2427 eeprom->boot_lun = 0; 2428 eeprom->reserved2 = 0; 2429 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2430 2431 chksum = 0; 2432 ep = (u_int16_t *)eeprom; 2433 for (i = 0; i < 63; i++) 2434 chksum += le16toh(*ep++); 2435 2436 chksum = TRM_NVRAM_CKSUM - chksum; 2437 eeprom->checksum0 = chksum & 0xFF; 2438 eeprom->checksum1 = chksum >> 8; 2439 2440 trm_eeprom_write_all(sc, eeprom); 2441 } 2442 } 2443 2444 /* 2445 * write struct eeprom 128 bytes to seeprom 2446 */ 2447 static void 2448 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2449 { 2450 bus_space_tag_t iot = sc->sc_iot; 2451 bus_space_handle_t ioh = sc->sc_ioh; 2452 u_int8_t *buf = (u_int8_t *)eeprom; 2453 u_int8_t addr; 2454 2455 /* Enable SEEPROM */ 2456 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2457 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2458 2459 /* 2460 * Write enable 2461 */ 2462 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2463 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2464 trm_eeprom_wait(); 2465 2466 for (addr = 0; addr < 128; addr++, buf++) 2467 trm_eeprom_set_data(sc, addr, *buf); 2468 2469 /* 2470 * Write disable 2471 */ 2472 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2473 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2474 trm_eeprom_wait(); 2475 2476 /* Disable SEEPROM */ 2477 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2478 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2479 } 2480 2481 /* 2482 * write one byte to seeprom 2483 */ 2484 static void 2485 trm_eeprom_set_data(struct trm_softc *sc, u_int8_t addr, u_int8_t data) 2486 { 2487 bus_space_tag_t iot = sc->sc_iot; 2488 bus_space_handle_t ioh = sc->sc_ioh; 2489 int i; 2490 u_int8_t send; 2491 2492 /* 2493 * Send write command & address 2494 */ 2495 trm_eeprom_write_cmd(sc, 0x05, addr); 2496 /* 2497 * Write data 2498 */ 2499 for (i = 0; i < 8; i++, data <<= 1) { 2500 send = NVR_SELECT; 2501 if (data & 0x80) /* Start from bit 7 */ 2502 send |= NVR_BITOUT; 2503 2504 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2505 trm_eeprom_wait(); 2506 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2507 trm_eeprom_wait(); 2508 } 2509 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2510 trm_eeprom_wait(); 2511 /* 2512 * Disable chip select 2513 */ 2514 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2515 trm_eeprom_wait(); 2516 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2517 trm_eeprom_wait(); 2518 /* 2519 * Wait for write ready 2520 */ 2521 for (;;) { 2522 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2523 NVR_SELECT | NVR_CLOCK); 2524 trm_eeprom_wait(); 2525 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2526 trm_eeprom_wait(); 2527 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2528 break; 2529 } 2530 /* 2531 * Disable chip select 2532 */ 2533 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2534 } 2535 2536 /* 2537 * read seeprom 128 bytes to struct eeprom 2538 */ 2539 static void 2540 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2541 { 2542 bus_space_tag_t iot = sc->sc_iot; 2543 bus_space_handle_t ioh = sc->sc_ioh; 2544 u_int8_t *buf = (u_int8_t *)eeprom; 2545 u_int8_t addr; 2546 2547 /* 2548 * Enable SEEPROM 2549 */ 2550 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2551 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2552 2553 for (addr = 0; addr < 128; addr++) 2554 *buf++ = trm_eeprom_get_data(sc, addr); 2555 2556 /* 2557 * Disable SEEPROM 2558 */ 2559 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2560 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2561 } 2562 2563 /* 2564 * read one byte from seeprom 2565 */ 2566 static u_int8_t 2567 trm_eeprom_get_data(struct trm_softc *sc, u_int8_t addr) 2568 { 2569 bus_space_tag_t iot = sc->sc_iot; 2570 bus_space_handle_t ioh = sc->sc_ioh; 2571 int i; 2572 u_int8_t read, data = 0; 2573 2574 /* 2575 * Send read command & address 2576 */ 2577 trm_eeprom_write_cmd(sc, 0x06, addr); 2578 2579 for (i = 0; i < 8; i++) { /* Read data */ 2580 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2581 NVR_SELECT | NVR_CLOCK); 2582 trm_eeprom_wait(); 2583 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2584 /* 2585 * Get data bit while falling edge 2586 */ 2587 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2588 data <<= 1; 2589 if (read & NVR_BITIN) 2590 data |= 1; 2591 2592 trm_eeprom_wait(); 2593 } 2594 /* 2595 * Disable chip select 2596 */ 2597 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2598 return (data); 2599 } 2600 2601 /* 2602 * write SB and Op Code into seeprom 2603 */ 2604 static void 2605 trm_eeprom_write_cmd(struct trm_softc *sc, u_int8_t cmd, u_int8_t addr) 2606 { 2607 bus_space_tag_t iot = sc->sc_iot; 2608 bus_space_handle_t ioh = sc->sc_ioh; 2609 int i; 2610 u_int8_t send; 2611 2612 /* Program SB+OP code */ 2613 for (i = 0; i < 3; i++, cmd <<= 1) { 2614 send = NVR_SELECT; 2615 if (cmd & 0x04) /* Start from bit 2 */ 2616 send |= NVR_BITOUT; 2617 2618 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2619 trm_eeprom_wait(); 2620 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2621 trm_eeprom_wait(); 2622 } 2623 2624 /* Program address */ 2625 for (i = 0; i < 7; i++, addr <<= 1) { 2626 send = NVR_SELECT; 2627 if (addr & 0x40) /* Start from bit 6 */ 2628 send |= NVR_BITOUT; 2629 2630 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2631 trm_eeprom_wait(); 2632 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2633 trm_eeprom_wait(); 2634 } 2635 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2636 trm_eeprom_wait(); 2637 } 2638
Indexes created Tue Sep 23 02:09:52 GMT 2025