trm.c revision 1.18
1 /* $NetBSD: trm.c,v 1.18 2005/02/27 00:27:34 perry Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.18 2005/02/27 00:27:34 perry Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_spc.h> 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsi_message.h> 71 #include <dev/scsipi/scsipi_all.h> 72 #include <dev/scsipi/scsiconf.h> 73 74 #include <dev/pci/pcidevs.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/trmreg.h> 78 79 /* 80 * feature of chip set MAX value 81 */ 82 #define TRM_MAX_TARGETS 16 83 #define TRM_MAX_LUNS 8 84 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 85 #define TRM_MAX_SRB 32 /* XXX */ 86 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 87 #define TRM_MAX_OFFSET 15 88 #define TRM_MAX_PERIOD 125 89 90 /* 91 * Segment Entry 92 */ 93 struct trm_sg_entry { 94 uint32_t address; 95 uint32_t length; 96 }; 97 98 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 99 100 /* 101 ********************************************************************** 102 * The SEEPROM structure for TRM_S1040 103 ********************************************************************** 104 */ 105 struct nvram_target { 106 uint8_t config0; /* Target configuration byte 0 */ 107 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 108 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 109 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 110 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 111 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 112 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 113 uint8_t period; /* Target period */ 114 uint8_t config2; /* Target configuration byte 2 */ 115 uint8_t config3; /* Target configuration byte 3 */ 116 }; 117 118 struct trm_nvram { 119 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 120 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 121 uint8_t subclass; /* 4 Sub Class */ 122 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 123 uint8_t device_id[2]; /* 7,8 Device ID */ 124 uint8_t reserved0; /* 9 Reserved */ 125 struct nvram_target target[TRM_MAX_TARGETS]; 126 /* 10,11,12,13 127 * 14,15,16,17 128 * .... 129 * 70,71,72,73 */ 130 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 131 uint8_t channel_cfg; /* 75 Channel configuration */ 132 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 133 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 134 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 135 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 136 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 137 uint8_t delay_time; /* 76 Power on delay time */ 138 uint8_t max_tag; /* 77 Maximum tags */ 139 uint8_t reserved1; /* 78 */ 140 uint8_t boot_target; /* 79 */ 141 uint8_t boot_lun; /* 80 */ 142 uint8_t reserved2; /* 81 */ 143 uint8_t reserved3[44]; /* 82,..125 */ 144 uint8_t checksum0; /* 126 */ 145 uint8_t checksum1; /* 127 */ 146 #define TRM_NVRAM_CKSUM 0x1234 147 }; 148 149 /* Nvram Initiater bits definition */ 150 #define MORE2_DRV 0x00000001 151 #define GREATER_1G 0x00000002 152 #define RST_SCSI_BUS 0x00000004 153 #define ACTIVE_NEGATION 0x00000008 154 #define NO_SEEK 0x00000010 155 #define LUN_CHECK 0x00000020 156 157 #define trm_eeprom_wait() DELAY(30) 158 159 /* 160 *----------------------------------------------------------------------- 161 * SCSI Request Block 162 *----------------------------------------------------------------------- 163 */ 164 struct trm_srb { 165 TAILQ_ENTRY(trm_srb) next; 166 167 struct trm_sg_entry *sgentry; 168 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 169 bus_dmamap_t dmap; 170 bus_size_t sgoffset; /* Xfer buf offset */ 171 172 uint32_t buflen; /* Total xfer length */ 173 uint32_t sgaddr; /* SGList physical starting address */ 174 175 int sgcnt; 176 int sgindex; 177 178 int hastat; /* Host Adapter Status */ 179 #define H_STATUS_GOOD 0x00 180 #define H_SEL_TIMEOUT 0x11 181 #define H_OVER_UNDER_RUN 0x12 182 #define H_UNEXP_BUS_FREE 0x13 183 #define H_TARGET_PHASE_F 0x14 184 #define H_INVALID_CCB_OP 0x16 185 #define H_LINK_CCB_BAD 0x17 186 #define H_BAD_TARGET_DIR 0x18 187 #define H_DUPLICATE_CCB 0x19 188 #define H_BAD_CCB_OR_SG 0x1A 189 #define H_ABORT 0xFF 190 int tastat; /* Target SCSI Status Byte */ 191 int flag; /* SRBFlag */ 192 #define AUTO_REQSENSE 0x0001 193 #define PARITY_ERROR 0x0002 194 #define SRB_TIMEOUT 0x0004 195 196 int cmdlen; /* SCSI command length */ 197 uint8_t cmd[12]; /* SCSI command */ 198 199 uint8_t tag[2]; 200 }; 201 202 /* 203 * some info about each target and lun on the SCSI bus 204 */ 205 struct trm_linfo { 206 int used; /* number of slots in use */ 207 int avail; /* where to start scanning */ 208 int busy; /* lun in use */ 209 struct trm_srb *untagged; 210 struct trm_srb *queued[TRM_MAX_TAG]; 211 }; 212 213 struct trm_tinfo { 214 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 215 #define SYNC_NEGO_ENABLE 0x0001 216 #define SYNC_NEGO_DOING 0x0002 217 #define SYNC_NEGO_DONE 0x0004 218 #define WIDE_NEGO_ENABLE 0x0008 219 #define WIDE_NEGO_DOING 0x0010 220 #define WIDE_NEGO_DONE 0x0020 221 #define USE_TAG_QUEUING 0x0040 222 #define NO_RESELECT 0x0080 223 struct trm_linfo *linfo[TRM_MAX_LUNS]; 224 225 uint8_t config0; /* Target Config */ 226 uint8_t period; /* Max Period for nego. */ 227 uint8_t synctl; /* Sync control for reg. */ 228 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 229 }; 230 231 /* 232 *----------------------------------------------------------------------- 233 * Adapter Control Block 234 *----------------------------------------------------------------------- 235 */ 236 struct trm_softc { 237 struct device sc_dev; 238 239 bus_space_tag_t sc_iot; 240 bus_space_handle_t sc_ioh; 241 bus_dma_tag_t sc_dmat; 242 bus_dmamap_t sc_dmamap; /* Map the control structures */ 243 244 struct trm_srb *sc_actsrb; 245 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 246 247 TAILQ_HEAD(, trm_srb) sc_freesrb, 248 sc_readysrb; 249 struct trm_srb *sc_srb; /* SRB array */ 250 251 struct trm_sg_entry *sc_sglist; 252 253 int sc_maxid; 254 /* 255 * Link to the generic SCSI driver 256 */ 257 struct scsipi_channel sc_channel; 258 struct scsipi_adapter sc_adapter; 259 260 int sc_id; /* Adapter SCSI Target ID */ 261 262 int sc_state; /* SRB State */ 263 #define TRM_IDLE 0 264 #define TRM_WAIT 1 265 #define TRM_READY 2 266 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 267 #define TRM_MSGIN 4 268 #define TRM_EXTEND_MSGIN 5 269 #define TRM_COMMAND 6 270 #define TRM_START 7 /* arbitration+msg_out+command_out */ 271 #define TRM_DISCONNECTED 8 272 #define TRM_DATA_XFER 9 273 #define TRM_XFERPAD 10 274 #define TRM_STATUS 11 275 #define TRM_COMPLETED 12 276 #define TRM_ABORT_SENT 13 277 #define TRM_UNEXPECT_RESEL 14 278 279 int sc_phase; /* SCSI phase */ 280 int sc_config; 281 #define HCC_WIDE_CARD 0x01 282 #define HCC_SCSI_RESET 0x02 283 #define HCC_PARITY 0x04 284 #define HCC_AUTOTERM 0x08 285 #define HCC_LOW8TERM 0x10 286 #define HCC_UP8TERM 0x20 287 288 int sc_flag; 289 #define RESET_DEV 0x01 290 #define RESET_DETECT 0x02 291 #define RESET_DONE 0x04 292 #define WAIT_TAGMSG 0x08 /* XXX */ 293 294 int sc_msgcnt; 295 296 int resel_target; /* XXX */ 297 int resel_lun; /* XXX */ 298 299 uint8_t *sc_msg; 300 uint8_t sc_msgbuf[6]; 301 }; 302 303 /* 304 * SCSI Status codes not defined in scsi_all.h 305 */ 306 #define SCSI_COND_MET 0x04 /* Condition Met */ 307 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 308 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 309 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 310 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 311 312 static int trm_probe(struct device *, struct cfdata *, void *); 313 static void trm_attach(struct device *, struct device *, void *); 314 315 static int trm_init(struct trm_softc *); 316 317 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 318 void *); 319 static void trm_update_xfer_mode(struct trm_softc *, int); 320 static void trm_sched(struct trm_softc *); 321 static int trm_select(struct trm_softc *, struct trm_srb *); 322 static void trm_reset(struct trm_softc *); 323 static void trm_timeout(void *); 324 static int trm_intr(void *); 325 326 static void trm_dataout_phase0(struct trm_softc *, int); 327 static void trm_datain_phase0(struct trm_softc *, int); 328 static void trm_status_phase0(struct trm_softc *); 329 static void trm_msgin_phase0(struct trm_softc *); 330 static void trm_command_phase1(struct trm_softc *); 331 static void trm_status_phase1(struct trm_softc *); 332 static void trm_msgout_phase1(struct trm_softc *); 333 static void trm_msgin_phase1(struct trm_softc *); 334 335 static void trm_dataio_xfer(struct trm_softc *, int); 336 static void trm_disconnect(struct trm_softc *); 337 static void trm_reselect(struct trm_softc *); 338 static void trm_done(struct trm_softc *, struct trm_srb *); 339 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 340 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 341 342 static void trm_scsi_reset_detect(struct trm_softc *); 343 static void trm_reset_scsi_bus(struct trm_softc *); 344 345 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 348 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 349 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 350 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 351 352 CFATTACH_DECL(trm, sizeof(struct trm_softc), 353 trm_probe, trm_attach, NULL, NULL); 354 355 /* real period: */ 356 static const uint8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(struct device *parent, struct cfdata *match, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 373 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 374 switch (PCI_PRODUCT(pa->pa_id)) { 375 case PCI_PRODUCT_TEKRAM2_DC315: 376 return (1); 377 } 378 return (0); 379 } 380 381 /* 382 * attach and init a host adapter 383 */ 384 static void 385 trm_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct pci_attach_args *const pa = aux; 388 struct trm_softc *sc = (struct trm_softc *)self; 389 bus_space_tag_t iot; 390 bus_space_handle_t ioh; 391 pci_intr_handle_t ih; 392 pcireg_t command; 393 const char *intrstr; 394 395 /* 396 * These cards do not allow memory mapped accesses 397 * pa_pc: chipset tag 398 * pa_tag: pci tag 399 */ 400 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 401 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 402 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 403 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 404 pci_conf_write(pa->pa_pc, pa->pa_tag, 405 PCI_COMMAND_STATUS_REG, command); 406 } 407 /* 408 * mask for get correct base address of pci IO port 409 */ 410 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 411 &iot, &ioh, NULL, NULL)) { 412 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 413 return; 414 } 415 /* 416 * test checksum of eeprom.. & initialize softc... 417 */ 418 sc->sc_iot = iot; 419 sc->sc_ioh = ioh; 420 sc->sc_dmat = pa->pa_dmat; 421 422 if (trm_init(sc) != 0) { 423 /* 424 * Error during initialization! 425 */ 426 printf(": Error during initialization\n"); 427 return; 428 } 429 /* 430 * Now try to attach all the sub-devices 431 */ 432 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 433 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 434 "Ultra Wide SCSI Adapter\n"); 435 else 436 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 437 "Ultra SCSI Adapter\n"); 438 439 /* 440 * Now tell the generic SCSI layer about our bus. 441 * map and establish interrupt 442 */ 443 if (pci_intr_map(pa, &ih)) { 444 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 445 return; 446 } 447 intrstr = pci_intr_string(pa->pa_pc, ih); 448 449 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 450 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 451 if (intrstr != NULL) 452 printf(" at %s", intrstr); 453 printf("\n"); 454 return; 455 } 456 if (intrstr != NULL) 457 printf("%s: interrupting at %s\n", 458 sc->sc_dev.dv_xname, intrstr); 459 460 sc->sc_adapter.adapt_dev = &sc->sc_dev; 461 sc->sc_adapter.adapt_nchannels = 1; 462 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 463 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 464 sc->sc_adapter.adapt_request = trm_scsipi_request; 465 sc->sc_adapter.adapt_minphys = minphys; 466 467 sc->sc_channel.chan_adapter = &sc->sc_adapter; 468 sc->sc_channel.chan_bustype = &scsi_bustype; 469 sc->sc_channel.chan_channel = 0; 470 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 471 sc->sc_channel.chan_nluns = 8; 472 sc->sc_channel.chan_id = sc->sc_id; 473 474 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 475 } 476 477 /* 478 * initialize the internal structures for a given SCSI host 479 */ 480 static int 481 trm_init(struct trm_softc *sc) 482 { 483 bus_space_tag_t iot = sc->sc_iot; 484 bus_space_handle_t ioh = sc->sc_ioh; 485 bus_dma_segment_t seg; 486 struct trm_nvram eeprom; 487 struct trm_srb *srb; 488 struct trm_tinfo *ti; 489 struct nvram_target *tconf; 490 int error, rseg, all_sgsize; 491 int i, target; 492 uint8_t bval; 493 494 DPRINTF(("\n")); 495 496 /* 497 * allocate the space for all SCSI control blocks (SRB) for DMA memory 498 */ 499 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 500 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 501 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 502 printf(": unable to allocate SCSI REQUEST BLOCKS, " 503 "error = %d\n", error); 504 return (1); 505 } 506 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 507 all_sgsize, (caddr_t *) &sc->sc_sglist, 508 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 509 printf(": unable to map SCSI REQUEST BLOCKS, " 510 "error = %d\n", error); 511 return (1); 512 } 513 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 514 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 515 printf(": unable to create SRB DMA maps, " 516 "error = %d\n", error); 517 return (1); 518 } 519 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 520 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 521 printf(": unable to load SRB DMA maps, " 522 "error = %d\n", error); 523 return (1); 524 } 525 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 526 memset(sc->sc_sglist, 0, all_sgsize); 527 528 /* 529 * EEPROM CHECKSUM 530 */ 531 trm_check_eeprom(sc, &eeprom); 532 533 sc->sc_maxid = 7; 534 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 535 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 536 sc->sc_config |= HCC_WIDE_CARD; 537 sc->sc_maxid = 15; 538 } 539 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 540 sc->sc_config |= HCC_SCSI_RESET; 541 542 sc->sc_actsrb = NULL; 543 sc->sc_id = eeprom.scsi_id; 544 sc->sc_flag = 0; 545 546 /* 547 * initialize and link all device's SRB queues of this adapter 548 */ 549 TAILQ_INIT(&sc->sc_freesrb); 550 TAILQ_INIT(&sc->sc_readysrb); 551 552 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 553 M_DEVBUF, M_NOWAIT|M_ZERO); 554 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 555 if (sc->sc_srb == NULL) { 556 printf(": can not allocate SRB\n"); 557 return (1); 558 } 559 560 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 561 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 562 srb->sgoffset = TRM_SG_SIZE * i; 563 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 564 /* 565 * map all SRB space to SRB_array 566 */ 567 if (bus_dmamap_create(sc->sc_dmat, 568 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 569 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 570 printf(": unable to create DMA transfer map...\n"); 571 free(sc->sc_srb, M_DEVBUF); 572 return (1); 573 } 574 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 575 srb++; 576 } 577 578 /* 579 * initialize all target info structures 580 */ 581 for (target = 0; target < TRM_MAX_TARGETS; target++) { 582 ti = &sc->sc_tinfo[target]; 583 ti->synctl = 0; 584 ti->offset = 0; 585 tconf = &eeprom.target[target]; 586 ti->config0 = tconf->config0; 587 ti->period = trm_clock_period[tconf->period & 0x07]; 588 ti->flag = 0; 589 if ((ti->config0 & NTC_DO_WIDE_NEGO) != 0 && 590 (sc->sc_config & HCC_WIDE_CARD) != 0) 591 ti->flag |= WIDE_NEGO_ENABLE; 592 if ((ti->config0 & NTC_DO_SYNC_NEGO) != 0) 593 ti->flag |= SYNC_NEGO_ENABLE; 594 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 595 #ifdef notyet 596 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 597 ti->flag |= USE_TAG_QUEUING; 598 #endif 599 } else 600 ti->flag |= NO_RESELECT; 601 602 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 603 target, ti->config0, ti->period)); 604 DPRINTF((", flag = 0x%02x\n", ti->flag)); 605 } 606 607 /* program configuration 0 */ 608 bval = PHASELATCH | INITIATOR | BLOCKRST; 609 if ((sc->sc_config & HCC_PARITY) != 0) 610 bval |= PARITYCHECK; 611 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 612 613 /* program configuration 1 */ 614 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 615 ACTIVE_NEG | ACTIVE_NEGPLUS); 616 617 /* 250ms selection timeout */ 618 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 619 620 /* Mask all interrupts */ 621 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 622 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 623 624 /* Reset SCSI module */ 625 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 626 627 /* program Host ID */ 628 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 629 630 /* set asynchronous transfer */ 631 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 632 633 /* Turn LED control off */ 634 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 635 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 636 637 /* DMA config */ 638 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 639 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 640 641 /* Clear pending interrupt status */ 642 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 643 644 /* Enable SCSI interrupt */ 645 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 646 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 647 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 648 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 649 650 trm_reset(sc); 651 652 return (0); 653 } 654 655 /* 656 * enqueues a SCSI command 657 * called by the higher level SCSI driver 658 */ 659 static void 660 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 661 void *arg) 662 { 663 bus_space_tag_t iot; 664 bus_space_handle_t ioh; 665 struct trm_softc *sc; 666 struct trm_srb *srb; 667 struct scsipi_xfer *xs; 668 int error, i, target, lun, s; 669 670 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 671 iot = sc->sc_iot; 672 ioh = sc->sc_ioh; 673 674 switch (req) { 675 case ADAPTER_REQ_RUN_XFER: 676 xs = arg; 677 target = xs->xs_periph->periph_target; 678 lun = xs->xs_periph->periph_lun; 679 DPRINTF(("trm_scsipi_request.....\n")); 680 DPRINTF(("target= %d lun= %d\n", target, lun)); 681 if (xs->xs_control & XS_CTL_RESET) { 682 trm_reset(sc); 683 xs->error = XS_NOERROR | XS_RESET; 684 return; 685 } 686 if (xs->xs_status & XS_STS_DONE) { 687 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 688 xs->xs_status &= ~XS_STS_DONE; 689 } 690 691 s = splbio(); 692 693 /* Get SRB */ 694 srb = TAILQ_FIRST(&sc->sc_freesrb); 695 if (srb != NULL) { 696 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 697 } else { 698 xs->error = XS_RESOURCE_SHORTAGE; 699 scsipi_done(xs); 700 splx(s); 701 return; 702 } 703 704 srb->xs = xs; 705 srb->cmdlen = xs->cmdlen; 706 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 707 708 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 709 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 710 xs->data, xs->datalen, NULL, 711 ((xs->xs_control & XS_CTL_NOSLEEP) ? 712 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 713 BUS_DMA_STREAMING | 714 ((xs->xs_control & XS_CTL_DATA_IN) ? 715 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 716 printf("%s: DMA transfer map unable to load, " 717 "error = %d\n", sc->sc_dev.dv_xname, error); 718 xs->error = XS_DRIVER_STUFFUP; 719 /* 720 * free SRB 721 */ 722 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 723 splx(s); 724 return; 725 } 726 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 727 srb->dmap->dm_mapsize, 728 (xs->xs_control & XS_CTL_DATA_IN) ? 729 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 730 731 /* Set up the scatter gather list */ 732 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 733 srb->sgentry[i].address = 734 htole32(srb->dmap->dm_segs[i].ds_addr); 735 srb->sgentry[i].length = 736 htole32(srb->dmap->dm_segs[i].ds_len); 737 } 738 srb->buflen = xs->datalen; 739 srb->sgcnt = srb->dmap->dm_nsegs; 740 } else { 741 srb->sgentry[0].address = 0; 742 srb->sgentry[0].length = 0; 743 srb->buflen = 0; 744 srb->sgcnt = 0; 745 } 746 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 747 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 748 749 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 750 751 srb->sgindex = 0; 752 srb->hastat = 0; 753 srb->tastat = 0; 754 srb->flag = 0; 755 756 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 757 if (sc->sc_actsrb == NULL) 758 trm_sched(sc); 759 splx(s); 760 761 if ((xs->xs_control & XS_CTL_POLL) != 0) { 762 int timeout = xs->timeout; 763 764 s = splbio(); 765 do { 766 while (--timeout) { 767 DELAY(1000); 768 if (bus_space_read_2(iot, ioh, 769 TRM_SCSI_STATUS) & SCSIINTERRUPT) 770 break; 771 } 772 if (timeout == 0) { 773 trm_timeout(srb); 774 break; 775 } else 776 trm_intr(sc); 777 } while ((xs->xs_status & XS_STS_DONE) == 0); 778 splx(s); 779 } 780 return; 781 782 case ADAPTER_REQ_GROW_RESOURCES: 783 /* XXX Not supported. */ 784 return; 785 786 case ADAPTER_REQ_SET_XFER_MODE: 787 { 788 struct trm_tinfo *ti; 789 struct scsipi_xfer_mode *xm; 790 791 xm = arg; 792 ti = &sc->sc_tinfo[xm->xm_target]; 793 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 794 795 #ifdef notyet 796 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 797 ti->flag |= USE_TAG_QUEUING; 798 else 799 #endif 800 ti->flag &= ~USE_TAG_QUEUING; 801 802 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0) { 803 ti->flag |= WIDE_NEGO_ENABLE; 804 ti->flag &= ~WIDE_NEGO_DONE; 805 } 806 807 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0) { 808 ti->flag |= SYNC_NEGO_ENABLE; 809 ti->flag &= ~SYNC_NEGO_DONE; 810 ti->period = trm_clock_period[0]; 811 } 812 813 /* 814 * If we're not going to negotiate, send the 815 * notification now, since it won't happen later. 816 */ 817 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 818 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 819 trm_update_xfer_mode(sc, xm->xm_target); 820 821 return; 822 } 823 } 824 } 825 826 static void 827 trm_update_xfer_mode(struct trm_softc *sc, int target) 828 { 829 struct scsipi_xfer_mode xm; 830 struct trm_tinfo *ti; 831 832 ti = &sc->sc_tinfo[target]; 833 xm.xm_target = target; 834 xm.xm_mode = 0; 835 xm.xm_period = 0; 836 xm.xm_offset = 0; 837 838 if ((ti->synctl & WIDE_SYNC) != 0) 839 xm.xm_mode |= PERIPH_CAP_WIDE16; 840 841 if (ti->period > 0) { 842 xm.xm_mode |= PERIPH_CAP_SYNC; 843 xm.xm_period = ti->period; 844 xm.xm_offset = ti->offset; 845 } 846 847 #ifdef notyet 848 if ((ti->flag & USE_TAG_QUEUING) != 0) 849 xm.xm_mode |= PERIPH_CAP_TQING; 850 #endif 851 852 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 853 } 854 855 static void 856 trm_sched(struct trm_softc *sc) 857 { 858 struct trm_srb *srb; 859 struct scsipi_periph *periph; 860 struct trm_tinfo *ti; 861 struct trm_linfo *li; 862 int s, lun, tag; 863 864 DPRINTF(("trm_sched...\n")); 865 866 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 867 periph = srb->xs->xs_periph; 868 ti = &sc->sc_tinfo[periph->periph_target]; 869 lun = periph->periph_lun; 870 871 /* select type of tag for this command */ 872 if ((ti->flag & NO_RESELECT) != 0 || 873 (ti->flag & USE_TAG_QUEUING) == 0 || 874 (srb->flag & AUTO_REQSENSE) != 0 || 875 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 876 tag = 0; 877 else 878 tag = srb->xs->xs_tag_type; 879 #if 0 880 /* XXX use tags for polled commands? */ 881 if (srb->xs->xs_control & XS_CTL_POLL) 882 tag = 0; 883 #endif 884 885 s = splbio(); 886 li = ti->linfo[lun]; 887 if (li == NULL) { 888 /* initialize lun info */ 889 if ((li = malloc(sizeof(*li), M_DEVBUF, 890 M_NOWAIT|M_ZERO)) == NULL) { 891 splx(s); 892 continue; 893 } 894 ti->linfo[lun] = li; 895 } 896 897 if (tag == 0) { 898 /* try to issue this srb as an un-tagged command */ 899 if (li->untagged == NULL) 900 li->untagged = srb; 901 } 902 if (li->untagged != NULL) { 903 tag = 0; 904 if (li->busy != 1 && li->used == 0) { 905 /* we need to issue the untagged command now */ 906 srb = li->untagged; 907 periph = srb->xs->xs_periph; 908 } else { 909 /* not ready yet */ 910 splx(s); 911 continue; 912 } 913 } 914 srb->tag[0] = tag; 915 if (tag != 0) { 916 li->queued[srb->xs->xs_tag_id] = srb; 917 srb->tag[1] = srb->xs->xs_tag_id; 918 li->used++; 919 } 920 921 if (li->untagged != NULL && li->busy != 1) { 922 li->busy = 1; 923 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 924 sc->sc_actsrb = srb; 925 trm_select(sc, srb); 926 splx(s); 927 break; 928 } 929 if (li->untagged == NULL && tag != 0) { 930 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 931 sc->sc_actsrb = srb; 932 trm_select(sc, srb); 933 splx(s); 934 break; 935 } else 936 splx(s); 937 } 938 } 939 940 static int 941 trm_select(struct trm_softc *sc, struct trm_srb *srb) 942 { 943 bus_space_tag_t iot = sc->sc_iot; 944 bus_space_handle_t ioh = sc->sc_ioh; 945 struct scsipi_periph *periph = srb->xs->xs_periph; 946 int target = periph->periph_target; 947 int lun = periph->periph_lun; 948 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 949 uint8_t scsicmd; 950 951 DPRINTF(("trm_select.....\n")); 952 953 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 954 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 955 trm_timeout, srb); 956 } 957 958 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 959 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 960 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 961 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 962 /* Flush FIFO */ 963 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 964 DELAY(10); 965 966 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 967 968 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 969 970 if (((ti->flag & WIDE_NEGO_ENABLE) && 971 (ti->flag & WIDE_NEGO_DONE) == 0) || 972 ((ti->flag & SYNC_NEGO_ENABLE) && 973 (ti->flag & SYNC_NEGO_DONE) == 0)) { 974 sc->sc_state = TRM_MSGOUT; 975 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 976 MSG_IDENTIFY(lun, 0)); 977 bus_space_write_multi_1(iot, ioh, 978 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 979 /* it's important for atn stop */ 980 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 981 DO_DATALATCH | DO_HWRESELECT); 982 /* SCSI command */ 983 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 984 DPRINTF(("select with SEL_ATNSTOP\n")); 985 return (0); 986 } 987 988 if (srb->tag[0] != 0) { 989 /* Send identify message */ 990 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 991 MSG_IDENTIFY(lun, 1)); 992 /* Send Tag id */ 993 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 994 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 995 scsicmd = SCMD_SEL_ATN3; 996 DPRINTF(("select with SEL_ATN3\n")); 997 } else { 998 /* Send identify message */ 999 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1000 MSG_IDENTIFY(lun, 1001 (ti->flag & NO_RESELECT) == 0 && 1002 (srb->flag & AUTO_REQSENSE) == 0 && 1003 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1004 scsicmd = SCMD_SEL_ATN; 1005 DPRINTF(("select with SEL_ATN\n")); 1006 } 1007 sc->sc_state = TRM_START; 1008 1009 /* 1010 * Send CDB ..command block... 1011 */ 1012 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1013 1014 /* 1015 * If trm_select returns 0: current interrupt status 1016 * is interrupt enable. It's said that SCSI processor is 1017 * unoccupied. 1018 */ 1019 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1020 /* SCSI command */ 1021 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1022 return (0); 1023 } 1024 1025 /* 1026 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1027 */ 1028 static void 1029 trm_reset(struct trm_softc *sc) 1030 { 1031 bus_space_tag_t iot = sc->sc_iot; 1032 bus_space_handle_t ioh = sc->sc_ioh; 1033 int s; 1034 1035 DPRINTF(("trm_reset.........\n")); 1036 1037 s = splbio(); 1038 1039 /* disable SCSI and DMA interrupt */ 1040 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1041 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1042 1043 trm_reset_scsi_bus(sc); 1044 DELAY(100000); 1045 1046 /* Enable SCSI interrupt */ 1047 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1048 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1049 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1050 1051 /* Enable DMA interrupt */ 1052 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1053 1054 /* Clear DMA FIFO */ 1055 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1056 1057 /* Clear SCSI FIFO */ 1058 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1059 1060 sc->sc_actsrb = NULL; 1061 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1062 1063 splx(s); 1064 } 1065 1066 static void 1067 trm_timeout(void *arg) 1068 { 1069 struct trm_srb *srb = (struct trm_srb *)arg; 1070 struct scsipi_xfer *xs = srb->xs; 1071 struct scsipi_periph *periph = xs->xs_periph; 1072 struct trm_softc *sc; 1073 int s; 1074 1075 if (xs == NULL) 1076 printf("trm_timeout called with xs == NULL\n"); 1077 1078 else { 1079 scsipi_printaddr(xs->xs_periph); 1080 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1081 } 1082 1083 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1084 1085 trm_reset_scsi_bus(sc); 1086 s = splbio(); 1087 srb->flag |= SRB_TIMEOUT; 1088 trm_done(sc, srb); 1089 /* XXX needs more.. */ 1090 splx(s); 1091 } 1092 1093 /* 1094 * Catch an interrupt from the adapter 1095 * Process pending device interrupts. 1096 */ 1097 static int 1098 trm_intr(void *arg) 1099 { 1100 bus_space_tag_t iot; 1101 bus_space_handle_t ioh; 1102 struct trm_softc *sc; 1103 int intstat, stat; 1104 1105 DPRINTF(("trm_intr......\n")); 1106 sc = (struct trm_softc *)arg; 1107 if (sc == NULL) 1108 return (0); 1109 1110 iot = sc->sc_iot; 1111 ioh = sc->sc_ioh; 1112 1113 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1114 if ((stat & SCSIINTERRUPT) == 0) 1115 return (0); 1116 1117 DPRINTF(("stat = %04x, ", stat)); 1118 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1119 1120 DPRINTF(("intstat=%02x, ", intstat)); 1121 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1122 DPRINTF(("\n")); 1123 trm_disconnect(sc); 1124 return (1); 1125 } 1126 if (intstat & INT_RESELECTED) { 1127 DPRINTF(("\n")); 1128 trm_reselect(sc); 1129 return (1); 1130 } 1131 if (intstat & INT_SCSIRESET) { 1132 DPRINTF(("\n")); 1133 trm_scsi_reset_detect(sc); 1134 return (1); 1135 } 1136 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1137 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1138 sc->sc_phase, sc->sc_state)); 1139 /* 1140 * software sequential machine 1141 */ 1142 1143 /* 1144 * call phase0 functions... "phase entry" handle 1145 * every phase before start transfer 1146 */ 1147 switch (sc->sc_phase) { 1148 case PH_DATA_OUT: 1149 trm_dataout_phase0(sc, stat); 1150 break; 1151 case PH_DATA_IN: 1152 trm_datain_phase0(sc, stat); 1153 break; 1154 case PH_COMMAND: 1155 break; 1156 case PH_STATUS: 1157 trm_status_phase0(sc); 1158 stat = PH_BUS_FREE; 1159 break; 1160 case PH_MSG_OUT: 1161 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1162 sc->sc_state == TRM_ABORT_SENT) 1163 stat = PH_BUS_FREE; 1164 break; 1165 case PH_MSG_IN: 1166 trm_msgin_phase0(sc); 1167 stat = PH_BUS_FREE; 1168 break; 1169 case PH_BUS_FREE: 1170 break; 1171 default: 1172 printf("%s: unexpected phase in trm_intr() phase0\n", 1173 sc->sc_dev.dv_xname); 1174 break; 1175 } 1176 1177 sc->sc_phase = stat & PHASEMASK; 1178 1179 switch (sc->sc_phase) { 1180 case PH_DATA_OUT: 1181 trm_dataio_xfer(sc, XFERDATAOUT); 1182 break; 1183 case PH_DATA_IN: 1184 trm_dataio_xfer(sc, XFERDATAIN); 1185 break; 1186 case PH_COMMAND: 1187 trm_command_phase1(sc); 1188 break; 1189 case PH_STATUS: 1190 trm_status_phase1(sc); 1191 break; 1192 case PH_MSG_OUT: 1193 trm_msgout_phase1(sc); 1194 break; 1195 case PH_MSG_IN: 1196 trm_msgin_phase1(sc); 1197 break; 1198 case PH_BUS_FREE: 1199 break; 1200 default: 1201 printf("%s: unexpected phase in trm_intr() phase1\n", 1202 sc->sc_dev.dv_xname); 1203 break; 1204 } 1205 1206 return (1); 1207 } 1208 return (0); 1209 } 1210 1211 static void 1212 trm_msgout_phase1(struct trm_softc *sc) 1213 { 1214 bus_space_tag_t iot = sc->sc_iot; 1215 bus_space_handle_t ioh = sc->sc_ioh; 1216 struct trm_srb *srb; 1217 struct scsipi_periph *periph; 1218 struct trm_tinfo *ti; 1219 1220 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1221 1222 srb = sc->sc_actsrb; 1223 1224 /* message out phase */ 1225 if (srb != NULL) { 1226 periph = srb->xs->xs_periph; 1227 ti = &sc->sc_tinfo[periph->periph_target]; 1228 1229 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1230 (ti->flag & WIDE_NEGO_ENABLE)) { 1231 /* send WDTR */ 1232 ti->flag &= ~SYNC_NEGO_DONE; 1233 1234 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1235 sc->sc_msgbuf[1] = MSG_EXTENDED; 1236 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1237 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1238 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1239 sc->sc_msgcnt = 5; 1240 1241 ti->flag |= WIDE_NEGO_DOING; 1242 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1243 (ti->flag & SYNC_NEGO_ENABLE)) { 1244 /* send SDTR */ 1245 int cnt = 0; 1246 1247 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1248 sc->sc_msgbuf[cnt++] = 1249 MSG_IDENTIFY(periph->periph_lun, 0); 1250 1251 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1252 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1253 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1254 sc->sc_msgbuf[cnt++] = ti->period; 1255 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1256 sc->sc_msgcnt = cnt; 1257 ti->flag |= SYNC_NEGO_DOING; 1258 } 1259 } 1260 if (sc->sc_msgcnt == 0) { 1261 sc->sc_msgbuf[0] = MSG_ABORT; 1262 sc->sc_msgcnt = 1; 1263 sc->sc_state = TRM_ABORT_SENT; 1264 } 1265 1266 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1267 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1268 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1269 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1270 1271 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1272 sc->sc_msgbuf, sc->sc_msgcnt); 1273 sc->sc_msgcnt = 0; 1274 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1275 1276 /* it's important for atn stop */ 1277 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1278 1279 /* 1280 * SCSI command 1281 */ 1282 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1283 } 1284 1285 static void 1286 trm_command_phase1(struct trm_softc *sc) 1287 { 1288 bus_space_tag_t iot = sc->sc_iot; 1289 bus_space_handle_t ioh = sc->sc_ioh; 1290 struct trm_srb *srb; 1291 1292 srb = sc->sc_actsrb; 1293 if (srb == NULL) { 1294 DPRINTF(("trm_command_phase1: no active srb\n")); 1295 return; 1296 } 1297 1298 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1299 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1300 1301 sc->sc_state = TRM_COMMAND; 1302 /* it's important for atn stop */ 1303 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1304 1305 /* 1306 * SCSI command 1307 */ 1308 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1309 } 1310 1311 static void 1312 trm_dataout_phase0(struct trm_softc *sc, int stat) 1313 { 1314 bus_space_tag_t iot = sc->sc_iot; 1315 bus_space_handle_t ioh = sc->sc_ioh; 1316 struct trm_srb *srb; 1317 struct scsipi_periph *periph; 1318 struct trm_tinfo *ti; 1319 struct trm_sg_entry *sg; 1320 int sgindex; 1321 uint32_t xferlen, leftcnt = 0; 1322 1323 if (sc->sc_state == TRM_XFERPAD) 1324 return; 1325 1326 srb = sc->sc_actsrb; 1327 if (srb == NULL) { 1328 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1329 return; 1330 } 1331 periph = srb->xs->xs_periph; 1332 ti = &sc->sc_tinfo[periph->periph_target]; 1333 1334 if ((stat & PARITYERROR) != 0) 1335 srb->flag |= PARITY_ERROR; 1336 1337 if ((stat & SCSIXFERDONE) == 0) { 1338 /* 1339 * when data transfer from DMA FIFO to SCSI FIFO 1340 * if there was some data left in SCSI FIFO 1341 */ 1342 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1343 SCSI_FIFOCNT_MASK; 1344 if (ti->synctl & WIDE_SYNC) 1345 /* 1346 * if WIDE scsi SCSI FIFOCNT unit is word 1347 * so need to * 2 1348 */ 1349 leftcnt <<= 1; 1350 } 1351 /* 1352 * calculate all the residue data that was not yet transferred 1353 * SCSI transfer counter + left in SCSI FIFO data 1354 * 1355 * .....TRM_SCSI_XCNT (24bits) 1356 * The counter always decrements by one for every SCSI 1357 * byte transfer. 1358 * .....TRM_SCSI_FIFOCNT ( 5bits) 1359 * The counter is SCSI FIFO offset counter 1360 */ 1361 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1362 if (leftcnt == 1) { 1363 leftcnt = 0; 1364 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1365 } 1366 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1367 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1368 DMAXFERCOMP) == 0) 1369 ; /* XXX needs timeout */ 1370 1371 srb->buflen = 0; 1372 } else { 1373 /* Update SG list */ 1374 1375 /* 1376 * if transfer not yet complete 1377 * there were some data residue in SCSI FIFO or 1378 * SCSI transfer counter not empty 1379 */ 1380 if (srb->buflen != leftcnt) { 1381 /* data that had transferred length */ 1382 xferlen = srb->buflen - leftcnt; 1383 1384 /* next time to be transferred length */ 1385 srb->buflen = leftcnt; 1386 1387 /* 1388 * parsing from last time disconnect sgindex 1389 */ 1390 sg = srb->sgentry + srb->sgindex; 1391 for (sgindex = srb->sgindex; 1392 sgindex < srb->sgcnt; 1393 sgindex++, sg++) { 1394 /* 1395 * find last time which SG transfer 1396 * be disconnect 1397 */ 1398 if (xferlen >= le32toh(sg->length)) 1399 xferlen -= le32toh(sg->length); 1400 else { 1401 /* 1402 * update last time 1403 * disconnected SG list 1404 */ 1405 /* residue data length */ 1406 sg->length = 1407 htole32(le32toh(sg->length) 1408 - xferlen); 1409 /* residue data pointer */ 1410 sg->address = 1411 htole32(le32toh(sg->address) 1412 + xferlen); 1413 srb->sgindex = sgindex; 1414 break; 1415 } 1416 } 1417 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1418 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1419 } 1420 } 1421 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1422 } 1423 1424 static void 1425 trm_datain_phase0(struct trm_softc *sc, int stat) 1426 { 1427 bus_space_tag_t iot = sc->sc_iot; 1428 bus_space_handle_t ioh = sc->sc_ioh; 1429 struct trm_srb *srb; 1430 struct trm_sg_entry *sg; 1431 int sgindex; 1432 uint32_t xferlen, leftcnt = 0; 1433 1434 if (sc->sc_state == TRM_XFERPAD) 1435 return; 1436 1437 srb = sc->sc_actsrb; 1438 if (srb == NULL) { 1439 DPRINTF(("trm_datain_phase0: no active srb\n")); 1440 return; 1441 } 1442 1443 if (stat & PARITYERROR) 1444 srb->flag |= PARITY_ERROR; 1445 1446 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1447 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1448 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1449 DMAXFERCOMP) == 0) 1450 ; /* XXX needs timeout */ 1451 1452 srb->buflen = 0; 1453 } else { /* phase changed */ 1454 /* 1455 * parsing the case: 1456 * when a transfer not yet complete 1457 * but be disconnected by upper layer 1458 * if transfer not yet complete 1459 * there were some data residue in SCSI FIFO or 1460 * SCSI transfer counter not empty 1461 */ 1462 if (srb->buflen != leftcnt) { 1463 /* 1464 * data that had transferred length 1465 */ 1466 xferlen = srb->buflen - leftcnt; 1467 1468 /* 1469 * next time to be transferred length 1470 */ 1471 srb->buflen = leftcnt; 1472 1473 /* 1474 * parsing from last time disconnect sgindex 1475 */ 1476 sg = srb->sgentry + srb->sgindex; 1477 for (sgindex = srb->sgindex; 1478 sgindex < srb->sgcnt; 1479 sgindex++, sg++) { 1480 /* 1481 * find last time which SG transfer 1482 * be disconnect 1483 */ 1484 if (xferlen >= le32toh(sg->length)) 1485 xferlen -= le32toh(sg->length); 1486 else { 1487 /* 1488 * update last time 1489 * disconnected SG list 1490 */ 1491 /* residue data length */ 1492 sg->length = 1493 htole32(le32toh(sg->length) 1494 - xferlen); 1495 /* residue data pointer */ 1496 sg->address = 1497 htole32(le32toh(sg->address) 1498 + xferlen); 1499 srb->sgindex = sgindex; 1500 break; 1501 } 1502 } 1503 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1504 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1505 } 1506 } 1507 } 1508 1509 static void 1510 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1511 { 1512 bus_space_tag_t iot = sc->sc_iot; 1513 bus_space_handle_t ioh = sc->sc_ioh; 1514 struct trm_srb *srb; 1515 struct scsipi_periph *periph; 1516 struct trm_tinfo *ti; 1517 1518 srb = sc->sc_actsrb; 1519 if (srb == NULL) { 1520 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1521 return; 1522 } 1523 periph = srb->xs->xs_periph; 1524 ti = &sc->sc_tinfo[periph->periph_target]; 1525 1526 if (srb->sgindex < srb->sgcnt) { 1527 if (srb->buflen > 0) { 1528 /* 1529 * load what physical address of Scatter/Gather 1530 * list table want to be transfer 1531 */ 1532 sc->sc_state = TRM_DATA_XFER; 1533 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1534 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1535 srb->sgaddr + 1536 srb->sgindex * sizeof(struct trm_sg_entry)); 1537 /* 1538 * load how many bytes in the Scatter/Gather list table 1539 */ 1540 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1541 (srb->sgcnt - srb->sgindex) 1542 * sizeof(struct trm_sg_entry)); 1543 /* 1544 * load total xfer length (24bits) max value 16Mbyte 1545 */ 1546 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1547 /* Start DMA transfer */ 1548 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1549 iodir | SGXFER); 1550 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1551 STARTDMAXFER); 1552 1553 /* Start SCSI transfer */ 1554 /* it's important for atn stop */ 1555 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1556 DO_DATALATCH); 1557 1558 /* 1559 * SCSI command 1560 */ 1561 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1562 (iodir == XFERDATAOUT) ? 1563 SCMD_DMA_OUT : SCMD_DMA_IN); 1564 } else { /* xfer pad */ 1565 if (srb->sgcnt) { 1566 srb->hastat = H_OVER_UNDER_RUN; 1567 } 1568 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1569 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1570 1571 if (iodir == XFERDATAOUT) 1572 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1573 else 1574 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1575 1576 sc->sc_state = TRM_XFERPAD; 1577 /* it's important for atn stop */ 1578 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1579 DO_DATALATCH); 1580 1581 /* 1582 * SCSI command 1583 */ 1584 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1585 (iodir == XFERDATAOUT) ? 1586 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1587 } 1588 } 1589 } 1590 1591 static void 1592 trm_status_phase0(struct trm_softc *sc) 1593 { 1594 bus_space_tag_t iot = sc->sc_iot; 1595 bus_space_handle_t ioh = sc->sc_ioh; 1596 struct trm_srb *srb; 1597 1598 srb = sc->sc_actsrb; 1599 if (srb == NULL) { 1600 DPRINTF(("trm_status_phase0: no active srb\n")); 1601 return; 1602 } 1603 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1604 sc->sc_state = TRM_COMPLETED; 1605 /* it's important for atn stop */ 1606 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1607 1608 /* 1609 * SCSI command 1610 */ 1611 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1612 } 1613 1614 static void 1615 trm_status_phase1(struct trm_softc *sc) 1616 { 1617 bus_space_tag_t iot = sc->sc_iot; 1618 bus_space_handle_t ioh = sc->sc_ioh; 1619 1620 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1621 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1622 & SCSI_FIFO_EMPTY) == 0) 1623 bus_space_write_2(iot, ioh, 1624 TRM_SCSI_CONTROL, DO_CLRFIFO); 1625 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1626 & DMA_FIFO_EMPTY) == 0) 1627 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1628 } else { 1629 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1630 & DMA_FIFO_EMPTY) == 0) 1631 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1632 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1633 & SCSI_FIFO_EMPTY) == 0) 1634 bus_space_write_2(iot, ioh, 1635 TRM_SCSI_CONTROL, DO_CLRFIFO); 1636 } 1637 sc->sc_state = TRM_STATUS; 1638 /* it's important for atn stop */ 1639 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1640 1641 /* 1642 * SCSI command 1643 */ 1644 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1645 } 1646 1647 static void 1648 trm_msgin_phase0(struct trm_softc *sc) 1649 { 1650 bus_space_tag_t iot = sc->sc_iot; 1651 bus_space_handle_t ioh = sc->sc_ioh; 1652 struct trm_srb *srb; 1653 struct scsipi_periph *periph; 1654 struct trm_tinfo *ti; 1655 int index; 1656 uint8_t msgin_code; 1657 1658 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1659 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1660 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1661 switch (msgin_code) { 1662 case MSG_DISCONNECT: 1663 sc->sc_state = TRM_DISCONNECTED; 1664 break; 1665 1666 case MSG_SAVEDATAPOINTER: 1667 break; 1668 1669 case MSG_EXTENDED: 1670 case MSG_SIMPLE_Q_TAG: 1671 case MSG_HEAD_OF_Q_TAG: 1672 case MSG_ORDERED_Q_TAG: 1673 sc->sc_state = TRM_EXTEND_MSGIN; 1674 /* extended message (01h) */ 1675 sc->sc_msgbuf[0] = msgin_code; 1676 1677 sc->sc_msgcnt = 1; 1678 /* extended message length (n) */ 1679 sc->sc_msg = &sc->sc_msgbuf[1]; 1680 1681 break; 1682 case MSG_MESSAGE_REJECT: 1683 /* Reject message */ 1684 srb = sc->sc_actsrb; 1685 if (srb == NULL) { 1686 DPRINTF(("trm_msgin_phase0: " 1687 " message reject without actsrb\n")); 1688 break; 1689 } 1690 periph = srb->xs->xs_periph; 1691 ti = &sc->sc_tinfo[periph->periph_target]; 1692 1693 if (ti->flag & WIDE_NEGO_ENABLE) { 1694 /* do wide nego reject */ 1695 ti->flag |= WIDE_NEGO_DONE; 1696 ti->flag &= 1697 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1698 if ((ti->flag & SYNC_NEGO_ENABLE) && 1699 (ti->flag & SYNC_NEGO_DONE) == 0) { 1700 /* Set ATN, in case ATN was clear */ 1701 sc->sc_state = TRM_MSGOUT; 1702 bus_space_write_2(iot, ioh, 1703 TRM_SCSI_CONTROL, DO_SETATN); 1704 } else 1705 /* Clear ATN */ 1706 bus_space_write_2(iot, ioh, 1707 TRM_SCSI_CONTROL, DO_CLRATN); 1708 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1709 /* do sync nego reject */ 1710 bus_space_write_2(iot, ioh, 1711 TRM_SCSI_CONTROL, DO_CLRATN); 1712 if (ti->flag & SYNC_NEGO_DOING) { 1713 ti->flag &=~(SYNC_NEGO_ENABLE | 1714 SYNC_NEGO_DONE); 1715 ti->synctl = 0; 1716 ti->offset = 0; 1717 bus_space_write_1(iot, ioh, 1718 TRM_SCSI_SYNC, ti->synctl); 1719 bus_space_write_1(iot, ioh, 1720 TRM_SCSI_OFFSET, ti->offset); 1721 } 1722 } 1723 break; 1724 1725 case MSG_IGN_WIDE_RESIDUE: 1726 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1727 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1728 break; 1729 1730 default: 1731 /* 1732 * Restore data pointer message 1733 * Save data pointer message 1734 * Completion message 1735 * NOP message 1736 */ 1737 break; 1738 } 1739 } else { 1740 /* 1741 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1742 * Parsing incoming extented messages 1743 */ 1744 *sc->sc_msg++ = msgin_code; 1745 sc->sc_msgcnt++; 1746 1747 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1748 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1749 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1750 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1751 1752 switch (sc->sc_msgbuf[0]) { 1753 case MSG_SIMPLE_Q_TAG: 1754 case MSG_HEAD_OF_Q_TAG: 1755 case MSG_ORDERED_Q_TAG: 1756 /* 1757 * is QUEUE tag message : 1758 * 1759 * byte 0: 1760 * HEAD QUEUE TAG (20h) 1761 * ORDERED QUEUE TAG (21h) 1762 * SIMPLE QUEUE TAG (22h) 1763 * byte 1: 1764 * Queue tag (00h - FFh) 1765 */ 1766 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1767 /* XXX XXX XXX */ 1768 struct trm_linfo *li; 1769 int tagid; 1770 1771 sc->sc_flag &= ~WAIT_TAGMSG; 1772 tagid = sc->sc_msgbuf[1]; 1773 ti = &sc->sc_tinfo[sc->resel_target]; 1774 li = ti->linfo[sc->resel_lun]; 1775 srb = li->queued[tagid]; 1776 if (srb != NULL) { 1777 sc->sc_actsrb = srb; 1778 sc->sc_state = TRM_DATA_XFER; 1779 break; 1780 } else { 1781 printf("%s: invalid tag id\n", 1782 sc->sc_dev.dv_xname); 1783 } 1784 1785 sc->sc_state = TRM_UNEXPECT_RESEL; 1786 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1787 sc->sc_msgcnt = 1; 1788 bus_space_write_2(iot, ioh, 1789 TRM_SCSI_CONTROL, DO_SETATN); 1790 } else 1791 sc->sc_state = TRM_IDLE; 1792 break; 1793 1794 case MSG_EXTENDED: 1795 srb = sc->sc_actsrb; 1796 if (srb == NULL) { 1797 DPRINTF(("trm_msgin_phase0: " 1798 "extended message without actsrb\n")); 1799 break; 1800 } 1801 periph = srb->xs->xs_periph; 1802 ti = &sc->sc_tinfo[periph->periph_target]; 1803 1804 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1805 sc->sc_msgcnt == 4) { 1806 /* 1807 * is Wide data xfer Extended message : 1808 * ====================================== 1809 * WIDE DATA TRANSFER REQUEST 1810 * ====================================== 1811 * byte 0 : Extended message (01h) 1812 * byte 1 : Extended message length (02h) 1813 * byte 2 : WIDE DATA TRANSFER code (03h) 1814 * byte 3 : Transfer width exponent 1815 */ 1816 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1817 /* Length is wrong, reject it */ 1818 ti->flag &= ~(WIDE_NEGO_ENABLE | 1819 WIDE_NEGO_DONE); 1820 sc->sc_state = TRM_MSGOUT; 1821 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1822 sc->sc_msgcnt = 1; 1823 bus_space_write_2(iot, ioh, 1824 TRM_SCSI_CONTROL, DO_SETATN); 1825 break; 1826 } 1827 1828 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1829 sc->sc_msgbuf[3] = 1830 MSG_EXT_WDTR_BUS_8_BIT; 1831 1832 if (sc->sc_msgbuf[3] > 1833 MSG_EXT_WDTR_BUS_32_BIT) { 1834 /* reject_msg: */ 1835 ti->flag &= ~(WIDE_NEGO_ENABLE | 1836 WIDE_NEGO_DONE); 1837 sc->sc_state = TRM_MSGOUT; 1838 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1839 sc->sc_msgcnt = 1; 1840 bus_space_write_2(iot, ioh, 1841 TRM_SCSI_CONTROL, DO_SETATN); 1842 break; 1843 } 1844 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1845 /* do 16 bits */ 1846 sc->sc_msgbuf[3] = 1847 MSG_EXT_WDTR_BUS_16_BIT; 1848 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1849 ti->flag |= WIDE_NEGO_DONE; 1850 ti->flag &= ~(SYNC_NEGO_DONE | 1851 WIDE_NEGO_ENABLE); 1852 if (sc->sc_msgbuf[3] != 1853 MSG_EXT_WDTR_BUS_8_BIT) 1854 /* is Wide data xfer */ 1855 ti->synctl |= WIDE_SYNC; 1856 trm_update_xfer_mode(sc, 1857 periph->periph_target); 1858 } 1859 1860 sc->sc_state = TRM_MSGOUT; 1861 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1862 DO_SETATN); 1863 break; 1864 1865 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1866 sc->sc_msgcnt == 5) { 1867 /* 1868 * is 8bit transfer Extended message : 1869 * ================================= 1870 * SYNCHRONOUS DATA TRANSFER REQUEST 1871 * ================================= 1872 * byte 0 : Extended message (01h) 1873 * byte 1 : Extended message length (03) 1874 * byte 2 : SYNC DATA TRANSFER code (01h) 1875 * byte 3 : Transfer period factor 1876 * byte 4 : REQ/ACK offset 1877 */ 1878 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1879 /* reject_msg */ 1880 sc->sc_state = TRM_MSGOUT; 1881 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1882 sc->sc_msgcnt = 1; 1883 bus_space_write_2(iot, ioh, 1884 TRM_SCSI_CONTROL, DO_SETATN); 1885 break; 1886 } 1887 1888 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1889 ti->flag &= 1890 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1891 ti->flag |= SYNC_NEGO_DONE; 1892 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1893 sc->sc_msgbuf[3] = 0; 1894 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1895 sc->sc_msgbuf[4] = 1896 TRM_MAX_OFFSET; 1897 1898 if (sc->sc_msgbuf[3] == 0 || 1899 sc->sc_msgbuf[4] == 0) { 1900 /* set async */ 1901 ti->synctl = 0; 1902 ti->offset = 0; 1903 } else { 1904 /* set sync */ 1905 /* Transfer period factor */ 1906 ti->period = sc->sc_msgbuf[3]; 1907 /* REQ/ACK offset */ 1908 ti->offset = sc->sc_msgbuf[4]; 1909 for (index = 0; 1910 index < NPERIOD; 1911 index++) 1912 if (ti->period <= 1913 trm_clock_period[ 1914 index]) 1915 break; 1916 1917 ti->synctl |= ALT_SYNC | index; 1918 } 1919 /* 1920 * program SCSI control register 1921 */ 1922 bus_space_write_1(iot, ioh, 1923 TRM_SCSI_SYNC, ti->synctl); 1924 bus_space_write_1(iot, ioh, 1925 TRM_SCSI_OFFSET, ti->offset); 1926 trm_update_xfer_mode(sc, 1927 periph->periph_target); 1928 } 1929 sc->sc_state = TRM_IDLE; 1930 } 1931 break; 1932 default: 1933 break; 1934 } 1935 } 1936 1937 /* it's important for atn stop */ 1938 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1939 1940 /* 1941 * SCSI command 1942 */ 1943 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1944 } 1945 1946 static void 1947 trm_msgin_phase1(struct trm_softc *sc) 1948 { 1949 bus_space_tag_t iot = sc->sc_iot; 1950 bus_space_handle_t ioh = sc->sc_ioh; 1951 1952 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1953 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1954 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1955 sc->sc_state = TRM_MSGIN; 1956 } 1957 1958 /* it's important for atn stop */ 1959 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1960 1961 /* 1962 * SCSI command 1963 */ 1964 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1965 } 1966 1967 static void 1968 trm_disconnect(struct trm_softc *sc) 1969 { 1970 bus_space_tag_t iot = sc->sc_iot; 1971 bus_space_handle_t ioh = sc->sc_ioh; 1972 struct trm_srb *srb; 1973 int s; 1974 1975 s = splbio(); 1976 1977 srb = sc->sc_actsrb; 1978 DPRINTF(("trm_disconnect...............\n")); 1979 1980 if (srb == NULL) { 1981 DPRINTF(("trm_disconnect: no active srb\n")); 1982 DELAY(1000); /* 1 msec */ 1983 1984 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1985 DO_CLRFIFO | DO_HWRESELECT); 1986 return; 1987 } 1988 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1989 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1990 DO_CLRFIFO | DO_HWRESELECT); 1991 DELAY(100); 1992 1993 switch (sc->sc_state) { 1994 case TRM_UNEXPECT_RESEL: 1995 sc->sc_state = TRM_IDLE; 1996 break; 1997 1998 case TRM_ABORT_SENT: 1999 goto finish; 2000 2001 case TRM_START: 2002 case TRM_MSGOUT: 2003 { 2004 /* Selection time out - discard all LUNs if empty */ 2005 struct scsipi_periph *periph; 2006 struct trm_tinfo *ti; 2007 struct trm_linfo *li; 2008 int lun; 2009 2010 DPRINTF(("selection timeout\n")); 2011 2012 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2013 2014 periph = srb->xs->xs_periph; 2015 ti = &sc->sc_tinfo[periph->periph_target]; 2016 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2017 li = ti->linfo[lun]; 2018 if (li != NULL && 2019 li->untagged == NULL && li->used == 0) { 2020 ti->linfo[lun] = NULL; 2021 free(li, M_DEVBUF); 2022 } 2023 } 2024 } 2025 goto finish; 2026 2027 case TRM_DISCONNECTED: 2028 sc->sc_actsrb = NULL; 2029 sc->sc_state = TRM_IDLE; 2030 goto sched; 2031 2032 case TRM_COMPLETED: 2033 goto finish; 2034 } 2035 2036 out: 2037 splx(s); 2038 return; 2039 2040 finish: 2041 sc->sc_state = TRM_IDLE; 2042 trm_done(sc, srb); 2043 goto out; 2044 2045 sched: 2046 trm_sched(sc); 2047 goto out; 2048 } 2049 2050 static void 2051 trm_reselect(struct trm_softc *sc) 2052 { 2053 bus_space_tag_t iot = sc->sc_iot; 2054 bus_space_handle_t ioh = sc->sc_ioh; 2055 struct trm_tinfo *ti; 2056 struct trm_linfo *li; 2057 int target, lun; 2058 2059 DPRINTF(("trm_reselect.................\n")); 2060 2061 if (sc->sc_actsrb != NULL) { 2062 /* arbitration lost but reselection win */ 2063 sc->sc_state = TRM_READY; 2064 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2065 ti = &sc->sc_tinfo[target]; 2066 } else { 2067 /* Read Reselected Target Id and LUN */ 2068 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2069 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2070 ti = &sc->sc_tinfo[target]; 2071 li = ti->linfo[lun]; 2072 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2073 2074 /* 2075 * Check to see if we are running an un-tagged command. 2076 * Otherwise ack the IDENTIFY and wait for a tag message. 2077 */ 2078 if (li != NULL) { 2079 if (li->untagged != NULL && li->busy) { 2080 sc->sc_actsrb = li->untagged; 2081 sc->sc_state = TRM_DATA_XFER; 2082 } else { 2083 sc->resel_target = target; 2084 sc->resel_lun = lun; 2085 /* XXX XXX XXX */ 2086 sc->sc_flag |= WAIT_TAGMSG; 2087 } 2088 } 2089 2090 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2091 sc->sc_actsrb == NULL) { 2092 printf("%s: reselect from target %d lun %d " 2093 "without nexus; sending abort\n", 2094 sc->sc_dev.dv_xname, target, lun); 2095 sc->sc_state = TRM_UNEXPECT_RESEL; 2096 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2097 sc->sc_msgcnt = 1; 2098 bus_space_write_2(iot, ioh, 2099 TRM_SCSI_CONTROL, DO_SETATN); 2100 } 2101 } 2102 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2103 /* 2104 * Program HA ID, target ID, period and offset 2105 */ 2106 /* target ID */ 2107 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2108 2109 /* host ID */ 2110 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2111 2112 /* period */ 2113 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2114 2115 /* offset */ 2116 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2117 2118 /* it's important for atn stop */ 2119 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2120 /* 2121 * SCSI command 2122 */ 2123 /* to rls the /ACK signal */ 2124 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2125 } 2126 2127 /* 2128 * Complete execution of a SCSI command 2129 * Signal completion to the generic SCSI driver 2130 */ 2131 static void 2132 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2133 { 2134 struct scsipi_xfer *xs = srb->xs; 2135 2136 DPRINTF(("trm_done..................\n")); 2137 2138 if (xs == NULL) 2139 return; 2140 2141 if ((xs->xs_control & XS_CTL_POLL) == 0) 2142 callout_stop(&xs->xs_callout); 2143 2144 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2145 srb->flag & AUTO_REQSENSE) { 2146 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2147 srb->dmap->dm_mapsize, 2148 ((xs->xs_control & XS_CTL_DATA_IN) || 2149 (srb->flag & AUTO_REQSENSE)) ? 2150 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2151 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2152 } 2153 2154 /* 2155 * target status 2156 */ 2157 xs->status = srb->tastat; 2158 2159 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2160 2161 switch (xs->status) { 2162 case SCSI_OK: 2163 /* 2164 * process initiator status...... 2165 * Adapter (initiator) status 2166 */ 2167 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2168 printf("%s: over/under run error\n", 2169 sc->sc_dev.dv_xname); 2170 srb->tastat = 0; 2171 /* Illegal length (over/under run) */ 2172 xs->error = XS_DRIVER_STUFFUP; 2173 } else if ((srb->flag & PARITY_ERROR) != 0) { 2174 printf("%s: parity error\n", 2175 sc->sc_dev.dv_xname); 2176 /* Driver failed to perform operation */ 2177 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2178 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2179 xs->resid = srb->buflen; 2180 xs->error = XS_TIMEOUT; 2181 } else { 2182 /* No error */ 2183 xs->resid = srb->buflen; 2184 srb->hastat = 0; 2185 if (srb->flag & AUTO_REQSENSE) { 2186 /* there is no error, (sense is invalid) */ 2187 xs->error = XS_SENSE; 2188 } else { 2189 srb->tastat = 0; 2190 xs->error = XS_NOERROR; 2191 } 2192 } 2193 break; 2194 2195 case SCSI_CHECK: 2196 if ((srb->flag & AUTO_REQSENSE) != 0 || 2197 trm_request_sense(sc, srb) != 0) { 2198 printf("%s: request sense failed\n", 2199 sc->sc_dev.dv_xname); 2200 xs->error = XS_DRIVER_STUFFUP; 2201 break; 2202 } 2203 xs->error = XS_SENSE; 2204 return; 2205 2206 case SCSI_SEL_TIMEOUT: 2207 srb->hastat = H_SEL_TIMEOUT; 2208 srb->tastat = 0; 2209 xs->error = XS_SELTIMEOUT; 2210 break; 2211 2212 case SCSI_QUEUE_FULL: 2213 case SCSI_BUSY: 2214 xs->error = XS_BUSY; 2215 break; 2216 2217 case SCSI_RESV_CONFLICT: 2218 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2219 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2220 xs->error = XS_BUSY; 2221 break; 2222 2223 default: 2224 srb->hastat = 0; 2225 printf("%s: trm_done(): unknown status = %02x\n", 2226 sc->sc_dev.dv_xname, xs->status); 2227 xs->error = XS_DRIVER_STUFFUP; 2228 break; 2229 } 2230 2231 trm_dequeue(sc, srb); 2232 if (srb == sc->sc_actsrb) { 2233 sc->sc_actsrb = NULL; 2234 trm_sched(sc); 2235 } 2236 2237 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2238 2239 /* Notify cmd done */ 2240 scsipi_done(xs); 2241 } 2242 2243 static int 2244 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2245 { 2246 struct scsipi_xfer *xs; 2247 struct scsipi_periph *periph; 2248 struct trm_tinfo *ti; 2249 struct trm_linfo *li; 2250 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2251 int error; 2252 2253 DPRINTF(("trm_request_sense...\n")); 2254 2255 xs = srb->xs; 2256 periph = xs->xs_periph; 2257 2258 srb->flag |= AUTO_REQSENSE; 2259 2260 /* Status of initiator/target */ 2261 srb->hastat = 0; 2262 srb->tastat = 0; 2263 2264 memset(ss, 0, sizeof(*ss)); 2265 ss->opcode = SCSI_REQUEST_SENSE; 2266 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2267 ss->length = sizeof(struct scsi_sense_data); 2268 2269 srb->buflen = sizeof(struct scsi_sense_data); 2270 srb->sgcnt = 1; 2271 srb->sgindex = 0; 2272 srb->cmdlen = sizeof(struct scsi_request_sense); 2273 2274 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2275 &xs->sense.scsi_sense, srb->buflen, NULL, 2276 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2277 return error; 2278 } 2279 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2280 srb->buflen, BUS_DMASYNC_PREREAD); 2281 2282 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2283 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2284 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2285 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2286 2287 ti = &sc->sc_tinfo[periph->periph_target]; 2288 li = ti->linfo[periph->periph_lun]; 2289 if (li->busy > 0) 2290 li->busy = 0; 2291 trm_dequeue(sc, srb); 2292 li->untagged = srb; /* must be executed first to fix C/A */ 2293 li->busy = 2; 2294 2295 if (srb == sc->sc_actsrb) 2296 trm_select(sc, srb); 2297 else { 2298 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2299 if (sc->sc_actsrb == NULL) 2300 trm_sched(sc); 2301 } 2302 return 0; 2303 } 2304 2305 static void 2306 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2307 { 2308 struct scsipi_periph *periph; 2309 struct trm_tinfo *ti; 2310 struct trm_linfo *li; 2311 2312 periph = srb->xs->xs_periph; 2313 ti = &sc->sc_tinfo[periph->periph_target]; 2314 li = ti->linfo[periph->periph_lun]; 2315 2316 if (li->untagged == srb) { 2317 li->busy = 0; 2318 li->untagged = NULL; 2319 } 2320 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2321 li->queued[srb->tag[1]] = NULL; 2322 li->used--; 2323 } 2324 } 2325 2326 static void 2327 trm_reset_scsi_bus(struct trm_softc *sc) 2328 { 2329 bus_space_tag_t iot = sc->sc_iot; 2330 bus_space_handle_t ioh = sc->sc_ioh; 2331 int timeout, s; 2332 2333 DPRINTF(("trm_reset_scsi_bus.........\n")); 2334 2335 s = splbio(); 2336 2337 sc->sc_flag |= RESET_DEV; 2338 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2339 for (timeout = 20000; timeout >= 0; timeout--) { 2340 DELAY(1); 2341 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2342 INT_SCSIRESET) == 0) 2343 break; 2344 } 2345 if (timeout == 0) 2346 printf(": scsibus reset timeout\n"); 2347 2348 splx(s); 2349 } 2350 2351 static void 2352 trm_scsi_reset_detect(struct trm_softc *sc) 2353 { 2354 bus_space_tag_t iot = sc->sc_iot; 2355 bus_space_handle_t ioh = sc->sc_ioh; 2356 int s; 2357 2358 DPRINTF(("trm_scsi_reset_detect...............\n")); 2359 DELAY(1000000); /* delay 1 sec */ 2360 2361 s = splbio(); 2362 2363 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2364 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2365 2366 if (sc->sc_flag & RESET_DEV) { 2367 sc->sc_flag |= RESET_DONE; 2368 } else { 2369 sc->sc_flag |= RESET_DETECT; 2370 sc->sc_actsrb = NULL; 2371 sc->sc_flag = 0; 2372 trm_sched(sc); 2373 } 2374 splx(s); 2375 } 2376 2377 /* 2378 * read seeprom 128 bytes to struct eeprom and check checksum. 2379 * If it is wrong, update with default value. 2380 */ 2381 static void 2382 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2383 { 2384 struct nvram_target *target; 2385 uint16_t *ep; 2386 uint16_t chksum; 2387 int i; 2388 2389 DPRINTF(("trm_check_eeprom......\n")); 2390 trm_eeprom_read_all(sc, eeprom); 2391 ep = (uint16_t *)eeprom; 2392 chksum = 0; 2393 for (i = 0; i < 64; i++) 2394 chksum += le16toh(*ep++); 2395 2396 if (chksum != TRM_NVRAM_CKSUM) { 2397 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2398 /* 2399 * Checksum error, load default 2400 */ 2401 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2402 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2403 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2404 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2405 eeprom->subclass = 0x00; 2406 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2407 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2408 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2409 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2410 eeprom->reserved0 = 0x00; 2411 2412 for (i = 0, target = eeprom->target; 2413 i < TRM_MAX_TARGETS; 2414 i++, target++) { 2415 target->config0 = 0x77; 2416 target->period = 0x00; 2417 target->config2 = 0x00; 2418 target->config3 = 0x00; 2419 } 2420 2421 eeprom->scsi_id = 7; 2422 eeprom->channel_cfg = 0x0F; 2423 eeprom->delay_time = 0; 2424 eeprom->max_tag = 4; 2425 eeprom->reserved1 = 0x15; 2426 eeprom->boot_target = 0; 2427 eeprom->boot_lun = 0; 2428 eeprom->reserved2 = 0; 2429 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2430 2431 chksum = 0; 2432 ep = (uint16_t *)eeprom; 2433 for (i = 0; i < 63; i++) 2434 chksum += le16toh(*ep++); 2435 2436 chksum = TRM_NVRAM_CKSUM - chksum; 2437 eeprom->checksum0 = chksum & 0xFF; 2438 eeprom->checksum1 = chksum >> 8; 2439 2440 trm_eeprom_write_all(sc, eeprom); 2441 } 2442 } 2443 2444 /* 2445 * write struct eeprom 128 bytes to seeprom 2446 */ 2447 static void 2448 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2449 { 2450 bus_space_tag_t iot = sc->sc_iot; 2451 bus_space_handle_t ioh = sc->sc_ioh; 2452 uint8_t *buf = (uint8_t *)eeprom; 2453 uint8_t addr; 2454 2455 /* Enable SEEPROM */ 2456 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2457 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2458 2459 /* 2460 * Write enable 2461 */ 2462 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2463 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2464 trm_eeprom_wait(); 2465 2466 for (addr = 0; addr < 128; addr++, buf++) 2467 trm_eeprom_set_data(sc, addr, *buf); 2468 2469 /* 2470 * Write disable 2471 */ 2472 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2473 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2474 trm_eeprom_wait(); 2475 2476 /* Disable SEEPROM */ 2477 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2478 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2479 } 2480 2481 /* 2482 * write one byte to seeprom 2483 */ 2484 static void 2485 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2486 { 2487 bus_space_tag_t iot = sc->sc_iot; 2488 bus_space_handle_t ioh = sc->sc_ioh; 2489 int i; 2490 uint8_t send; 2491 2492 /* 2493 * Send write command & address 2494 */ 2495 trm_eeprom_write_cmd(sc, 0x05, addr); 2496 /* 2497 * Write data 2498 */ 2499 for (i = 0; i < 8; i++, data <<= 1) { 2500 send = NVR_SELECT; 2501 if (data & 0x80) /* Start from bit 7 */ 2502 send |= NVR_BITOUT; 2503 2504 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2505 trm_eeprom_wait(); 2506 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2507 trm_eeprom_wait(); 2508 } 2509 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2510 trm_eeprom_wait(); 2511 /* 2512 * Disable chip select 2513 */ 2514 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2515 trm_eeprom_wait(); 2516 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2517 trm_eeprom_wait(); 2518 /* 2519 * Wait for write ready 2520 */ 2521 for (;;) { 2522 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2523 NVR_SELECT | NVR_CLOCK); 2524 trm_eeprom_wait(); 2525 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2526 trm_eeprom_wait(); 2527 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2528 break; 2529 } 2530 /* 2531 * Disable chip select 2532 */ 2533 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2534 } 2535 2536 /* 2537 * read seeprom 128 bytes to struct eeprom 2538 */ 2539 static void 2540 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2541 { 2542 bus_space_tag_t iot = sc->sc_iot; 2543 bus_space_handle_t ioh = sc->sc_ioh; 2544 uint8_t *buf = (uint8_t *)eeprom; 2545 uint8_t addr; 2546 2547 /* 2548 * Enable SEEPROM 2549 */ 2550 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2551 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2552 2553 for (addr = 0; addr < 128; addr++) 2554 *buf++ = trm_eeprom_get_data(sc, addr); 2555 2556 /* 2557 * Disable SEEPROM 2558 */ 2559 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2560 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2561 } 2562 2563 /* 2564 * read one byte from seeprom 2565 */ 2566 static uint8_t 2567 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2568 { 2569 bus_space_tag_t iot = sc->sc_iot; 2570 bus_space_handle_t ioh = sc->sc_ioh; 2571 int i; 2572 uint8_t read, data = 0; 2573 2574 /* 2575 * Send read command & address 2576 */ 2577 trm_eeprom_write_cmd(sc, 0x06, addr); 2578 2579 for (i = 0; i < 8; i++) { /* Read data */ 2580 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2581 NVR_SELECT | NVR_CLOCK); 2582 trm_eeprom_wait(); 2583 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2584 /* 2585 * Get data bit while falling edge 2586 */ 2587 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2588 data <<= 1; 2589 if (read & NVR_BITIN) 2590 data |= 1; 2591 2592 trm_eeprom_wait(); 2593 } 2594 /* 2595 * Disable chip select 2596 */ 2597 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2598 return (data); 2599 } 2600 2601 /* 2602 * write SB and Op Code into seeprom 2603 */ 2604 static void 2605 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2606 { 2607 bus_space_tag_t iot = sc->sc_iot; 2608 bus_space_handle_t ioh = sc->sc_ioh; 2609 int i; 2610 uint8_t send; 2611 2612 /* Program SB+OP code */ 2613 for (i = 0; i < 3; i++, cmd <<= 1) { 2614 send = NVR_SELECT; 2615 if (cmd & 0x04) /* Start from bit 2 */ 2616 send |= NVR_BITOUT; 2617 2618 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2619 trm_eeprom_wait(); 2620 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2621 trm_eeprom_wait(); 2622 } 2623 2624 /* Program address */ 2625 for (i = 0; i < 7; i++, addr <<= 1) { 2626 send = NVR_SELECT; 2627 if (addr & 0x40) /* Start from bit 6 */ 2628 send |= NVR_BITOUT; 2629 2630 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2631 trm_eeprom_wait(); 2632 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2633 trm_eeprom_wait(); 2634 } 2635 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2636 trm_eeprom_wait(); 2637 } 2638
Indexes created Mon Sep 22 13:09:51 GMT 2025