trm.c revision 1.19
1 /* $NetBSD: trm.c,v 1.19 2005/04/16 13:46:20 bouyer Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.19 2005/04/16 13:46:20 bouyer Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_spc.h> 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsi_message.h> 71 #include <dev/scsipi/scsipi_all.h> 72 #include <dev/scsipi/scsiconf.h> 73 74 #include <dev/pci/pcidevs.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/trmreg.h> 78 79 /* 80 * feature of chip set MAX value 81 */ 82 #define TRM_MAX_TARGETS 16 83 #define TRM_MAX_LUNS 8 84 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 85 #define TRM_MAX_SRB 32 /* XXX */ 86 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 87 #define TRM_MAX_OFFSET 15 88 #define TRM_MAX_PERIOD 125 89 90 /* 91 * Segment Entry 92 */ 93 struct trm_sg_entry { 94 uint32_t address; 95 uint32_t length; 96 }; 97 98 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 99 100 /* 101 ********************************************************************** 102 * The SEEPROM structure for TRM_S1040 103 ********************************************************************** 104 */ 105 struct nvram_target { 106 uint8_t config0; /* Target configuration byte 0 */ 107 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 108 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 109 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 110 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 111 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 112 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 113 uint8_t period; /* Target period */ 114 uint8_t config2; /* Target configuration byte 2 */ 115 uint8_t config3; /* Target configuration byte 3 */ 116 }; 117 118 struct trm_nvram { 119 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 120 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 121 uint8_t subclass; /* 4 Sub Class */ 122 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 123 uint8_t device_id[2]; /* 7,8 Device ID */ 124 uint8_t reserved0; /* 9 Reserved */ 125 struct nvram_target target[TRM_MAX_TARGETS]; 126 /* 10,11,12,13 127 * 14,15,16,17 128 * .... 129 * 70,71,72,73 */ 130 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 131 uint8_t channel_cfg; /* 75 Channel configuration */ 132 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 133 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 134 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 135 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 136 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 137 uint8_t delay_time; /* 76 Power on delay time */ 138 uint8_t max_tag; /* 77 Maximum tags */ 139 uint8_t reserved1; /* 78 */ 140 uint8_t boot_target; /* 79 */ 141 uint8_t boot_lun; /* 80 */ 142 uint8_t reserved2; /* 81 */ 143 uint8_t reserved3[44]; /* 82,..125 */ 144 uint8_t checksum0; /* 126 */ 145 uint8_t checksum1; /* 127 */ 146 #define TRM_NVRAM_CKSUM 0x1234 147 }; 148 149 /* Nvram Initiater bits definition */ 150 #define MORE2_DRV 0x00000001 151 #define GREATER_1G 0x00000002 152 #define RST_SCSI_BUS 0x00000004 153 #define ACTIVE_NEGATION 0x00000008 154 #define NO_SEEK 0x00000010 155 #define LUN_CHECK 0x00000020 156 157 #define trm_eeprom_wait() DELAY(30) 158 159 /* 160 *----------------------------------------------------------------------- 161 * SCSI Request Block 162 *----------------------------------------------------------------------- 163 */ 164 struct trm_srb { 165 TAILQ_ENTRY(trm_srb) next; 166 167 struct trm_sg_entry *sgentry; 168 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 169 bus_dmamap_t dmap; 170 bus_size_t sgoffset; /* Xfer buf offset */ 171 172 uint32_t buflen; /* Total xfer length */ 173 uint32_t sgaddr; /* SGList physical starting address */ 174 175 int sgcnt; 176 int sgindex; 177 178 int hastat; /* Host Adapter Status */ 179 #define H_STATUS_GOOD 0x00 180 #define H_SEL_TIMEOUT 0x11 181 #define H_OVER_UNDER_RUN 0x12 182 #define H_UNEXP_BUS_FREE 0x13 183 #define H_TARGET_PHASE_F 0x14 184 #define H_INVALID_CCB_OP 0x16 185 #define H_LINK_CCB_BAD 0x17 186 #define H_BAD_TARGET_DIR 0x18 187 #define H_DUPLICATE_CCB 0x19 188 #define H_BAD_CCB_OR_SG 0x1A 189 #define H_ABORT 0xFF 190 int tastat; /* Target SCSI Status Byte */ 191 int flag; /* SRBFlag */ 192 #define AUTO_REQSENSE 0x0001 193 #define PARITY_ERROR 0x0002 194 #define SRB_TIMEOUT 0x0004 195 196 int cmdlen; /* SCSI command length */ 197 uint8_t cmd[12]; /* SCSI command */ 198 199 uint8_t tag[2]; 200 }; 201 202 /* 203 * some info about each target and lun on the SCSI bus 204 */ 205 struct trm_linfo { 206 int used; /* number of slots in use */ 207 int avail; /* where to start scanning */ 208 int busy; /* lun in use */ 209 struct trm_srb *untagged; 210 struct trm_srb *queued[TRM_MAX_TAG]; 211 }; 212 213 struct trm_tinfo { 214 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 215 #define SYNC_NEGO_ENABLE 0x0001 216 #define SYNC_NEGO_DOING 0x0002 217 #define SYNC_NEGO_DONE 0x0004 218 #define WIDE_NEGO_ENABLE 0x0008 219 #define WIDE_NEGO_DOING 0x0010 220 #define WIDE_NEGO_DONE 0x0020 221 #define USE_TAG_QUEUING 0x0040 222 #define NO_RESELECT 0x0080 223 struct trm_linfo *linfo[TRM_MAX_LUNS]; 224 225 uint8_t config0; /* Target Config */ 226 uint8_t period; /* Max Period for nego. */ 227 uint8_t synctl; /* Sync control for reg. */ 228 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 229 }; 230 231 /* 232 *----------------------------------------------------------------------- 233 * Adapter Control Block 234 *----------------------------------------------------------------------- 235 */ 236 struct trm_softc { 237 struct device sc_dev; 238 239 bus_space_tag_t sc_iot; 240 bus_space_handle_t sc_ioh; 241 bus_dma_tag_t sc_dmat; 242 bus_dmamap_t sc_dmamap; /* Map the control structures */ 243 244 struct trm_srb *sc_actsrb; 245 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 246 247 TAILQ_HEAD(, trm_srb) sc_freesrb, 248 sc_readysrb; 249 struct trm_srb *sc_srb; /* SRB array */ 250 251 struct trm_sg_entry *sc_sglist; 252 253 int sc_maxid; 254 /* 255 * Link to the generic SCSI driver 256 */ 257 struct scsipi_channel sc_channel; 258 struct scsipi_adapter sc_adapter; 259 260 int sc_id; /* Adapter SCSI Target ID */ 261 262 int sc_state; /* SRB State */ 263 #define TRM_IDLE 0 264 #define TRM_WAIT 1 265 #define TRM_READY 2 266 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 267 #define TRM_MSGIN 4 268 #define TRM_EXTEND_MSGIN 5 269 #define TRM_COMMAND 6 270 #define TRM_START 7 /* arbitration+msg_out+command_out */ 271 #define TRM_DISCONNECTED 8 272 #define TRM_DATA_XFER 9 273 #define TRM_XFERPAD 10 274 #define TRM_STATUS 11 275 #define TRM_COMPLETED 12 276 #define TRM_ABORT_SENT 13 277 #define TRM_UNEXPECT_RESEL 14 278 279 int sc_phase; /* SCSI phase */ 280 int sc_config; 281 #define HCC_WIDE_CARD 0x01 282 #define HCC_SCSI_RESET 0x02 283 #define HCC_PARITY 0x04 284 #define HCC_AUTOTERM 0x08 285 #define HCC_LOW8TERM 0x10 286 #define HCC_UP8TERM 0x20 287 288 int sc_flag; 289 #define RESET_DEV 0x01 290 #define RESET_DETECT 0x02 291 #define RESET_DONE 0x04 292 #define WAIT_TAGMSG 0x08 /* XXX */ 293 294 int sc_msgcnt; 295 296 int resel_target; /* XXX */ 297 int resel_lun; /* XXX */ 298 299 uint8_t *sc_msg; 300 uint8_t sc_msgbuf[6]; 301 }; 302 303 /* 304 * SCSI Status codes not defined in scsi_all.h 305 */ 306 #define SCSI_COND_MET 0x04 /* Condition Met */ 307 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 308 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 309 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 310 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 311 312 static int trm_probe(struct device *, struct cfdata *, void *); 313 static void trm_attach(struct device *, struct device *, void *); 314 315 static int trm_init(struct trm_softc *); 316 317 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 318 void *); 319 static void trm_update_xfer_mode(struct trm_softc *, int); 320 static void trm_sched(struct trm_softc *); 321 static int trm_select(struct trm_softc *, struct trm_srb *); 322 static void trm_reset(struct trm_softc *); 323 static void trm_timeout(void *); 324 static int trm_intr(void *); 325 326 static void trm_dataout_phase0(struct trm_softc *, int); 327 static void trm_datain_phase0(struct trm_softc *, int); 328 static void trm_status_phase0(struct trm_softc *); 329 static void trm_msgin_phase0(struct trm_softc *); 330 static void trm_command_phase1(struct trm_softc *); 331 static void trm_status_phase1(struct trm_softc *); 332 static void trm_msgout_phase1(struct trm_softc *); 333 static void trm_msgin_phase1(struct trm_softc *); 334 335 static void trm_dataio_xfer(struct trm_softc *, int); 336 static void trm_disconnect(struct trm_softc *); 337 static void trm_reselect(struct trm_softc *); 338 static void trm_done(struct trm_softc *, struct trm_srb *); 339 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 340 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 341 342 static void trm_scsi_reset_detect(struct trm_softc *); 343 static void trm_reset_scsi_bus(struct trm_softc *); 344 345 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 348 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 349 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 350 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 351 352 CFATTACH_DECL(trm, sizeof(struct trm_softc), 353 trm_probe, trm_attach, NULL, NULL); 354 355 /* real period: */ 356 static const uint8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(struct device *parent, struct cfdata *match, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 373 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 374 switch (PCI_PRODUCT(pa->pa_id)) { 375 case PCI_PRODUCT_TEKRAM2_DC315: 376 return (1); 377 } 378 return (0); 379 } 380 381 /* 382 * attach and init a host adapter 383 */ 384 static void 385 trm_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct pci_attach_args *const pa = aux; 388 struct trm_softc *sc = (struct trm_softc *)self; 389 bus_space_tag_t iot; 390 bus_space_handle_t ioh; 391 pci_intr_handle_t ih; 392 pcireg_t command; 393 const char *intrstr; 394 395 /* 396 * These cards do not allow memory mapped accesses 397 * pa_pc: chipset tag 398 * pa_tag: pci tag 399 */ 400 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 401 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 402 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 403 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 404 pci_conf_write(pa->pa_pc, pa->pa_tag, 405 PCI_COMMAND_STATUS_REG, command); 406 } 407 /* 408 * mask for get correct base address of pci IO port 409 */ 410 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 411 &iot, &ioh, NULL, NULL)) { 412 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 413 return; 414 } 415 /* 416 * test checksum of eeprom.. & initialize softc... 417 */ 418 sc->sc_iot = iot; 419 sc->sc_ioh = ioh; 420 sc->sc_dmat = pa->pa_dmat; 421 422 if (trm_init(sc) != 0) { 423 /* 424 * Error during initialization! 425 */ 426 printf(": Error during initialization\n"); 427 return; 428 } 429 /* 430 * Now try to attach all the sub-devices 431 */ 432 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 433 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 434 "Ultra Wide SCSI Adapter\n"); 435 else 436 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 437 "Ultra SCSI Adapter\n"); 438 439 /* 440 * Now tell the generic SCSI layer about our bus. 441 * map and establish interrupt 442 */ 443 if (pci_intr_map(pa, &ih)) { 444 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 445 return; 446 } 447 intrstr = pci_intr_string(pa->pa_pc, ih); 448 449 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 450 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 451 if (intrstr != NULL) 452 printf(" at %s", intrstr); 453 printf("\n"); 454 return; 455 } 456 if (intrstr != NULL) 457 printf("%s: interrupting at %s\n", 458 sc->sc_dev.dv_xname, intrstr); 459 460 sc->sc_adapter.adapt_dev = &sc->sc_dev; 461 sc->sc_adapter.adapt_nchannels = 1; 462 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 463 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 464 sc->sc_adapter.adapt_request = trm_scsipi_request; 465 sc->sc_adapter.adapt_minphys = minphys; 466 467 sc->sc_channel.chan_adapter = &sc->sc_adapter; 468 sc->sc_channel.chan_bustype = &scsi_bustype; 469 sc->sc_channel.chan_channel = 0; 470 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 471 sc->sc_channel.chan_nluns = 8; 472 sc->sc_channel.chan_id = sc->sc_id; 473 474 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 475 } 476 477 /* 478 * initialize the internal structures for a given SCSI host 479 */ 480 static int 481 trm_init(struct trm_softc *sc) 482 { 483 bus_space_tag_t iot = sc->sc_iot; 484 bus_space_handle_t ioh = sc->sc_ioh; 485 bus_dma_segment_t seg; 486 struct trm_nvram eeprom; 487 struct trm_srb *srb; 488 struct trm_tinfo *ti; 489 struct nvram_target *tconf; 490 int error, rseg, all_sgsize; 491 int i, target; 492 uint8_t bval; 493 494 DPRINTF(("\n")); 495 496 /* 497 * allocate the space for all SCSI control blocks (SRB) for DMA memory 498 */ 499 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 500 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 501 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 502 printf(": unable to allocate SCSI REQUEST BLOCKS, " 503 "error = %d\n", error); 504 return (1); 505 } 506 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 507 all_sgsize, (caddr_t *) &sc->sc_sglist, 508 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 509 printf(": unable to map SCSI REQUEST BLOCKS, " 510 "error = %d\n", error); 511 return (1); 512 } 513 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 514 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 515 printf(": unable to create SRB DMA maps, " 516 "error = %d\n", error); 517 return (1); 518 } 519 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 520 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 521 printf(": unable to load SRB DMA maps, " 522 "error = %d\n", error); 523 return (1); 524 } 525 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 526 memset(sc->sc_sglist, 0, all_sgsize); 527 528 /* 529 * EEPROM CHECKSUM 530 */ 531 trm_check_eeprom(sc, &eeprom); 532 533 sc->sc_maxid = 7; 534 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 535 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 536 sc->sc_config |= HCC_WIDE_CARD; 537 sc->sc_maxid = 15; 538 } 539 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 540 sc->sc_config |= HCC_SCSI_RESET; 541 542 sc->sc_actsrb = NULL; 543 sc->sc_id = eeprom.scsi_id; 544 sc->sc_flag = 0; 545 546 /* 547 * initialize and link all device's SRB queues of this adapter 548 */ 549 TAILQ_INIT(&sc->sc_freesrb); 550 TAILQ_INIT(&sc->sc_readysrb); 551 552 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 553 M_DEVBUF, M_NOWAIT|M_ZERO); 554 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 555 if (sc->sc_srb == NULL) { 556 printf(": can not allocate SRB\n"); 557 return (1); 558 } 559 560 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 561 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 562 srb->sgoffset = TRM_SG_SIZE * i; 563 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 564 /* 565 * map all SRB space to SRB_array 566 */ 567 if (bus_dmamap_create(sc->sc_dmat, 568 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 569 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 570 printf(": unable to create DMA transfer map...\n"); 571 free(sc->sc_srb, M_DEVBUF); 572 return (1); 573 } 574 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 575 srb++; 576 } 577 578 /* 579 * initialize all target info structures 580 */ 581 for (target = 0; target < TRM_MAX_TARGETS; target++) { 582 ti = &sc->sc_tinfo[target]; 583 ti->synctl = 0; 584 ti->offset = 0; 585 tconf = &eeprom.target[target]; 586 ti->config0 = tconf->config0; 587 ti->period = trm_clock_period[tconf->period & 0x07]; 588 ti->flag = 0; 589 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 590 #ifdef notyet 591 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 592 ti->flag |= USE_TAG_QUEUING; 593 #endif 594 } else 595 ti->flag |= NO_RESELECT; 596 597 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 598 target, ti->config0, ti->period)); 599 DPRINTF((", flag = 0x%02x\n", ti->flag)); 600 } 601 602 /* program configuration 0 */ 603 bval = PHASELATCH | INITIATOR | BLOCKRST; 604 if ((sc->sc_config & HCC_PARITY) != 0) 605 bval |= PARITYCHECK; 606 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 607 608 /* program configuration 1 */ 609 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 610 ACTIVE_NEG | ACTIVE_NEGPLUS); 611 612 /* 250ms selection timeout */ 613 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 614 615 /* Mask all interrupts */ 616 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 617 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 618 619 /* Reset SCSI module */ 620 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 621 622 /* program Host ID */ 623 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 624 625 /* set asynchronous transfer */ 626 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 627 628 /* Turn LED control off */ 629 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 630 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 631 632 /* DMA config */ 633 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 634 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 635 636 /* Clear pending interrupt status */ 637 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 638 639 /* Enable SCSI interrupt */ 640 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 641 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 642 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 643 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 644 645 trm_reset(sc); 646 647 return (0); 648 } 649 650 /* 651 * enqueues a SCSI command 652 * called by the higher level SCSI driver 653 */ 654 static void 655 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 656 void *arg) 657 { 658 bus_space_tag_t iot; 659 bus_space_handle_t ioh; 660 struct trm_softc *sc; 661 struct trm_srb *srb; 662 struct scsipi_xfer *xs; 663 int error, i, target, lun, s; 664 665 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 666 iot = sc->sc_iot; 667 ioh = sc->sc_ioh; 668 669 switch (req) { 670 case ADAPTER_REQ_RUN_XFER: 671 xs = arg; 672 target = xs->xs_periph->periph_target; 673 lun = xs->xs_periph->periph_lun; 674 DPRINTF(("trm_scsipi_request.....\n")); 675 DPRINTF(("target= %d lun= %d\n", target, lun)); 676 if (xs->xs_control & XS_CTL_RESET) { 677 trm_reset(sc); 678 xs->error = XS_NOERROR | XS_RESET; 679 return; 680 } 681 if (xs->xs_status & XS_STS_DONE) { 682 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 683 xs->xs_status &= ~XS_STS_DONE; 684 } 685 686 s = splbio(); 687 688 /* Get SRB */ 689 srb = TAILQ_FIRST(&sc->sc_freesrb); 690 if (srb != NULL) { 691 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 692 } else { 693 xs->error = XS_RESOURCE_SHORTAGE; 694 scsipi_done(xs); 695 splx(s); 696 return; 697 } 698 699 srb->xs = xs; 700 srb->cmdlen = xs->cmdlen; 701 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 702 703 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 704 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 705 xs->data, xs->datalen, NULL, 706 ((xs->xs_control & XS_CTL_NOSLEEP) ? 707 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 708 BUS_DMA_STREAMING | 709 ((xs->xs_control & XS_CTL_DATA_IN) ? 710 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 711 printf("%s: DMA transfer map unable to load, " 712 "error = %d\n", sc->sc_dev.dv_xname, error); 713 xs->error = XS_DRIVER_STUFFUP; 714 /* 715 * free SRB 716 */ 717 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 718 splx(s); 719 return; 720 } 721 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 722 srb->dmap->dm_mapsize, 723 (xs->xs_control & XS_CTL_DATA_IN) ? 724 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 725 726 /* Set up the scatter gather list */ 727 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 728 srb->sgentry[i].address = 729 htole32(srb->dmap->dm_segs[i].ds_addr); 730 srb->sgentry[i].length = 731 htole32(srb->dmap->dm_segs[i].ds_len); 732 } 733 srb->buflen = xs->datalen; 734 srb->sgcnt = srb->dmap->dm_nsegs; 735 } else { 736 srb->sgentry[0].address = 0; 737 srb->sgentry[0].length = 0; 738 srb->buflen = 0; 739 srb->sgcnt = 0; 740 } 741 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 742 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 743 744 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 745 746 srb->sgindex = 0; 747 srb->hastat = 0; 748 srb->tastat = 0; 749 srb->flag = 0; 750 751 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 752 if (sc->sc_actsrb == NULL) 753 trm_sched(sc); 754 splx(s); 755 756 if ((xs->xs_control & XS_CTL_POLL) != 0) { 757 int timeout = xs->timeout; 758 759 s = splbio(); 760 do { 761 while (--timeout) { 762 DELAY(1000); 763 if (bus_space_read_2(iot, ioh, 764 TRM_SCSI_STATUS) & SCSIINTERRUPT) 765 break; 766 } 767 if (timeout == 0) { 768 trm_timeout(srb); 769 break; 770 } else 771 trm_intr(sc); 772 } while ((xs->xs_status & XS_STS_DONE) == 0); 773 splx(s); 774 } 775 return; 776 777 case ADAPTER_REQ_GROW_RESOURCES: 778 /* XXX Not supported. */ 779 return; 780 781 case ADAPTER_REQ_SET_XFER_MODE: 782 { 783 struct trm_tinfo *ti; 784 struct scsipi_xfer_mode *xm; 785 786 xm = arg; 787 ti = &sc->sc_tinfo[xm->xm_target]; 788 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 789 790 #ifdef notyet 791 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 792 ti->flag |= USE_TAG_QUEUING; 793 else 794 #endif 795 ti->flag &= ~USE_TAG_QUEUING; 796 797 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 798 (sc->sc_config & HCC_WIDE_CARD) != 0 && 799 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 800 ti->flag |= WIDE_NEGO_ENABLE; 801 ti->flag &= ~WIDE_NEGO_DONE; 802 } 803 804 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 805 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 806 ti->flag |= SYNC_NEGO_ENABLE; 807 ti->flag &= ~SYNC_NEGO_DONE; 808 ti->period = trm_clock_period[0]; 809 } 810 811 /* 812 * If we're not going to negotiate, send the 813 * notification now, since it won't happen later. 814 */ 815 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 816 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 817 trm_update_xfer_mode(sc, xm->xm_target); 818 819 return; 820 } 821 } 822 } 823 824 static void 825 trm_update_xfer_mode(struct trm_softc *sc, int target) 826 { 827 struct scsipi_xfer_mode xm; 828 struct trm_tinfo *ti; 829 830 ti = &sc->sc_tinfo[target]; 831 xm.xm_target = target; 832 xm.xm_mode = 0; 833 xm.xm_period = 0; 834 xm.xm_offset = 0; 835 836 if ((ti->synctl & WIDE_SYNC) != 0) 837 xm.xm_mode |= PERIPH_CAP_WIDE16; 838 839 if (ti->period > 0) { 840 xm.xm_mode |= PERIPH_CAP_SYNC; 841 xm.xm_period = ti->period; 842 xm.xm_offset = ti->offset; 843 } 844 845 #ifdef notyet 846 if ((ti->flag & USE_TAG_QUEUING) != 0) 847 xm.xm_mode |= PERIPH_CAP_TQING; 848 #endif 849 850 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 851 } 852 853 static void 854 trm_sched(struct trm_softc *sc) 855 { 856 struct trm_srb *srb; 857 struct scsipi_periph *periph; 858 struct trm_tinfo *ti; 859 struct trm_linfo *li; 860 int s, lun, tag; 861 862 DPRINTF(("trm_sched...\n")); 863 864 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 865 periph = srb->xs->xs_periph; 866 ti = &sc->sc_tinfo[periph->periph_target]; 867 lun = periph->periph_lun; 868 869 /* select type of tag for this command */ 870 if ((ti->flag & NO_RESELECT) != 0 || 871 (ti->flag & USE_TAG_QUEUING) == 0 || 872 (srb->flag & AUTO_REQSENSE) != 0 || 873 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 874 tag = 0; 875 else 876 tag = srb->xs->xs_tag_type; 877 #if 0 878 /* XXX use tags for polled commands? */ 879 if (srb->xs->xs_control & XS_CTL_POLL) 880 tag = 0; 881 #endif 882 883 s = splbio(); 884 li = ti->linfo[lun]; 885 if (li == NULL) { 886 /* initialize lun info */ 887 if ((li = malloc(sizeof(*li), M_DEVBUF, 888 M_NOWAIT|M_ZERO)) == NULL) { 889 splx(s); 890 continue; 891 } 892 ti->linfo[lun] = li; 893 } 894 895 if (tag == 0) { 896 /* try to issue this srb as an un-tagged command */ 897 if (li->untagged == NULL) 898 li->untagged = srb; 899 } 900 if (li->untagged != NULL) { 901 tag = 0; 902 if (li->busy != 1 && li->used == 0) { 903 /* we need to issue the untagged command now */ 904 srb = li->untagged; 905 periph = srb->xs->xs_periph; 906 } else { 907 /* not ready yet */ 908 splx(s); 909 continue; 910 } 911 } 912 srb->tag[0] = tag; 913 if (tag != 0) { 914 li->queued[srb->xs->xs_tag_id] = srb; 915 srb->tag[1] = srb->xs->xs_tag_id; 916 li->used++; 917 } 918 919 if (li->untagged != NULL && li->busy != 1) { 920 li->busy = 1; 921 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 922 sc->sc_actsrb = srb; 923 trm_select(sc, srb); 924 splx(s); 925 break; 926 } 927 if (li->untagged == NULL && tag != 0) { 928 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 929 sc->sc_actsrb = srb; 930 trm_select(sc, srb); 931 splx(s); 932 break; 933 } else 934 splx(s); 935 } 936 } 937 938 static int 939 trm_select(struct trm_softc *sc, struct trm_srb *srb) 940 { 941 bus_space_tag_t iot = sc->sc_iot; 942 bus_space_handle_t ioh = sc->sc_ioh; 943 struct scsipi_periph *periph = srb->xs->xs_periph; 944 int target = periph->periph_target; 945 int lun = periph->periph_lun; 946 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 947 uint8_t scsicmd; 948 949 DPRINTF(("trm_select.....\n")); 950 951 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 952 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 953 trm_timeout, srb); 954 } 955 956 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 957 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 958 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 959 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 960 /* Flush FIFO */ 961 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 962 DELAY(10); 963 964 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 965 966 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 967 968 if (((ti->flag & WIDE_NEGO_ENABLE) && 969 (ti->flag & WIDE_NEGO_DONE) == 0) || 970 ((ti->flag & SYNC_NEGO_ENABLE) && 971 (ti->flag & SYNC_NEGO_DONE) == 0)) { 972 sc->sc_state = TRM_MSGOUT; 973 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 974 MSG_IDENTIFY(lun, 0)); 975 bus_space_write_multi_1(iot, ioh, 976 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 977 /* it's important for atn stop */ 978 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 979 DO_DATALATCH | DO_HWRESELECT); 980 /* SCSI command */ 981 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 982 DPRINTF(("select with SEL_ATNSTOP\n")); 983 return (0); 984 } 985 986 if (srb->tag[0] != 0) { 987 /* Send identify message */ 988 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 989 MSG_IDENTIFY(lun, 1)); 990 /* Send Tag id */ 991 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 993 scsicmd = SCMD_SEL_ATN3; 994 DPRINTF(("select with SEL_ATN3\n")); 995 } else { 996 /* Send identify message */ 997 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 998 MSG_IDENTIFY(lun, 999 (ti->flag & NO_RESELECT) == 0 && 1000 (srb->flag & AUTO_REQSENSE) == 0 && 1001 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1002 scsicmd = SCMD_SEL_ATN; 1003 DPRINTF(("select with SEL_ATN\n")); 1004 } 1005 sc->sc_state = TRM_START; 1006 1007 /* 1008 * Send CDB ..command block... 1009 */ 1010 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1011 1012 /* 1013 * If trm_select returns 0: current interrupt status 1014 * is interrupt enable. It's said that SCSI processor is 1015 * unoccupied. 1016 */ 1017 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1018 /* SCSI command */ 1019 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1020 return (0); 1021 } 1022 1023 /* 1024 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1025 */ 1026 static void 1027 trm_reset(struct trm_softc *sc) 1028 { 1029 bus_space_tag_t iot = sc->sc_iot; 1030 bus_space_handle_t ioh = sc->sc_ioh; 1031 int s; 1032 1033 DPRINTF(("trm_reset.........\n")); 1034 1035 s = splbio(); 1036 1037 /* disable SCSI and DMA interrupt */ 1038 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1039 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1040 1041 trm_reset_scsi_bus(sc); 1042 DELAY(100000); 1043 1044 /* Enable SCSI interrupt */ 1045 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1046 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1047 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1048 1049 /* Enable DMA interrupt */ 1050 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1051 1052 /* Clear DMA FIFO */ 1053 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1054 1055 /* Clear SCSI FIFO */ 1056 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1057 1058 sc->sc_actsrb = NULL; 1059 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1060 1061 splx(s); 1062 } 1063 1064 static void 1065 trm_timeout(void *arg) 1066 { 1067 struct trm_srb *srb = (struct trm_srb *)arg; 1068 struct scsipi_xfer *xs = srb->xs; 1069 struct scsipi_periph *periph = xs->xs_periph; 1070 struct trm_softc *sc; 1071 int s; 1072 1073 if (xs == NULL) 1074 printf("trm_timeout called with xs == NULL\n"); 1075 1076 else { 1077 scsipi_printaddr(xs->xs_periph); 1078 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1079 } 1080 1081 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1082 1083 trm_reset_scsi_bus(sc); 1084 s = splbio(); 1085 srb->flag |= SRB_TIMEOUT; 1086 trm_done(sc, srb); 1087 /* XXX needs more.. */ 1088 splx(s); 1089 } 1090 1091 /* 1092 * Catch an interrupt from the adapter 1093 * Process pending device interrupts. 1094 */ 1095 static int 1096 trm_intr(void *arg) 1097 { 1098 bus_space_tag_t iot; 1099 bus_space_handle_t ioh; 1100 struct trm_softc *sc; 1101 int intstat, stat; 1102 1103 DPRINTF(("trm_intr......\n")); 1104 sc = (struct trm_softc *)arg; 1105 if (sc == NULL) 1106 return (0); 1107 1108 iot = sc->sc_iot; 1109 ioh = sc->sc_ioh; 1110 1111 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1112 if ((stat & SCSIINTERRUPT) == 0) 1113 return (0); 1114 1115 DPRINTF(("stat = %04x, ", stat)); 1116 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1117 1118 DPRINTF(("intstat=%02x, ", intstat)); 1119 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1120 DPRINTF(("\n")); 1121 trm_disconnect(sc); 1122 return (1); 1123 } 1124 if (intstat & INT_RESELECTED) { 1125 DPRINTF(("\n")); 1126 trm_reselect(sc); 1127 return (1); 1128 } 1129 if (intstat & INT_SCSIRESET) { 1130 DPRINTF(("\n")); 1131 trm_scsi_reset_detect(sc); 1132 return (1); 1133 } 1134 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1135 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1136 sc->sc_phase, sc->sc_state)); 1137 /* 1138 * software sequential machine 1139 */ 1140 1141 /* 1142 * call phase0 functions... "phase entry" handle 1143 * every phase before start transfer 1144 */ 1145 switch (sc->sc_phase) { 1146 case PH_DATA_OUT: 1147 trm_dataout_phase0(sc, stat); 1148 break; 1149 case PH_DATA_IN: 1150 trm_datain_phase0(sc, stat); 1151 break; 1152 case PH_COMMAND: 1153 break; 1154 case PH_STATUS: 1155 trm_status_phase0(sc); 1156 stat = PH_BUS_FREE; 1157 break; 1158 case PH_MSG_OUT: 1159 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1160 sc->sc_state == TRM_ABORT_SENT) 1161 stat = PH_BUS_FREE; 1162 break; 1163 case PH_MSG_IN: 1164 trm_msgin_phase0(sc); 1165 stat = PH_BUS_FREE; 1166 break; 1167 case PH_BUS_FREE: 1168 break; 1169 default: 1170 printf("%s: unexpected phase in trm_intr() phase0\n", 1171 sc->sc_dev.dv_xname); 1172 break; 1173 } 1174 1175 sc->sc_phase = stat & PHASEMASK; 1176 1177 switch (sc->sc_phase) { 1178 case PH_DATA_OUT: 1179 trm_dataio_xfer(sc, XFERDATAOUT); 1180 break; 1181 case PH_DATA_IN: 1182 trm_dataio_xfer(sc, XFERDATAIN); 1183 break; 1184 case PH_COMMAND: 1185 trm_command_phase1(sc); 1186 break; 1187 case PH_STATUS: 1188 trm_status_phase1(sc); 1189 break; 1190 case PH_MSG_OUT: 1191 trm_msgout_phase1(sc); 1192 break; 1193 case PH_MSG_IN: 1194 trm_msgin_phase1(sc); 1195 break; 1196 case PH_BUS_FREE: 1197 break; 1198 default: 1199 printf("%s: unexpected phase in trm_intr() phase1\n", 1200 sc->sc_dev.dv_xname); 1201 break; 1202 } 1203 1204 return (1); 1205 } 1206 return (0); 1207 } 1208 1209 static void 1210 trm_msgout_phase1(struct trm_softc *sc) 1211 { 1212 bus_space_tag_t iot = sc->sc_iot; 1213 bus_space_handle_t ioh = sc->sc_ioh; 1214 struct trm_srb *srb; 1215 struct scsipi_periph *periph; 1216 struct trm_tinfo *ti; 1217 1218 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1219 1220 srb = sc->sc_actsrb; 1221 1222 /* message out phase */ 1223 if (srb != NULL) { 1224 periph = srb->xs->xs_periph; 1225 ti = &sc->sc_tinfo[periph->periph_target]; 1226 1227 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1228 (ti->flag & WIDE_NEGO_ENABLE)) { 1229 /* send WDTR */ 1230 ti->flag &= ~SYNC_NEGO_DONE; 1231 1232 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1233 sc->sc_msgbuf[1] = MSG_EXTENDED; 1234 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1235 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1236 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1237 sc->sc_msgcnt = 5; 1238 1239 ti->flag |= WIDE_NEGO_DOING; 1240 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1241 (ti->flag & SYNC_NEGO_ENABLE)) { 1242 /* send SDTR */ 1243 int cnt = 0; 1244 1245 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1246 sc->sc_msgbuf[cnt++] = 1247 MSG_IDENTIFY(periph->periph_lun, 0); 1248 1249 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1250 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1251 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1252 sc->sc_msgbuf[cnt++] = ti->period; 1253 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1254 sc->sc_msgcnt = cnt; 1255 ti->flag |= SYNC_NEGO_DOING; 1256 } 1257 } 1258 if (sc->sc_msgcnt == 0) { 1259 sc->sc_msgbuf[0] = MSG_ABORT; 1260 sc->sc_msgcnt = 1; 1261 sc->sc_state = TRM_ABORT_SENT; 1262 } 1263 1264 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1265 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1266 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1267 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1268 1269 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1270 sc->sc_msgbuf, sc->sc_msgcnt); 1271 sc->sc_msgcnt = 0; 1272 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1273 1274 /* it's important for atn stop */ 1275 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1276 1277 /* 1278 * SCSI command 1279 */ 1280 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1281 } 1282 1283 static void 1284 trm_command_phase1(struct trm_softc *sc) 1285 { 1286 bus_space_tag_t iot = sc->sc_iot; 1287 bus_space_handle_t ioh = sc->sc_ioh; 1288 struct trm_srb *srb; 1289 1290 srb = sc->sc_actsrb; 1291 if (srb == NULL) { 1292 DPRINTF(("trm_command_phase1: no active srb\n")); 1293 return; 1294 } 1295 1296 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1297 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1298 1299 sc->sc_state = TRM_COMMAND; 1300 /* it's important for atn stop */ 1301 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1302 1303 /* 1304 * SCSI command 1305 */ 1306 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1307 } 1308 1309 static void 1310 trm_dataout_phase0(struct trm_softc *sc, int stat) 1311 { 1312 bus_space_tag_t iot = sc->sc_iot; 1313 bus_space_handle_t ioh = sc->sc_ioh; 1314 struct trm_srb *srb; 1315 struct scsipi_periph *periph; 1316 struct trm_tinfo *ti; 1317 struct trm_sg_entry *sg; 1318 int sgindex; 1319 uint32_t xferlen, leftcnt = 0; 1320 1321 if (sc->sc_state == TRM_XFERPAD) 1322 return; 1323 1324 srb = sc->sc_actsrb; 1325 if (srb == NULL) { 1326 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1327 return; 1328 } 1329 periph = srb->xs->xs_periph; 1330 ti = &sc->sc_tinfo[periph->periph_target]; 1331 1332 if ((stat & PARITYERROR) != 0) 1333 srb->flag |= PARITY_ERROR; 1334 1335 if ((stat & SCSIXFERDONE) == 0) { 1336 /* 1337 * when data transfer from DMA FIFO to SCSI FIFO 1338 * if there was some data left in SCSI FIFO 1339 */ 1340 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1341 SCSI_FIFOCNT_MASK; 1342 if (ti->synctl & WIDE_SYNC) 1343 /* 1344 * if WIDE scsi SCSI FIFOCNT unit is word 1345 * so need to * 2 1346 */ 1347 leftcnt <<= 1; 1348 } 1349 /* 1350 * calculate all the residue data that was not yet transferred 1351 * SCSI transfer counter + left in SCSI FIFO data 1352 * 1353 * .....TRM_SCSI_XCNT (24bits) 1354 * The counter always decrements by one for every SCSI 1355 * byte transfer. 1356 * .....TRM_SCSI_FIFOCNT ( 5bits) 1357 * The counter is SCSI FIFO offset counter 1358 */ 1359 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1360 if (leftcnt == 1) { 1361 leftcnt = 0; 1362 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1363 } 1364 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1365 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1366 DMAXFERCOMP) == 0) 1367 ; /* XXX needs timeout */ 1368 1369 srb->buflen = 0; 1370 } else { 1371 /* Update SG list */ 1372 1373 /* 1374 * if transfer not yet complete 1375 * there were some data residue in SCSI FIFO or 1376 * SCSI transfer counter not empty 1377 */ 1378 if (srb->buflen != leftcnt) { 1379 /* data that had transferred length */ 1380 xferlen = srb->buflen - leftcnt; 1381 1382 /* next time to be transferred length */ 1383 srb->buflen = leftcnt; 1384 1385 /* 1386 * parsing from last time disconnect sgindex 1387 */ 1388 sg = srb->sgentry + srb->sgindex; 1389 for (sgindex = srb->sgindex; 1390 sgindex < srb->sgcnt; 1391 sgindex++, sg++) { 1392 /* 1393 * find last time which SG transfer 1394 * be disconnect 1395 */ 1396 if (xferlen >= le32toh(sg->length)) 1397 xferlen -= le32toh(sg->length); 1398 else { 1399 /* 1400 * update last time 1401 * disconnected SG list 1402 */ 1403 /* residue data length */ 1404 sg->length = 1405 htole32(le32toh(sg->length) 1406 - xferlen); 1407 /* residue data pointer */ 1408 sg->address = 1409 htole32(le32toh(sg->address) 1410 + xferlen); 1411 srb->sgindex = sgindex; 1412 break; 1413 } 1414 } 1415 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1416 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1417 } 1418 } 1419 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1420 } 1421 1422 static void 1423 trm_datain_phase0(struct trm_softc *sc, int stat) 1424 { 1425 bus_space_tag_t iot = sc->sc_iot; 1426 bus_space_handle_t ioh = sc->sc_ioh; 1427 struct trm_srb *srb; 1428 struct trm_sg_entry *sg; 1429 int sgindex; 1430 uint32_t xferlen, leftcnt = 0; 1431 1432 if (sc->sc_state == TRM_XFERPAD) 1433 return; 1434 1435 srb = sc->sc_actsrb; 1436 if (srb == NULL) { 1437 DPRINTF(("trm_datain_phase0: no active srb\n")); 1438 return; 1439 } 1440 1441 if (stat & PARITYERROR) 1442 srb->flag |= PARITY_ERROR; 1443 1444 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1445 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1446 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1447 DMAXFERCOMP) == 0) 1448 ; /* XXX needs timeout */ 1449 1450 srb->buflen = 0; 1451 } else { /* phase changed */ 1452 /* 1453 * parsing the case: 1454 * when a transfer not yet complete 1455 * but be disconnected by upper layer 1456 * if transfer not yet complete 1457 * there were some data residue in SCSI FIFO or 1458 * SCSI transfer counter not empty 1459 */ 1460 if (srb->buflen != leftcnt) { 1461 /* 1462 * data that had transferred length 1463 */ 1464 xferlen = srb->buflen - leftcnt; 1465 1466 /* 1467 * next time to be transferred length 1468 */ 1469 srb->buflen = leftcnt; 1470 1471 /* 1472 * parsing from last time disconnect sgindex 1473 */ 1474 sg = srb->sgentry + srb->sgindex; 1475 for (sgindex = srb->sgindex; 1476 sgindex < srb->sgcnt; 1477 sgindex++, sg++) { 1478 /* 1479 * find last time which SG transfer 1480 * be disconnect 1481 */ 1482 if (xferlen >= le32toh(sg->length)) 1483 xferlen -= le32toh(sg->length); 1484 else { 1485 /* 1486 * update last time 1487 * disconnected SG list 1488 */ 1489 /* residue data length */ 1490 sg->length = 1491 htole32(le32toh(sg->length) 1492 - xferlen); 1493 /* residue data pointer */ 1494 sg->address = 1495 htole32(le32toh(sg->address) 1496 + xferlen); 1497 srb->sgindex = sgindex; 1498 break; 1499 } 1500 } 1501 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1502 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1503 } 1504 } 1505 } 1506 1507 static void 1508 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1509 { 1510 bus_space_tag_t iot = sc->sc_iot; 1511 bus_space_handle_t ioh = sc->sc_ioh; 1512 struct trm_srb *srb; 1513 struct scsipi_periph *periph; 1514 struct trm_tinfo *ti; 1515 1516 srb = sc->sc_actsrb; 1517 if (srb == NULL) { 1518 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1519 return; 1520 } 1521 periph = srb->xs->xs_periph; 1522 ti = &sc->sc_tinfo[periph->periph_target]; 1523 1524 if (srb->sgindex < srb->sgcnt) { 1525 if (srb->buflen > 0) { 1526 /* 1527 * load what physical address of Scatter/Gather 1528 * list table want to be transfer 1529 */ 1530 sc->sc_state = TRM_DATA_XFER; 1531 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1532 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1533 srb->sgaddr + 1534 srb->sgindex * sizeof(struct trm_sg_entry)); 1535 /* 1536 * load how many bytes in the Scatter/Gather list table 1537 */ 1538 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1539 (srb->sgcnt - srb->sgindex) 1540 * sizeof(struct trm_sg_entry)); 1541 /* 1542 * load total xfer length (24bits) max value 16Mbyte 1543 */ 1544 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1545 /* Start DMA transfer */ 1546 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1547 iodir | SGXFER); 1548 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1549 STARTDMAXFER); 1550 1551 /* Start SCSI transfer */ 1552 /* it's important for atn stop */ 1553 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1554 DO_DATALATCH); 1555 1556 /* 1557 * SCSI command 1558 */ 1559 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1560 (iodir == XFERDATAOUT) ? 1561 SCMD_DMA_OUT : SCMD_DMA_IN); 1562 } else { /* xfer pad */ 1563 if (srb->sgcnt) { 1564 srb->hastat = H_OVER_UNDER_RUN; 1565 } 1566 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1567 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1568 1569 if (iodir == XFERDATAOUT) 1570 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1571 else 1572 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1573 1574 sc->sc_state = TRM_XFERPAD; 1575 /* it's important for atn stop */ 1576 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1577 DO_DATALATCH); 1578 1579 /* 1580 * SCSI command 1581 */ 1582 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1583 (iodir == XFERDATAOUT) ? 1584 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1585 } 1586 } 1587 } 1588 1589 static void 1590 trm_status_phase0(struct trm_softc *sc) 1591 { 1592 bus_space_tag_t iot = sc->sc_iot; 1593 bus_space_handle_t ioh = sc->sc_ioh; 1594 struct trm_srb *srb; 1595 1596 srb = sc->sc_actsrb; 1597 if (srb == NULL) { 1598 DPRINTF(("trm_status_phase0: no active srb\n")); 1599 return; 1600 } 1601 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1602 sc->sc_state = TRM_COMPLETED; 1603 /* it's important for atn stop */ 1604 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1605 1606 /* 1607 * SCSI command 1608 */ 1609 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1610 } 1611 1612 static void 1613 trm_status_phase1(struct trm_softc *sc) 1614 { 1615 bus_space_tag_t iot = sc->sc_iot; 1616 bus_space_handle_t ioh = sc->sc_ioh; 1617 1618 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1619 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1620 & SCSI_FIFO_EMPTY) == 0) 1621 bus_space_write_2(iot, ioh, 1622 TRM_SCSI_CONTROL, DO_CLRFIFO); 1623 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1624 & DMA_FIFO_EMPTY) == 0) 1625 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1626 } else { 1627 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1628 & DMA_FIFO_EMPTY) == 0) 1629 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1630 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1631 & SCSI_FIFO_EMPTY) == 0) 1632 bus_space_write_2(iot, ioh, 1633 TRM_SCSI_CONTROL, DO_CLRFIFO); 1634 } 1635 sc->sc_state = TRM_STATUS; 1636 /* it's important for atn stop */ 1637 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1638 1639 /* 1640 * SCSI command 1641 */ 1642 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1643 } 1644 1645 static void 1646 trm_msgin_phase0(struct trm_softc *sc) 1647 { 1648 bus_space_tag_t iot = sc->sc_iot; 1649 bus_space_handle_t ioh = sc->sc_ioh; 1650 struct trm_srb *srb; 1651 struct scsipi_periph *periph; 1652 struct trm_tinfo *ti; 1653 int index; 1654 uint8_t msgin_code; 1655 1656 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1657 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1658 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1659 switch (msgin_code) { 1660 case MSG_DISCONNECT: 1661 sc->sc_state = TRM_DISCONNECTED; 1662 break; 1663 1664 case MSG_SAVEDATAPOINTER: 1665 break; 1666 1667 case MSG_EXTENDED: 1668 case MSG_SIMPLE_Q_TAG: 1669 case MSG_HEAD_OF_Q_TAG: 1670 case MSG_ORDERED_Q_TAG: 1671 sc->sc_state = TRM_EXTEND_MSGIN; 1672 /* extended message (01h) */ 1673 sc->sc_msgbuf[0] = msgin_code; 1674 1675 sc->sc_msgcnt = 1; 1676 /* extended message length (n) */ 1677 sc->sc_msg = &sc->sc_msgbuf[1]; 1678 1679 break; 1680 case MSG_MESSAGE_REJECT: 1681 /* Reject message */ 1682 srb = sc->sc_actsrb; 1683 if (srb == NULL) { 1684 DPRINTF(("trm_msgin_phase0: " 1685 " message reject without actsrb\n")); 1686 break; 1687 } 1688 periph = srb->xs->xs_periph; 1689 ti = &sc->sc_tinfo[periph->periph_target]; 1690 1691 if (ti->flag & WIDE_NEGO_ENABLE) { 1692 /* do wide nego reject */ 1693 ti->flag |= WIDE_NEGO_DONE; 1694 ti->flag &= 1695 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1696 if ((ti->flag & SYNC_NEGO_ENABLE) && 1697 (ti->flag & SYNC_NEGO_DONE) == 0) { 1698 /* Set ATN, in case ATN was clear */ 1699 sc->sc_state = TRM_MSGOUT; 1700 bus_space_write_2(iot, ioh, 1701 TRM_SCSI_CONTROL, DO_SETATN); 1702 } else 1703 /* Clear ATN */ 1704 bus_space_write_2(iot, ioh, 1705 TRM_SCSI_CONTROL, DO_CLRATN); 1706 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1707 /* do sync nego reject */ 1708 bus_space_write_2(iot, ioh, 1709 TRM_SCSI_CONTROL, DO_CLRATN); 1710 if (ti->flag & SYNC_NEGO_DOING) { 1711 ti->flag &=~(SYNC_NEGO_ENABLE | 1712 SYNC_NEGO_DONE); 1713 ti->synctl = 0; 1714 ti->offset = 0; 1715 bus_space_write_1(iot, ioh, 1716 TRM_SCSI_SYNC, ti->synctl); 1717 bus_space_write_1(iot, ioh, 1718 TRM_SCSI_OFFSET, ti->offset); 1719 } 1720 } 1721 break; 1722 1723 case MSG_IGN_WIDE_RESIDUE: 1724 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1725 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1726 break; 1727 1728 default: 1729 /* 1730 * Restore data pointer message 1731 * Save data pointer message 1732 * Completion message 1733 * NOP message 1734 */ 1735 break; 1736 } 1737 } else { 1738 /* 1739 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1740 * Parsing incoming extented messages 1741 */ 1742 *sc->sc_msg++ = msgin_code; 1743 sc->sc_msgcnt++; 1744 1745 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1746 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1747 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1748 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1749 1750 switch (sc->sc_msgbuf[0]) { 1751 case MSG_SIMPLE_Q_TAG: 1752 case MSG_HEAD_OF_Q_TAG: 1753 case MSG_ORDERED_Q_TAG: 1754 /* 1755 * is QUEUE tag message : 1756 * 1757 * byte 0: 1758 * HEAD QUEUE TAG (20h) 1759 * ORDERED QUEUE TAG (21h) 1760 * SIMPLE QUEUE TAG (22h) 1761 * byte 1: 1762 * Queue tag (00h - FFh) 1763 */ 1764 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1765 /* XXX XXX XXX */ 1766 struct trm_linfo *li; 1767 int tagid; 1768 1769 sc->sc_flag &= ~WAIT_TAGMSG; 1770 tagid = sc->sc_msgbuf[1]; 1771 ti = &sc->sc_tinfo[sc->resel_target]; 1772 li = ti->linfo[sc->resel_lun]; 1773 srb = li->queued[tagid]; 1774 if (srb != NULL) { 1775 sc->sc_actsrb = srb; 1776 sc->sc_state = TRM_DATA_XFER; 1777 break; 1778 } else { 1779 printf("%s: invalid tag id\n", 1780 sc->sc_dev.dv_xname); 1781 } 1782 1783 sc->sc_state = TRM_UNEXPECT_RESEL; 1784 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1785 sc->sc_msgcnt = 1; 1786 bus_space_write_2(iot, ioh, 1787 TRM_SCSI_CONTROL, DO_SETATN); 1788 } else 1789 sc->sc_state = TRM_IDLE; 1790 break; 1791 1792 case MSG_EXTENDED: 1793 srb = sc->sc_actsrb; 1794 if (srb == NULL) { 1795 DPRINTF(("trm_msgin_phase0: " 1796 "extended message without actsrb\n")); 1797 break; 1798 } 1799 periph = srb->xs->xs_periph; 1800 ti = &sc->sc_tinfo[periph->periph_target]; 1801 1802 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1803 sc->sc_msgcnt == 4) { 1804 /* 1805 * is Wide data xfer Extended message : 1806 * ====================================== 1807 * WIDE DATA TRANSFER REQUEST 1808 * ====================================== 1809 * byte 0 : Extended message (01h) 1810 * byte 1 : Extended message length (02h) 1811 * byte 2 : WIDE DATA TRANSFER code (03h) 1812 * byte 3 : Transfer width exponent 1813 */ 1814 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1815 /* Length is wrong, reject it */ 1816 ti->flag &= ~(WIDE_NEGO_ENABLE | 1817 WIDE_NEGO_DONE); 1818 sc->sc_state = TRM_MSGOUT; 1819 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1820 sc->sc_msgcnt = 1; 1821 bus_space_write_2(iot, ioh, 1822 TRM_SCSI_CONTROL, DO_SETATN); 1823 break; 1824 } 1825 1826 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1827 sc->sc_msgbuf[3] = 1828 MSG_EXT_WDTR_BUS_8_BIT; 1829 1830 if (sc->sc_msgbuf[3] > 1831 MSG_EXT_WDTR_BUS_32_BIT) { 1832 /* reject_msg: */ 1833 ti->flag &= ~(WIDE_NEGO_ENABLE | 1834 WIDE_NEGO_DONE); 1835 sc->sc_state = TRM_MSGOUT; 1836 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1837 sc->sc_msgcnt = 1; 1838 bus_space_write_2(iot, ioh, 1839 TRM_SCSI_CONTROL, DO_SETATN); 1840 break; 1841 } 1842 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1843 /* do 16 bits */ 1844 sc->sc_msgbuf[3] = 1845 MSG_EXT_WDTR_BUS_16_BIT; 1846 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1847 ti->flag |= WIDE_NEGO_DONE; 1848 ti->flag &= ~(SYNC_NEGO_DONE | 1849 WIDE_NEGO_ENABLE); 1850 if (sc->sc_msgbuf[3] != 1851 MSG_EXT_WDTR_BUS_8_BIT) 1852 /* is Wide data xfer */ 1853 ti->synctl |= WIDE_SYNC; 1854 trm_update_xfer_mode(sc, 1855 periph->periph_target); 1856 } 1857 1858 sc->sc_state = TRM_MSGOUT; 1859 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1860 DO_SETATN); 1861 break; 1862 1863 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1864 sc->sc_msgcnt == 5) { 1865 /* 1866 * is 8bit transfer Extended message : 1867 * ================================= 1868 * SYNCHRONOUS DATA TRANSFER REQUEST 1869 * ================================= 1870 * byte 0 : Extended message (01h) 1871 * byte 1 : Extended message length (03) 1872 * byte 2 : SYNC DATA TRANSFER code (01h) 1873 * byte 3 : Transfer period factor 1874 * byte 4 : REQ/ACK offset 1875 */ 1876 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1877 /* reject_msg */ 1878 sc->sc_state = TRM_MSGOUT; 1879 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1880 sc->sc_msgcnt = 1; 1881 bus_space_write_2(iot, ioh, 1882 TRM_SCSI_CONTROL, DO_SETATN); 1883 break; 1884 } 1885 1886 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1887 ti->flag &= 1888 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1889 ti->flag |= SYNC_NEGO_DONE; 1890 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1891 sc->sc_msgbuf[3] = 0; 1892 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1893 sc->sc_msgbuf[4] = 1894 TRM_MAX_OFFSET; 1895 1896 if (sc->sc_msgbuf[3] == 0 || 1897 sc->sc_msgbuf[4] == 0) { 1898 /* set async */ 1899 ti->synctl = 0; 1900 ti->offset = 0; 1901 } else { 1902 /* set sync */ 1903 /* Transfer period factor */ 1904 ti->period = sc->sc_msgbuf[3]; 1905 /* REQ/ACK offset */ 1906 ti->offset = sc->sc_msgbuf[4]; 1907 for (index = 0; 1908 index < NPERIOD; 1909 index++) 1910 if (ti->period <= 1911 trm_clock_period[ 1912 index]) 1913 break; 1914 1915 ti->synctl |= ALT_SYNC | index; 1916 } 1917 /* 1918 * program SCSI control register 1919 */ 1920 bus_space_write_1(iot, ioh, 1921 TRM_SCSI_SYNC, ti->synctl); 1922 bus_space_write_1(iot, ioh, 1923 TRM_SCSI_OFFSET, ti->offset); 1924 trm_update_xfer_mode(sc, 1925 periph->periph_target); 1926 } 1927 sc->sc_state = TRM_IDLE; 1928 } 1929 break; 1930 default: 1931 break; 1932 } 1933 } 1934 1935 /* it's important for atn stop */ 1936 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1937 1938 /* 1939 * SCSI command 1940 */ 1941 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1942 } 1943 1944 static void 1945 trm_msgin_phase1(struct trm_softc *sc) 1946 { 1947 bus_space_tag_t iot = sc->sc_iot; 1948 bus_space_handle_t ioh = sc->sc_ioh; 1949 1950 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1951 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1952 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1953 sc->sc_state = TRM_MSGIN; 1954 } 1955 1956 /* it's important for atn stop */ 1957 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1958 1959 /* 1960 * SCSI command 1961 */ 1962 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1963 } 1964 1965 static void 1966 trm_disconnect(struct trm_softc *sc) 1967 { 1968 bus_space_tag_t iot = sc->sc_iot; 1969 bus_space_handle_t ioh = sc->sc_ioh; 1970 struct trm_srb *srb; 1971 int s; 1972 1973 s = splbio(); 1974 1975 srb = sc->sc_actsrb; 1976 DPRINTF(("trm_disconnect...............\n")); 1977 1978 if (srb == NULL) { 1979 DPRINTF(("trm_disconnect: no active srb\n")); 1980 DELAY(1000); /* 1 msec */ 1981 1982 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1983 DO_CLRFIFO | DO_HWRESELECT); 1984 return; 1985 } 1986 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1987 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1988 DO_CLRFIFO | DO_HWRESELECT); 1989 DELAY(100); 1990 1991 switch (sc->sc_state) { 1992 case TRM_UNEXPECT_RESEL: 1993 sc->sc_state = TRM_IDLE; 1994 break; 1995 1996 case TRM_ABORT_SENT: 1997 goto finish; 1998 1999 case TRM_START: 2000 case TRM_MSGOUT: 2001 { 2002 /* Selection time out - discard all LUNs if empty */ 2003 struct scsipi_periph *periph; 2004 struct trm_tinfo *ti; 2005 struct trm_linfo *li; 2006 int lun; 2007 2008 DPRINTF(("selection timeout\n")); 2009 2010 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2011 2012 periph = srb->xs->xs_periph; 2013 ti = &sc->sc_tinfo[periph->periph_target]; 2014 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2015 li = ti->linfo[lun]; 2016 if (li != NULL && 2017 li->untagged == NULL && li->used == 0) { 2018 ti->linfo[lun] = NULL; 2019 free(li, M_DEVBUF); 2020 } 2021 } 2022 } 2023 goto finish; 2024 2025 case TRM_DISCONNECTED: 2026 sc->sc_actsrb = NULL; 2027 sc->sc_state = TRM_IDLE; 2028 goto sched; 2029 2030 case TRM_COMPLETED: 2031 goto finish; 2032 } 2033 2034 out: 2035 splx(s); 2036 return; 2037 2038 finish: 2039 sc->sc_state = TRM_IDLE; 2040 trm_done(sc, srb); 2041 goto out; 2042 2043 sched: 2044 trm_sched(sc); 2045 goto out; 2046 } 2047 2048 static void 2049 trm_reselect(struct trm_softc *sc) 2050 { 2051 bus_space_tag_t iot = sc->sc_iot; 2052 bus_space_handle_t ioh = sc->sc_ioh; 2053 struct trm_tinfo *ti; 2054 struct trm_linfo *li; 2055 int target, lun; 2056 2057 DPRINTF(("trm_reselect.................\n")); 2058 2059 if (sc->sc_actsrb != NULL) { 2060 /* arbitration lost but reselection win */ 2061 sc->sc_state = TRM_READY; 2062 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2063 ti = &sc->sc_tinfo[target]; 2064 } else { 2065 /* Read Reselected Target Id and LUN */ 2066 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2067 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2068 ti = &sc->sc_tinfo[target]; 2069 li = ti->linfo[lun]; 2070 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2071 2072 /* 2073 * Check to see if we are running an un-tagged command. 2074 * Otherwise ack the IDENTIFY and wait for a tag message. 2075 */ 2076 if (li != NULL) { 2077 if (li->untagged != NULL && li->busy) { 2078 sc->sc_actsrb = li->untagged; 2079 sc->sc_state = TRM_DATA_XFER; 2080 } else { 2081 sc->resel_target = target; 2082 sc->resel_lun = lun; 2083 /* XXX XXX XXX */ 2084 sc->sc_flag |= WAIT_TAGMSG; 2085 } 2086 } 2087 2088 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2089 sc->sc_actsrb == NULL) { 2090 printf("%s: reselect from target %d lun %d " 2091 "without nexus; sending abort\n", 2092 sc->sc_dev.dv_xname, target, lun); 2093 sc->sc_state = TRM_UNEXPECT_RESEL; 2094 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2095 sc->sc_msgcnt = 1; 2096 bus_space_write_2(iot, ioh, 2097 TRM_SCSI_CONTROL, DO_SETATN); 2098 } 2099 } 2100 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2101 /* 2102 * Program HA ID, target ID, period and offset 2103 */ 2104 /* target ID */ 2105 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2106 2107 /* host ID */ 2108 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2109 2110 /* period */ 2111 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2112 2113 /* offset */ 2114 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2115 2116 /* it's important for atn stop */ 2117 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2118 /* 2119 * SCSI command 2120 */ 2121 /* to rls the /ACK signal */ 2122 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2123 } 2124 2125 /* 2126 * Complete execution of a SCSI command 2127 * Signal completion to the generic SCSI driver 2128 */ 2129 static void 2130 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2131 { 2132 struct scsipi_xfer *xs = srb->xs; 2133 2134 DPRINTF(("trm_done..................\n")); 2135 2136 if (xs == NULL) 2137 return; 2138 2139 if ((xs->xs_control & XS_CTL_POLL) == 0) 2140 callout_stop(&xs->xs_callout); 2141 2142 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2143 srb->flag & AUTO_REQSENSE) { 2144 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2145 srb->dmap->dm_mapsize, 2146 ((xs->xs_control & XS_CTL_DATA_IN) || 2147 (srb->flag & AUTO_REQSENSE)) ? 2148 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2149 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2150 } 2151 2152 /* 2153 * target status 2154 */ 2155 xs->status = srb->tastat; 2156 2157 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2158 2159 switch (xs->status) { 2160 case SCSI_OK: 2161 /* 2162 * process initiator status...... 2163 * Adapter (initiator) status 2164 */ 2165 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2166 printf("%s: over/under run error\n", 2167 sc->sc_dev.dv_xname); 2168 srb->tastat = 0; 2169 /* Illegal length (over/under run) */ 2170 xs->error = XS_DRIVER_STUFFUP; 2171 } else if ((srb->flag & PARITY_ERROR) != 0) { 2172 printf("%s: parity error\n", 2173 sc->sc_dev.dv_xname); 2174 /* Driver failed to perform operation */ 2175 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2176 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2177 xs->resid = srb->buflen; 2178 xs->error = XS_TIMEOUT; 2179 } else { 2180 /* No error */ 2181 xs->resid = srb->buflen; 2182 srb->hastat = 0; 2183 if (srb->flag & AUTO_REQSENSE) { 2184 /* there is no error, (sense is invalid) */ 2185 xs->error = XS_SENSE; 2186 } else { 2187 srb->tastat = 0; 2188 xs->error = XS_NOERROR; 2189 } 2190 } 2191 break; 2192 2193 case SCSI_CHECK: 2194 if ((srb->flag & AUTO_REQSENSE) != 0 || 2195 trm_request_sense(sc, srb) != 0) { 2196 printf("%s: request sense failed\n", 2197 sc->sc_dev.dv_xname); 2198 xs->error = XS_DRIVER_STUFFUP; 2199 break; 2200 } 2201 xs->error = XS_SENSE; 2202 return; 2203 2204 case SCSI_SEL_TIMEOUT: 2205 srb->hastat = H_SEL_TIMEOUT; 2206 srb->tastat = 0; 2207 xs->error = XS_SELTIMEOUT; 2208 break; 2209 2210 case SCSI_QUEUE_FULL: 2211 case SCSI_BUSY: 2212 xs->error = XS_BUSY; 2213 break; 2214 2215 case SCSI_RESV_CONFLICT: 2216 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2217 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2218 xs->error = XS_BUSY; 2219 break; 2220 2221 default: 2222 srb->hastat = 0; 2223 printf("%s: trm_done(): unknown status = %02x\n", 2224 sc->sc_dev.dv_xname, xs->status); 2225 xs->error = XS_DRIVER_STUFFUP; 2226 break; 2227 } 2228 2229 trm_dequeue(sc, srb); 2230 if (srb == sc->sc_actsrb) { 2231 sc->sc_actsrb = NULL; 2232 trm_sched(sc); 2233 } 2234 2235 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2236 2237 /* Notify cmd done */ 2238 scsipi_done(xs); 2239 } 2240 2241 static int 2242 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2243 { 2244 struct scsipi_xfer *xs; 2245 struct scsipi_periph *periph; 2246 struct trm_tinfo *ti; 2247 struct trm_linfo *li; 2248 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2249 int error; 2250 2251 DPRINTF(("trm_request_sense...\n")); 2252 2253 xs = srb->xs; 2254 periph = xs->xs_periph; 2255 2256 srb->flag |= AUTO_REQSENSE; 2257 2258 /* Status of initiator/target */ 2259 srb->hastat = 0; 2260 srb->tastat = 0; 2261 2262 memset(ss, 0, sizeof(*ss)); 2263 ss->opcode = SCSI_REQUEST_SENSE; 2264 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2265 ss->length = sizeof(struct scsi_sense_data); 2266 2267 srb->buflen = sizeof(struct scsi_sense_data); 2268 srb->sgcnt = 1; 2269 srb->sgindex = 0; 2270 srb->cmdlen = sizeof(struct scsi_request_sense); 2271 2272 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2273 &xs->sense.scsi_sense, srb->buflen, NULL, 2274 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2275 return error; 2276 } 2277 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2278 srb->buflen, BUS_DMASYNC_PREREAD); 2279 2280 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2281 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2282 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2283 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2284 2285 ti = &sc->sc_tinfo[periph->periph_target]; 2286 li = ti->linfo[periph->periph_lun]; 2287 if (li->busy > 0) 2288 li->busy = 0; 2289 trm_dequeue(sc, srb); 2290 li->untagged = srb; /* must be executed first to fix C/A */ 2291 li->busy = 2; 2292 2293 if (srb == sc->sc_actsrb) 2294 trm_select(sc, srb); 2295 else { 2296 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2297 if (sc->sc_actsrb == NULL) 2298 trm_sched(sc); 2299 } 2300 return 0; 2301 } 2302 2303 static void 2304 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2305 { 2306 struct scsipi_periph *periph; 2307 struct trm_tinfo *ti; 2308 struct trm_linfo *li; 2309 2310 periph = srb->xs->xs_periph; 2311 ti = &sc->sc_tinfo[periph->periph_target]; 2312 li = ti->linfo[periph->periph_lun]; 2313 2314 if (li->untagged == srb) { 2315 li->busy = 0; 2316 li->untagged = NULL; 2317 } 2318 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2319 li->queued[srb->tag[1]] = NULL; 2320 li->used--; 2321 } 2322 } 2323 2324 static void 2325 trm_reset_scsi_bus(struct trm_softc *sc) 2326 { 2327 bus_space_tag_t iot = sc->sc_iot; 2328 bus_space_handle_t ioh = sc->sc_ioh; 2329 int timeout, s; 2330 2331 DPRINTF(("trm_reset_scsi_bus.........\n")); 2332 2333 s = splbio(); 2334 2335 sc->sc_flag |= RESET_DEV; 2336 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2337 for (timeout = 20000; timeout >= 0; timeout--) { 2338 DELAY(1); 2339 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2340 INT_SCSIRESET) == 0) 2341 break; 2342 } 2343 if (timeout == 0) 2344 printf(": scsibus reset timeout\n"); 2345 2346 splx(s); 2347 } 2348 2349 static void 2350 trm_scsi_reset_detect(struct trm_softc *sc) 2351 { 2352 bus_space_tag_t iot = sc->sc_iot; 2353 bus_space_handle_t ioh = sc->sc_ioh; 2354 int s; 2355 2356 DPRINTF(("trm_scsi_reset_detect...............\n")); 2357 DELAY(1000000); /* delay 1 sec */ 2358 2359 s = splbio(); 2360 2361 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2362 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2363 2364 if (sc->sc_flag & RESET_DEV) { 2365 sc->sc_flag |= RESET_DONE; 2366 } else { 2367 sc->sc_flag |= RESET_DETECT; 2368 sc->sc_actsrb = NULL; 2369 sc->sc_flag = 0; 2370 trm_sched(sc); 2371 } 2372 splx(s); 2373 } 2374 2375 /* 2376 * read seeprom 128 bytes to struct eeprom and check checksum. 2377 * If it is wrong, update with default value. 2378 */ 2379 static void 2380 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2381 { 2382 struct nvram_target *target; 2383 uint16_t *ep; 2384 uint16_t chksum; 2385 int i; 2386 2387 DPRINTF(("trm_check_eeprom......\n")); 2388 trm_eeprom_read_all(sc, eeprom); 2389 ep = (uint16_t *)eeprom; 2390 chksum = 0; 2391 for (i = 0; i < 64; i++) 2392 chksum += le16toh(*ep++); 2393 2394 if (chksum != TRM_NVRAM_CKSUM) { 2395 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2396 /* 2397 * Checksum error, load default 2398 */ 2399 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2400 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2401 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2402 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2403 eeprom->subclass = 0x00; 2404 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2405 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2406 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2407 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2408 eeprom->reserved0 = 0x00; 2409 2410 for (i = 0, target = eeprom->target; 2411 i < TRM_MAX_TARGETS; 2412 i++, target++) { 2413 target->config0 = 0x77; 2414 target->period = 0x00; 2415 target->config2 = 0x00; 2416 target->config3 = 0x00; 2417 } 2418 2419 eeprom->scsi_id = 7; 2420 eeprom->channel_cfg = 0x0F; 2421 eeprom->delay_time = 0; 2422 eeprom->max_tag = 4; 2423 eeprom->reserved1 = 0x15; 2424 eeprom->boot_target = 0; 2425 eeprom->boot_lun = 0; 2426 eeprom->reserved2 = 0; 2427 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2428 2429 chksum = 0; 2430 ep = (uint16_t *)eeprom; 2431 for (i = 0; i < 63; i++) 2432 chksum += le16toh(*ep++); 2433 2434 chksum = TRM_NVRAM_CKSUM - chksum; 2435 eeprom->checksum0 = chksum & 0xFF; 2436 eeprom->checksum1 = chksum >> 8; 2437 2438 trm_eeprom_write_all(sc, eeprom); 2439 } 2440 } 2441 2442 /* 2443 * write struct eeprom 128 bytes to seeprom 2444 */ 2445 static void 2446 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2447 { 2448 bus_space_tag_t iot = sc->sc_iot; 2449 bus_space_handle_t ioh = sc->sc_ioh; 2450 uint8_t *buf = (uint8_t *)eeprom; 2451 uint8_t addr; 2452 2453 /* Enable SEEPROM */ 2454 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2455 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2456 2457 /* 2458 * Write enable 2459 */ 2460 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2461 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2462 trm_eeprom_wait(); 2463 2464 for (addr = 0; addr < 128; addr++, buf++) 2465 trm_eeprom_set_data(sc, addr, *buf); 2466 2467 /* 2468 * Write disable 2469 */ 2470 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2471 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2472 trm_eeprom_wait(); 2473 2474 /* Disable SEEPROM */ 2475 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2476 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2477 } 2478 2479 /* 2480 * write one byte to seeprom 2481 */ 2482 static void 2483 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2484 { 2485 bus_space_tag_t iot = sc->sc_iot; 2486 bus_space_handle_t ioh = sc->sc_ioh; 2487 int i; 2488 uint8_t send; 2489 2490 /* 2491 * Send write command & address 2492 */ 2493 trm_eeprom_write_cmd(sc, 0x05, addr); 2494 /* 2495 * Write data 2496 */ 2497 for (i = 0; i < 8; i++, data <<= 1) { 2498 send = NVR_SELECT; 2499 if (data & 0x80) /* Start from bit 7 */ 2500 send |= NVR_BITOUT; 2501 2502 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2503 trm_eeprom_wait(); 2504 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2505 trm_eeprom_wait(); 2506 } 2507 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2508 trm_eeprom_wait(); 2509 /* 2510 * Disable chip select 2511 */ 2512 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2513 trm_eeprom_wait(); 2514 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2515 trm_eeprom_wait(); 2516 /* 2517 * Wait for write ready 2518 */ 2519 for (;;) { 2520 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2521 NVR_SELECT | NVR_CLOCK); 2522 trm_eeprom_wait(); 2523 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2524 trm_eeprom_wait(); 2525 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2526 break; 2527 } 2528 /* 2529 * Disable chip select 2530 */ 2531 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2532 } 2533 2534 /* 2535 * read seeprom 128 bytes to struct eeprom 2536 */ 2537 static void 2538 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2539 { 2540 bus_space_tag_t iot = sc->sc_iot; 2541 bus_space_handle_t ioh = sc->sc_ioh; 2542 uint8_t *buf = (uint8_t *)eeprom; 2543 uint8_t addr; 2544 2545 /* 2546 * Enable SEEPROM 2547 */ 2548 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2549 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2550 2551 for (addr = 0; addr < 128; addr++) 2552 *buf++ = trm_eeprom_get_data(sc, addr); 2553 2554 /* 2555 * Disable SEEPROM 2556 */ 2557 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2558 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2559 } 2560 2561 /* 2562 * read one byte from seeprom 2563 */ 2564 static uint8_t 2565 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2566 { 2567 bus_space_tag_t iot = sc->sc_iot; 2568 bus_space_handle_t ioh = sc->sc_ioh; 2569 int i; 2570 uint8_t read, data = 0; 2571 2572 /* 2573 * Send read command & address 2574 */ 2575 trm_eeprom_write_cmd(sc, 0x06, addr); 2576 2577 for (i = 0; i < 8; i++) { /* Read data */ 2578 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2579 NVR_SELECT | NVR_CLOCK); 2580 trm_eeprom_wait(); 2581 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2582 /* 2583 * Get data bit while falling edge 2584 */ 2585 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2586 data <<= 1; 2587 if (read & NVR_BITIN) 2588 data |= 1; 2589 2590 trm_eeprom_wait(); 2591 } 2592 /* 2593 * Disable chip select 2594 */ 2595 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2596 return (data); 2597 } 2598 2599 /* 2600 * write SB and Op Code into seeprom 2601 */ 2602 static void 2603 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2604 { 2605 bus_space_tag_t iot = sc->sc_iot; 2606 bus_space_handle_t ioh = sc->sc_ioh; 2607 int i; 2608 uint8_t send; 2609 2610 /* Program SB+OP code */ 2611 for (i = 0; i < 3; i++, cmd <<= 1) { 2612 send = NVR_SELECT; 2613 if (cmd & 0x04) /* Start from bit 2 */ 2614 send |= NVR_BITOUT; 2615 2616 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2617 trm_eeprom_wait(); 2618 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2619 trm_eeprom_wait(); 2620 } 2621 2622 /* Program address */ 2623 for (i = 0; i < 7; i++, addr <<= 1) { 2624 send = NVR_SELECT; 2625 if (addr & 0x40) /* Start from bit 6 */ 2626 send |= NVR_BITOUT; 2627 2628 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2629 trm_eeprom_wait(); 2630 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2631 trm_eeprom_wait(); 2632 } 2633 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2634 trm_eeprom_wait(); 2635 } 2636
Indexes created Tue Sep 23 13:09:54 GMT 2025