trm.c revision 1.23
1 /* $NetBSD: trm.c,v 1.23 2006/05/22 00:09:34 christos Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.23 2006/05/22 00:09:34 christos Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <machine/bus.h> 64 #include <machine/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_spc.h> 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsi_message.h> 71 #include <dev/scsipi/scsipi_all.h> 72 #include <dev/scsipi/scsiconf.h> 73 74 #include <dev/pci/pcidevs.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/trmreg.h> 78 79 /* 80 * feature of chip set MAX value 81 */ 82 #define TRM_MAX_TARGETS 16 83 #define TRM_MAX_LUNS 8 84 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 85 #define TRM_MAX_SRB 32 /* XXX */ 86 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 87 #define TRM_MAX_OFFSET 15 88 #define TRM_MAX_PERIOD 125 89 90 /* 91 * Segment Entry 92 */ 93 struct trm_sg_entry { 94 uint32_t address; 95 uint32_t length; 96 }; 97 98 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 99 100 /* 101 ********************************************************************** 102 * The SEEPROM structure for TRM_S1040 103 ********************************************************************** 104 */ 105 struct nvram_target { 106 uint8_t config0; /* Target configuration byte 0 */ 107 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 108 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 109 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 110 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 111 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 112 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 113 uint8_t period; /* Target period */ 114 uint8_t config2; /* Target configuration byte 2 */ 115 uint8_t config3; /* Target configuration byte 3 */ 116 }; 117 118 struct trm_nvram { 119 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 120 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 121 uint8_t subclass; /* 4 Sub Class */ 122 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 123 uint8_t device_id[2]; /* 7,8 Device ID */ 124 uint8_t reserved0; /* 9 Reserved */ 125 struct nvram_target target[TRM_MAX_TARGETS]; 126 /* 10,11,12,13 127 * 14,15,16,17 128 * .... 129 * 70,71,72,73 */ 130 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 131 uint8_t channel_cfg; /* 75 Channel configuration */ 132 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 133 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 134 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 135 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 136 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 137 uint8_t delay_time; /* 76 Power on delay time */ 138 uint8_t max_tag; /* 77 Maximum tags */ 139 uint8_t reserved1; /* 78 */ 140 uint8_t boot_target; /* 79 */ 141 uint8_t boot_lun; /* 80 */ 142 uint8_t reserved2; /* 81 */ 143 uint8_t reserved3[44]; /* 82,..125 */ 144 uint8_t checksum0; /* 126 */ 145 uint8_t checksum1; /* 127 */ 146 #define TRM_NVRAM_CKSUM 0x1234 147 }; 148 149 /* Nvram Initiater bits definition */ 150 #define MORE2_DRV 0x00000001 151 #define GREATER_1G 0x00000002 152 #define RST_SCSI_BUS 0x00000004 153 #define ACTIVE_NEGATION 0x00000008 154 #define NO_SEEK 0x00000010 155 #define LUN_CHECK 0x00000020 156 157 #define trm_eeprom_wait() DELAY(30) 158 159 /* 160 *----------------------------------------------------------------------- 161 * SCSI Request Block 162 *----------------------------------------------------------------------- 163 */ 164 struct trm_srb { 165 TAILQ_ENTRY(trm_srb) next; 166 167 struct trm_sg_entry *sgentry; 168 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 169 bus_dmamap_t dmap; 170 bus_size_t sgoffset; /* Xfer buf offset */ 171 172 uint32_t buflen; /* Total xfer length */ 173 uint32_t sgaddr; /* SGList physical starting address */ 174 175 int sgcnt; 176 int sgindex; 177 178 int hastat; /* Host Adapter Status */ 179 #define H_STATUS_GOOD 0x00 180 #define H_SEL_TIMEOUT 0x11 181 #define H_OVER_UNDER_RUN 0x12 182 #define H_UNEXP_BUS_FREE 0x13 183 #define H_TARGET_PHASE_F 0x14 184 #define H_INVALID_CCB_OP 0x16 185 #define H_LINK_CCB_BAD 0x17 186 #define H_BAD_TARGET_DIR 0x18 187 #define H_DUPLICATE_CCB 0x19 188 #define H_BAD_CCB_OR_SG 0x1A 189 #define H_ABORT 0xFF 190 int tastat; /* Target SCSI Status Byte */ 191 int flag; /* SRBFlag */ 192 #define AUTO_REQSENSE 0x0001 193 #define PARITY_ERROR 0x0002 194 #define SRB_TIMEOUT 0x0004 195 196 int cmdlen; /* SCSI command length */ 197 uint8_t cmd[12]; /* SCSI command */ 198 199 uint8_t tag[2]; 200 }; 201 202 /* 203 * some info about each target and lun on the SCSI bus 204 */ 205 struct trm_linfo { 206 int used; /* number of slots in use */ 207 int avail; /* where to start scanning */ 208 int busy; /* lun in use */ 209 struct trm_srb *untagged; 210 struct trm_srb *queued[TRM_MAX_TAG]; 211 }; 212 213 struct trm_tinfo { 214 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 215 #define SYNC_NEGO_ENABLE 0x0001 216 #define SYNC_NEGO_DOING 0x0002 217 #define SYNC_NEGO_DONE 0x0004 218 #define WIDE_NEGO_ENABLE 0x0008 219 #define WIDE_NEGO_DOING 0x0010 220 #define WIDE_NEGO_DONE 0x0020 221 #define USE_TAG_QUEUING 0x0040 222 #define NO_RESELECT 0x0080 223 struct trm_linfo *linfo[TRM_MAX_LUNS]; 224 225 uint8_t config0; /* Target Config */ 226 uint8_t period; /* Max Period for nego. */ 227 uint8_t synctl; /* Sync control for reg. */ 228 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 229 }; 230 231 /* 232 *----------------------------------------------------------------------- 233 * Adapter Control Block 234 *----------------------------------------------------------------------- 235 */ 236 struct trm_softc { 237 struct device sc_dev; 238 239 bus_space_tag_t sc_iot; 240 bus_space_handle_t sc_ioh; 241 bus_dma_tag_t sc_dmat; 242 bus_dmamap_t sc_dmamap; /* Map the control structures */ 243 244 struct trm_srb *sc_actsrb; 245 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 246 247 TAILQ_HEAD(, trm_srb) sc_freesrb, 248 sc_readysrb; 249 struct trm_srb *sc_srb; /* SRB array */ 250 251 struct trm_sg_entry *sc_sglist; 252 253 int sc_maxid; 254 /* 255 * Link to the generic SCSI driver 256 */ 257 struct scsipi_channel sc_channel; 258 struct scsipi_adapter sc_adapter; 259 260 int sc_id; /* Adapter SCSI Target ID */ 261 262 int sc_state; /* SRB State */ 263 #define TRM_IDLE 0 264 #define TRM_WAIT 1 265 #define TRM_READY 2 266 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 267 #define TRM_MSGIN 4 268 #define TRM_EXTEND_MSGIN 5 269 #define TRM_COMMAND 6 270 #define TRM_START 7 /* arbitration+msg_out+command_out */ 271 #define TRM_DISCONNECTED 8 272 #define TRM_DATA_XFER 9 273 #define TRM_XFERPAD 10 274 #define TRM_STATUS 11 275 #define TRM_COMPLETED 12 276 #define TRM_ABORT_SENT 13 277 #define TRM_UNEXPECT_RESEL 14 278 279 int sc_phase; /* SCSI phase */ 280 int sc_config; 281 #define HCC_WIDE_CARD 0x01 282 #define HCC_SCSI_RESET 0x02 283 #define HCC_PARITY 0x04 284 #define HCC_AUTOTERM 0x08 285 #define HCC_LOW8TERM 0x10 286 #define HCC_UP8TERM 0x20 287 288 int sc_flag; 289 #define RESET_DEV 0x01 290 #define RESET_DETECT 0x02 291 #define RESET_DONE 0x04 292 #define WAIT_TAGMSG 0x08 /* XXX */ 293 294 int sc_msgcnt; 295 296 int resel_target; /* XXX */ 297 int resel_lun; /* XXX */ 298 299 uint8_t *sc_msg; 300 uint8_t sc_msgbuf[6]; 301 }; 302 303 /* 304 * SCSI Status codes not defined in scsi_all.h 305 */ 306 #define SCSI_COND_MET 0x04 /* Condition Met */ 307 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 308 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 309 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 310 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 311 312 static int trm_probe(struct device *, struct cfdata *, void *); 313 static void trm_attach(struct device *, struct device *, void *); 314 315 static int trm_init(struct trm_softc *); 316 317 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 318 void *); 319 static void trm_update_xfer_mode(struct trm_softc *, int); 320 static void trm_sched(struct trm_softc *); 321 static int trm_select(struct trm_softc *, struct trm_srb *); 322 static void trm_reset(struct trm_softc *); 323 static void trm_timeout(void *); 324 static int trm_intr(void *); 325 326 static void trm_dataout_phase0(struct trm_softc *, int); 327 static void trm_datain_phase0(struct trm_softc *, int); 328 static void trm_status_phase0(struct trm_softc *); 329 static void trm_msgin_phase0(struct trm_softc *); 330 static void trm_command_phase1(struct trm_softc *); 331 static void trm_status_phase1(struct trm_softc *); 332 static void trm_msgout_phase1(struct trm_softc *); 333 static void trm_msgin_phase1(struct trm_softc *); 334 335 static void trm_dataio_xfer(struct trm_softc *, int); 336 static void trm_disconnect(struct trm_softc *); 337 static void trm_reselect(struct trm_softc *); 338 static void trm_done(struct trm_softc *, struct trm_srb *); 339 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 340 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 341 342 static void trm_scsi_reset_detect(struct trm_softc *); 343 static void trm_reset_scsi_bus(struct trm_softc *); 344 345 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 348 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 349 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 350 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 351 352 CFATTACH_DECL(trm, sizeof(struct trm_softc), 353 trm_probe, trm_attach, NULL, NULL); 354 355 /* real period: */ 356 static const uint8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(struct device *parent, struct cfdata *match, void *aux) 370 { 371 struct pci_attach_args *pa = aux; 372 373 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 374 switch (PCI_PRODUCT(pa->pa_id)) { 375 case PCI_PRODUCT_TEKRAM2_DC315: 376 return (1); 377 } 378 return (0); 379 } 380 381 /* 382 * attach and init a host adapter 383 */ 384 static void 385 trm_attach(struct device *parent, struct device *self, void *aux) 386 { 387 struct pci_attach_args *const pa = aux; 388 struct trm_softc *sc = (struct trm_softc *)self; 389 bus_space_tag_t iot; 390 bus_space_handle_t ioh; 391 pci_intr_handle_t ih; 392 pcireg_t command; 393 const char *intrstr; 394 395 /* 396 * These cards do not allow memory mapped accesses 397 * pa_pc: chipset tag 398 * pa_tag: pci tag 399 */ 400 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 401 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 402 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 403 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 404 pci_conf_write(pa->pa_pc, pa->pa_tag, 405 PCI_COMMAND_STATUS_REG, command); 406 } 407 /* 408 * mask for get correct base address of pci IO port 409 */ 410 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 411 &iot, &ioh, NULL, NULL)) { 412 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 413 return; 414 } 415 /* 416 * test checksum of eeprom.. & initialize softc... 417 */ 418 sc->sc_iot = iot; 419 sc->sc_ioh = ioh; 420 sc->sc_dmat = pa->pa_dmat; 421 422 if (trm_init(sc) != 0) { 423 /* 424 * Error during initialization! 425 */ 426 printf(": Error during initialization\n"); 427 return; 428 } 429 /* 430 * Now try to attach all the sub-devices 431 */ 432 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 433 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 434 "Ultra Wide SCSI Adapter\n"); 435 else 436 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 437 "Ultra SCSI Adapter\n"); 438 439 /* 440 * Now tell the generic SCSI layer about our bus. 441 * map and establish interrupt 442 */ 443 if (pci_intr_map(pa, &ih)) { 444 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 445 return; 446 } 447 intrstr = pci_intr_string(pa->pa_pc, ih); 448 449 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 450 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 451 if (intrstr != NULL) 452 printf(" at %s", intrstr); 453 printf("\n"); 454 return; 455 } 456 if (intrstr != NULL) 457 printf("%s: interrupting at %s\n", 458 sc->sc_dev.dv_xname, intrstr); 459 460 sc->sc_adapter.adapt_dev = &sc->sc_dev; 461 sc->sc_adapter.adapt_nchannels = 1; 462 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 463 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 464 sc->sc_adapter.adapt_request = trm_scsipi_request; 465 sc->sc_adapter.adapt_minphys = minphys; 466 467 sc->sc_channel.chan_adapter = &sc->sc_adapter; 468 sc->sc_channel.chan_bustype = &scsi_bustype; 469 sc->sc_channel.chan_channel = 0; 470 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 471 sc->sc_channel.chan_nluns = 8; 472 sc->sc_channel.chan_id = sc->sc_id; 473 474 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 475 } 476 477 /* 478 * initialize the internal structures for a given SCSI host 479 */ 480 static int 481 trm_init(struct trm_softc *sc) 482 { 483 bus_space_tag_t iot = sc->sc_iot; 484 bus_space_handle_t ioh = sc->sc_ioh; 485 bus_dma_segment_t seg; 486 struct trm_nvram eeprom; 487 struct trm_srb *srb; 488 struct trm_tinfo *ti; 489 struct nvram_target *tconf; 490 int error, rseg, all_sgsize; 491 int i, target; 492 uint8_t bval; 493 494 DPRINTF(("\n")); 495 496 /* 497 * allocate the space for all SCSI control blocks (SRB) for DMA memory 498 */ 499 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 500 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 501 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 502 printf(": unable to allocate SCSI REQUEST BLOCKS, " 503 "error = %d\n", error); 504 return (1); 505 } 506 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 507 all_sgsize, (caddr_t *) &sc->sc_sglist, 508 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 509 printf(": unable to map SCSI REQUEST BLOCKS, " 510 "error = %d\n", error); 511 return (1); 512 } 513 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 514 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 515 printf(": unable to create SRB DMA maps, " 516 "error = %d\n", error); 517 return (1); 518 } 519 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 520 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 521 printf(": unable to load SRB DMA maps, " 522 "error = %d\n", error); 523 return (1); 524 } 525 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 526 memset(sc->sc_sglist, 0, all_sgsize); 527 528 /* 529 * EEPROM CHECKSUM 530 */ 531 trm_check_eeprom(sc, &eeprom); 532 533 sc->sc_maxid = 7; 534 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 535 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 536 sc->sc_config |= HCC_WIDE_CARD; 537 sc->sc_maxid = 15; 538 } 539 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 540 sc->sc_config |= HCC_SCSI_RESET; 541 542 sc->sc_actsrb = NULL; 543 sc->sc_id = eeprom.scsi_id; 544 sc->sc_flag = 0; 545 546 /* 547 * initialize and link all device's SRB queues of this adapter 548 */ 549 TAILQ_INIT(&sc->sc_freesrb); 550 TAILQ_INIT(&sc->sc_readysrb); 551 552 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 553 M_DEVBUF, M_NOWAIT|M_ZERO); 554 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 555 if (sc->sc_srb == NULL) { 556 printf(": can not allocate SRB\n"); 557 return (1); 558 } 559 560 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 561 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 562 srb->sgoffset = TRM_SG_SIZE * i; 563 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 564 /* 565 * map all SRB space to SRB_array 566 */ 567 if (bus_dmamap_create(sc->sc_dmat, 568 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 569 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 570 printf(": unable to create DMA transfer map...\n"); 571 free(sc->sc_srb, M_DEVBUF); 572 return (1); 573 } 574 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 575 srb++; 576 } 577 578 /* 579 * initialize all target info structures 580 */ 581 for (target = 0; target < TRM_MAX_TARGETS; target++) { 582 ti = &sc->sc_tinfo[target]; 583 ti->synctl = 0; 584 ti->offset = 0; 585 tconf = &eeprom.target[target]; 586 ti->config0 = tconf->config0; 587 ti->period = trm_clock_period[tconf->period & 0x07]; 588 ti->flag = 0; 589 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 590 #ifdef notyet 591 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 592 ti->flag |= USE_TAG_QUEUING; 593 #endif 594 } else 595 ti->flag |= NO_RESELECT; 596 597 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 598 target, ti->config0, ti->period)); 599 DPRINTF((", flag = 0x%02x\n", ti->flag)); 600 } 601 602 /* program configuration 0 */ 603 bval = PHASELATCH | INITIATOR | BLOCKRST; 604 if ((sc->sc_config & HCC_PARITY) != 0) 605 bval |= PARITYCHECK; 606 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 607 608 /* program configuration 1 */ 609 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 610 ACTIVE_NEG | ACTIVE_NEGPLUS); 611 612 /* 250ms selection timeout */ 613 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 614 615 /* Mask all interrupts */ 616 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 617 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 618 619 /* Reset SCSI module */ 620 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 621 622 /* program Host ID */ 623 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 624 625 /* set asynchronous transfer */ 626 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 627 628 /* Turn LED control off */ 629 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 630 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 631 632 /* DMA config */ 633 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 634 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 635 636 /* Clear pending interrupt status */ 637 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 638 639 /* Enable SCSI interrupt */ 640 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 641 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 642 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 643 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 644 645 trm_reset(sc); 646 647 return (0); 648 } 649 650 /* 651 * enqueues a SCSI command 652 * called by the higher level SCSI driver 653 */ 654 static void 655 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 656 void *arg) 657 { 658 bus_space_tag_t iot; 659 bus_space_handle_t ioh; 660 struct trm_softc *sc; 661 struct trm_srb *srb; 662 struct scsipi_xfer *xs; 663 int error, i, target, lun, s; 664 665 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 666 iot = sc->sc_iot; 667 ioh = sc->sc_ioh; 668 669 switch (req) { 670 case ADAPTER_REQ_RUN_XFER: 671 xs = arg; 672 target = xs->xs_periph->periph_target; 673 lun = xs->xs_periph->periph_lun; 674 DPRINTF(("trm_scsipi_request.....\n")); 675 DPRINTF(("target= %d lun= %d\n", target, lun)); 676 if (xs->xs_control & XS_CTL_RESET) { 677 trm_reset(sc); 678 xs->error = XS_NOERROR | XS_RESET; 679 return; 680 } 681 if (xs->xs_status & XS_STS_DONE) { 682 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 683 xs->xs_status &= ~XS_STS_DONE; 684 } 685 686 s = splbio(); 687 688 /* Get SRB */ 689 srb = TAILQ_FIRST(&sc->sc_freesrb); 690 if (srb != NULL) { 691 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 692 } else { 693 xs->error = XS_RESOURCE_SHORTAGE; 694 scsipi_done(xs); 695 splx(s); 696 return; 697 } 698 699 srb->xs = xs; 700 srb->cmdlen = xs->cmdlen; 701 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 702 703 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 704 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 705 xs->data, xs->datalen, NULL, 706 ((xs->xs_control & XS_CTL_NOSLEEP) ? 707 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 708 BUS_DMA_STREAMING | 709 ((xs->xs_control & XS_CTL_DATA_IN) ? 710 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 711 printf("%s: DMA transfer map unable to load, " 712 "error = %d\n", sc->sc_dev.dv_xname, error); 713 xs->error = XS_DRIVER_STUFFUP; 714 /* 715 * free SRB 716 */ 717 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 718 splx(s); 719 return; 720 } 721 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 722 srb->dmap->dm_mapsize, 723 (xs->xs_control & XS_CTL_DATA_IN) ? 724 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 725 726 /* Set up the scatter gather list */ 727 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 728 srb->sgentry[i].address = 729 htole32(srb->dmap->dm_segs[i].ds_addr); 730 srb->sgentry[i].length = 731 htole32(srb->dmap->dm_segs[i].ds_len); 732 } 733 srb->buflen = xs->datalen; 734 srb->sgcnt = srb->dmap->dm_nsegs; 735 } else { 736 srb->sgentry[0].address = 0; 737 srb->sgentry[0].length = 0; 738 srb->buflen = 0; 739 srb->sgcnt = 0; 740 } 741 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 742 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 743 744 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 745 746 srb->sgindex = 0; 747 srb->hastat = 0; 748 srb->tastat = 0; 749 srb->flag = 0; 750 751 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 752 if (sc->sc_actsrb == NULL) 753 trm_sched(sc); 754 splx(s); 755 756 if ((xs->xs_control & XS_CTL_POLL) != 0) { 757 int timeout = xs->timeout; 758 759 s = splbio(); 760 do { 761 while (--timeout) { 762 DELAY(1000); 763 if (bus_space_read_2(iot, ioh, 764 TRM_SCSI_STATUS) & SCSIINTERRUPT) 765 break; 766 } 767 if (timeout == 0) { 768 trm_timeout(srb); 769 break; 770 } else 771 trm_intr(sc); 772 } while ((xs->xs_status & XS_STS_DONE) == 0); 773 splx(s); 774 } 775 return; 776 777 case ADAPTER_REQ_GROW_RESOURCES: 778 /* XXX Not supported. */ 779 return; 780 781 case ADAPTER_REQ_SET_XFER_MODE: 782 { 783 struct trm_tinfo *ti; 784 struct scsipi_xfer_mode *xm; 785 786 xm = arg; 787 ti = &sc->sc_tinfo[xm->xm_target]; 788 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 789 790 #ifdef notyet 791 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 792 ti->flag |= USE_TAG_QUEUING; 793 else 794 #endif 795 ti->flag &= ~USE_TAG_QUEUING; 796 797 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 798 (sc->sc_config & HCC_WIDE_CARD) != 0 && 799 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 800 ti->flag |= WIDE_NEGO_ENABLE; 801 ti->flag &= ~WIDE_NEGO_DONE; 802 } 803 804 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 805 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 806 ti->flag |= SYNC_NEGO_ENABLE; 807 ti->flag &= ~SYNC_NEGO_DONE; 808 ti->period = trm_clock_period[0]; 809 } 810 811 /* 812 * If we're not going to negotiate, send the 813 * notification now, since it won't happen later. 814 */ 815 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 816 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 817 trm_update_xfer_mode(sc, xm->xm_target); 818 819 return; 820 } 821 } 822 } 823 824 static void 825 trm_update_xfer_mode(struct trm_softc *sc, int target) 826 { 827 struct scsipi_xfer_mode xm; 828 struct trm_tinfo *ti; 829 830 ti = &sc->sc_tinfo[target]; 831 xm.xm_target = target; 832 xm.xm_mode = 0; 833 xm.xm_period = 0; 834 xm.xm_offset = 0; 835 836 if ((ti->synctl & WIDE_SYNC) != 0) 837 xm.xm_mode |= PERIPH_CAP_WIDE16; 838 839 if (ti->period > 0) { 840 xm.xm_mode |= PERIPH_CAP_SYNC; 841 xm.xm_period = ti->period; 842 xm.xm_offset = ti->offset; 843 } 844 845 #ifdef notyet 846 if ((ti->flag & USE_TAG_QUEUING) != 0) 847 xm.xm_mode |= PERIPH_CAP_TQING; 848 #endif 849 850 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 851 } 852 853 static void 854 trm_sched(struct trm_softc *sc) 855 { 856 struct trm_srb *srb; 857 struct scsipi_periph *periph; 858 struct trm_tinfo *ti; 859 struct trm_linfo *li; 860 int s, lun, tag; 861 862 DPRINTF(("trm_sched...\n")); 863 864 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 865 periph = srb->xs->xs_periph; 866 ti = &sc->sc_tinfo[periph->periph_target]; 867 lun = periph->periph_lun; 868 869 /* select type of tag for this command */ 870 if ((ti->flag & NO_RESELECT) != 0 || 871 (ti->flag & USE_TAG_QUEUING) == 0 || 872 (srb->flag & AUTO_REQSENSE) != 0 || 873 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 874 tag = 0; 875 else 876 tag = srb->xs->xs_tag_type; 877 #if 0 878 /* XXX use tags for polled commands? */ 879 if (srb->xs->xs_control & XS_CTL_POLL) 880 tag = 0; 881 #endif 882 883 s = splbio(); 884 li = ti->linfo[lun]; 885 if (li == NULL) { 886 /* initialize lun info */ 887 if ((li = malloc(sizeof(*li), M_DEVBUF, 888 M_NOWAIT|M_ZERO)) == NULL) { 889 splx(s); 890 continue; 891 } 892 ti->linfo[lun] = li; 893 } 894 895 if (tag == 0) { 896 /* try to issue this srb as an un-tagged command */ 897 if (li->untagged == NULL) 898 li->untagged = srb; 899 } 900 if (li->untagged != NULL) { 901 tag = 0; 902 if (li->busy != 1 && li->used == 0) { 903 /* we need to issue the untagged command now */ 904 srb = li->untagged; 905 periph = srb->xs->xs_periph; 906 } else { 907 /* not ready yet */ 908 splx(s); 909 continue; 910 } 911 } 912 srb->tag[0] = tag; 913 if (tag != 0) { 914 li->queued[srb->xs->xs_tag_id] = srb; 915 srb->tag[1] = srb->xs->xs_tag_id; 916 li->used++; 917 } 918 919 if (li->untagged != NULL && li->busy != 1) { 920 li->busy = 1; 921 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 922 sc->sc_actsrb = srb; 923 trm_select(sc, srb); 924 splx(s); 925 break; 926 } 927 if (li->untagged == NULL && tag != 0) { 928 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 929 sc->sc_actsrb = srb; 930 trm_select(sc, srb); 931 splx(s); 932 break; 933 } else 934 splx(s); 935 } 936 } 937 938 static int 939 trm_select(struct trm_softc *sc, struct trm_srb *srb) 940 { 941 bus_space_tag_t iot = sc->sc_iot; 942 bus_space_handle_t ioh = sc->sc_ioh; 943 struct scsipi_periph *periph = srb->xs->xs_periph; 944 int target = periph->periph_target; 945 int lun = periph->periph_lun; 946 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 947 uint8_t scsicmd; 948 949 DPRINTF(("trm_select.....\n")); 950 951 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 952 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 953 trm_timeout, srb); 954 } 955 956 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 957 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 958 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 959 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 960 /* Flush FIFO */ 961 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 962 DELAY(10); 963 964 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 965 966 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 967 968 if (((ti->flag & WIDE_NEGO_ENABLE) && 969 (ti->flag & WIDE_NEGO_DONE) == 0) || 970 ((ti->flag & SYNC_NEGO_ENABLE) && 971 (ti->flag & SYNC_NEGO_DONE) == 0)) { 972 sc->sc_state = TRM_MSGOUT; 973 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 974 MSG_IDENTIFY(lun, 0)); 975 bus_space_write_multi_1(iot, ioh, 976 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 977 /* it's important for atn stop */ 978 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 979 DO_DATALATCH | DO_HWRESELECT); 980 /* SCSI command */ 981 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 982 DPRINTF(("select with SEL_ATNSTOP\n")); 983 return (0); 984 } 985 986 if (srb->tag[0] != 0) { 987 /* Send identify message */ 988 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 989 MSG_IDENTIFY(lun, 1)); 990 /* Send Tag id */ 991 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 993 scsicmd = SCMD_SEL_ATN3; 994 DPRINTF(("select with SEL_ATN3\n")); 995 } else { 996 /* Send identify message */ 997 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 998 MSG_IDENTIFY(lun, 999 (ti->flag & NO_RESELECT) == 0 && 1000 (srb->flag & AUTO_REQSENSE) == 0 && 1001 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1002 scsicmd = SCMD_SEL_ATN; 1003 DPRINTF(("select with SEL_ATN\n")); 1004 } 1005 sc->sc_state = TRM_START; 1006 1007 /* 1008 * Send CDB ..command block... 1009 */ 1010 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1011 1012 /* 1013 * If trm_select returns 0: current interrupt status 1014 * is interrupt enable. It's said that SCSI processor is 1015 * unoccupied. 1016 */ 1017 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1018 /* SCSI command */ 1019 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1020 return (0); 1021 } 1022 1023 /* 1024 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1025 */ 1026 static void 1027 trm_reset(struct trm_softc *sc) 1028 { 1029 bus_space_tag_t iot = sc->sc_iot; 1030 bus_space_handle_t ioh = sc->sc_ioh; 1031 int s; 1032 1033 DPRINTF(("trm_reset.........\n")); 1034 1035 s = splbio(); 1036 1037 /* disable SCSI and DMA interrupt */ 1038 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1039 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1040 1041 trm_reset_scsi_bus(sc); 1042 DELAY(100000); 1043 1044 /* Enable SCSI interrupt */ 1045 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1046 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1047 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1048 1049 /* Enable DMA interrupt */ 1050 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1051 1052 /* Clear DMA FIFO */ 1053 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1054 1055 /* Clear SCSI FIFO */ 1056 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1057 1058 sc->sc_actsrb = NULL; 1059 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1060 1061 splx(s); 1062 } 1063 1064 static void 1065 trm_timeout(void *arg) 1066 { 1067 struct trm_srb *srb = (struct trm_srb *)arg; 1068 struct scsipi_xfer *xs; 1069 struct scsipi_periph *periph; 1070 struct trm_softc *sc; 1071 int s; 1072 1073 if (srb == NULL) { 1074 printf("trm_timeout called with srb == NULL\n"); 1075 return; 1076 } 1077 1078 xs = srb->xs; 1079 if (xs == NULL) { 1080 printf("trm_timeout called with xs == NULL\n"); 1081 return; 1082 } 1083 1084 periph = xs->xs_periph; 1085 scsipi_printaddr(xs->xs_periph); 1086 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1087 1088 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1089 1090 trm_reset_scsi_bus(sc); 1091 s = splbio(); 1092 srb->flag |= SRB_TIMEOUT; 1093 trm_done(sc, srb); 1094 /* XXX needs more.. */ 1095 splx(s); 1096 } 1097 1098 /* 1099 * Catch an interrupt from the adapter 1100 * Process pending device interrupts. 1101 */ 1102 static int 1103 trm_intr(void *arg) 1104 { 1105 bus_space_tag_t iot; 1106 bus_space_handle_t ioh; 1107 struct trm_softc *sc; 1108 int intstat, stat; 1109 1110 DPRINTF(("trm_intr......\n")); 1111 sc = (struct trm_softc *)arg; 1112 if (sc == NULL) 1113 return (0); 1114 1115 iot = sc->sc_iot; 1116 ioh = sc->sc_ioh; 1117 1118 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1119 if ((stat & SCSIINTERRUPT) == 0) 1120 return (0); 1121 1122 DPRINTF(("stat = %04x, ", stat)); 1123 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1124 1125 DPRINTF(("intstat=%02x, ", intstat)); 1126 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1127 DPRINTF(("\n")); 1128 trm_disconnect(sc); 1129 return (1); 1130 } 1131 if (intstat & INT_RESELECTED) { 1132 DPRINTF(("\n")); 1133 trm_reselect(sc); 1134 return (1); 1135 } 1136 if (intstat & INT_SCSIRESET) { 1137 DPRINTF(("\n")); 1138 trm_scsi_reset_detect(sc); 1139 return (1); 1140 } 1141 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1142 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1143 sc->sc_phase, sc->sc_state)); 1144 /* 1145 * software sequential machine 1146 */ 1147 1148 /* 1149 * call phase0 functions... "phase entry" handle 1150 * every phase before start transfer 1151 */ 1152 switch (sc->sc_phase) { 1153 case PH_DATA_OUT: 1154 trm_dataout_phase0(sc, stat); 1155 break; 1156 case PH_DATA_IN: 1157 trm_datain_phase0(sc, stat); 1158 break; 1159 case PH_COMMAND: 1160 break; 1161 case PH_STATUS: 1162 trm_status_phase0(sc); 1163 stat = PH_BUS_FREE; 1164 break; 1165 case PH_MSG_OUT: 1166 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1167 sc->sc_state == TRM_ABORT_SENT) 1168 stat = PH_BUS_FREE; 1169 break; 1170 case PH_MSG_IN: 1171 trm_msgin_phase0(sc); 1172 stat = PH_BUS_FREE; 1173 break; 1174 case PH_BUS_FREE: 1175 break; 1176 default: 1177 printf("%s: unexpected phase in trm_intr() phase0\n", 1178 sc->sc_dev.dv_xname); 1179 break; 1180 } 1181 1182 sc->sc_phase = stat & PHASEMASK; 1183 1184 switch (sc->sc_phase) { 1185 case PH_DATA_OUT: 1186 trm_dataio_xfer(sc, XFERDATAOUT); 1187 break; 1188 case PH_DATA_IN: 1189 trm_dataio_xfer(sc, XFERDATAIN); 1190 break; 1191 case PH_COMMAND: 1192 trm_command_phase1(sc); 1193 break; 1194 case PH_STATUS: 1195 trm_status_phase1(sc); 1196 break; 1197 case PH_MSG_OUT: 1198 trm_msgout_phase1(sc); 1199 break; 1200 case PH_MSG_IN: 1201 trm_msgin_phase1(sc); 1202 break; 1203 case PH_BUS_FREE: 1204 break; 1205 default: 1206 printf("%s: unexpected phase in trm_intr() phase1\n", 1207 sc->sc_dev.dv_xname); 1208 break; 1209 } 1210 1211 return (1); 1212 } 1213 return (0); 1214 } 1215 1216 static void 1217 trm_msgout_phase1(struct trm_softc *sc) 1218 { 1219 bus_space_tag_t iot = sc->sc_iot; 1220 bus_space_handle_t ioh = sc->sc_ioh; 1221 struct trm_srb *srb; 1222 struct scsipi_periph *periph; 1223 struct trm_tinfo *ti; 1224 1225 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1226 1227 srb = sc->sc_actsrb; 1228 1229 /* message out phase */ 1230 if (srb != NULL) { 1231 periph = srb->xs->xs_periph; 1232 ti = &sc->sc_tinfo[periph->periph_target]; 1233 1234 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1235 (ti->flag & WIDE_NEGO_ENABLE)) { 1236 /* send WDTR */ 1237 ti->flag &= ~SYNC_NEGO_DONE; 1238 1239 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1240 sc->sc_msgbuf[1] = MSG_EXTENDED; 1241 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1242 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1243 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1244 sc->sc_msgcnt = 5; 1245 1246 ti->flag |= WIDE_NEGO_DOING; 1247 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1248 (ti->flag & SYNC_NEGO_ENABLE)) { 1249 /* send SDTR */ 1250 int cnt = 0; 1251 1252 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1253 sc->sc_msgbuf[cnt++] = 1254 MSG_IDENTIFY(periph->periph_lun, 0); 1255 1256 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1257 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1258 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1259 sc->sc_msgbuf[cnt++] = ti->period; 1260 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1261 sc->sc_msgcnt = cnt; 1262 ti->flag |= SYNC_NEGO_DOING; 1263 } 1264 } 1265 if (sc->sc_msgcnt == 0) { 1266 sc->sc_msgbuf[0] = MSG_ABORT; 1267 sc->sc_msgcnt = 1; 1268 sc->sc_state = TRM_ABORT_SENT; 1269 } 1270 1271 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1272 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1273 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1274 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1275 1276 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1277 sc->sc_msgbuf, sc->sc_msgcnt); 1278 sc->sc_msgcnt = 0; 1279 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1280 1281 /* it's important for atn stop */ 1282 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1283 1284 /* 1285 * SCSI command 1286 */ 1287 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1288 } 1289 1290 static void 1291 trm_command_phase1(struct trm_softc *sc) 1292 { 1293 bus_space_tag_t iot = sc->sc_iot; 1294 bus_space_handle_t ioh = sc->sc_ioh; 1295 struct trm_srb *srb; 1296 1297 srb = sc->sc_actsrb; 1298 if (srb == NULL) { 1299 DPRINTF(("trm_command_phase1: no active srb\n")); 1300 return; 1301 } 1302 1303 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1304 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1305 1306 sc->sc_state = TRM_COMMAND; 1307 /* it's important for atn stop */ 1308 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1309 1310 /* 1311 * SCSI command 1312 */ 1313 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1314 } 1315 1316 static void 1317 trm_dataout_phase0(struct trm_softc *sc, int stat) 1318 { 1319 bus_space_tag_t iot = sc->sc_iot; 1320 bus_space_handle_t ioh = sc->sc_ioh; 1321 struct trm_srb *srb; 1322 struct scsipi_periph *periph; 1323 struct trm_tinfo *ti; 1324 struct trm_sg_entry *sg; 1325 int sgindex; 1326 uint32_t xferlen, leftcnt = 0; 1327 1328 if (sc->sc_state == TRM_XFERPAD) 1329 return; 1330 1331 srb = sc->sc_actsrb; 1332 if (srb == NULL) { 1333 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1334 return; 1335 } 1336 periph = srb->xs->xs_periph; 1337 ti = &sc->sc_tinfo[periph->periph_target]; 1338 1339 if ((stat & PARITYERROR) != 0) 1340 srb->flag |= PARITY_ERROR; 1341 1342 if ((stat & SCSIXFERDONE) == 0) { 1343 /* 1344 * when data transfer from DMA FIFO to SCSI FIFO 1345 * if there was some data left in SCSI FIFO 1346 */ 1347 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1348 SCSI_FIFOCNT_MASK; 1349 if (ti->synctl & WIDE_SYNC) 1350 /* 1351 * if WIDE scsi SCSI FIFOCNT unit is word 1352 * so need to * 2 1353 */ 1354 leftcnt <<= 1; 1355 } 1356 /* 1357 * calculate all the residue data that was not yet transferred 1358 * SCSI transfer counter + left in SCSI FIFO data 1359 * 1360 * .....TRM_SCSI_XCNT (24bits) 1361 * The counter always decrements by one for every SCSI 1362 * byte transfer. 1363 * .....TRM_SCSI_FIFOCNT ( 5bits) 1364 * The counter is SCSI FIFO offset counter 1365 */ 1366 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1367 if (leftcnt == 1) { 1368 leftcnt = 0; 1369 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1370 } 1371 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1372 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1373 DMAXFERCOMP) == 0) 1374 ; /* XXX needs timeout */ 1375 1376 srb->buflen = 0; 1377 } else { 1378 /* Update SG list */ 1379 1380 /* 1381 * if transfer not yet complete 1382 * there were some data residue in SCSI FIFO or 1383 * SCSI transfer counter not empty 1384 */ 1385 if (srb->buflen != leftcnt) { 1386 /* data that had transferred length */ 1387 xferlen = srb->buflen - leftcnt; 1388 1389 /* next time to be transferred length */ 1390 srb->buflen = leftcnt; 1391 1392 /* 1393 * parsing from last time disconnect sgindex 1394 */ 1395 sg = srb->sgentry + srb->sgindex; 1396 for (sgindex = srb->sgindex; 1397 sgindex < srb->sgcnt; 1398 sgindex++, sg++) { 1399 /* 1400 * find last time which SG transfer 1401 * be disconnect 1402 */ 1403 if (xferlen >= le32toh(sg->length)) 1404 xferlen -= le32toh(sg->length); 1405 else { 1406 /* 1407 * update last time 1408 * disconnected SG list 1409 */ 1410 /* residue data length */ 1411 sg->length = 1412 htole32(le32toh(sg->length) 1413 - xferlen); 1414 /* residue data pointer */ 1415 sg->address = 1416 htole32(le32toh(sg->address) 1417 + xferlen); 1418 srb->sgindex = sgindex; 1419 break; 1420 } 1421 } 1422 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1423 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1424 } 1425 } 1426 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1427 } 1428 1429 static void 1430 trm_datain_phase0(struct trm_softc *sc, int stat) 1431 { 1432 bus_space_tag_t iot = sc->sc_iot; 1433 bus_space_handle_t ioh = sc->sc_ioh; 1434 struct trm_srb *srb; 1435 struct trm_sg_entry *sg; 1436 int sgindex; 1437 uint32_t xferlen, leftcnt = 0; 1438 1439 if (sc->sc_state == TRM_XFERPAD) 1440 return; 1441 1442 srb = sc->sc_actsrb; 1443 if (srb == NULL) { 1444 DPRINTF(("trm_datain_phase0: no active srb\n")); 1445 return; 1446 } 1447 1448 if (stat & PARITYERROR) 1449 srb->flag |= PARITY_ERROR; 1450 1451 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1452 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1453 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1454 DMAXFERCOMP) == 0) 1455 ; /* XXX needs timeout */ 1456 1457 srb->buflen = 0; 1458 } else { /* phase changed */ 1459 /* 1460 * parsing the case: 1461 * when a transfer not yet complete 1462 * but be disconnected by upper layer 1463 * if transfer not yet complete 1464 * there were some data residue in SCSI FIFO or 1465 * SCSI transfer counter not empty 1466 */ 1467 if (srb->buflen != leftcnt) { 1468 /* 1469 * data that had transferred length 1470 */ 1471 xferlen = srb->buflen - leftcnt; 1472 1473 /* 1474 * next time to be transferred length 1475 */ 1476 srb->buflen = leftcnt; 1477 1478 /* 1479 * parsing from last time disconnect sgindex 1480 */ 1481 sg = srb->sgentry + srb->sgindex; 1482 for (sgindex = srb->sgindex; 1483 sgindex < srb->sgcnt; 1484 sgindex++, sg++) { 1485 /* 1486 * find last time which SG transfer 1487 * be disconnect 1488 */ 1489 if (xferlen >= le32toh(sg->length)) 1490 xferlen -= le32toh(sg->length); 1491 else { 1492 /* 1493 * update last time 1494 * disconnected SG list 1495 */ 1496 /* residue data length */ 1497 sg->length = 1498 htole32(le32toh(sg->length) 1499 - xferlen); 1500 /* residue data pointer */ 1501 sg->address = 1502 htole32(le32toh(sg->address) 1503 + xferlen); 1504 srb->sgindex = sgindex; 1505 break; 1506 } 1507 } 1508 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1509 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1510 } 1511 } 1512 } 1513 1514 static void 1515 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1516 { 1517 bus_space_tag_t iot = sc->sc_iot; 1518 bus_space_handle_t ioh = sc->sc_ioh; 1519 struct trm_srb *srb; 1520 struct scsipi_periph *periph; 1521 struct trm_tinfo *ti; 1522 1523 srb = sc->sc_actsrb; 1524 if (srb == NULL) { 1525 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1526 return; 1527 } 1528 periph = srb->xs->xs_periph; 1529 ti = &sc->sc_tinfo[periph->periph_target]; 1530 1531 if (srb->sgindex < srb->sgcnt) { 1532 if (srb->buflen > 0) { 1533 /* 1534 * load what physical address of Scatter/Gather 1535 * list table want to be transfer 1536 */ 1537 sc->sc_state = TRM_DATA_XFER; 1538 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1539 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1540 srb->sgaddr + 1541 srb->sgindex * sizeof(struct trm_sg_entry)); 1542 /* 1543 * load how many bytes in the Scatter/Gather list table 1544 */ 1545 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1546 (srb->sgcnt - srb->sgindex) 1547 * sizeof(struct trm_sg_entry)); 1548 /* 1549 * load total xfer length (24bits) max value 16Mbyte 1550 */ 1551 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1552 /* Start DMA transfer */ 1553 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1554 iodir | SGXFER); 1555 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1556 STARTDMAXFER); 1557 1558 /* Start SCSI transfer */ 1559 /* it's important for atn stop */ 1560 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1561 DO_DATALATCH); 1562 1563 /* 1564 * SCSI command 1565 */ 1566 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1567 (iodir == XFERDATAOUT) ? 1568 SCMD_DMA_OUT : SCMD_DMA_IN); 1569 } else { /* xfer pad */ 1570 if (srb->sgcnt) { 1571 srb->hastat = H_OVER_UNDER_RUN; 1572 } 1573 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1574 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1575 1576 if (iodir == XFERDATAOUT) 1577 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1578 else 1579 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1580 1581 sc->sc_state = TRM_XFERPAD; 1582 /* it's important for atn stop */ 1583 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1584 DO_DATALATCH); 1585 1586 /* 1587 * SCSI command 1588 */ 1589 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1590 (iodir == XFERDATAOUT) ? 1591 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1592 } 1593 } 1594 } 1595 1596 static void 1597 trm_status_phase0(struct trm_softc *sc) 1598 { 1599 bus_space_tag_t iot = sc->sc_iot; 1600 bus_space_handle_t ioh = sc->sc_ioh; 1601 struct trm_srb *srb; 1602 1603 srb = sc->sc_actsrb; 1604 if (srb == NULL) { 1605 DPRINTF(("trm_status_phase0: no active srb\n")); 1606 return; 1607 } 1608 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1609 sc->sc_state = TRM_COMPLETED; 1610 /* it's important for atn stop */ 1611 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1612 1613 /* 1614 * SCSI command 1615 */ 1616 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1617 } 1618 1619 static void 1620 trm_status_phase1(struct trm_softc *sc) 1621 { 1622 bus_space_tag_t iot = sc->sc_iot; 1623 bus_space_handle_t ioh = sc->sc_ioh; 1624 1625 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1626 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1627 & SCSI_FIFO_EMPTY) == 0) 1628 bus_space_write_2(iot, ioh, 1629 TRM_SCSI_CONTROL, DO_CLRFIFO); 1630 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1631 & DMA_FIFO_EMPTY) == 0) 1632 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1633 } else { 1634 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1635 & DMA_FIFO_EMPTY) == 0) 1636 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1637 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1638 & SCSI_FIFO_EMPTY) == 0) 1639 bus_space_write_2(iot, ioh, 1640 TRM_SCSI_CONTROL, DO_CLRFIFO); 1641 } 1642 sc->sc_state = TRM_STATUS; 1643 /* it's important for atn stop */ 1644 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1645 1646 /* 1647 * SCSI command 1648 */ 1649 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1650 } 1651 1652 static void 1653 trm_msgin_phase0(struct trm_softc *sc) 1654 { 1655 bus_space_tag_t iot = sc->sc_iot; 1656 bus_space_handle_t ioh = sc->sc_ioh; 1657 struct trm_srb *srb; 1658 struct scsipi_periph *periph; 1659 struct trm_tinfo *ti; 1660 int index; 1661 uint8_t msgin_code; 1662 1663 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1664 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1665 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1666 switch (msgin_code) { 1667 case MSG_DISCONNECT: 1668 sc->sc_state = TRM_DISCONNECTED; 1669 break; 1670 1671 case MSG_SAVEDATAPOINTER: 1672 break; 1673 1674 case MSG_EXTENDED: 1675 case MSG_SIMPLE_Q_TAG: 1676 case MSG_HEAD_OF_Q_TAG: 1677 case MSG_ORDERED_Q_TAG: 1678 sc->sc_state = TRM_EXTEND_MSGIN; 1679 /* extended message (01h) */ 1680 sc->sc_msgbuf[0] = msgin_code; 1681 1682 sc->sc_msgcnt = 1; 1683 /* extended message length (n) */ 1684 sc->sc_msg = &sc->sc_msgbuf[1]; 1685 1686 break; 1687 case MSG_MESSAGE_REJECT: 1688 /* Reject message */ 1689 srb = sc->sc_actsrb; 1690 if (srb == NULL) { 1691 DPRINTF(("trm_msgin_phase0: " 1692 " message reject without actsrb\n")); 1693 break; 1694 } 1695 periph = srb->xs->xs_periph; 1696 ti = &sc->sc_tinfo[periph->periph_target]; 1697 1698 if (ti->flag & WIDE_NEGO_ENABLE) { 1699 /* do wide nego reject */ 1700 ti->flag |= WIDE_NEGO_DONE; 1701 ti->flag &= 1702 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1703 if ((ti->flag & SYNC_NEGO_ENABLE) && 1704 (ti->flag & SYNC_NEGO_DONE) == 0) { 1705 /* Set ATN, in case ATN was clear */ 1706 sc->sc_state = TRM_MSGOUT; 1707 bus_space_write_2(iot, ioh, 1708 TRM_SCSI_CONTROL, DO_SETATN); 1709 } else 1710 /* Clear ATN */ 1711 bus_space_write_2(iot, ioh, 1712 TRM_SCSI_CONTROL, DO_CLRATN); 1713 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1714 /* do sync nego reject */ 1715 bus_space_write_2(iot, ioh, 1716 TRM_SCSI_CONTROL, DO_CLRATN); 1717 if (ti->flag & SYNC_NEGO_DOING) { 1718 ti->flag &=~(SYNC_NEGO_ENABLE | 1719 SYNC_NEGO_DONE); 1720 ti->synctl = 0; 1721 ti->offset = 0; 1722 bus_space_write_1(iot, ioh, 1723 TRM_SCSI_SYNC, ti->synctl); 1724 bus_space_write_1(iot, ioh, 1725 TRM_SCSI_OFFSET, ti->offset); 1726 } 1727 } 1728 break; 1729 1730 case MSG_IGN_WIDE_RESIDUE: 1731 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1732 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1733 break; 1734 1735 default: 1736 /* 1737 * Restore data pointer message 1738 * Save data pointer message 1739 * Completion message 1740 * NOP message 1741 */ 1742 break; 1743 } 1744 } else { 1745 /* 1746 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1747 * Parsing incoming extented messages 1748 */ 1749 *sc->sc_msg++ = msgin_code; 1750 sc->sc_msgcnt++; 1751 1752 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1753 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1754 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1755 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1756 1757 switch (sc->sc_msgbuf[0]) { 1758 case MSG_SIMPLE_Q_TAG: 1759 case MSG_HEAD_OF_Q_TAG: 1760 case MSG_ORDERED_Q_TAG: 1761 /* 1762 * is QUEUE tag message : 1763 * 1764 * byte 0: 1765 * HEAD QUEUE TAG (20h) 1766 * ORDERED QUEUE TAG (21h) 1767 * SIMPLE QUEUE TAG (22h) 1768 * byte 1: 1769 * Queue tag (00h - FFh) 1770 */ 1771 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1772 /* XXX XXX XXX */ 1773 struct trm_linfo *li; 1774 int tagid; 1775 1776 sc->sc_flag &= ~WAIT_TAGMSG; 1777 tagid = sc->sc_msgbuf[1]; 1778 ti = &sc->sc_tinfo[sc->resel_target]; 1779 li = ti->linfo[sc->resel_lun]; 1780 srb = li->queued[tagid]; 1781 if (srb != NULL) { 1782 sc->sc_actsrb = srb; 1783 sc->sc_state = TRM_DATA_XFER; 1784 break; 1785 } else { 1786 printf("%s: invalid tag id\n", 1787 sc->sc_dev.dv_xname); 1788 } 1789 1790 sc->sc_state = TRM_UNEXPECT_RESEL; 1791 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1792 sc->sc_msgcnt = 1; 1793 bus_space_write_2(iot, ioh, 1794 TRM_SCSI_CONTROL, DO_SETATN); 1795 } else 1796 sc->sc_state = TRM_IDLE; 1797 break; 1798 1799 case MSG_EXTENDED: 1800 srb = sc->sc_actsrb; 1801 if (srb == NULL) { 1802 DPRINTF(("trm_msgin_phase0: " 1803 "extended message without actsrb\n")); 1804 break; 1805 } 1806 periph = srb->xs->xs_periph; 1807 ti = &sc->sc_tinfo[periph->periph_target]; 1808 1809 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1810 sc->sc_msgcnt == 4) { 1811 /* 1812 * is Wide data xfer Extended message : 1813 * ====================================== 1814 * WIDE DATA TRANSFER REQUEST 1815 * ====================================== 1816 * byte 0 : Extended message (01h) 1817 * byte 1 : Extended message length (02h) 1818 * byte 2 : WIDE DATA TRANSFER code (03h) 1819 * byte 3 : Transfer width exponent 1820 */ 1821 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1822 /* Length is wrong, reject it */ 1823 ti->flag &= ~(WIDE_NEGO_ENABLE | 1824 WIDE_NEGO_DONE); 1825 sc->sc_state = TRM_MSGOUT; 1826 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1827 sc->sc_msgcnt = 1; 1828 bus_space_write_2(iot, ioh, 1829 TRM_SCSI_CONTROL, DO_SETATN); 1830 break; 1831 } 1832 1833 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1834 sc->sc_msgbuf[3] = 1835 MSG_EXT_WDTR_BUS_8_BIT; 1836 1837 if (sc->sc_msgbuf[3] > 1838 MSG_EXT_WDTR_BUS_32_BIT) { 1839 /* reject_msg: */ 1840 ti->flag &= ~(WIDE_NEGO_ENABLE | 1841 WIDE_NEGO_DONE); 1842 sc->sc_state = TRM_MSGOUT; 1843 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1844 sc->sc_msgcnt = 1; 1845 bus_space_write_2(iot, ioh, 1846 TRM_SCSI_CONTROL, DO_SETATN); 1847 break; 1848 } 1849 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1850 /* do 16 bits */ 1851 sc->sc_msgbuf[3] = 1852 MSG_EXT_WDTR_BUS_16_BIT; 1853 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1854 ti->flag |= WIDE_NEGO_DONE; 1855 ti->flag &= ~(SYNC_NEGO_DONE | 1856 WIDE_NEGO_ENABLE); 1857 if (sc->sc_msgbuf[3] != 1858 MSG_EXT_WDTR_BUS_8_BIT) 1859 /* is Wide data xfer */ 1860 ti->synctl |= WIDE_SYNC; 1861 trm_update_xfer_mode(sc, 1862 periph->periph_target); 1863 } 1864 1865 sc->sc_state = TRM_MSGOUT; 1866 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1867 DO_SETATN); 1868 break; 1869 1870 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1871 sc->sc_msgcnt == 5) { 1872 /* 1873 * is 8bit transfer Extended message : 1874 * ================================= 1875 * SYNCHRONOUS DATA TRANSFER REQUEST 1876 * ================================= 1877 * byte 0 : Extended message (01h) 1878 * byte 1 : Extended message length (03) 1879 * byte 2 : SYNC DATA TRANSFER code (01h) 1880 * byte 3 : Transfer period factor 1881 * byte 4 : REQ/ACK offset 1882 */ 1883 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1884 /* reject_msg */ 1885 sc->sc_state = TRM_MSGOUT; 1886 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1887 sc->sc_msgcnt = 1; 1888 bus_space_write_2(iot, ioh, 1889 TRM_SCSI_CONTROL, DO_SETATN); 1890 break; 1891 } 1892 1893 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1894 ti->flag &= 1895 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1896 ti->flag |= SYNC_NEGO_DONE; 1897 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1898 sc->sc_msgbuf[3] = 0; 1899 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1900 sc->sc_msgbuf[4] = 1901 TRM_MAX_OFFSET; 1902 1903 if (sc->sc_msgbuf[3] == 0 || 1904 sc->sc_msgbuf[4] == 0) { 1905 /* set async */ 1906 ti->synctl = 0; 1907 ti->offset = 0; 1908 } else { 1909 /* set sync */ 1910 /* Transfer period factor */ 1911 ti->period = sc->sc_msgbuf[3]; 1912 /* REQ/ACK offset */ 1913 ti->offset = sc->sc_msgbuf[4]; 1914 for (index = 0; 1915 index < NPERIOD; 1916 index++) 1917 if (ti->period <= 1918 trm_clock_period[ 1919 index]) 1920 break; 1921 1922 ti->synctl |= ALT_SYNC | index; 1923 } 1924 /* 1925 * program SCSI control register 1926 */ 1927 bus_space_write_1(iot, ioh, 1928 TRM_SCSI_SYNC, ti->synctl); 1929 bus_space_write_1(iot, ioh, 1930 TRM_SCSI_OFFSET, ti->offset); 1931 trm_update_xfer_mode(sc, 1932 periph->periph_target); 1933 } 1934 sc->sc_state = TRM_IDLE; 1935 } 1936 break; 1937 default: 1938 break; 1939 } 1940 } 1941 1942 /* it's important for atn stop */ 1943 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1944 1945 /* 1946 * SCSI command 1947 */ 1948 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1949 } 1950 1951 static void 1952 trm_msgin_phase1(struct trm_softc *sc) 1953 { 1954 bus_space_tag_t iot = sc->sc_iot; 1955 bus_space_handle_t ioh = sc->sc_ioh; 1956 1957 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1958 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1959 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1960 sc->sc_state = TRM_MSGIN; 1961 } 1962 1963 /* it's important for atn stop */ 1964 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1965 1966 /* 1967 * SCSI command 1968 */ 1969 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1970 } 1971 1972 static void 1973 trm_disconnect(struct trm_softc *sc) 1974 { 1975 bus_space_tag_t iot = sc->sc_iot; 1976 bus_space_handle_t ioh = sc->sc_ioh; 1977 struct trm_srb *srb; 1978 int s; 1979 1980 s = splbio(); 1981 1982 srb = sc->sc_actsrb; 1983 DPRINTF(("trm_disconnect...............\n")); 1984 1985 if (srb == NULL) { 1986 DPRINTF(("trm_disconnect: no active srb\n")); 1987 DELAY(1000); /* 1 msec */ 1988 1989 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1990 DO_CLRFIFO | DO_HWRESELECT); 1991 return; 1992 } 1993 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1994 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1995 DO_CLRFIFO | DO_HWRESELECT); 1996 DELAY(100); 1997 1998 switch (sc->sc_state) { 1999 case TRM_UNEXPECT_RESEL: 2000 sc->sc_state = TRM_IDLE; 2001 break; 2002 2003 case TRM_ABORT_SENT: 2004 goto finish; 2005 2006 case TRM_START: 2007 case TRM_MSGOUT: 2008 { 2009 /* Selection time out - discard all LUNs if empty */ 2010 struct scsipi_periph *periph; 2011 struct trm_tinfo *ti; 2012 struct trm_linfo *li; 2013 int lun; 2014 2015 DPRINTF(("selection timeout\n")); 2016 2017 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2018 2019 periph = srb->xs->xs_periph; 2020 ti = &sc->sc_tinfo[periph->periph_target]; 2021 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2022 li = ti->linfo[lun]; 2023 if (li != NULL && 2024 li->untagged == NULL && li->used == 0) { 2025 ti->linfo[lun] = NULL; 2026 free(li, M_DEVBUF); 2027 } 2028 } 2029 } 2030 goto finish; 2031 2032 case TRM_DISCONNECTED: 2033 sc->sc_actsrb = NULL; 2034 sc->sc_state = TRM_IDLE; 2035 goto sched; 2036 2037 case TRM_COMPLETED: 2038 goto finish; 2039 } 2040 2041 out: 2042 splx(s); 2043 return; 2044 2045 finish: 2046 sc->sc_state = TRM_IDLE; 2047 trm_done(sc, srb); 2048 goto out; 2049 2050 sched: 2051 trm_sched(sc); 2052 goto out; 2053 } 2054 2055 static void 2056 trm_reselect(struct trm_softc *sc) 2057 { 2058 bus_space_tag_t iot = sc->sc_iot; 2059 bus_space_handle_t ioh = sc->sc_ioh; 2060 struct trm_tinfo *ti; 2061 struct trm_linfo *li; 2062 int target, lun; 2063 2064 DPRINTF(("trm_reselect.................\n")); 2065 2066 if (sc->sc_actsrb != NULL) { 2067 /* arbitration lost but reselection win */ 2068 sc->sc_state = TRM_READY; 2069 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2070 ti = &sc->sc_tinfo[target]; 2071 } else { 2072 /* Read Reselected Target Id and LUN */ 2073 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2074 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2075 ti = &sc->sc_tinfo[target]; 2076 li = ti->linfo[lun]; 2077 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2078 2079 /* 2080 * Check to see if we are running an un-tagged command. 2081 * Otherwise ack the IDENTIFY and wait for a tag message. 2082 */ 2083 if (li != NULL) { 2084 if (li->untagged != NULL && li->busy) { 2085 sc->sc_actsrb = li->untagged; 2086 sc->sc_state = TRM_DATA_XFER; 2087 } else { 2088 sc->resel_target = target; 2089 sc->resel_lun = lun; 2090 /* XXX XXX XXX */ 2091 sc->sc_flag |= WAIT_TAGMSG; 2092 } 2093 } 2094 2095 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2096 sc->sc_actsrb == NULL) { 2097 printf("%s: reselect from target %d lun %d " 2098 "without nexus; sending abort\n", 2099 sc->sc_dev.dv_xname, target, lun); 2100 sc->sc_state = TRM_UNEXPECT_RESEL; 2101 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2102 sc->sc_msgcnt = 1; 2103 bus_space_write_2(iot, ioh, 2104 TRM_SCSI_CONTROL, DO_SETATN); 2105 } 2106 } 2107 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2108 /* 2109 * Program HA ID, target ID, period and offset 2110 */ 2111 /* target ID */ 2112 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2113 2114 /* host ID */ 2115 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2116 2117 /* period */ 2118 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2119 2120 /* offset */ 2121 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2122 2123 /* it's important for atn stop */ 2124 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2125 /* 2126 * SCSI command 2127 */ 2128 /* to rls the /ACK signal */ 2129 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2130 } 2131 2132 /* 2133 * Complete execution of a SCSI command 2134 * Signal completion to the generic SCSI driver 2135 */ 2136 static void 2137 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2138 { 2139 struct scsipi_xfer *xs = srb->xs; 2140 2141 DPRINTF(("trm_done..................\n")); 2142 2143 if (xs == NULL) 2144 return; 2145 2146 if ((xs->xs_control & XS_CTL_POLL) == 0) 2147 callout_stop(&xs->xs_callout); 2148 2149 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2150 srb->flag & AUTO_REQSENSE) { 2151 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2152 srb->dmap->dm_mapsize, 2153 ((xs->xs_control & XS_CTL_DATA_IN) || 2154 (srb->flag & AUTO_REQSENSE)) ? 2155 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2156 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2157 } 2158 2159 /* 2160 * target status 2161 */ 2162 xs->status = srb->tastat; 2163 2164 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2165 2166 switch (xs->status) { 2167 case SCSI_OK: 2168 /* 2169 * process initiator status...... 2170 * Adapter (initiator) status 2171 */ 2172 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2173 printf("%s: over/under run error\n", 2174 sc->sc_dev.dv_xname); 2175 srb->tastat = 0; 2176 /* Illegal length (over/under run) */ 2177 xs->error = XS_DRIVER_STUFFUP; 2178 } else if ((srb->flag & PARITY_ERROR) != 0) { 2179 printf("%s: parity error\n", 2180 sc->sc_dev.dv_xname); 2181 /* Driver failed to perform operation */ 2182 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2183 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2184 xs->resid = srb->buflen; 2185 xs->error = XS_TIMEOUT; 2186 } else { 2187 /* No error */ 2188 xs->resid = srb->buflen; 2189 srb->hastat = 0; 2190 if (srb->flag & AUTO_REQSENSE) { 2191 /* there is no error, (sense is invalid) */ 2192 xs->error = XS_SENSE; 2193 } else { 2194 srb->tastat = 0; 2195 xs->error = XS_NOERROR; 2196 } 2197 } 2198 break; 2199 2200 case SCSI_CHECK: 2201 if ((srb->flag & AUTO_REQSENSE) != 0 || 2202 trm_request_sense(sc, srb) != 0) { 2203 printf("%s: request sense failed\n", 2204 sc->sc_dev.dv_xname); 2205 xs->error = XS_DRIVER_STUFFUP; 2206 break; 2207 } 2208 xs->error = XS_SENSE; 2209 return; 2210 2211 case SCSI_SEL_TIMEOUT: 2212 srb->hastat = H_SEL_TIMEOUT; 2213 srb->tastat = 0; 2214 xs->error = XS_SELTIMEOUT; 2215 break; 2216 2217 case SCSI_QUEUE_FULL: 2218 case SCSI_BUSY: 2219 xs->error = XS_BUSY; 2220 break; 2221 2222 case SCSI_RESV_CONFLICT: 2223 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2224 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2225 xs->error = XS_BUSY; 2226 break; 2227 2228 default: 2229 srb->hastat = 0; 2230 printf("%s: trm_done(): unknown status = %02x\n", 2231 sc->sc_dev.dv_xname, xs->status); 2232 xs->error = XS_DRIVER_STUFFUP; 2233 break; 2234 } 2235 2236 trm_dequeue(sc, srb); 2237 if (srb == sc->sc_actsrb) { 2238 sc->sc_actsrb = NULL; 2239 trm_sched(sc); 2240 } 2241 2242 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2243 2244 /* Notify cmd done */ 2245 scsipi_done(xs); 2246 } 2247 2248 static int 2249 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2250 { 2251 struct scsipi_xfer *xs; 2252 struct scsipi_periph *periph; 2253 struct trm_tinfo *ti; 2254 struct trm_linfo *li; 2255 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2256 int error; 2257 2258 DPRINTF(("trm_request_sense...\n")); 2259 2260 xs = srb->xs; 2261 periph = xs->xs_periph; 2262 2263 srb->flag |= AUTO_REQSENSE; 2264 2265 /* Status of initiator/target */ 2266 srb->hastat = 0; 2267 srb->tastat = 0; 2268 2269 memset(ss, 0, sizeof(*ss)); 2270 ss->opcode = SCSI_REQUEST_SENSE; 2271 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2272 ss->length = sizeof(struct scsi_sense_data); 2273 2274 srb->buflen = sizeof(struct scsi_sense_data); 2275 srb->sgcnt = 1; 2276 srb->sgindex = 0; 2277 srb->cmdlen = sizeof(struct scsi_request_sense); 2278 2279 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2280 &xs->sense.scsi_sense, srb->buflen, NULL, 2281 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2282 return error; 2283 } 2284 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2285 srb->buflen, BUS_DMASYNC_PREREAD); 2286 2287 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2288 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2289 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2290 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2291 2292 ti = &sc->sc_tinfo[periph->periph_target]; 2293 li = ti->linfo[periph->periph_lun]; 2294 if (li->busy > 0) 2295 li->busy = 0; 2296 trm_dequeue(sc, srb); 2297 li->untagged = srb; /* must be executed first to fix C/A */ 2298 li->busy = 2; 2299 2300 if (srb == sc->sc_actsrb) 2301 trm_select(sc, srb); 2302 else { 2303 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2304 if (sc->sc_actsrb == NULL) 2305 trm_sched(sc); 2306 } 2307 return 0; 2308 } 2309 2310 static void 2311 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2312 { 2313 struct scsipi_periph *periph; 2314 struct trm_tinfo *ti; 2315 struct trm_linfo *li; 2316 2317 periph = srb->xs->xs_periph; 2318 ti = &sc->sc_tinfo[periph->periph_target]; 2319 li = ti->linfo[periph->periph_lun]; 2320 2321 if (li->untagged == srb) { 2322 li->busy = 0; 2323 li->untagged = NULL; 2324 } 2325 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2326 li->queued[srb->tag[1]] = NULL; 2327 li->used--; 2328 } 2329 } 2330 2331 static void 2332 trm_reset_scsi_bus(struct trm_softc *sc) 2333 { 2334 bus_space_tag_t iot = sc->sc_iot; 2335 bus_space_handle_t ioh = sc->sc_ioh; 2336 int timeout, s; 2337 2338 DPRINTF(("trm_reset_scsi_bus.........\n")); 2339 2340 s = splbio(); 2341 2342 sc->sc_flag |= RESET_DEV; 2343 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2344 for (timeout = 20000; timeout >= 0; timeout--) { 2345 DELAY(1); 2346 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2347 INT_SCSIRESET) == 0) 2348 break; 2349 } 2350 if (timeout == 0) 2351 printf(": scsibus reset timeout\n"); 2352 2353 splx(s); 2354 } 2355 2356 static void 2357 trm_scsi_reset_detect(struct trm_softc *sc) 2358 { 2359 bus_space_tag_t iot = sc->sc_iot; 2360 bus_space_handle_t ioh = sc->sc_ioh; 2361 int s; 2362 2363 DPRINTF(("trm_scsi_reset_detect...............\n")); 2364 DELAY(1000000); /* delay 1 sec */ 2365 2366 s = splbio(); 2367 2368 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2369 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2370 2371 if (sc->sc_flag & RESET_DEV) { 2372 sc->sc_flag |= RESET_DONE; 2373 } else { 2374 sc->sc_flag |= RESET_DETECT; 2375 sc->sc_actsrb = NULL; 2376 sc->sc_flag = 0; 2377 trm_sched(sc); 2378 } 2379 splx(s); 2380 } 2381 2382 /* 2383 * read seeprom 128 bytes to struct eeprom and check checksum. 2384 * If it is wrong, update with default value. 2385 */ 2386 static void 2387 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2388 { 2389 struct nvram_target *target; 2390 uint16_t *ep; 2391 uint16_t chksum; 2392 int i; 2393 2394 DPRINTF(("trm_check_eeprom......\n")); 2395 trm_eeprom_read_all(sc, eeprom); 2396 ep = (uint16_t *)eeprom; 2397 chksum = 0; 2398 for (i = 0; i < 64; i++) 2399 chksum += le16toh(*ep++); 2400 2401 if (chksum != TRM_NVRAM_CKSUM) { 2402 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2403 /* 2404 * Checksum error, load default 2405 */ 2406 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2407 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2408 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2409 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2410 eeprom->subclass = 0x00; 2411 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2412 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2413 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2414 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2415 eeprom->reserved0 = 0x00; 2416 2417 for (i = 0, target = eeprom->target; 2418 i < TRM_MAX_TARGETS; 2419 i++, target++) { 2420 target->config0 = 0x77; 2421 target->period = 0x00; 2422 target->config2 = 0x00; 2423 target->config3 = 0x00; 2424 } 2425 2426 eeprom->scsi_id = 7; 2427 eeprom->channel_cfg = 0x0F; 2428 eeprom->delay_time = 0; 2429 eeprom->max_tag = 4; 2430 eeprom->reserved1 = 0x15; 2431 eeprom->boot_target = 0; 2432 eeprom->boot_lun = 0; 2433 eeprom->reserved2 = 0; 2434 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2435 2436 chksum = 0; 2437 ep = (uint16_t *)eeprom; 2438 for (i = 0; i < 63; i++) 2439 chksum += le16toh(*ep++); 2440 2441 chksum = TRM_NVRAM_CKSUM - chksum; 2442 eeprom->checksum0 = chksum & 0xFF; 2443 eeprom->checksum1 = chksum >> 8; 2444 2445 trm_eeprom_write_all(sc, eeprom); 2446 } 2447 } 2448 2449 /* 2450 * write struct eeprom 128 bytes to seeprom 2451 */ 2452 static void 2453 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2454 { 2455 bus_space_tag_t iot = sc->sc_iot; 2456 bus_space_handle_t ioh = sc->sc_ioh; 2457 uint8_t *sbuf = (uint8_t *)eeprom; 2458 uint8_t addr; 2459 2460 /* Enable SEEPROM */ 2461 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2462 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2463 2464 /* 2465 * Write enable 2466 */ 2467 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2468 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2469 trm_eeprom_wait(); 2470 2471 for (addr = 0; addr < 128; addr++, sbuf++) 2472 trm_eeprom_set_data(sc, addr, *sbuf); 2473 2474 /* 2475 * Write disable 2476 */ 2477 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2478 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2479 trm_eeprom_wait(); 2480 2481 /* Disable SEEPROM */ 2482 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2483 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2484 } 2485 2486 /* 2487 * write one byte to seeprom 2488 */ 2489 static void 2490 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2491 { 2492 bus_space_tag_t iot = sc->sc_iot; 2493 bus_space_handle_t ioh = sc->sc_ioh; 2494 int i; 2495 uint8_t send; 2496 2497 /* 2498 * Send write command & address 2499 */ 2500 trm_eeprom_write_cmd(sc, 0x05, addr); 2501 /* 2502 * Write data 2503 */ 2504 for (i = 0; i < 8; i++, data <<= 1) { 2505 send = NVR_SELECT; 2506 if (data & 0x80) /* Start from bit 7 */ 2507 send |= NVR_BITOUT; 2508 2509 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2510 trm_eeprom_wait(); 2511 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2512 trm_eeprom_wait(); 2513 } 2514 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2515 trm_eeprom_wait(); 2516 /* 2517 * Disable chip select 2518 */ 2519 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2520 trm_eeprom_wait(); 2521 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2522 trm_eeprom_wait(); 2523 /* 2524 * Wait for write ready 2525 */ 2526 for (;;) { 2527 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2528 NVR_SELECT | NVR_CLOCK); 2529 trm_eeprom_wait(); 2530 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2531 trm_eeprom_wait(); 2532 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2533 break; 2534 } 2535 /* 2536 * Disable chip select 2537 */ 2538 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2539 } 2540 2541 /* 2542 * read seeprom 128 bytes to struct eeprom 2543 */ 2544 static void 2545 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2546 { 2547 bus_space_tag_t iot = sc->sc_iot; 2548 bus_space_handle_t ioh = sc->sc_ioh; 2549 uint8_t *sbuf = (uint8_t *)eeprom; 2550 uint8_t addr; 2551 2552 /* 2553 * Enable SEEPROM 2554 */ 2555 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2556 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2557 2558 for (addr = 0; addr < 128; addr++) 2559 *sbuf++ = trm_eeprom_get_data(sc, addr); 2560 2561 /* 2562 * Disable SEEPROM 2563 */ 2564 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2565 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2566 } 2567 2568 /* 2569 * read one byte from seeprom 2570 */ 2571 static uint8_t 2572 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2573 { 2574 bus_space_tag_t iot = sc->sc_iot; 2575 bus_space_handle_t ioh = sc->sc_ioh; 2576 int i; 2577 uint8_t read, data = 0; 2578 2579 /* 2580 * Send read command & address 2581 */ 2582 trm_eeprom_write_cmd(sc, 0x06, addr); 2583 2584 for (i = 0; i < 8; i++) { /* Read data */ 2585 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2586 NVR_SELECT | NVR_CLOCK); 2587 trm_eeprom_wait(); 2588 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2589 /* 2590 * Get data bit while falling edge 2591 */ 2592 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2593 data <<= 1; 2594 if (read & NVR_BITIN) 2595 data |= 1; 2596 2597 trm_eeprom_wait(); 2598 } 2599 /* 2600 * Disable chip select 2601 */ 2602 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2603 return (data); 2604 } 2605 2606 /* 2607 * write SB and Op Code into seeprom 2608 */ 2609 static void 2610 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2611 { 2612 bus_space_tag_t iot = sc->sc_iot; 2613 bus_space_handle_t ioh = sc->sc_ioh; 2614 int i; 2615 uint8_t send; 2616 2617 /* Program SB+OP code */ 2618 for (i = 0; i < 3; i++, cmd <<= 1) { 2619 send = NVR_SELECT; 2620 if (cmd & 0x04) /* Start from bit 2 */ 2621 send |= NVR_BITOUT; 2622 2623 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2624 trm_eeprom_wait(); 2625 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2626 trm_eeprom_wait(); 2627 } 2628 2629 /* Program address */ 2630 for (i = 0; i < 7; i++, addr <<= 1) { 2631 send = NVR_SELECT; 2632 if (addr & 0x40) /* Start from bit 6 */ 2633 send |= NVR_BITOUT; 2634 2635 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2636 trm_eeprom_wait(); 2637 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2638 trm_eeprom_wait(); 2639 } 2640 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2641 trm_eeprom_wait(); 2642 } 2643
Indexes created Tue Sep 23 21:09:50 GMT 2025