trm.c revision 1.27
1 /* $NetBSD: trm.c,v 1.27 2007/10/19 12:00:55 ad Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.27 2007/10/19 12:00:55 ad Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_spc.h> 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsi_message.h> 71 #include <dev/scsipi/scsipi_all.h> 72 #include <dev/scsipi/scsiconf.h> 73 74 #include <dev/pci/pcidevs.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/trmreg.h> 78 79 /* 80 * feature of chip set MAX value 81 */ 82 #define TRM_MAX_TARGETS 16 83 #define TRM_MAX_LUNS 8 84 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 85 #define TRM_MAX_SRB 32 /* XXX */ 86 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 87 #define TRM_MAX_OFFSET 15 88 #define TRM_MAX_PERIOD 125 89 90 /* 91 * Segment Entry 92 */ 93 struct trm_sg_entry { 94 uint32_t address; 95 uint32_t length; 96 }; 97 98 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 99 100 /* 101 ********************************************************************** 102 * The SEEPROM structure for TRM_S1040 103 ********************************************************************** 104 */ 105 struct nvram_target { 106 uint8_t config0; /* Target configuration byte 0 */ 107 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 108 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 109 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 110 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 111 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 112 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 113 uint8_t period; /* Target period */ 114 uint8_t config2; /* Target configuration byte 2 */ 115 uint8_t config3; /* Target configuration byte 3 */ 116 }; 117 118 struct trm_nvram { 119 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 120 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 121 uint8_t subclass; /* 4 Sub Class */ 122 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 123 uint8_t device_id[2]; /* 7,8 Device ID */ 124 uint8_t reserved0; /* 9 Reserved */ 125 struct nvram_target target[TRM_MAX_TARGETS]; 126 /* 10,11,12,13 127 * 14,15,16,17 128 * .... 129 * 70,71,72,73 */ 130 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 131 uint8_t channel_cfg; /* 75 Channel configuration */ 132 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 133 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 134 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 135 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 136 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 137 uint8_t delay_time; /* 76 Power on delay time */ 138 uint8_t max_tag; /* 77 Maximum tags */ 139 uint8_t reserved1; /* 78 */ 140 uint8_t boot_target; /* 79 */ 141 uint8_t boot_lun; /* 80 */ 142 uint8_t reserved2; /* 81 */ 143 uint8_t reserved3[44]; /* 82,..125 */ 144 uint8_t checksum0; /* 126 */ 145 uint8_t checksum1; /* 127 */ 146 #define TRM_NVRAM_CKSUM 0x1234 147 }; 148 149 /* Nvram Initiater bits definition */ 150 #define MORE2_DRV 0x00000001 151 #define GREATER_1G 0x00000002 152 #define RST_SCSI_BUS 0x00000004 153 #define ACTIVE_NEGATION 0x00000008 154 #define NO_SEEK 0x00000010 155 #define LUN_CHECK 0x00000020 156 157 #define trm_eeprom_wait() DELAY(30) 158 159 /* 160 *----------------------------------------------------------------------- 161 * SCSI Request Block 162 *----------------------------------------------------------------------- 163 */ 164 struct trm_srb { 165 TAILQ_ENTRY(trm_srb) next; 166 167 struct trm_sg_entry *sgentry; 168 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 169 bus_dmamap_t dmap; 170 bus_size_t sgoffset; /* Xfer buf offset */ 171 172 uint32_t buflen; /* Total xfer length */ 173 uint32_t sgaddr; /* SGList physical starting address */ 174 175 int sgcnt; 176 int sgindex; 177 178 int hastat; /* Host Adapter Status */ 179 #define H_STATUS_GOOD 0x00 180 #define H_SEL_TIMEOUT 0x11 181 #define H_OVER_UNDER_RUN 0x12 182 #define H_UNEXP_BUS_FREE 0x13 183 #define H_TARGET_PHASE_F 0x14 184 #define H_INVALID_CCB_OP 0x16 185 #define H_LINK_CCB_BAD 0x17 186 #define H_BAD_TARGET_DIR 0x18 187 #define H_DUPLICATE_CCB 0x19 188 #define H_BAD_CCB_OR_SG 0x1A 189 #define H_ABORT 0xFF 190 int tastat; /* Target SCSI Status Byte */ 191 int flag; /* SRBFlag */ 192 #define AUTO_REQSENSE 0x0001 193 #define PARITY_ERROR 0x0002 194 #define SRB_TIMEOUT 0x0004 195 196 int cmdlen; /* SCSI command length */ 197 uint8_t cmd[12]; /* SCSI command */ 198 199 uint8_t tag[2]; 200 }; 201 202 /* 203 * some info about each target and lun on the SCSI bus 204 */ 205 struct trm_linfo { 206 int used; /* number of slots in use */ 207 int avail; /* where to start scanning */ 208 int busy; /* lun in use */ 209 struct trm_srb *untagged; 210 struct trm_srb *queued[TRM_MAX_TAG]; 211 }; 212 213 struct trm_tinfo { 214 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 215 #define SYNC_NEGO_ENABLE 0x0001 216 #define SYNC_NEGO_DOING 0x0002 217 #define SYNC_NEGO_DONE 0x0004 218 #define WIDE_NEGO_ENABLE 0x0008 219 #define WIDE_NEGO_DOING 0x0010 220 #define WIDE_NEGO_DONE 0x0020 221 #define USE_TAG_QUEUING 0x0040 222 #define NO_RESELECT 0x0080 223 struct trm_linfo *linfo[TRM_MAX_LUNS]; 224 225 uint8_t config0; /* Target Config */ 226 uint8_t period; /* Max Period for nego. */ 227 uint8_t synctl; /* Sync control for reg. */ 228 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 229 }; 230 231 /* 232 *----------------------------------------------------------------------- 233 * Adapter Control Block 234 *----------------------------------------------------------------------- 235 */ 236 struct trm_softc { 237 struct device sc_dev; 238 239 bus_space_tag_t sc_iot; 240 bus_space_handle_t sc_ioh; 241 bus_dma_tag_t sc_dmat; 242 bus_dmamap_t sc_dmamap; /* Map the control structures */ 243 244 struct trm_srb *sc_actsrb; 245 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 246 247 TAILQ_HEAD(, trm_srb) sc_freesrb, 248 sc_readysrb; 249 struct trm_srb *sc_srb; /* SRB array */ 250 251 struct trm_sg_entry *sc_sglist; 252 253 int sc_maxid; 254 /* 255 * Link to the generic SCSI driver 256 */ 257 struct scsipi_channel sc_channel; 258 struct scsipi_adapter sc_adapter; 259 260 int sc_id; /* Adapter SCSI Target ID */ 261 262 int sc_state; /* SRB State */ 263 #define TRM_IDLE 0 264 #define TRM_WAIT 1 265 #define TRM_READY 2 266 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 267 #define TRM_MSGIN 4 268 #define TRM_EXTEND_MSGIN 5 269 #define TRM_COMMAND 6 270 #define TRM_START 7 /* arbitration+msg_out+command_out */ 271 #define TRM_DISCONNECTED 8 272 #define TRM_DATA_XFER 9 273 #define TRM_XFERPAD 10 274 #define TRM_STATUS 11 275 #define TRM_COMPLETED 12 276 #define TRM_ABORT_SENT 13 277 #define TRM_UNEXPECT_RESEL 14 278 279 int sc_phase; /* SCSI phase */ 280 int sc_config; 281 #define HCC_WIDE_CARD 0x01 282 #define HCC_SCSI_RESET 0x02 283 #define HCC_PARITY 0x04 284 #define HCC_AUTOTERM 0x08 285 #define HCC_LOW8TERM 0x10 286 #define HCC_UP8TERM 0x20 287 288 int sc_flag; 289 #define RESET_DEV 0x01 290 #define RESET_DETECT 0x02 291 #define RESET_DONE 0x04 292 #define WAIT_TAGMSG 0x08 /* XXX */ 293 294 int sc_msgcnt; 295 296 int resel_target; /* XXX */ 297 int resel_lun; /* XXX */ 298 299 uint8_t *sc_msg; 300 uint8_t sc_msgbuf[6]; 301 }; 302 303 /* 304 * SCSI Status codes not defined in scsi_all.h 305 */ 306 #define SCSI_COND_MET 0x04 /* Condition Met */ 307 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 308 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 309 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 310 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 311 312 static int trm_probe(struct device *, struct cfdata *, void *); 313 static void trm_attach(struct device *, struct device *, void *); 314 315 static int trm_init(struct trm_softc *); 316 317 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 318 void *); 319 static void trm_update_xfer_mode(struct trm_softc *, int); 320 static void trm_sched(struct trm_softc *); 321 static int trm_select(struct trm_softc *, struct trm_srb *); 322 static void trm_reset(struct trm_softc *); 323 static void trm_timeout(void *); 324 static int trm_intr(void *); 325 326 static void trm_dataout_phase0(struct trm_softc *, int); 327 static void trm_datain_phase0(struct trm_softc *, int); 328 static void trm_status_phase0(struct trm_softc *); 329 static void trm_msgin_phase0(struct trm_softc *); 330 static void trm_command_phase1(struct trm_softc *); 331 static void trm_status_phase1(struct trm_softc *); 332 static void trm_msgout_phase1(struct trm_softc *); 333 static void trm_msgin_phase1(struct trm_softc *); 334 335 static void trm_dataio_xfer(struct trm_softc *, int); 336 static void trm_disconnect(struct trm_softc *); 337 static void trm_reselect(struct trm_softc *); 338 static void trm_done(struct trm_softc *, struct trm_srb *); 339 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 340 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 341 342 static void trm_scsi_reset_detect(struct trm_softc *); 343 static void trm_reset_scsi_bus(struct trm_softc *); 344 345 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 348 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 349 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 350 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 351 352 CFATTACH_DECL(trm, sizeof(struct trm_softc), 353 trm_probe, trm_attach, NULL, NULL); 354 355 /* real period: */ 356 static const uint8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(struct device *parent, struct cfdata *match, 370 void *aux) 371 { 372 struct pci_attach_args *pa = aux; 373 374 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 375 switch (PCI_PRODUCT(pa->pa_id)) { 376 case PCI_PRODUCT_TEKRAM2_DC315: 377 return (1); 378 } 379 return (0); 380 } 381 382 /* 383 * attach and init a host adapter 384 */ 385 static void 386 trm_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct pci_attach_args *const pa = aux; 389 struct trm_softc *sc = (struct trm_softc *)self; 390 bus_space_tag_t iot; 391 bus_space_handle_t ioh; 392 pci_intr_handle_t ih; 393 pcireg_t command; 394 const char *intrstr; 395 396 /* 397 * These cards do not allow memory mapped accesses 398 * pa_pc: chipset tag 399 * pa_tag: pci tag 400 */ 401 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 402 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 403 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 404 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 405 pci_conf_write(pa->pa_pc, pa->pa_tag, 406 PCI_COMMAND_STATUS_REG, command); 407 } 408 /* 409 * mask for get correct base address of pci IO port 410 */ 411 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 412 &iot, &ioh, NULL, NULL)) { 413 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 414 return; 415 } 416 /* 417 * test checksum of eeprom.. & initialize softc... 418 */ 419 sc->sc_iot = iot; 420 sc->sc_ioh = ioh; 421 sc->sc_dmat = pa->pa_dmat; 422 423 if (trm_init(sc) != 0) { 424 /* 425 * Error during initialization! 426 */ 427 printf(": Error during initialization\n"); 428 return; 429 } 430 /* 431 * Now try to attach all the sub-devices 432 */ 433 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 434 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 435 "Ultra Wide SCSI Adapter\n"); 436 else 437 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 438 "Ultra SCSI Adapter\n"); 439 440 /* 441 * Now tell the generic SCSI layer about our bus. 442 * map and establish interrupt 443 */ 444 if (pci_intr_map(pa, &ih)) { 445 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 446 return; 447 } 448 intrstr = pci_intr_string(pa->pa_pc, ih); 449 450 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 451 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 452 if (intrstr != NULL) 453 printf(" at %s", intrstr); 454 printf("\n"); 455 return; 456 } 457 if (intrstr != NULL) 458 printf("%s: interrupting at %s\n", 459 sc->sc_dev.dv_xname, intrstr); 460 461 sc->sc_adapter.adapt_dev = &sc->sc_dev; 462 sc->sc_adapter.adapt_nchannels = 1; 463 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 464 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 465 sc->sc_adapter.adapt_request = trm_scsipi_request; 466 sc->sc_adapter.adapt_minphys = minphys; 467 468 sc->sc_channel.chan_adapter = &sc->sc_adapter; 469 sc->sc_channel.chan_bustype = &scsi_bustype; 470 sc->sc_channel.chan_channel = 0; 471 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 472 sc->sc_channel.chan_nluns = 8; 473 sc->sc_channel.chan_id = sc->sc_id; 474 475 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 476 } 477 478 /* 479 * initialize the internal structures for a given SCSI host 480 */ 481 static int 482 trm_init(struct trm_softc *sc) 483 { 484 bus_space_tag_t iot = sc->sc_iot; 485 bus_space_handle_t ioh = sc->sc_ioh; 486 bus_dma_segment_t seg; 487 struct trm_nvram eeprom; 488 struct trm_srb *srb; 489 struct trm_tinfo *ti; 490 struct nvram_target *tconf; 491 int error, rseg, all_sgsize; 492 int i, target; 493 uint8_t bval; 494 495 DPRINTF(("\n")); 496 497 /* 498 * allocate the space for all SCSI control blocks (SRB) for DMA memory 499 */ 500 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 501 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 502 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 503 printf(": unable to allocate SCSI REQUEST BLOCKS, " 504 "error = %d\n", error); 505 return (1); 506 } 507 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 508 all_sgsize, (void **) &sc->sc_sglist, 509 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 510 printf(": unable to map SCSI REQUEST BLOCKS, " 511 "error = %d\n", error); 512 return (1); 513 } 514 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 515 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 516 printf(": unable to create SRB DMA maps, " 517 "error = %d\n", error); 518 return (1); 519 } 520 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 521 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 522 printf(": unable to load SRB DMA maps, " 523 "error = %d\n", error); 524 return (1); 525 } 526 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 527 memset(sc->sc_sglist, 0, all_sgsize); 528 529 /* 530 * EEPROM CHECKSUM 531 */ 532 trm_check_eeprom(sc, &eeprom); 533 534 sc->sc_maxid = 7; 535 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 536 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 537 sc->sc_config |= HCC_WIDE_CARD; 538 sc->sc_maxid = 15; 539 } 540 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 541 sc->sc_config |= HCC_SCSI_RESET; 542 543 sc->sc_actsrb = NULL; 544 sc->sc_id = eeprom.scsi_id; 545 sc->sc_flag = 0; 546 547 /* 548 * initialize and link all device's SRB queues of this adapter 549 */ 550 TAILQ_INIT(&sc->sc_freesrb); 551 TAILQ_INIT(&sc->sc_readysrb); 552 553 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 554 M_DEVBUF, M_NOWAIT|M_ZERO); 555 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 556 if (sc->sc_srb == NULL) { 557 printf(": can not allocate SRB\n"); 558 return (1); 559 } 560 561 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 562 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 563 srb->sgoffset = TRM_SG_SIZE * i; 564 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 565 /* 566 * map all SRB space to SRB_array 567 */ 568 if (bus_dmamap_create(sc->sc_dmat, 569 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 570 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 571 printf(": unable to create DMA transfer map...\n"); 572 free(sc->sc_srb, M_DEVBUF); 573 return (1); 574 } 575 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 576 srb++; 577 } 578 579 /* 580 * initialize all target info structures 581 */ 582 for (target = 0; target < TRM_MAX_TARGETS; target++) { 583 ti = &sc->sc_tinfo[target]; 584 ti->synctl = 0; 585 ti->offset = 0; 586 tconf = &eeprom.target[target]; 587 ti->config0 = tconf->config0; 588 ti->period = trm_clock_period[tconf->period & 0x07]; 589 ti->flag = 0; 590 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 591 #ifdef notyet 592 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 593 ti->flag |= USE_TAG_QUEUING; 594 #endif 595 } else 596 ti->flag |= NO_RESELECT; 597 598 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 599 target, ti->config0, ti->period)); 600 DPRINTF((", flag = 0x%02x\n", ti->flag)); 601 } 602 603 /* program configuration 0 */ 604 bval = PHASELATCH | INITIATOR | BLOCKRST; 605 if ((sc->sc_config & HCC_PARITY) != 0) 606 bval |= PARITYCHECK; 607 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 608 609 /* program configuration 1 */ 610 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 611 ACTIVE_NEG | ACTIVE_NEGPLUS); 612 613 /* 250ms selection timeout */ 614 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 615 616 /* Mask all interrupts */ 617 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 618 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 619 620 /* Reset SCSI module */ 621 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 622 623 /* program Host ID */ 624 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 625 626 /* set asynchronous transfer */ 627 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 628 629 /* Turn LED control off */ 630 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 631 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 632 633 /* DMA config */ 634 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 635 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 636 637 /* Clear pending interrupt status */ 638 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 639 640 /* Enable SCSI interrupt */ 641 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 642 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 643 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 644 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 645 646 trm_reset(sc); 647 648 return (0); 649 } 650 651 /* 652 * enqueues a SCSI command 653 * called by the higher level SCSI driver 654 */ 655 static void 656 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 657 void *arg) 658 { 659 bus_space_tag_t iot; 660 bus_space_handle_t ioh; 661 struct trm_softc *sc; 662 struct trm_srb *srb; 663 struct scsipi_xfer *xs; 664 int error, i, target, lun, s; 665 666 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 667 iot = sc->sc_iot; 668 ioh = sc->sc_ioh; 669 670 switch (req) { 671 case ADAPTER_REQ_RUN_XFER: 672 xs = arg; 673 target = xs->xs_periph->periph_target; 674 lun = xs->xs_periph->periph_lun; 675 DPRINTF(("trm_scsipi_request.....\n")); 676 DPRINTF(("target= %d lun= %d\n", target, lun)); 677 if (xs->xs_control & XS_CTL_RESET) { 678 trm_reset(sc); 679 xs->error = XS_NOERROR | XS_RESET; 680 return; 681 } 682 if (xs->xs_status & XS_STS_DONE) { 683 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 684 xs->xs_status &= ~XS_STS_DONE; 685 } 686 687 s = splbio(); 688 689 /* Get SRB */ 690 srb = TAILQ_FIRST(&sc->sc_freesrb); 691 if (srb != NULL) { 692 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 693 } else { 694 xs->error = XS_RESOURCE_SHORTAGE; 695 scsipi_done(xs); 696 splx(s); 697 return; 698 } 699 700 srb->xs = xs; 701 srb->cmdlen = xs->cmdlen; 702 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 703 704 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 705 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 706 xs->data, xs->datalen, NULL, 707 ((xs->xs_control & XS_CTL_NOSLEEP) ? 708 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 709 BUS_DMA_STREAMING | 710 ((xs->xs_control & XS_CTL_DATA_IN) ? 711 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 712 printf("%s: DMA transfer map unable to load, " 713 "error = %d\n", sc->sc_dev.dv_xname, error); 714 xs->error = XS_DRIVER_STUFFUP; 715 /* 716 * free SRB 717 */ 718 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 719 splx(s); 720 return; 721 } 722 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 723 srb->dmap->dm_mapsize, 724 (xs->xs_control & XS_CTL_DATA_IN) ? 725 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 726 727 /* Set up the scatter gather list */ 728 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 729 srb->sgentry[i].address = 730 htole32(srb->dmap->dm_segs[i].ds_addr); 731 srb->sgentry[i].length = 732 htole32(srb->dmap->dm_segs[i].ds_len); 733 } 734 srb->buflen = xs->datalen; 735 srb->sgcnt = srb->dmap->dm_nsegs; 736 } else { 737 srb->sgentry[0].address = 0; 738 srb->sgentry[0].length = 0; 739 srb->buflen = 0; 740 srb->sgcnt = 0; 741 } 742 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 743 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 744 745 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 746 747 srb->sgindex = 0; 748 srb->hastat = 0; 749 srb->tastat = 0; 750 srb->flag = 0; 751 752 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 753 if (sc->sc_actsrb == NULL) 754 trm_sched(sc); 755 splx(s); 756 757 if ((xs->xs_control & XS_CTL_POLL) != 0) { 758 int timeout = xs->timeout; 759 760 s = splbio(); 761 do { 762 while (--timeout) { 763 DELAY(1000); 764 if (bus_space_read_2(iot, ioh, 765 TRM_SCSI_STATUS) & SCSIINTERRUPT) 766 break; 767 } 768 if (timeout == 0) { 769 trm_timeout(srb); 770 break; 771 } else 772 trm_intr(sc); 773 } while ((xs->xs_status & XS_STS_DONE) == 0); 774 splx(s); 775 } 776 return; 777 778 case ADAPTER_REQ_GROW_RESOURCES: 779 /* XXX Not supported. */ 780 return; 781 782 case ADAPTER_REQ_SET_XFER_MODE: 783 { 784 struct trm_tinfo *ti; 785 struct scsipi_xfer_mode *xm; 786 787 xm = arg; 788 ti = &sc->sc_tinfo[xm->xm_target]; 789 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 790 791 #ifdef notyet 792 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 793 ti->flag |= USE_TAG_QUEUING; 794 else 795 #endif 796 ti->flag &= ~USE_TAG_QUEUING; 797 798 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 799 (sc->sc_config & HCC_WIDE_CARD) != 0 && 800 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 801 ti->flag |= WIDE_NEGO_ENABLE; 802 ti->flag &= ~WIDE_NEGO_DONE; 803 } 804 805 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 806 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 807 ti->flag |= SYNC_NEGO_ENABLE; 808 ti->flag &= ~SYNC_NEGO_DONE; 809 ti->period = trm_clock_period[0]; 810 } 811 812 /* 813 * If we're not going to negotiate, send the 814 * notification now, since it won't happen later. 815 */ 816 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 817 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 818 trm_update_xfer_mode(sc, xm->xm_target); 819 820 return; 821 } 822 } 823 } 824 825 static void 826 trm_update_xfer_mode(struct trm_softc *sc, int target) 827 { 828 struct scsipi_xfer_mode xm; 829 struct trm_tinfo *ti; 830 831 ti = &sc->sc_tinfo[target]; 832 xm.xm_target = target; 833 xm.xm_mode = 0; 834 xm.xm_period = 0; 835 xm.xm_offset = 0; 836 837 if ((ti->synctl & WIDE_SYNC) != 0) 838 xm.xm_mode |= PERIPH_CAP_WIDE16; 839 840 if (ti->period > 0) { 841 xm.xm_mode |= PERIPH_CAP_SYNC; 842 xm.xm_period = ti->period; 843 xm.xm_offset = ti->offset; 844 } 845 846 #ifdef notyet 847 if ((ti->flag & USE_TAG_QUEUING) != 0) 848 xm.xm_mode |= PERIPH_CAP_TQING; 849 #endif 850 851 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 852 } 853 854 static void 855 trm_sched(struct trm_softc *sc) 856 { 857 struct trm_srb *srb; 858 struct scsipi_periph *periph; 859 struct trm_tinfo *ti; 860 struct trm_linfo *li; 861 int s, lun, tag; 862 863 DPRINTF(("trm_sched...\n")); 864 865 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 866 periph = srb->xs->xs_periph; 867 ti = &sc->sc_tinfo[periph->periph_target]; 868 lun = periph->periph_lun; 869 870 /* select type of tag for this command */ 871 if ((ti->flag & NO_RESELECT) != 0 || 872 (ti->flag & USE_TAG_QUEUING) == 0 || 873 (srb->flag & AUTO_REQSENSE) != 0 || 874 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 875 tag = 0; 876 else 877 tag = srb->xs->xs_tag_type; 878 #if 0 879 /* XXX use tags for polled commands? */ 880 if (srb->xs->xs_control & XS_CTL_POLL) 881 tag = 0; 882 #endif 883 884 s = splbio(); 885 li = ti->linfo[lun]; 886 if (li == NULL) { 887 /* initialize lun info */ 888 if ((li = malloc(sizeof(*li), M_DEVBUF, 889 M_NOWAIT|M_ZERO)) == NULL) { 890 splx(s); 891 continue; 892 } 893 ti->linfo[lun] = li; 894 } 895 896 if (tag == 0) { 897 /* try to issue this srb as an un-tagged command */ 898 if (li->untagged == NULL) 899 li->untagged = srb; 900 } 901 if (li->untagged != NULL) { 902 tag = 0; 903 if (li->busy != 1 && li->used == 0) { 904 /* we need to issue the untagged command now */ 905 srb = li->untagged; 906 periph = srb->xs->xs_periph; 907 } else { 908 /* not ready yet */ 909 splx(s); 910 continue; 911 } 912 } 913 srb->tag[0] = tag; 914 if (tag != 0) { 915 li->queued[srb->xs->xs_tag_id] = srb; 916 srb->tag[1] = srb->xs->xs_tag_id; 917 li->used++; 918 } 919 920 if (li->untagged != NULL && li->busy != 1) { 921 li->busy = 1; 922 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 923 sc->sc_actsrb = srb; 924 trm_select(sc, srb); 925 splx(s); 926 break; 927 } 928 if (li->untagged == NULL && tag != 0) { 929 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 930 sc->sc_actsrb = srb; 931 trm_select(sc, srb); 932 splx(s); 933 break; 934 } else 935 splx(s); 936 } 937 } 938 939 static int 940 trm_select(struct trm_softc *sc, struct trm_srb *srb) 941 { 942 bus_space_tag_t iot = sc->sc_iot; 943 bus_space_handle_t ioh = sc->sc_ioh; 944 struct scsipi_periph *periph = srb->xs->xs_periph; 945 int target = periph->periph_target; 946 int lun = periph->periph_lun; 947 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 948 uint8_t scsicmd; 949 950 DPRINTF(("trm_select.....\n")); 951 952 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 953 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 954 trm_timeout, srb); 955 } 956 957 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 958 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 959 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 960 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 961 /* Flush FIFO */ 962 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 963 DELAY(10); 964 965 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 966 967 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 968 969 if (((ti->flag & WIDE_NEGO_ENABLE) && 970 (ti->flag & WIDE_NEGO_DONE) == 0) || 971 ((ti->flag & SYNC_NEGO_ENABLE) && 972 (ti->flag & SYNC_NEGO_DONE) == 0)) { 973 sc->sc_state = TRM_MSGOUT; 974 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 975 MSG_IDENTIFY(lun, 0)); 976 bus_space_write_multi_1(iot, ioh, 977 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 978 /* it's important for atn stop */ 979 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 980 DO_DATALATCH | DO_HWRESELECT); 981 /* SCSI command */ 982 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 983 DPRINTF(("select with SEL_ATNSTOP\n")); 984 return (0); 985 } 986 987 if (srb->tag[0] != 0) { 988 /* Send identify message */ 989 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 990 MSG_IDENTIFY(lun, 1)); 991 /* Send Tag id */ 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 993 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 994 scsicmd = SCMD_SEL_ATN3; 995 DPRINTF(("select with SEL_ATN3\n")); 996 } else { 997 /* Send identify message */ 998 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 999 MSG_IDENTIFY(lun, 1000 (ti->flag & NO_RESELECT) == 0 && 1001 (srb->flag & AUTO_REQSENSE) == 0 && 1002 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1003 scsicmd = SCMD_SEL_ATN; 1004 DPRINTF(("select with SEL_ATN\n")); 1005 } 1006 sc->sc_state = TRM_START; 1007 1008 /* 1009 * Send CDB ..command block... 1010 */ 1011 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1012 1013 /* 1014 * If trm_select returns 0: current interrupt status 1015 * is interrupt enable. It's said that SCSI processor is 1016 * unoccupied. 1017 */ 1018 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1019 /* SCSI command */ 1020 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1021 return (0); 1022 } 1023 1024 /* 1025 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1026 */ 1027 static void 1028 trm_reset(struct trm_softc *sc) 1029 { 1030 bus_space_tag_t iot = sc->sc_iot; 1031 bus_space_handle_t ioh = sc->sc_ioh; 1032 int s; 1033 1034 DPRINTF(("trm_reset.........\n")); 1035 1036 s = splbio(); 1037 1038 /* disable SCSI and DMA interrupt */ 1039 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1040 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1041 1042 trm_reset_scsi_bus(sc); 1043 DELAY(100000); 1044 1045 /* Enable SCSI interrupt */ 1046 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1047 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1048 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1049 1050 /* Enable DMA interrupt */ 1051 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1052 1053 /* Clear DMA FIFO */ 1054 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1055 1056 /* Clear SCSI FIFO */ 1057 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1058 1059 sc->sc_actsrb = NULL; 1060 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1061 1062 splx(s); 1063 } 1064 1065 static void 1066 trm_timeout(void *arg) 1067 { 1068 struct trm_srb *srb = (struct trm_srb *)arg; 1069 struct scsipi_xfer *xs; 1070 struct scsipi_periph *periph; 1071 struct trm_softc *sc; 1072 int s; 1073 1074 if (srb == NULL) { 1075 printf("trm_timeout called with srb == NULL\n"); 1076 return; 1077 } 1078 1079 xs = srb->xs; 1080 if (xs == NULL) { 1081 printf("trm_timeout called with xs == NULL\n"); 1082 return; 1083 } 1084 1085 periph = xs->xs_periph; 1086 scsipi_printaddr(xs->xs_periph); 1087 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1088 1089 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1090 1091 trm_reset_scsi_bus(sc); 1092 s = splbio(); 1093 srb->flag |= SRB_TIMEOUT; 1094 trm_done(sc, srb); 1095 /* XXX needs more.. */ 1096 splx(s); 1097 } 1098 1099 /* 1100 * Catch an interrupt from the adapter 1101 * Process pending device interrupts. 1102 */ 1103 static int 1104 trm_intr(void *arg) 1105 { 1106 bus_space_tag_t iot; 1107 bus_space_handle_t ioh; 1108 struct trm_softc *sc; 1109 int intstat, stat; 1110 1111 DPRINTF(("trm_intr......\n")); 1112 sc = (struct trm_softc *)arg; 1113 if (sc == NULL) 1114 return (0); 1115 1116 iot = sc->sc_iot; 1117 ioh = sc->sc_ioh; 1118 1119 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1120 if ((stat & SCSIINTERRUPT) == 0) 1121 return (0); 1122 1123 DPRINTF(("stat = %04x, ", stat)); 1124 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1125 1126 DPRINTF(("intstat=%02x, ", intstat)); 1127 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1128 DPRINTF(("\n")); 1129 trm_disconnect(sc); 1130 return (1); 1131 } 1132 if (intstat & INT_RESELECTED) { 1133 DPRINTF(("\n")); 1134 trm_reselect(sc); 1135 return (1); 1136 } 1137 if (intstat & INT_SCSIRESET) { 1138 DPRINTF(("\n")); 1139 trm_scsi_reset_detect(sc); 1140 return (1); 1141 } 1142 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1143 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1144 sc->sc_phase, sc->sc_state)); 1145 /* 1146 * software sequential machine 1147 */ 1148 1149 /* 1150 * call phase0 functions... "phase entry" handle 1151 * every phase before start transfer 1152 */ 1153 switch (sc->sc_phase) { 1154 case PH_DATA_OUT: 1155 trm_dataout_phase0(sc, stat); 1156 break; 1157 case PH_DATA_IN: 1158 trm_datain_phase0(sc, stat); 1159 break; 1160 case PH_COMMAND: 1161 break; 1162 case PH_STATUS: 1163 trm_status_phase0(sc); 1164 stat = PH_BUS_FREE; 1165 break; 1166 case PH_MSG_OUT: 1167 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1168 sc->sc_state == TRM_ABORT_SENT) 1169 stat = PH_BUS_FREE; 1170 break; 1171 case PH_MSG_IN: 1172 trm_msgin_phase0(sc); 1173 stat = PH_BUS_FREE; 1174 break; 1175 case PH_BUS_FREE: 1176 break; 1177 default: 1178 printf("%s: unexpected phase in trm_intr() phase0\n", 1179 sc->sc_dev.dv_xname); 1180 break; 1181 } 1182 1183 sc->sc_phase = stat & PHASEMASK; 1184 1185 switch (sc->sc_phase) { 1186 case PH_DATA_OUT: 1187 trm_dataio_xfer(sc, XFERDATAOUT); 1188 break; 1189 case PH_DATA_IN: 1190 trm_dataio_xfer(sc, XFERDATAIN); 1191 break; 1192 case PH_COMMAND: 1193 trm_command_phase1(sc); 1194 break; 1195 case PH_STATUS: 1196 trm_status_phase1(sc); 1197 break; 1198 case PH_MSG_OUT: 1199 trm_msgout_phase1(sc); 1200 break; 1201 case PH_MSG_IN: 1202 trm_msgin_phase1(sc); 1203 break; 1204 case PH_BUS_FREE: 1205 break; 1206 default: 1207 printf("%s: unexpected phase in trm_intr() phase1\n", 1208 sc->sc_dev.dv_xname); 1209 break; 1210 } 1211 1212 return (1); 1213 } 1214 return (0); 1215 } 1216 1217 static void 1218 trm_msgout_phase1(struct trm_softc *sc) 1219 { 1220 bus_space_tag_t iot = sc->sc_iot; 1221 bus_space_handle_t ioh = sc->sc_ioh; 1222 struct trm_srb *srb; 1223 struct scsipi_periph *periph; 1224 struct trm_tinfo *ti; 1225 1226 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1227 1228 srb = sc->sc_actsrb; 1229 1230 /* message out phase */ 1231 if (srb != NULL) { 1232 periph = srb->xs->xs_periph; 1233 ti = &sc->sc_tinfo[periph->periph_target]; 1234 1235 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1236 (ti->flag & WIDE_NEGO_ENABLE)) { 1237 /* send WDTR */ 1238 ti->flag &= ~SYNC_NEGO_DONE; 1239 1240 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1241 sc->sc_msgbuf[1] = MSG_EXTENDED; 1242 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1243 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1244 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1245 sc->sc_msgcnt = 5; 1246 1247 ti->flag |= WIDE_NEGO_DOING; 1248 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1249 (ti->flag & SYNC_NEGO_ENABLE)) { 1250 /* send SDTR */ 1251 int cnt = 0; 1252 1253 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1254 sc->sc_msgbuf[cnt++] = 1255 MSG_IDENTIFY(periph->periph_lun, 0); 1256 1257 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1258 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1259 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1260 sc->sc_msgbuf[cnt++] = ti->period; 1261 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1262 sc->sc_msgcnt = cnt; 1263 ti->flag |= SYNC_NEGO_DOING; 1264 } 1265 } 1266 if (sc->sc_msgcnt == 0) { 1267 sc->sc_msgbuf[0] = MSG_ABORT; 1268 sc->sc_msgcnt = 1; 1269 sc->sc_state = TRM_ABORT_SENT; 1270 } 1271 1272 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1273 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1274 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1275 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1276 1277 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1278 sc->sc_msgbuf, sc->sc_msgcnt); 1279 sc->sc_msgcnt = 0; 1280 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1281 1282 /* it's important for atn stop */ 1283 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1284 1285 /* 1286 * SCSI command 1287 */ 1288 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1289 } 1290 1291 static void 1292 trm_command_phase1(struct trm_softc *sc) 1293 { 1294 bus_space_tag_t iot = sc->sc_iot; 1295 bus_space_handle_t ioh = sc->sc_ioh; 1296 struct trm_srb *srb; 1297 1298 srb = sc->sc_actsrb; 1299 if (srb == NULL) { 1300 DPRINTF(("trm_command_phase1: no active srb\n")); 1301 return; 1302 } 1303 1304 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1305 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1306 1307 sc->sc_state = TRM_COMMAND; 1308 /* it's important for atn stop */ 1309 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1310 1311 /* 1312 * SCSI command 1313 */ 1314 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1315 } 1316 1317 static void 1318 trm_dataout_phase0(struct trm_softc *sc, int stat) 1319 { 1320 bus_space_tag_t iot = sc->sc_iot; 1321 bus_space_handle_t ioh = sc->sc_ioh; 1322 struct trm_srb *srb; 1323 struct scsipi_periph *periph; 1324 struct trm_tinfo *ti; 1325 struct trm_sg_entry *sg; 1326 int sgindex; 1327 uint32_t xferlen, leftcnt = 0; 1328 1329 if (sc->sc_state == TRM_XFERPAD) 1330 return; 1331 1332 srb = sc->sc_actsrb; 1333 if (srb == NULL) { 1334 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1335 return; 1336 } 1337 periph = srb->xs->xs_periph; 1338 ti = &sc->sc_tinfo[periph->periph_target]; 1339 1340 if ((stat & PARITYERROR) != 0) 1341 srb->flag |= PARITY_ERROR; 1342 1343 if ((stat & SCSIXFERDONE) == 0) { 1344 /* 1345 * when data transfer from DMA FIFO to SCSI FIFO 1346 * if there was some data left in SCSI FIFO 1347 */ 1348 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1349 SCSI_FIFOCNT_MASK; 1350 if (ti->synctl & WIDE_SYNC) 1351 /* 1352 * if WIDE scsi SCSI FIFOCNT unit is word 1353 * so need to * 2 1354 */ 1355 leftcnt <<= 1; 1356 } 1357 /* 1358 * calculate all the residue data that was not yet transferred 1359 * SCSI transfer counter + left in SCSI FIFO data 1360 * 1361 * .....TRM_SCSI_XCNT (24bits) 1362 * The counter always decrements by one for every SCSI 1363 * byte transfer. 1364 * .....TRM_SCSI_FIFOCNT ( 5bits) 1365 * The counter is SCSI FIFO offset counter 1366 */ 1367 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1368 if (leftcnt == 1) { 1369 leftcnt = 0; 1370 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1371 } 1372 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1373 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1374 DMAXFERCOMP) == 0) 1375 ; /* XXX needs timeout */ 1376 1377 srb->buflen = 0; 1378 } else { 1379 /* Update SG list */ 1380 1381 /* 1382 * if transfer not yet complete 1383 * there were some data residue in SCSI FIFO or 1384 * SCSI transfer counter not empty 1385 */ 1386 if (srb->buflen != leftcnt) { 1387 /* data that had transferred length */ 1388 xferlen = srb->buflen - leftcnt; 1389 1390 /* next time to be transferred length */ 1391 srb->buflen = leftcnt; 1392 1393 /* 1394 * parsing from last time disconnect sgindex 1395 */ 1396 sg = srb->sgentry + srb->sgindex; 1397 for (sgindex = srb->sgindex; 1398 sgindex < srb->sgcnt; 1399 sgindex++, sg++) { 1400 /* 1401 * find last time which SG transfer 1402 * be disconnect 1403 */ 1404 if (xferlen >= le32toh(sg->length)) 1405 xferlen -= le32toh(sg->length); 1406 else { 1407 /* 1408 * update last time 1409 * disconnected SG list 1410 */ 1411 /* residue data length */ 1412 sg->length = 1413 htole32(le32toh(sg->length) 1414 - xferlen); 1415 /* residue data pointer */ 1416 sg->address = 1417 htole32(le32toh(sg->address) 1418 + xferlen); 1419 srb->sgindex = sgindex; 1420 break; 1421 } 1422 } 1423 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1424 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1425 } 1426 } 1427 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1428 } 1429 1430 static void 1431 trm_datain_phase0(struct trm_softc *sc, int stat) 1432 { 1433 bus_space_tag_t iot = sc->sc_iot; 1434 bus_space_handle_t ioh = sc->sc_ioh; 1435 struct trm_srb *srb; 1436 struct trm_sg_entry *sg; 1437 int sgindex; 1438 uint32_t xferlen, leftcnt = 0; 1439 1440 if (sc->sc_state == TRM_XFERPAD) 1441 return; 1442 1443 srb = sc->sc_actsrb; 1444 if (srb == NULL) { 1445 DPRINTF(("trm_datain_phase0: no active srb\n")); 1446 return; 1447 } 1448 1449 if (stat & PARITYERROR) 1450 srb->flag |= PARITY_ERROR; 1451 1452 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1453 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1454 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1455 DMAXFERCOMP) == 0) 1456 ; /* XXX needs timeout */ 1457 1458 srb->buflen = 0; 1459 } else { /* phase changed */ 1460 /* 1461 * parsing the case: 1462 * when a transfer not yet complete 1463 * but be disconnected by upper layer 1464 * if transfer not yet complete 1465 * there were some data residue in SCSI FIFO or 1466 * SCSI transfer counter not empty 1467 */ 1468 if (srb->buflen != leftcnt) { 1469 /* 1470 * data that had transferred length 1471 */ 1472 xferlen = srb->buflen - leftcnt; 1473 1474 /* 1475 * next time to be transferred length 1476 */ 1477 srb->buflen = leftcnt; 1478 1479 /* 1480 * parsing from last time disconnect sgindex 1481 */ 1482 sg = srb->sgentry + srb->sgindex; 1483 for (sgindex = srb->sgindex; 1484 sgindex < srb->sgcnt; 1485 sgindex++, sg++) { 1486 /* 1487 * find last time which SG transfer 1488 * be disconnect 1489 */ 1490 if (xferlen >= le32toh(sg->length)) 1491 xferlen -= le32toh(sg->length); 1492 else { 1493 /* 1494 * update last time 1495 * disconnected SG list 1496 */ 1497 /* residue data length */ 1498 sg->length = 1499 htole32(le32toh(sg->length) 1500 - xferlen); 1501 /* residue data pointer */ 1502 sg->address = 1503 htole32(le32toh(sg->address) 1504 + xferlen); 1505 srb->sgindex = sgindex; 1506 break; 1507 } 1508 } 1509 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1510 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1511 } 1512 } 1513 } 1514 1515 static void 1516 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1517 { 1518 bus_space_tag_t iot = sc->sc_iot; 1519 bus_space_handle_t ioh = sc->sc_ioh; 1520 struct trm_srb *srb; 1521 struct scsipi_periph *periph; 1522 struct trm_tinfo *ti; 1523 1524 srb = sc->sc_actsrb; 1525 if (srb == NULL) { 1526 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1527 return; 1528 } 1529 periph = srb->xs->xs_periph; 1530 ti = &sc->sc_tinfo[periph->periph_target]; 1531 1532 if (srb->sgindex < srb->sgcnt) { 1533 if (srb->buflen > 0) { 1534 /* 1535 * load what physical address of Scatter/Gather 1536 * list table want to be transfer 1537 */ 1538 sc->sc_state = TRM_DATA_XFER; 1539 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1540 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1541 srb->sgaddr + 1542 srb->sgindex * sizeof(struct trm_sg_entry)); 1543 /* 1544 * load how many bytes in the Scatter/Gather list table 1545 */ 1546 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1547 (srb->sgcnt - srb->sgindex) 1548 * sizeof(struct trm_sg_entry)); 1549 /* 1550 * load total xfer length (24bits) max value 16Mbyte 1551 */ 1552 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1553 /* Start DMA transfer */ 1554 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1555 iodir | SGXFER); 1556 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1557 STARTDMAXFER); 1558 1559 /* Start SCSI transfer */ 1560 /* it's important for atn stop */ 1561 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1562 DO_DATALATCH); 1563 1564 /* 1565 * SCSI command 1566 */ 1567 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1568 (iodir == XFERDATAOUT) ? 1569 SCMD_DMA_OUT : SCMD_DMA_IN); 1570 } else { /* xfer pad */ 1571 if (srb->sgcnt) { 1572 srb->hastat = H_OVER_UNDER_RUN; 1573 } 1574 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1575 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1576 1577 if (iodir == XFERDATAOUT) 1578 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1579 else 1580 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1581 1582 sc->sc_state = TRM_XFERPAD; 1583 /* it's important for atn stop */ 1584 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1585 DO_DATALATCH); 1586 1587 /* 1588 * SCSI command 1589 */ 1590 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1591 (iodir == XFERDATAOUT) ? 1592 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1593 } 1594 } 1595 } 1596 1597 static void 1598 trm_status_phase0(struct trm_softc *sc) 1599 { 1600 bus_space_tag_t iot = sc->sc_iot; 1601 bus_space_handle_t ioh = sc->sc_ioh; 1602 struct trm_srb *srb; 1603 1604 srb = sc->sc_actsrb; 1605 if (srb == NULL) { 1606 DPRINTF(("trm_status_phase0: no active srb\n")); 1607 return; 1608 } 1609 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1610 sc->sc_state = TRM_COMPLETED; 1611 /* it's important for atn stop */ 1612 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1613 1614 /* 1615 * SCSI command 1616 */ 1617 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1618 } 1619 1620 static void 1621 trm_status_phase1(struct trm_softc *sc) 1622 { 1623 bus_space_tag_t iot = sc->sc_iot; 1624 bus_space_handle_t ioh = sc->sc_ioh; 1625 1626 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1627 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1628 & SCSI_FIFO_EMPTY) == 0) 1629 bus_space_write_2(iot, ioh, 1630 TRM_SCSI_CONTROL, DO_CLRFIFO); 1631 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1632 & DMA_FIFO_EMPTY) == 0) 1633 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1634 } else { 1635 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1636 & DMA_FIFO_EMPTY) == 0) 1637 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1638 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1639 & SCSI_FIFO_EMPTY) == 0) 1640 bus_space_write_2(iot, ioh, 1641 TRM_SCSI_CONTROL, DO_CLRFIFO); 1642 } 1643 sc->sc_state = TRM_STATUS; 1644 /* it's important for atn stop */ 1645 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1646 1647 /* 1648 * SCSI command 1649 */ 1650 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1651 } 1652 1653 static void 1654 trm_msgin_phase0(struct trm_softc *sc) 1655 { 1656 bus_space_tag_t iot = sc->sc_iot; 1657 bus_space_handle_t ioh = sc->sc_ioh; 1658 struct trm_srb *srb; 1659 struct scsipi_periph *periph; 1660 struct trm_tinfo *ti; 1661 int index; 1662 uint8_t msgin_code; 1663 1664 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1665 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1666 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1667 switch (msgin_code) { 1668 case MSG_DISCONNECT: 1669 sc->sc_state = TRM_DISCONNECTED; 1670 break; 1671 1672 case MSG_SAVEDATAPOINTER: 1673 break; 1674 1675 case MSG_EXTENDED: 1676 case MSG_SIMPLE_Q_TAG: 1677 case MSG_HEAD_OF_Q_TAG: 1678 case MSG_ORDERED_Q_TAG: 1679 sc->sc_state = TRM_EXTEND_MSGIN; 1680 /* extended message (01h) */ 1681 sc->sc_msgbuf[0] = msgin_code; 1682 1683 sc->sc_msgcnt = 1; 1684 /* extended message length (n) */ 1685 sc->sc_msg = &sc->sc_msgbuf[1]; 1686 1687 break; 1688 case MSG_MESSAGE_REJECT: 1689 /* Reject message */ 1690 srb = sc->sc_actsrb; 1691 if (srb == NULL) { 1692 DPRINTF(("trm_msgin_phase0: " 1693 " message reject without actsrb\n")); 1694 break; 1695 } 1696 periph = srb->xs->xs_periph; 1697 ti = &sc->sc_tinfo[periph->periph_target]; 1698 1699 if (ti->flag & WIDE_NEGO_ENABLE) { 1700 /* do wide nego reject */ 1701 ti->flag |= WIDE_NEGO_DONE; 1702 ti->flag &= 1703 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1704 if ((ti->flag & SYNC_NEGO_ENABLE) && 1705 (ti->flag & SYNC_NEGO_DONE) == 0) { 1706 /* Set ATN, in case ATN was clear */ 1707 sc->sc_state = TRM_MSGOUT; 1708 bus_space_write_2(iot, ioh, 1709 TRM_SCSI_CONTROL, DO_SETATN); 1710 } else 1711 /* Clear ATN */ 1712 bus_space_write_2(iot, ioh, 1713 TRM_SCSI_CONTROL, DO_CLRATN); 1714 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1715 /* do sync nego reject */ 1716 bus_space_write_2(iot, ioh, 1717 TRM_SCSI_CONTROL, DO_CLRATN); 1718 if (ti->flag & SYNC_NEGO_DOING) { 1719 ti->flag &=~(SYNC_NEGO_ENABLE | 1720 SYNC_NEGO_DONE); 1721 ti->synctl = 0; 1722 ti->offset = 0; 1723 bus_space_write_1(iot, ioh, 1724 TRM_SCSI_SYNC, ti->synctl); 1725 bus_space_write_1(iot, ioh, 1726 TRM_SCSI_OFFSET, ti->offset); 1727 } 1728 } 1729 break; 1730 1731 case MSG_IGN_WIDE_RESIDUE: 1732 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1733 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1734 break; 1735 1736 default: 1737 /* 1738 * Restore data pointer message 1739 * Save data pointer message 1740 * Completion message 1741 * NOP message 1742 */ 1743 break; 1744 } 1745 } else { 1746 /* 1747 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1748 * Parsing incoming extented messages 1749 */ 1750 *sc->sc_msg++ = msgin_code; 1751 sc->sc_msgcnt++; 1752 1753 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1754 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1755 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1756 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1757 1758 switch (sc->sc_msgbuf[0]) { 1759 case MSG_SIMPLE_Q_TAG: 1760 case MSG_HEAD_OF_Q_TAG: 1761 case MSG_ORDERED_Q_TAG: 1762 /* 1763 * is QUEUE tag message : 1764 * 1765 * byte 0: 1766 * HEAD QUEUE TAG (20h) 1767 * ORDERED QUEUE TAG (21h) 1768 * SIMPLE QUEUE TAG (22h) 1769 * byte 1: 1770 * Queue tag (00h - FFh) 1771 */ 1772 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1773 /* XXX XXX XXX */ 1774 struct trm_linfo *li; 1775 int tagid; 1776 1777 sc->sc_flag &= ~WAIT_TAGMSG; 1778 tagid = sc->sc_msgbuf[1]; 1779 ti = &sc->sc_tinfo[sc->resel_target]; 1780 li = ti->linfo[sc->resel_lun]; 1781 srb = li->queued[tagid]; 1782 if (srb != NULL) { 1783 sc->sc_actsrb = srb; 1784 sc->sc_state = TRM_DATA_XFER; 1785 break; 1786 } else { 1787 printf("%s: invalid tag id\n", 1788 sc->sc_dev.dv_xname); 1789 } 1790 1791 sc->sc_state = TRM_UNEXPECT_RESEL; 1792 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1793 sc->sc_msgcnt = 1; 1794 bus_space_write_2(iot, ioh, 1795 TRM_SCSI_CONTROL, DO_SETATN); 1796 } else 1797 sc->sc_state = TRM_IDLE; 1798 break; 1799 1800 case MSG_EXTENDED: 1801 srb = sc->sc_actsrb; 1802 if (srb == NULL) { 1803 DPRINTF(("trm_msgin_phase0: " 1804 "extended message without actsrb\n")); 1805 break; 1806 } 1807 periph = srb->xs->xs_periph; 1808 ti = &sc->sc_tinfo[periph->periph_target]; 1809 1810 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1811 sc->sc_msgcnt == 4) { 1812 /* 1813 * is Wide data xfer Extended message : 1814 * ====================================== 1815 * WIDE DATA TRANSFER REQUEST 1816 * ====================================== 1817 * byte 0 : Extended message (01h) 1818 * byte 1 : Extended message length (02h) 1819 * byte 2 : WIDE DATA TRANSFER code (03h) 1820 * byte 3 : Transfer width exponent 1821 */ 1822 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1823 /* Length is wrong, reject it */ 1824 ti->flag &= ~(WIDE_NEGO_ENABLE | 1825 WIDE_NEGO_DONE); 1826 sc->sc_state = TRM_MSGOUT; 1827 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1828 sc->sc_msgcnt = 1; 1829 bus_space_write_2(iot, ioh, 1830 TRM_SCSI_CONTROL, DO_SETATN); 1831 break; 1832 } 1833 1834 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1835 sc->sc_msgbuf[3] = 1836 MSG_EXT_WDTR_BUS_8_BIT; 1837 1838 if (sc->sc_msgbuf[3] > 1839 MSG_EXT_WDTR_BUS_32_BIT) { 1840 /* reject_msg: */ 1841 ti->flag &= ~(WIDE_NEGO_ENABLE | 1842 WIDE_NEGO_DONE); 1843 sc->sc_state = TRM_MSGOUT; 1844 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1845 sc->sc_msgcnt = 1; 1846 bus_space_write_2(iot, ioh, 1847 TRM_SCSI_CONTROL, DO_SETATN); 1848 break; 1849 } 1850 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1851 /* do 16 bits */ 1852 sc->sc_msgbuf[3] = 1853 MSG_EXT_WDTR_BUS_16_BIT; 1854 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1855 ti->flag |= WIDE_NEGO_DONE; 1856 ti->flag &= ~(SYNC_NEGO_DONE | 1857 WIDE_NEGO_ENABLE); 1858 if (sc->sc_msgbuf[3] != 1859 MSG_EXT_WDTR_BUS_8_BIT) 1860 /* is Wide data xfer */ 1861 ti->synctl |= WIDE_SYNC; 1862 trm_update_xfer_mode(sc, 1863 periph->periph_target); 1864 } 1865 1866 sc->sc_state = TRM_MSGOUT; 1867 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1868 DO_SETATN); 1869 break; 1870 1871 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1872 sc->sc_msgcnt == 5) { 1873 /* 1874 * is 8bit transfer Extended message : 1875 * ================================= 1876 * SYNCHRONOUS DATA TRANSFER REQUEST 1877 * ================================= 1878 * byte 0 : Extended message (01h) 1879 * byte 1 : Extended message length (03) 1880 * byte 2 : SYNC DATA TRANSFER code (01h) 1881 * byte 3 : Transfer period factor 1882 * byte 4 : REQ/ACK offset 1883 */ 1884 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1885 /* reject_msg */ 1886 sc->sc_state = TRM_MSGOUT; 1887 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1888 sc->sc_msgcnt = 1; 1889 bus_space_write_2(iot, ioh, 1890 TRM_SCSI_CONTROL, DO_SETATN); 1891 break; 1892 } 1893 1894 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1895 ti->flag &= 1896 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1897 ti->flag |= SYNC_NEGO_DONE; 1898 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1899 sc->sc_msgbuf[3] = 0; 1900 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1901 sc->sc_msgbuf[4] = 1902 TRM_MAX_OFFSET; 1903 1904 if (sc->sc_msgbuf[3] == 0 || 1905 sc->sc_msgbuf[4] == 0) { 1906 /* set async */ 1907 ti->synctl = 0; 1908 ti->offset = 0; 1909 } else { 1910 /* set sync */ 1911 /* Transfer period factor */ 1912 ti->period = sc->sc_msgbuf[3]; 1913 /* REQ/ACK offset */ 1914 ti->offset = sc->sc_msgbuf[4]; 1915 for (index = 0; 1916 index < NPERIOD; 1917 index++) 1918 if (ti->period <= 1919 trm_clock_period[ 1920 index]) 1921 break; 1922 1923 ti->synctl |= ALT_SYNC | index; 1924 } 1925 /* 1926 * program SCSI control register 1927 */ 1928 bus_space_write_1(iot, ioh, 1929 TRM_SCSI_SYNC, ti->synctl); 1930 bus_space_write_1(iot, ioh, 1931 TRM_SCSI_OFFSET, ti->offset); 1932 trm_update_xfer_mode(sc, 1933 periph->periph_target); 1934 } 1935 sc->sc_state = TRM_IDLE; 1936 } 1937 break; 1938 default: 1939 break; 1940 } 1941 } 1942 1943 /* it's important for atn stop */ 1944 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1945 1946 /* 1947 * SCSI command 1948 */ 1949 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1950 } 1951 1952 static void 1953 trm_msgin_phase1(struct trm_softc *sc) 1954 { 1955 bus_space_tag_t iot = sc->sc_iot; 1956 bus_space_handle_t ioh = sc->sc_ioh; 1957 1958 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1959 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1960 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1961 sc->sc_state = TRM_MSGIN; 1962 } 1963 1964 /* it's important for atn stop */ 1965 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1966 1967 /* 1968 * SCSI command 1969 */ 1970 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1971 } 1972 1973 static void 1974 trm_disconnect(struct trm_softc *sc) 1975 { 1976 bus_space_tag_t iot = sc->sc_iot; 1977 bus_space_handle_t ioh = sc->sc_ioh; 1978 struct trm_srb *srb; 1979 int s; 1980 1981 s = splbio(); 1982 1983 srb = sc->sc_actsrb; 1984 DPRINTF(("trm_disconnect...............\n")); 1985 1986 if (srb == NULL) { 1987 DPRINTF(("trm_disconnect: no active srb\n")); 1988 DELAY(1000); /* 1 msec */ 1989 1990 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1991 DO_CLRFIFO | DO_HWRESELECT); 1992 return; 1993 } 1994 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1995 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1996 DO_CLRFIFO | DO_HWRESELECT); 1997 DELAY(100); 1998 1999 switch (sc->sc_state) { 2000 case TRM_UNEXPECT_RESEL: 2001 sc->sc_state = TRM_IDLE; 2002 break; 2003 2004 case TRM_ABORT_SENT: 2005 goto finish; 2006 2007 case TRM_START: 2008 case TRM_MSGOUT: 2009 { 2010 /* Selection time out - discard all LUNs if empty */ 2011 struct scsipi_periph *periph; 2012 struct trm_tinfo *ti; 2013 struct trm_linfo *li; 2014 int lun; 2015 2016 DPRINTF(("selection timeout\n")); 2017 2018 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2019 2020 periph = srb->xs->xs_periph; 2021 ti = &sc->sc_tinfo[periph->periph_target]; 2022 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2023 li = ti->linfo[lun]; 2024 if (li != NULL && 2025 li->untagged == NULL && li->used == 0) { 2026 ti->linfo[lun] = NULL; 2027 free(li, M_DEVBUF); 2028 } 2029 } 2030 } 2031 goto finish; 2032 2033 case TRM_DISCONNECTED: 2034 sc->sc_actsrb = NULL; 2035 sc->sc_state = TRM_IDLE; 2036 goto sched; 2037 2038 case TRM_COMPLETED: 2039 goto finish; 2040 } 2041 2042 out: 2043 splx(s); 2044 return; 2045 2046 finish: 2047 sc->sc_state = TRM_IDLE; 2048 trm_done(sc, srb); 2049 goto out; 2050 2051 sched: 2052 trm_sched(sc); 2053 goto out; 2054 } 2055 2056 static void 2057 trm_reselect(struct trm_softc *sc) 2058 { 2059 bus_space_tag_t iot = sc->sc_iot; 2060 bus_space_handle_t ioh = sc->sc_ioh; 2061 struct trm_tinfo *ti; 2062 struct trm_linfo *li; 2063 int target, lun; 2064 2065 DPRINTF(("trm_reselect.................\n")); 2066 2067 if (sc->sc_actsrb != NULL) { 2068 /* arbitration lost but reselection win */ 2069 sc->sc_state = TRM_READY; 2070 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2071 ti = &sc->sc_tinfo[target]; 2072 } else { 2073 /* Read Reselected Target Id and LUN */ 2074 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2075 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2076 ti = &sc->sc_tinfo[target]; 2077 li = ti->linfo[lun]; 2078 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2079 2080 /* 2081 * Check to see if we are running an un-tagged command. 2082 * Otherwise ack the IDENTIFY and wait for a tag message. 2083 */ 2084 if (li != NULL) { 2085 if (li->untagged != NULL && li->busy) { 2086 sc->sc_actsrb = li->untagged; 2087 sc->sc_state = TRM_DATA_XFER; 2088 } else { 2089 sc->resel_target = target; 2090 sc->resel_lun = lun; 2091 /* XXX XXX XXX */ 2092 sc->sc_flag |= WAIT_TAGMSG; 2093 } 2094 } 2095 2096 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2097 sc->sc_actsrb == NULL) { 2098 printf("%s: reselect from target %d lun %d " 2099 "without nexus; sending abort\n", 2100 sc->sc_dev.dv_xname, target, lun); 2101 sc->sc_state = TRM_UNEXPECT_RESEL; 2102 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2103 sc->sc_msgcnt = 1; 2104 bus_space_write_2(iot, ioh, 2105 TRM_SCSI_CONTROL, DO_SETATN); 2106 } 2107 } 2108 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2109 /* 2110 * Program HA ID, target ID, period and offset 2111 */ 2112 /* target ID */ 2113 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2114 2115 /* host ID */ 2116 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2117 2118 /* period */ 2119 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2120 2121 /* offset */ 2122 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2123 2124 /* it's important for atn stop */ 2125 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2126 /* 2127 * SCSI command 2128 */ 2129 /* to rls the /ACK signal */ 2130 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2131 } 2132 2133 /* 2134 * Complete execution of a SCSI command 2135 * Signal completion to the generic SCSI driver 2136 */ 2137 static void 2138 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2139 { 2140 struct scsipi_xfer *xs = srb->xs; 2141 2142 DPRINTF(("trm_done..................\n")); 2143 2144 if (xs == NULL) 2145 return; 2146 2147 if ((xs->xs_control & XS_CTL_POLL) == 0) 2148 callout_stop(&xs->xs_callout); 2149 2150 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2151 srb->flag & AUTO_REQSENSE) { 2152 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2153 srb->dmap->dm_mapsize, 2154 ((xs->xs_control & XS_CTL_DATA_IN) || 2155 (srb->flag & AUTO_REQSENSE)) ? 2156 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2157 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2158 } 2159 2160 /* 2161 * target status 2162 */ 2163 xs->status = srb->tastat; 2164 2165 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2166 2167 switch (xs->status) { 2168 case SCSI_OK: 2169 /* 2170 * process initiator status...... 2171 * Adapter (initiator) status 2172 */ 2173 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2174 printf("%s: over/under run error\n", 2175 sc->sc_dev.dv_xname); 2176 srb->tastat = 0; 2177 /* Illegal length (over/under run) */ 2178 xs->error = XS_DRIVER_STUFFUP; 2179 } else if ((srb->flag & PARITY_ERROR) != 0) { 2180 printf("%s: parity error\n", 2181 sc->sc_dev.dv_xname); 2182 /* Driver failed to perform operation */ 2183 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2184 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2185 xs->resid = srb->buflen; 2186 xs->error = XS_TIMEOUT; 2187 } else { 2188 /* No error */ 2189 xs->resid = srb->buflen; 2190 srb->hastat = 0; 2191 if (srb->flag & AUTO_REQSENSE) { 2192 /* there is no error, (sense is invalid) */ 2193 xs->error = XS_SENSE; 2194 } else { 2195 srb->tastat = 0; 2196 xs->error = XS_NOERROR; 2197 } 2198 } 2199 break; 2200 2201 case SCSI_CHECK: 2202 if ((srb->flag & AUTO_REQSENSE) != 0 || 2203 trm_request_sense(sc, srb) != 0) { 2204 printf("%s: request sense failed\n", 2205 sc->sc_dev.dv_xname); 2206 xs->error = XS_DRIVER_STUFFUP; 2207 break; 2208 } 2209 xs->error = XS_SENSE; 2210 return; 2211 2212 case SCSI_SEL_TIMEOUT: 2213 srb->hastat = H_SEL_TIMEOUT; 2214 srb->tastat = 0; 2215 xs->error = XS_SELTIMEOUT; 2216 break; 2217 2218 case SCSI_QUEUE_FULL: 2219 case SCSI_BUSY: 2220 xs->error = XS_BUSY; 2221 break; 2222 2223 case SCSI_RESV_CONFLICT: 2224 DPRINTF(("%s: target reserved at ", sc->sc_dev.dv_xname)); 2225 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2226 xs->error = XS_BUSY; 2227 break; 2228 2229 default: 2230 srb->hastat = 0; 2231 printf("%s: trm_done(): unknown status = %02x\n", 2232 sc->sc_dev.dv_xname, xs->status); 2233 xs->error = XS_DRIVER_STUFFUP; 2234 break; 2235 } 2236 2237 trm_dequeue(sc, srb); 2238 if (srb == sc->sc_actsrb) { 2239 sc->sc_actsrb = NULL; 2240 trm_sched(sc); 2241 } 2242 2243 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2244 2245 /* Notify cmd done */ 2246 scsipi_done(xs); 2247 } 2248 2249 static int 2250 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2251 { 2252 struct scsipi_xfer *xs; 2253 struct scsipi_periph *periph; 2254 struct trm_tinfo *ti; 2255 struct trm_linfo *li; 2256 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2257 int error; 2258 2259 DPRINTF(("trm_request_sense...\n")); 2260 2261 xs = srb->xs; 2262 periph = xs->xs_periph; 2263 2264 srb->flag |= AUTO_REQSENSE; 2265 2266 /* Status of initiator/target */ 2267 srb->hastat = 0; 2268 srb->tastat = 0; 2269 2270 memset(ss, 0, sizeof(*ss)); 2271 ss->opcode = SCSI_REQUEST_SENSE; 2272 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2273 ss->length = sizeof(struct scsi_sense_data); 2274 2275 srb->buflen = sizeof(struct scsi_sense_data); 2276 srb->sgcnt = 1; 2277 srb->sgindex = 0; 2278 srb->cmdlen = sizeof(struct scsi_request_sense); 2279 2280 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2281 &xs->sense.scsi_sense, srb->buflen, NULL, 2282 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2283 return error; 2284 } 2285 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2286 srb->buflen, BUS_DMASYNC_PREREAD); 2287 2288 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2289 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2290 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2291 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2292 2293 ti = &sc->sc_tinfo[periph->periph_target]; 2294 li = ti->linfo[periph->periph_lun]; 2295 if (li->busy > 0) 2296 li->busy = 0; 2297 trm_dequeue(sc, srb); 2298 li->untagged = srb; /* must be executed first to fix C/A */ 2299 li->busy = 2; 2300 2301 if (srb == sc->sc_actsrb) 2302 trm_select(sc, srb); 2303 else { 2304 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2305 if (sc->sc_actsrb == NULL) 2306 trm_sched(sc); 2307 } 2308 return 0; 2309 } 2310 2311 static void 2312 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2313 { 2314 struct scsipi_periph *periph; 2315 struct trm_tinfo *ti; 2316 struct trm_linfo *li; 2317 2318 periph = srb->xs->xs_periph; 2319 ti = &sc->sc_tinfo[periph->periph_target]; 2320 li = ti->linfo[periph->periph_lun]; 2321 2322 if (li->untagged == srb) { 2323 li->busy = 0; 2324 li->untagged = NULL; 2325 } 2326 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2327 li->queued[srb->tag[1]] = NULL; 2328 li->used--; 2329 } 2330 } 2331 2332 static void 2333 trm_reset_scsi_bus(struct trm_softc *sc) 2334 { 2335 bus_space_tag_t iot = sc->sc_iot; 2336 bus_space_handle_t ioh = sc->sc_ioh; 2337 int timeout, s; 2338 2339 DPRINTF(("trm_reset_scsi_bus.........\n")); 2340 2341 s = splbio(); 2342 2343 sc->sc_flag |= RESET_DEV; 2344 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2345 for (timeout = 20000; timeout >= 0; timeout--) { 2346 DELAY(1); 2347 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2348 INT_SCSIRESET) == 0) 2349 break; 2350 } 2351 if (timeout == 0) 2352 printf(": scsibus reset timeout\n"); 2353 2354 splx(s); 2355 } 2356 2357 static void 2358 trm_scsi_reset_detect(struct trm_softc *sc) 2359 { 2360 bus_space_tag_t iot = sc->sc_iot; 2361 bus_space_handle_t ioh = sc->sc_ioh; 2362 int s; 2363 2364 DPRINTF(("trm_scsi_reset_detect...............\n")); 2365 DELAY(1000000); /* delay 1 sec */ 2366 2367 s = splbio(); 2368 2369 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2370 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2371 2372 if (sc->sc_flag & RESET_DEV) { 2373 sc->sc_flag |= RESET_DONE; 2374 } else { 2375 sc->sc_flag |= RESET_DETECT; 2376 sc->sc_actsrb = NULL; 2377 sc->sc_flag = 0; 2378 trm_sched(sc); 2379 } 2380 splx(s); 2381 } 2382 2383 /* 2384 * read seeprom 128 bytes to struct eeprom and check checksum. 2385 * If it is wrong, update with default value. 2386 */ 2387 static void 2388 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2389 { 2390 struct nvram_target *target; 2391 uint16_t *ep; 2392 uint16_t chksum; 2393 int i; 2394 2395 DPRINTF(("trm_check_eeprom......\n")); 2396 trm_eeprom_read_all(sc, eeprom); 2397 ep = (uint16_t *)eeprom; 2398 chksum = 0; 2399 for (i = 0; i < 64; i++) 2400 chksum += le16toh(*ep++); 2401 2402 if (chksum != TRM_NVRAM_CKSUM) { 2403 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2404 /* 2405 * Checksum error, load default 2406 */ 2407 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2408 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2409 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2410 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2411 eeprom->subclass = 0x00; 2412 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2413 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2414 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2415 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2416 eeprom->reserved0 = 0x00; 2417 2418 for (i = 0, target = eeprom->target; 2419 i < TRM_MAX_TARGETS; 2420 i++, target++) { 2421 target->config0 = 0x77; 2422 target->period = 0x00; 2423 target->config2 = 0x00; 2424 target->config3 = 0x00; 2425 } 2426 2427 eeprom->scsi_id = 7; 2428 eeprom->channel_cfg = 0x0F; 2429 eeprom->delay_time = 0; 2430 eeprom->max_tag = 4; 2431 eeprom->reserved1 = 0x15; 2432 eeprom->boot_target = 0; 2433 eeprom->boot_lun = 0; 2434 eeprom->reserved2 = 0; 2435 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2436 2437 chksum = 0; 2438 ep = (uint16_t *)eeprom; 2439 for (i = 0; i < 63; i++) 2440 chksum += le16toh(*ep++); 2441 2442 chksum = TRM_NVRAM_CKSUM - chksum; 2443 eeprom->checksum0 = chksum & 0xFF; 2444 eeprom->checksum1 = chksum >> 8; 2445 2446 trm_eeprom_write_all(sc, eeprom); 2447 } 2448 } 2449 2450 /* 2451 * write struct eeprom 128 bytes to seeprom 2452 */ 2453 static void 2454 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2455 { 2456 bus_space_tag_t iot = sc->sc_iot; 2457 bus_space_handle_t ioh = sc->sc_ioh; 2458 uint8_t *sbuf = (uint8_t *)eeprom; 2459 uint8_t addr; 2460 2461 /* Enable SEEPROM */ 2462 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2463 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2464 2465 /* 2466 * Write enable 2467 */ 2468 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2469 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2470 trm_eeprom_wait(); 2471 2472 for (addr = 0; addr < 128; addr++, sbuf++) 2473 trm_eeprom_set_data(sc, addr, *sbuf); 2474 2475 /* 2476 * Write disable 2477 */ 2478 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2479 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2480 trm_eeprom_wait(); 2481 2482 /* Disable SEEPROM */ 2483 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2484 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2485 } 2486 2487 /* 2488 * write one byte to seeprom 2489 */ 2490 static void 2491 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2492 { 2493 bus_space_tag_t iot = sc->sc_iot; 2494 bus_space_handle_t ioh = sc->sc_ioh; 2495 int i; 2496 uint8_t send; 2497 2498 /* 2499 * Send write command & address 2500 */ 2501 trm_eeprom_write_cmd(sc, 0x05, addr); 2502 /* 2503 * Write data 2504 */ 2505 for (i = 0; i < 8; i++, data <<= 1) { 2506 send = NVR_SELECT; 2507 if (data & 0x80) /* Start from bit 7 */ 2508 send |= NVR_BITOUT; 2509 2510 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2511 trm_eeprom_wait(); 2512 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2513 trm_eeprom_wait(); 2514 } 2515 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2516 trm_eeprom_wait(); 2517 /* 2518 * Disable chip select 2519 */ 2520 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2521 trm_eeprom_wait(); 2522 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2523 trm_eeprom_wait(); 2524 /* 2525 * Wait for write ready 2526 */ 2527 for (;;) { 2528 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2529 NVR_SELECT | NVR_CLOCK); 2530 trm_eeprom_wait(); 2531 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2532 trm_eeprom_wait(); 2533 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2534 break; 2535 } 2536 /* 2537 * Disable chip select 2538 */ 2539 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2540 } 2541 2542 /* 2543 * read seeprom 128 bytes to struct eeprom 2544 */ 2545 static void 2546 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2547 { 2548 bus_space_tag_t iot = sc->sc_iot; 2549 bus_space_handle_t ioh = sc->sc_ioh; 2550 uint8_t *sbuf = (uint8_t *)eeprom; 2551 uint8_t addr; 2552 2553 /* 2554 * Enable SEEPROM 2555 */ 2556 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2557 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2558 2559 for (addr = 0; addr < 128; addr++) 2560 *sbuf++ = trm_eeprom_get_data(sc, addr); 2561 2562 /* 2563 * Disable SEEPROM 2564 */ 2565 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2566 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2567 } 2568 2569 /* 2570 * read one byte from seeprom 2571 */ 2572 static uint8_t 2573 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2574 { 2575 bus_space_tag_t iot = sc->sc_iot; 2576 bus_space_handle_t ioh = sc->sc_ioh; 2577 int i; 2578 uint8_t read, data = 0; 2579 2580 /* 2581 * Send read command & address 2582 */ 2583 trm_eeprom_write_cmd(sc, 0x06, addr); 2584 2585 for (i = 0; i < 8; i++) { /* Read data */ 2586 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2587 NVR_SELECT | NVR_CLOCK); 2588 trm_eeprom_wait(); 2589 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2590 /* 2591 * Get data bit while falling edge 2592 */ 2593 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2594 data <<= 1; 2595 if (read & NVR_BITIN) 2596 data |= 1; 2597 2598 trm_eeprom_wait(); 2599 } 2600 /* 2601 * Disable chip select 2602 */ 2603 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2604 return (data); 2605 } 2606 2607 /* 2608 * write SB and Op Code into seeprom 2609 */ 2610 static void 2611 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2612 { 2613 bus_space_tag_t iot = sc->sc_iot; 2614 bus_space_handle_t ioh = sc->sc_ioh; 2615 int i; 2616 uint8_t send; 2617 2618 /* Program SB+OP code */ 2619 for (i = 0; i < 3; i++, cmd <<= 1) { 2620 send = NVR_SELECT; 2621 if (cmd & 0x04) /* Start from bit 2 */ 2622 send |= NVR_BITOUT; 2623 2624 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2625 trm_eeprom_wait(); 2626 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2627 trm_eeprom_wait(); 2628 } 2629 2630 /* Program address */ 2631 for (i = 0; i < 7; i++, addr <<= 1) { 2632 send = NVR_SELECT; 2633 if (addr & 0x40) /* Start from bit 6 */ 2634 send |= NVR_BITOUT; 2635 2636 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2637 trm_eeprom_wait(); 2638 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2639 trm_eeprom_wait(); 2640 } 2641 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2642 trm_eeprom_wait(); 2643 } 2644
Indexes created Mon Sep 22 13:09:51 GMT 2025