trm.c revision 1.28
1 /* $NetBSD: trm.c,v 1.28 2008/04/10 19:13:38 cegger Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2002 Izumi Tsutsui 8 * Copyright (c) 2001 Rui-Xiang Guo 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 /* 34 * Ported from 35 * dc395x_trm.c 36 * 37 * Written for NetBSD 1.4.x by 38 * Erich Chen (erich (at) tekram.com.tw) 39 * 40 * Provided by 41 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 42 */ 43 44 #include <sys/cdefs.h> 45 __KERNEL_RCSID(0, "$NetBSD: trm.c,v 1.28 2008/04/10 19:13:38 cegger Exp $"); 46 47 /* #define TRM_DEBUG */ 48 #ifdef TRM_DEBUG 49 int trm_debug = 1; 50 #define DPRINTF(arg) if (trm_debug > 0) printf arg; 51 #else 52 #define DPRINTF(arg) 53 #endif 54 55 #include <sys/param.h> 56 #include <sys/systm.h> 57 #include <sys/malloc.h> 58 #include <sys/buf.h> 59 #include <sys/kernel.h> 60 #include <sys/device.h> 61 #include <sys/queue.h> 62 63 #include <sys/bus.h> 64 #include <sys/intr.h> 65 66 #include <uvm/uvm_extern.h> 67 68 #include <dev/scsipi/scsi_spc.h> 69 #include <dev/scsipi/scsi_all.h> 70 #include <dev/scsipi/scsi_message.h> 71 #include <dev/scsipi/scsipi_all.h> 72 #include <dev/scsipi/scsiconf.h> 73 74 #include <dev/pci/pcidevs.h> 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/trmreg.h> 78 79 /* 80 * feature of chip set MAX value 81 */ 82 #define TRM_MAX_TARGETS 16 83 #define TRM_MAX_LUNS 8 84 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 85 #define TRM_MAX_SRB 32 /* XXX */ 86 #define TRM_MAX_TAG TRM_MAX_SRB /* XXX */ 87 #define TRM_MAX_OFFSET 15 88 #define TRM_MAX_PERIOD 125 89 90 /* 91 * Segment Entry 92 */ 93 struct trm_sg_entry { 94 uint32_t address; 95 uint32_t length; 96 }; 97 98 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 99 100 /* 101 ********************************************************************** 102 * The SEEPROM structure for TRM_S1040 103 ********************************************************************** 104 */ 105 struct nvram_target { 106 uint8_t config0; /* Target configuration byte 0 */ 107 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 108 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tagged queuing */ 109 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 110 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 111 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 112 #define NTC_DO_PARITY_CHK 0x01 /* Parity check enable */ 113 uint8_t period; /* Target period */ 114 uint8_t config2; /* Target configuration byte 2 */ 115 uint8_t config3; /* Target configuration byte 3 */ 116 }; 117 118 struct trm_nvram { 119 uint8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 120 uint8_t subsys_id[2]; /* 2,3 Sub System ID */ 121 uint8_t subclass; /* 4 Sub Class */ 122 uint8_t vendor_id[2]; /* 5,6 Vendor ID */ 123 uint8_t device_id[2]; /* 7,8 Device ID */ 124 uint8_t reserved0; /* 9 Reserved */ 125 struct nvram_target target[TRM_MAX_TARGETS]; 126 /* 10,11,12,13 127 * 14,15,16,17 128 * .... 129 * 70,71,72,73 */ 130 uint8_t scsi_id; /* 74 Host Adapter SCSI ID */ 131 uint8_t channel_cfg; /* 75 Channel configuration */ 132 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 133 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 134 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 135 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 136 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 137 uint8_t delay_time; /* 76 Power on delay time */ 138 uint8_t max_tag; /* 77 Maximum tags */ 139 uint8_t reserved1; /* 78 */ 140 uint8_t boot_target; /* 79 */ 141 uint8_t boot_lun; /* 80 */ 142 uint8_t reserved2; /* 81 */ 143 uint8_t reserved3[44]; /* 82,..125 */ 144 uint8_t checksum0; /* 126 */ 145 uint8_t checksum1; /* 127 */ 146 #define TRM_NVRAM_CKSUM 0x1234 147 }; 148 149 /* Nvram Initiater bits definition */ 150 #define MORE2_DRV 0x00000001 151 #define GREATER_1G 0x00000002 152 #define RST_SCSI_BUS 0x00000004 153 #define ACTIVE_NEGATION 0x00000008 154 #define NO_SEEK 0x00000010 155 #define LUN_CHECK 0x00000020 156 157 #define trm_eeprom_wait() DELAY(30) 158 159 /* 160 *----------------------------------------------------------------------- 161 * SCSI Request Block 162 *----------------------------------------------------------------------- 163 */ 164 struct trm_srb { 165 TAILQ_ENTRY(trm_srb) next; 166 167 struct trm_sg_entry *sgentry; 168 struct scsipi_xfer *xs; /* scsipi_xfer for this cmd */ 169 bus_dmamap_t dmap; 170 bus_size_t sgoffset; /* Xfer buf offset */ 171 172 uint32_t buflen; /* Total xfer length */ 173 uint32_t sgaddr; /* SGList physical starting address */ 174 175 int sgcnt; 176 int sgindex; 177 178 int hastat; /* Host Adapter Status */ 179 #define H_STATUS_GOOD 0x00 180 #define H_SEL_TIMEOUT 0x11 181 #define H_OVER_UNDER_RUN 0x12 182 #define H_UNEXP_BUS_FREE 0x13 183 #define H_TARGET_PHASE_F 0x14 184 #define H_INVALID_CCB_OP 0x16 185 #define H_LINK_CCB_BAD 0x17 186 #define H_BAD_TARGET_DIR 0x18 187 #define H_DUPLICATE_CCB 0x19 188 #define H_BAD_CCB_OR_SG 0x1A 189 #define H_ABORT 0xFF 190 int tastat; /* Target SCSI Status Byte */ 191 int flag; /* SRBFlag */ 192 #define AUTO_REQSENSE 0x0001 193 #define PARITY_ERROR 0x0002 194 #define SRB_TIMEOUT 0x0004 195 196 int cmdlen; /* SCSI command length */ 197 uint8_t cmd[12]; /* SCSI command */ 198 199 uint8_t tag[2]; 200 }; 201 202 /* 203 * some info about each target and lun on the SCSI bus 204 */ 205 struct trm_linfo { 206 int used; /* number of slots in use */ 207 int avail; /* where to start scanning */ 208 int busy; /* lun in use */ 209 struct trm_srb *untagged; 210 struct trm_srb *queued[TRM_MAX_TAG]; 211 }; 212 213 struct trm_tinfo { 214 u_int flag; /* Sync mode ? (1 sync):(0 async) */ 215 #define SYNC_NEGO_ENABLE 0x0001 216 #define SYNC_NEGO_DOING 0x0002 217 #define SYNC_NEGO_DONE 0x0004 218 #define WIDE_NEGO_ENABLE 0x0008 219 #define WIDE_NEGO_DOING 0x0010 220 #define WIDE_NEGO_DONE 0x0020 221 #define USE_TAG_QUEUING 0x0040 222 #define NO_RESELECT 0x0080 223 struct trm_linfo *linfo[TRM_MAX_LUNS]; 224 225 uint8_t config0; /* Target Config */ 226 uint8_t period; /* Max Period for nego. */ 227 uint8_t synctl; /* Sync control for reg. */ 228 uint8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 229 }; 230 231 /* 232 *----------------------------------------------------------------------- 233 * Adapter Control Block 234 *----------------------------------------------------------------------- 235 */ 236 struct trm_softc { 237 struct device sc_dev; 238 239 bus_space_tag_t sc_iot; 240 bus_space_handle_t sc_ioh; 241 bus_dma_tag_t sc_dmat; 242 bus_dmamap_t sc_dmamap; /* Map the control structures */ 243 244 struct trm_srb *sc_actsrb; 245 struct trm_tinfo sc_tinfo[TRM_MAX_TARGETS]; 246 247 TAILQ_HEAD(, trm_srb) sc_freesrb, 248 sc_readysrb; 249 struct trm_srb *sc_srb; /* SRB array */ 250 251 struct trm_sg_entry *sc_sglist; 252 253 int sc_maxid; 254 /* 255 * Link to the generic SCSI driver 256 */ 257 struct scsipi_channel sc_channel; 258 struct scsipi_adapter sc_adapter; 259 260 int sc_id; /* Adapter SCSI Target ID */ 261 262 int sc_state; /* SRB State */ 263 #define TRM_IDLE 0 264 #define TRM_WAIT 1 265 #define TRM_READY 2 266 #define TRM_MSGOUT 3 /* arbitration+msg_out 1st byte */ 267 #define TRM_MSGIN 4 268 #define TRM_EXTEND_MSGIN 5 269 #define TRM_COMMAND 6 270 #define TRM_START 7 /* arbitration+msg_out+command_out */ 271 #define TRM_DISCONNECTED 8 272 #define TRM_DATA_XFER 9 273 #define TRM_XFERPAD 10 274 #define TRM_STATUS 11 275 #define TRM_COMPLETED 12 276 #define TRM_ABORT_SENT 13 277 #define TRM_UNEXPECT_RESEL 14 278 279 int sc_phase; /* SCSI phase */ 280 int sc_config; 281 #define HCC_WIDE_CARD 0x01 282 #define HCC_SCSI_RESET 0x02 283 #define HCC_PARITY 0x04 284 #define HCC_AUTOTERM 0x08 285 #define HCC_LOW8TERM 0x10 286 #define HCC_UP8TERM 0x20 287 288 int sc_flag; 289 #define RESET_DEV 0x01 290 #define RESET_DETECT 0x02 291 #define RESET_DONE 0x04 292 #define WAIT_TAGMSG 0x08 /* XXX */ 293 294 int sc_msgcnt; 295 296 int resel_target; /* XXX */ 297 int resel_lun; /* XXX */ 298 299 uint8_t *sc_msg; 300 uint8_t sc_msgbuf[6]; 301 }; 302 303 /* 304 * SCSI Status codes not defined in scsi_all.h 305 */ 306 #define SCSI_COND_MET 0x04 /* Condition Met */ 307 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 308 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpected Bus Free */ 309 #define SCSI_BUS_RST_DETECT 0xFE /* SCSI Bus Reset detected */ 310 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Timeout */ 311 312 static int trm_probe(struct device *, struct cfdata *, void *); 313 static void trm_attach(struct device *, struct device *, void *); 314 315 static int trm_init(struct trm_softc *); 316 317 static void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, 318 void *); 319 static void trm_update_xfer_mode(struct trm_softc *, int); 320 static void trm_sched(struct trm_softc *); 321 static int trm_select(struct trm_softc *, struct trm_srb *); 322 static void trm_reset(struct trm_softc *); 323 static void trm_timeout(void *); 324 static int trm_intr(void *); 325 326 static void trm_dataout_phase0(struct trm_softc *, int); 327 static void trm_datain_phase0(struct trm_softc *, int); 328 static void trm_status_phase0(struct trm_softc *); 329 static void trm_msgin_phase0(struct trm_softc *); 330 static void trm_command_phase1(struct trm_softc *); 331 static void trm_status_phase1(struct trm_softc *); 332 static void trm_msgout_phase1(struct trm_softc *); 333 static void trm_msgin_phase1(struct trm_softc *); 334 335 static void trm_dataio_xfer(struct trm_softc *, int); 336 static void trm_disconnect(struct trm_softc *); 337 static void trm_reselect(struct trm_softc *); 338 static void trm_done(struct trm_softc *, struct trm_srb *); 339 static int trm_request_sense(struct trm_softc *, struct trm_srb *); 340 static void trm_dequeue(struct trm_softc *, struct trm_srb *); 341 342 static void trm_scsi_reset_detect(struct trm_softc *); 343 static void trm_reset_scsi_bus(struct trm_softc *); 344 345 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 346 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 347 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 348 static void trm_eeprom_set_data(struct trm_softc *, uint8_t, uint8_t); 349 static void trm_eeprom_write_cmd(struct trm_softc *, uint8_t, uint8_t); 350 static uint8_t trm_eeprom_get_data(struct trm_softc *, uint8_t); 351 352 CFATTACH_DECL(trm, sizeof(struct trm_softc), 353 trm_probe, trm_attach, NULL, NULL); 354 355 /* real period: */ 356 static const uint8_t trm_clock_period[] = { 357 12, /* 48 ns 20.0 MB/sec */ 358 18, /* 72 ns 13.3 MB/sec */ 359 25, /* 100 ns 10.0 MB/sec */ 360 31, /* 124 ns 8.0 MB/sec */ 361 37, /* 148 ns 6.6 MB/sec */ 362 43, /* 172 ns 5.7 MB/sec */ 363 50, /* 200 ns 5.0 MB/sec */ 364 62 /* 248 ns 4.0 MB/sec */ 365 }; 366 #define NPERIOD (sizeof(trm_clock_period)/sizeof(trm_clock_period[0])) 367 368 static int 369 trm_probe(struct device *parent, struct cfdata *match, 370 void *aux) 371 { 372 struct pci_attach_args *pa = aux; 373 374 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 375 switch (PCI_PRODUCT(pa->pa_id)) { 376 case PCI_PRODUCT_TEKRAM2_DC315: 377 return (1); 378 } 379 return (0); 380 } 381 382 /* 383 * attach and init a host adapter 384 */ 385 static void 386 trm_attach(struct device *parent, struct device *self, void *aux) 387 { 388 struct pci_attach_args *const pa = aux; 389 struct trm_softc *sc = (struct trm_softc *)self; 390 bus_space_tag_t iot; 391 bus_space_handle_t ioh; 392 pci_intr_handle_t ih; 393 pcireg_t command; 394 const char *intrstr; 395 396 /* 397 * These cards do not allow memory mapped accesses 398 * pa_pc: chipset tag 399 * pa_tag: pci tag 400 */ 401 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 402 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 403 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 404 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 405 pci_conf_write(pa->pa_pc, pa->pa_tag, 406 PCI_COMMAND_STATUS_REG, command); 407 } 408 /* 409 * mask for get correct base address of pci IO port 410 */ 411 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 412 &iot, &ioh, NULL, NULL)) { 413 aprint_error_dev(&sc->sc_dev, "unable to map registers\n"); 414 return; 415 } 416 /* 417 * test checksum of eeprom.. & initialize softc... 418 */ 419 sc->sc_iot = iot; 420 sc->sc_ioh = ioh; 421 sc->sc_dmat = pa->pa_dmat; 422 423 if (trm_init(sc) != 0) { 424 /* 425 * Error during initialization! 426 */ 427 printf(": Error during initialization\n"); 428 return; 429 } 430 /* 431 * Now try to attach all the sub-devices 432 */ 433 if ((sc->sc_config & HCC_WIDE_CARD) != 0) 434 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 435 "Ultra Wide SCSI Adapter\n"); 436 else 437 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 438 "Ultra SCSI Adapter\n"); 439 440 /* 441 * Now tell the generic SCSI layer about our bus. 442 * map and establish interrupt 443 */ 444 if (pci_intr_map(pa, &ih)) { 445 aprint_error_dev(&sc->sc_dev, "couldn't map interrupt\n"); 446 return; 447 } 448 intrstr = pci_intr_string(pa->pa_pc, ih); 449 450 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 451 aprint_error_dev(&sc->sc_dev, "couldn't establish interrupt"); 452 if (intrstr != NULL) 453 printf(" at %s", intrstr); 454 printf("\n"); 455 return; 456 } 457 if (intrstr != NULL) 458 printf("%s: interrupting at %s\n", 459 device_xname(&sc->sc_dev), intrstr); 460 461 sc->sc_adapter.adapt_dev = &sc->sc_dev; 462 sc->sc_adapter.adapt_nchannels = 1; 463 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 464 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 465 sc->sc_adapter.adapt_request = trm_scsipi_request; 466 sc->sc_adapter.adapt_minphys = minphys; 467 468 sc->sc_channel.chan_adapter = &sc->sc_adapter; 469 sc->sc_channel.chan_bustype = &scsi_bustype; 470 sc->sc_channel.chan_channel = 0; 471 sc->sc_channel.chan_ntargets = sc->sc_maxid + 1; 472 sc->sc_channel.chan_nluns = 8; 473 sc->sc_channel.chan_id = sc->sc_id; 474 475 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 476 } 477 478 /* 479 * initialize the internal structures for a given SCSI host 480 */ 481 static int 482 trm_init(struct trm_softc *sc) 483 { 484 bus_space_tag_t iot = sc->sc_iot; 485 bus_space_handle_t ioh = sc->sc_ioh; 486 bus_dma_segment_t seg; 487 struct trm_nvram eeprom; 488 struct trm_srb *srb; 489 struct trm_tinfo *ti; 490 struct nvram_target *tconf; 491 int error, rseg, all_sgsize; 492 int i, target; 493 uint8_t bval; 494 495 DPRINTF(("\n")); 496 497 /* 498 * allocate the space for all SCSI control blocks (SRB) for DMA memory 499 */ 500 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 501 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 502 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 503 printf(": unable to allocate SCSI REQUEST BLOCKS, " 504 "error = %d\n", error); 505 return (1); 506 } 507 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 508 all_sgsize, (void **) &sc->sc_sglist, 509 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 510 printf(": unable to map SCSI REQUEST BLOCKS, " 511 "error = %d\n", error); 512 return (1); 513 } 514 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 515 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 516 printf(": unable to create SRB DMA maps, " 517 "error = %d\n", error); 518 return (1); 519 } 520 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 521 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 522 printf(": unable to load SRB DMA maps, " 523 "error = %d\n", error); 524 return (1); 525 } 526 DPRINTF(("all_sgsize=%x\n", all_sgsize)); 527 memset(sc->sc_sglist, 0, all_sgsize); 528 529 /* 530 * EEPROM CHECKSUM 531 */ 532 trm_check_eeprom(sc, &eeprom); 533 534 sc->sc_maxid = 7; 535 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 536 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 537 sc->sc_config |= HCC_WIDE_CARD; 538 sc->sc_maxid = 15; 539 } 540 if (eeprom.channel_cfg & NAC_POWERON_SCSI_RESET) 541 sc->sc_config |= HCC_SCSI_RESET; 542 543 sc->sc_actsrb = NULL; 544 sc->sc_id = eeprom.scsi_id; 545 sc->sc_flag = 0; 546 547 /* 548 * initialize and link all device's SRB queues of this adapter 549 */ 550 TAILQ_INIT(&sc->sc_freesrb); 551 TAILQ_INIT(&sc->sc_readysrb); 552 553 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 554 M_DEVBUF, M_NOWAIT|M_ZERO); 555 DPRINTF(("all SRB size=%x\n", sizeof(struct trm_srb) * TRM_MAX_SRB)); 556 if (sc->sc_srb == NULL) { 557 printf(": can not allocate SRB\n"); 558 return (1); 559 } 560 561 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++) { 562 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 563 srb->sgoffset = TRM_SG_SIZE * i; 564 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 565 /* 566 * map all SRB space to SRB_array 567 */ 568 if (bus_dmamap_create(sc->sc_dmat, 569 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 570 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 571 printf(": unable to create DMA transfer map...\n"); 572 free(sc->sc_srb, M_DEVBUF); 573 return (1); 574 } 575 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 576 srb++; 577 } 578 579 /* 580 * initialize all target info structures 581 */ 582 for (target = 0; target < TRM_MAX_TARGETS; target++) { 583 ti = &sc->sc_tinfo[target]; 584 ti->synctl = 0; 585 ti->offset = 0; 586 tconf = &eeprom.target[target]; 587 ti->config0 = tconf->config0; 588 ti->period = trm_clock_period[tconf->period & 0x07]; 589 ti->flag = 0; 590 if ((ti->config0 & NTC_DO_DISCONNECT) != 0) { 591 #ifdef notyet 592 if ((ti->config0 & NTC_DO_TAG_QUEUING) != 0) 593 ti->flag |= USE_TAG_QUEUING; 594 #endif 595 } else 596 ti->flag |= NO_RESELECT; 597 598 DPRINTF(("target %d: config0 = 0x%02x, period = 0x%02x", 599 target, ti->config0, ti->period)); 600 DPRINTF((", flag = 0x%02x\n", ti->flag)); 601 } 602 603 /* program configuration 0 */ 604 bval = PHASELATCH | INITIATOR | BLOCKRST; 605 if ((sc->sc_config & HCC_PARITY) != 0) 606 bval |= PARITYCHECK; 607 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 608 609 /* program configuration 1 */ 610 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 611 ACTIVE_NEG | ACTIVE_NEGPLUS); 612 613 /* 250ms selection timeout */ 614 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 615 616 /* Mask all interrupts */ 617 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 618 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 619 620 /* Reset SCSI module */ 621 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 622 623 /* program Host ID */ 624 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 625 626 /* set asynchronous transfer */ 627 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 628 629 /* Turn LED control off */ 630 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 631 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 632 633 /* DMA config */ 634 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 635 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 636 637 /* Clear pending interrupt status */ 638 (void)bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 639 640 /* Enable SCSI interrupt */ 641 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 642 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 643 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 644 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 645 646 trm_reset(sc); 647 648 return (0); 649 } 650 651 /* 652 * enqueues a SCSI command 653 * called by the higher level SCSI driver 654 */ 655 static void 656 trm_scsipi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, 657 void *arg) 658 { 659 bus_space_tag_t iot; 660 bus_space_handle_t ioh; 661 struct trm_softc *sc; 662 struct trm_srb *srb; 663 struct scsipi_xfer *xs; 664 int error, i, target, lun, s; 665 666 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 667 iot = sc->sc_iot; 668 ioh = sc->sc_ioh; 669 670 switch (req) { 671 case ADAPTER_REQ_RUN_XFER: 672 xs = arg; 673 target = xs->xs_periph->periph_target; 674 lun = xs->xs_periph->periph_lun; 675 DPRINTF(("trm_scsipi_request.....\n")); 676 DPRINTF(("target= %d lun= %d\n", target, lun)); 677 if (xs->xs_control & XS_CTL_RESET) { 678 trm_reset(sc); 679 xs->error = XS_NOERROR | XS_RESET; 680 return; 681 } 682 if (xs->xs_status & XS_STS_DONE) { 683 printf("%s: Is it done?\n", device_xname(&sc->sc_dev)); 684 xs->xs_status &= ~XS_STS_DONE; 685 } 686 687 s = splbio(); 688 689 /* Get SRB */ 690 srb = TAILQ_FIRST(&sc->sc_freesrb); 691 if (srb != NULL) { 692 TAILQ_REMOVE(&sc->sc_freesrb, srb, next); 693 } else { 694 xs->error = XS_RESOURCE_SHORTAGE; 695 scsipi_done(xs); 696 splx(s); 697 return; 698 } 699 700 srb->xs = xs; 701 srb->cmdlen = xs->cmdlen; 702 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 703 704 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT)) { 705 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 706 xs->data, xs->datalen, NULL, 707 ((xs->xs_control & XS_CTL_NOSLEEP) ? 708 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | 709 BUS_DMA_STREAMING | 710 ((xs->xs_control & XS_CTL_DATA_IN) ? 711 BUS_DMA_READ : BUS_DMA_WRITE))) != 0) { 712 aprint_error_dev(&sc->sc_dev, "DMA transfer map unable to load, " 713 "error = %d\n", error); 714 xs->error = XS_DRIVER_STUFFUP; 715 /* 716 * free SRB 717 */ 718 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 719 splx(s); 720 return; 721 } 722 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 723 srb->dmap->dm_mapsize, 724 (xs->xs_control & XS_CTL_DATA_IN) ? 725 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 726 727 /* Set up the scatter gather list */ 728 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 729 srb->sgentry[i].address = 730 htole32(srb->dmap->dm_segs[i].ds_addr); 731 srb->sgentry[i].length = 732 htole32(srb->dmap->dm_segs[i].ds_len); 733 } 734 srb->buflen = xs->datalen; 735 srb->sgcnt = srb->dmap->dm_nsegs; 736 } else { 737 srb->sgentry[0].address = 0; 738 srb->sgentry[0].length = 0; 739 srb->buflen = 0; 740 srb->sgcnt = 0; 741 } 742 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 743 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 744 745 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 746 747 srb->sgindex = 0; 748 srb->hastat = 0; 749 srb->tastat = 0; 750 srb->flag = 0; 751 752 TAILQ_INSERT_TAIL(&sc->sc_readysrb, srb, next); 753 if (sc->sc_actsrb == NULL) 754 trm_sched(sc); 755 splx(s); 756 757 if ((xs->xs_control & XS_CTL_POLL) != 0) { 758 int timeout = xs->timeout; 759 760 s = splbio(); 761 do { 762 while (--timeout) { 763 DELAY(1000); 764 if (bus_space_read_2(iot, ioh, 765 TRM_SCSI_STATUS) & SCSIINTERRUPT) 766 break; 767 } 768 if (timeout == 0) { 769 trm_timeout(srb); 770 break; 771 } else 772 trm_intr(sc); 773 } while ((xs->xs_status & XS_STS_DONE) == 0); 774 splx(s); 775 } 776 return; 777 778 case ADAPTER_REQ_GROW_RESOURCES: 779 /* XXX Not supported. */ 780 return; 781 782 case ADAPTER_REQ_SET_XFER_MODE: 783 { 784 struct trm_tinfo *ti; 785 struct scsipi_xfer_mode *xm; 786 787 xm = arg; 788 ti = &sc->sc_tinfo[xm->xm_target]; 789 ti->flag &= ~(SYNC_NEGO_ENABLE|WIDE_NEGO_ENABLE); 790 791 #ifdef notyet 792 if ((xm->xm_mode & PERIPH_CAP_TQING) != 0) 793 ti->flag |= USE_TAG_QUEUING; 794 else 795 #endif 796 ti->flag &= ~USE_TAG_QUEUING; 797 798 if ((xm->xm_mode & PERIPH_CAP_WIDE16) != 0 && 799 (sc->sc_config & HCC_WIDE_CARD) != 0 && 800 (ti->config0 & NTC_DO_WIDE_NEGO) != 0) { 801 ti->flag |= WIDE_NEGO_ENABLE; 802 ti->flag &= ~WIDE_NEGO_DONE; 803 } 804 805 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 && 806 (ti->config0 & NTC_DO_SYNC_NEGO) != 0) { 807 ti->flag |= SYNC_NEGO_ENABLE; 808 ti->flag &= ~SYNC_NEGO_DONE; 809 ti->period = trm_clock_period[0]; 810 } 811 812 /* 813 * If we're not going to negotiate, send the 814 * notification now, since it won't happen later. 815 */ 816 if ((ti->flag & (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) == 817 (WIDE_NEGO_DONE|SYNC_NEGO_DONE)) 818 trm_update_xfer_mode(sc, xm->xm_target); 819 820 return; 821 } 822 } 823 } 824 825 static void 826 trm_update_xfer_mode(struct trm_softc *sc, int target) 827 { 828 struct scsipi_xfer_mode xm; 829 struct trm_tinfo *ti; 830 831 ti = &sc->sc_tinfo[target]; 832 xm.xm_target = target; 833 xm.xm_mode = 0; 834 xm.xm_period = 0; 835 xm.xm_offset = 0; 836 837 if ((ti->synctl & WIDE_SYNC) != 0) 838 xm.xm_mode |= PERIPH_CAP_WIDE16; 839 840 if (ti->period > 0) { 841 xm.xm_mode |= PERIPH_CAP_SYNC; 842 xm.xm_period = ti->period; 843 xm.xm_offset = ti->offset; 844 } 845 846 #ifdef notyet 847 if ((ti->flag & USE_TAG_QUEUING) != 0) 848 xm.xm_mode |= PERIPH_CAP_TQING; 849 #endif 850 851 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm); 852 } 853 854 static void 855 trm_sched(struct trm_softc *sc) 856 { 857 struct trm_srb *srb; 858 struct scsipi_periph *periph; 859 struct trm_tinfo *ti; 860 struct trm_linfo *li; 861 int s, lun, tag; 862 863 DPRINTF(("trm_sched...\n")); 864 865 TAILQ_FOREACH(srb, &sc->sc_readysrb, next) { 866 periph = srb->xs->xs_periph; 867 ti = &sc->sc_tinfo[periph->periph_target]; 868 lun = periph->periph_lun; 869 870 /* select type of tag for this command */ 871 if ((ti->flag & NO_RESELECT) != 0 || 872 (ti->flag & USE_TAG_QUEUING) == 0 || 873 (srb->flag & AUTO_REQSENSE) != 0 || 874 (srb->xs->xs_control & XS_CTL_REQSENSE) != 0) 875 tag = 0; 876 else 877 tag = srb->xs->xs_tag_type; 878 #if 0 879 /* XXX use tags for polled commands? */ 880 if (srb->xs->xs_control & XS_CTL_POLL) 881 tag = 0; 882 #endif 883 884 s = splbio(); 885 li = ti->linfo[lun]; 886 if (li == NULL) { 887 /* initialize lun info */ 888 if ((li = malloc(sizeof(*li), M_DEVBUF, 889 M_NOWAIT|M_ZERO)) == NULL) { 890 splx(s); 891 continue; 892 } 893 ti->linfo[lun] = li; 894 } 895 896 if (tag == 0) { 897 /* try to issue this srb as an un-tagged command */ 898 if (li->untagged == NULL) 899 li->untagged = srb; 900 } 901 if (li->untagged != NULL) { 902 tag = 0; 903 if (li->busy != 1 && li->used == 0) { 904 /* we need to issue the untagged command now */ 905 srb = li->untagged; 906 periph = srb->xs->xs_periph; 907 } else { 908 /* not ready yet */ 909 splx(s); 910 continue; 911 } 912 } 913 srb->tag[0] = tag; 914 if (tag != 0) { 915 li->queued[srb->xs->xs_tag_id] = srb; 916 srb->tag[1] = srb->xs->xs_tag_id; 917 li->used++; 918 } 919 920 if (li->untagged != NULL && li->busy != 1) { 921 li->busy = 1; 922 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 923 sc->sc_actsrb = srb; 924 trm_select(sc, srb); 925 splx(s); 926 break; 927 } 928 if (li->untagged == NULL && tag != 0) { 929 TAILQ_REMOVE(&sc->sc_readysrb, srb, next); 930 sc->sc_actsrb = srb; 931 trm_select(sc, srb); 932 splx(s); 933 break; 934 } else 935 splx(s); 936 } 937 } 938 939 static int 940 trm_select(struct trm_softc *sc, struct trm_srb *srb) 941 { 942 bus_space_tag_t iot = sc->sc_iot; 943 bus_space_handle_t ioh = sc->sc_ioh; 944 struct scsipi_periph *periph = srb->xs->xs_periph; 945 int target = periph->periph_target; 946 int lun = periph->periph_lun; 947 struct trm_tinfo *ti = &sc->sc_tinfo[target]; 948 uint8_t scsicmd; 949 950 DPRINTF(("trm_select.....\n")); 951 952 if ((srb->xs->xs_control & XS_CTL_POLL) == 0) { 953 callout_reset(&srb->xs->xs_callout, mstohz(srb->xs->timeout), 954 trm_timeout, srb); 955 } 956 957 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 958 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 959 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 960 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 961 /* Flush FIFO */ 962 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 963 DELAY(10); 964 965 sc->sc_phase = PH_BUS_FREE; /* initial phase */ 966 967 DPRINTF(("cmd = 0x%02x\n", srb->cmd[0])); 968 969 if (((ti->flag & WIDE_NEGO_ENABLE) && 970 (ti->flag & WIDE_NEGO_DONE) == 0) || 971 ((ti->flag & SYNC_NEGO_ENABLE) && 972 (ti->flag & SYNC_NEGO_DONE) == 0)) { 973 sc->sc_state = TRM_MSGOUT; 974 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 975 MSG_IDENTIFY(lun, 0)); 976 bus_space_write_multi_1(iot, ioh, 977 TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 978 /* it's important for atn stop */ 979 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 980 DO_DATALATCH | DO_HWRESELECT); 981 /* SCSI command */ 982 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_SEL_ATNSTOP); 983 DPRINTF(("select with SEL_ATNSTOP\n")); 984 return (0); 985 } 986 987 if (srb->tag[0] != 0) { 988 /* Send identify message */ 989 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 990 MSG_IDENTIFY(lun, 1)); 991 /* Send Tag id */ 992 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[0]); 993 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, srb->tag[1]); 994 scsicmd = SCMD_SEL_ATN3; 995 DPRINTF(("select with SEL_ATN3\n")); 996 } else { 997 /* Send identify message */ 998 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 999 MSG_IDENTIFY(lun, 1000 (ti->flag & NO_RESELECT) == 0 && 1001 (srb->flag & AUTO_REQSENSE) == 0 && 1002 (srb->xs->xs_control & XS_CTL_REQSENSE) == 0)); 1003 scsicmd = SCMD_SEL_ATN; 1004 DPRINTF(("select with SEL_ATN\n")); 1005 } 1006 sc->sc_state = TRM_START; 1007 1008 /* 1009 * Send CDB ..command block... 1010 */ 1011 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1012 1013 /* 1014 * If trm_select returns 0: current interrupt status 1015 * is interrupt enable. It's said that SCSI processor is 1016 * unoccupied. 1017 */ 1018 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1019 /* SCSI command */ 1020 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1021 return (0); 1022 } 1023 1024 /* 1025 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 1026 */ 1027 static void 1028 trm_reset(struct trm_softc *sc) 1029 { 1030 bus_space_tag_t iot = sc->sc_iot; 1031 bus_space_handle_t ioh = sc->sc_ioh; 1032 int s; 1033 1034 DPRINTF(("trm_reset.........\n")); 1035 1036 s = splbio(); 1037 1038 /* disable SCSI and DMA interrupt */ 1039 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 1040 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 1041 1042 trm_reset_scsi_bus(sc); 1043 DELAY(100000); 1044 1045 /* Enable SCSI interrupt */ 1046 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 1047 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 1048 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 1049 1050 /* Enable DMA interrupt */ 1051 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 1052 1053 /* Clear DMA FIFO */ 1054 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1055 1056 /* Clear SCSI FIFO */ 1057 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1058 1059 sc->sc_actsrb = NULL; 1060 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 1061 1062 splx(s); 1063 } 1064 1065 static void 1066 trm_timeout(void *arg) 1067 { 1068 struct trm_srb *srb = (struct trm_srb *)arg; 1069 struct scsipi_xfer *xs; 1070 struct scsipi_periph *periph; 1071 struct trm_softc *sc; 1072 int s; 1073 1074 if (srb == NULL) { 1075 printf("trm_timeout called with srb == NULL\n"); 1076 return; 1077 } 1078 1079 xs = srb->xs; 1080 if (xs == NULL) { 1081 printf("trm_timeout called with xs == NULL\n"); 1082 return; 1083 } 1084 1085 periph = xs->xs_periph; 1086 scsipi_printaddr(xs->xs_periph); 1087 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 1088 1089 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 1090 1091 trm_reset_scsi_bus(sc); 1092 s = splbio(); 1093 srb->flag |= SRB_TIMEOUT; 1094 trm_done(sc, srb); 1095 /* XXX needs more.. */ 1096 splx(s); 1097 } 1098 1099 /* 1100 * Catch an interrupt from the adapter 1101 * Process pending device interrupts. 1102 */ 1103 static int 1104 trm_intr(void *arg) 1105 { 1106 bus_space_tag_t iot; 1107 bus_space_handle_t ioh; 1108 struct trm_softc *sc; 1109 int intstat, stat; 1110 1111 DPRINTF(("trm_intr......\n")); 1112 sc = (struct trm_softc *)arg; 1113 if (sc == NULL) 1114 return (0); 1115 1116 iot = sc->sc_iot; 1117 ioh = sc->sc_ioh; 1118 1119 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1120 if ((stat & SCSIINTERRUPT) == 0) 1121 return (0); 1122 1123 DPRINTF(("stat = %04x, ", stat)); 1124 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1125 1126 DPRINTF(("intstat=%02x, ", intstat)); 1127 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1128 DPRINTF(("\n")); 1129 trm_disconnect(sc); 1130 return (1); 1131 } 1132 if (intstat & INT_RESELECTED) { 1133 DPRINTF(("\n")); 1134 trm_reselect(sc); 1135 return (1); 1136 } 1137 if (intstat & INT_SCSIRESET) { 1138 DPRINTF(("\n")); 1139 trm_scsi_reset_detect(sc); 1140 return (1); 1141 } 1142 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1143 DPRINTF(("sc->sc_phase = %2d, sc->sc_state = %2d\n", 1144 sc->sc_phase, sc->sc_state)); 1145 /* 1146 * software sequential machine 1147 */ 1148 1149 /* 1150 * call phase0 functions... "phase entry" handle 1151 * every phase before start transfer 1152 */ 1153 switch (sc->sc_phase) { 1154 case PH_DATA_OUT: 1155 trm_dataout_phase0(sc, stat); 1156 break; 1157 case PH_DATA_IN: 1158 trm_datain_phase0(sc, stat); 1159 break; 1160 case PH_COMMAND: 1161 break; 1162 case PH_STATUS: 1163 trm_status_phase0(sc); 1164 stat = PH_BUS_FREE; 1165 break; 1166 case PH_MSG_OUT: 1167 if (sc->sc_state == TRM_UNEXPECT_RESEL || 1168 sc->sc_state == TRM_ABORT_SENT) 1169 stat = PH_BUS_FREE; 1170 break; 1171 case PH_MSG_IN: 1172 trm_msgin_phase0(sc); 1173 stat = PH_BUS_FREE; 1174 break; 1175 case PH_BUS_FREE: 1176 break; 1177 default: 1178 aprint_error_dev(&sc->sc_dev, "unexpected phase in trm_intr() phase0\n"); 1179 break; 1180 } 1181 1182 sc->sc_phase = stat & PHASEMASK; 1183 1184 switch (sc->sc_phase) { 1185 case PH_DATA_OUT: 1186 trm_dataio_xfer(sc, XFERDATAOUT); 1187 break; 1188 case PH_DATA_IN: 1189 trm_dataio_xfer(sc, XFERDATAIN); 1190 break; 1191 case PH_COMMAND: 1192 trm_command_phase1(sc); 1193 break; 1194 case PH_STATUS: 1195 trm_status_phase1(sc); 1196 break; 1197 case PH_MSG_OUT: 1198 trm_msgout_phase1(sc); 1199 break; 1200 case PH_MSG_IN: 1201 trm_msgin_phase1(sc); 1202 break; 1203 case PH_BUS_FREE: 1204 break; 1205 default: 1206 aprint_error_dev(&sc->sc_dev, "unexpected phase in trm_intr() phase1\n"); 1207 break; 1208 } 1209 1210 return (1); 1211 } 1212 return (0); 1213 } 1214 1215 static void 1216 trm_msgout_phase1(struct trm_softc *sc) 1217 { 1218 bus_space_tag_t iot = sc->sc_iot; 1219 bus_space_handle_t ioh = sc->sc_ioh; 1220 struct trm_srb *srb; 1221 struct scsipi_periph *periph; 1222 struct trm_tinfo *ti; 1223 1224 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1225 1226 srb = sc->sc_actsrb; 1227 1228 /* message out phase */ 1229 if (srb != NULL) { 1230 periph = srb->xs->xs_periph; 1231 ti = &sc->sc_tinfo[periph->periph_target]; 1232 1233 if ((ti->flag & WIDE_NEGO_DOING) == 0 && 1234 (ti->flag & WIDE_NEGO_ENABLE)) { 1235 /* send WDTR */ 1236 ti->flag &= ~SYNC_NEGO_DONE; 1237 1238 sc->sc_msgbuf[0] = MSG_IDENTIFY(periph->periph_lun, 0); 1239 sc->sc_msgbuf[1] = MSG_EXTENDED; 1240 sc->sc_msgbuf[2] = MSG_EXT_WDTR_LEN; 1241 sc->sc_msgbuf[3] = MSG_EXT_WDTR; 1242 sc->sc_msgbuf[4] = MSG_EXT_WDTR_BUS_16_BIT; 1243 sc->sc_msgcnt = 5; 1244 1245 ti->flag |= WIDE_NEGO_DOING; 1246 } else if ((ti->flag & SYNC_NEGO_DOING) == 0 && 1247 (ti->flag & SYNC_NEGO_ENABLE)) { 1248 /* send SDTR */ 1249 int cnt = 0; 1250 1251 if ((ti->flag & WIDE_NEGO_DONE) == 0) 1252 sc->sc_msgbuf[cnt++] = 1253 MSG_IDENTIFY(periph->periph_lun, 0); 1254 1255 sc->sc_msgbuf[cnt++] = MSG_EXTENDED; 1256 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR_LEN; 1257 sc->sc_msgbuf[cnt++] = MSG_EXT_SDTR; 1258 sc->sc_msgbuf[cnt++] = ti->period; 1259 sc->sc_msgbuf[cnt++] = TRM_MAX_OFFSET; 1260 sc->sc_msgcnt = cnt; 1261 ti->flag |= SYNC_NEGO_DOING; 1262 } 1263 } 1264 if (sc->sc_msgcnt == 0) { 1265 sc->sc_msgbuf[0] = MSG_ABORT; 1266 sc->sc_msgcnt = 1; 1267 sc->sc_state = TRM_ABORT_SENT; 1268 } 1269 1270 DPRINTF(("msgout: cnt = %d, ", sc->sc_msgcnt)); 1271 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1272 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1273 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1274 1275 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1276 sc->sc_msgbuf, sc->sc_msgcnt); 1277 sc->sc_msgcnt = 0; 1278 memset(sc->sc_msgbuf, 0, sizeof(sc->sc_msgbuf)); 1279 1280 /* it's important for atn stop */ 1281 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1282 1283 /* 1284 * SCSI command 1285 */ 1286 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1287 } 1288 1289 static void 1290 trm_command_phase1(struct trm_softc *sc) 1291 { 1292 bus_space_tag_t iot = sc->sc_iot; 1293 bus_space_handle_t ioh = sc->sc_ioh; 1294 struct trm_srb *srb; 1295 1296 srb = sc->sc_actsrb; 1297 if (srb == NULL) { 1298 DPRINTF(("trm_command_phase1: no active srb\n")); 1299 return; 1300 } 1301 1302 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1303 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, srb->cmd, srb->cmdlen); 1304 1305 sc->sc_state = TRM_COMMAND; 1306 /* it's important for atn stop */ 1307 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1308 1309 /* 1310 * SCSI command 1311 */ 1312 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1313 } 1314 1315 static void 1316 trm_dataout_phase0(struct trm_softc *sc, int stat) 1317 { 1318 bus_space_tag_t iot = sc->sc_iot; 1319 bus_space_handle_t ioh = sc->sc_ioh; 1320 struct trm_srb *srb; 1321 struct scsipi_periph *periph; 1322 struct trm_tinfo *ti; 1323 struct trm_sg_entry *sg; 1324 int sgindex; 1325 uint32_t xferlen, leftcnt = 0; 1326 1327 if (sc->sc_state == TRM_XFERPAD) 1328 return; 1329 1330 srb = sc->sc_actsrb; 1331 if (srb == NULL) { 1332 DPRINTF(("trm_dataout_phase0: no active srb\n")); 1333 return; 1334 } 1335 periph = srb->xs->xs_periph; 1336 ti = &sc->sc_tinfo[periph->periph_target]; 1337 1338 if ((stat & PARITYERROR) != 0) 1339 srb->flag |= PARITY_ERROR; 1340 1341 if ((stat & SCSIXFERDONE) == 0) { 1342 /* 1343 * when data transfer from DMA FIFO to SCSI FIFO 1344 * if there was some data left in SCSI FIFO 1345 */ 1346 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1347 SCSI_FIFOCNT_MASK; 1348 if (ti->synctl & WIDE_SYNC) 1349 /* 1350 * if WIDE scsi SCSI FIFOCNT unit is word 1351 * so need to * 2 1352 */ 1353 leftcnt <<= 1; 1354 } 1355 /* 1356 * calculate all the residue data that was not yet transferred 1357 * SCSI transfer counter + left in SCSI FIFO data 1358 * 1359 * .....TRM_SCSI_XCNT (24bits) 1360 * The counter always decrements by one for every SCSI 1361 * byte transfer. 1362 * .....TRM_SCSI_FIFOCNT ( 5bits) 1363 * The counter is SCSI FIFO offset counter 1364 */ 1365 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1366 if (leftcnt == 1) { 1367 leftcnt = 0; 1368 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1369 } 1370 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1371 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1372 DMAXFERCOMP) == 0) 1373 ; /* XXX needs timeout */ 1374 1375 srb->buflen = 0; 1376 } else { 1377 /* Update SG list */ 1378 1379 /* 1380 * if transfer not yet complete 1381 * there were some data residue in SCSI FIFO or 1382 * SCSI transfer counter not empty 1383 */ 1384 if (srb->buflen != leftcnt) { 1385 /* data that had transferred length */ 1386 xferlen = srb->buflen - leftcnt; 1387 1388 /* next time to be transferred length */ 1389 srb->buflen = leftcnt; 1390 1391 /* 1392 * parsing from last time disconnect sgindex 1393 */ 1394 sg = srb->sgentry + srb->sgindex; 1395 for (sgindex = srb->sgindex; 1396 sgindex < srb->sgcnt; 1397 sgindex++, sg++) { 1398 /* 1399 * find last time which SG transfer 1400 * be disconnect 1401 */ 1402 if (xferlen >= le32toh(sg->length)) 1403 xferlen -= le32toh(sg->length); 1404 else { 1405 /* 1406 * update last time 1407 * disconnected SG list 1408 */ 1409 /* residue data length */ 1410 sg->length = 1411 htole32(le32toh(sg->length) 1412 - xferlen); 1413 /* residue data pointer */ 1414 sg->address = 1415 htole32(le32toh(sg->address) 1416 + xferlen); 1417 srb->sgindex = sgindex; 1418 break; 1419 } 1420 } 1421 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1422 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1423 } 1424 } 1425 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1426 } 1427 1428 static void 1429 trm_datain_phase0(struct trm_softc *sc, int stat) 1430 { 1431 bus_space_tag_t iot = sc->sc_iot; 1432 bus_space_handle_t ioh = sc->sc_ioh; 1433 struct trm_srb *srb; 1434 struct trm_sg_entry *sg; 1435 int sgindex; 1436 uint32_t xferlen, leftcnt = 0; 1437 1438 if (sc->sc_state == TRM_XFERPAD) 1439 return; 1440 1441 srb = sc->sc_actsrb; 1442 if (srb == NULL) { 1443 DPRINTF(("trm_datain_phase0: no active srb\n")); 1444 return; 1445 } 1446 1447 if (stat & PARITYERROR) 1448 srb->flag |= PARITY_ERROR; 1449 1450 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1451 if ((leftcnt == 0) || (stat & SCSIXFERCNT_2_ZERO)) { 1452 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1453 DMAXFERCOMP) == 0) 1454 ; /* XXX needs timeout */ 1455 1456 srb->buflen = 0; 1457 } else { /* phase changed */ 1458 /* 1459 * parsing the case: 1460 * when a transfer not yet complete 1461 * but be disconnected by upper layer 1462 * if transfer not yet complete 1463 * there were some data residue in SCSI FIFO or 1464 * SCSI transfer counter not empty 1465 */ 1466 if (srb->buflen != leftcnt) { 1467 /* 1468 * data that had transferred length 1469 */ 1470 xferlen = srb->buflen - leftcnt; 1471 1472 /* 1473 * next time to be transferred length 1474 */ 1475 srb->buflen = leftcnt; 1476 1477 /* 1478 * parsing from last time disconnect sgindex 1479 */ 1480 sg = srb->sgentry + srb->sgindex; 1481 for (sgindex = srb->sgindex; 1482 sgindex < srb->sgcnt; 1483 sgindex++, sg++) { 1484 /* 1485 * find last time which SG transfer 1486 * be disconnect 1487 */ 1488 if (xferlen >= le32toh(sg->length)) 1489 xferlen -= le32toh(sg->length); 1490 else { 1491 /* 1492 * update last time 1493 * disconnected SG list 1494 */ 1495 /* residue data length */ 1496 sg->length = 1497 htole32(le32toh(sg->length) 1498 - xferlen); 1499 /* residue data pointer */ 1500 sg->address = 1501 htole32(le32toh(sg->address) 1502 + xferlen); 1503 srb->sgindex = sgindex; 1504 break; 1505 } 1506 } 1507 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1508 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 1509 } 1510 } 1511 } 1512 1513 static void 1514 trm_dataio_xfer(struct trm_softc *sc, int iodir) 1515 { 1516 bus_space_tag_t iot = sc->sc_iot; 1517 bus_space_handle_t ioh = sc->sc_ioh; 1518 struct trm_srb *srb; 1519 struct scsipi_periph *periph; 1520 struct trm_tinfo *ti; 1521 1522 srb = sc->sc_actsrb; 1523 if (srb == NULL) { 1524 DPRINTF(("trm_dataio_xfer: no active srb\n")); 1525 return; 1526 } 1527 periph = srb->xs->xs_periph; 1528 ti = &sc->sc_tinfo[periph->periph_target]; 1529 1530 if (srb->sgindex < srb->sgcnt) { 1531 if (srb->buflen > 0) { 1532 /* 1533 * load what physical address of Scatter/Gather 1534 * list table want to be transfer 1535 */ 1536 sc->sc_state = TRM_DATA_XFER; 1537 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1538 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1539 srb->sgaddr + 1540 srb->sgindex * sizeof(struct trm_sg_entry)); 1541 /* 1542 * load how many bytes in the Scatter/Gather list table 1543 */ 1544 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1545 (srb->sgcnt - srb->sgindex) 1546 * sizeof(struct trm_sg_entry)); 1547 /* 1548 * load total xfer length (24bits) max value 16Mbyte 1549 */ 1550 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1551 /* Start DMA transfer */ 1552 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1553 iodir | SGXFER); 1554 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1555 STARTDMAXFER); 1556 1557 /* Start SCSI transfer */ 1558 /* it's important for atn stop */ 1559 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1560 DO_DATALATCH); 1561 1562 /* 1563 * SCSI command 1564 */ 1565 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1566 (iodir == XFERDATAOUT) ? 1567 SCMD_DMA_OUT : SCMD_DMA_IN); 1568 } else { /* xfer pad */ 1569 if (srb->sgcnt) { 1570 srb->hastat = H_OVER_UNDER_RUN; 1571 } 1572 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1573 (ti->synctl & WIDE_SYNC) ? 2 : 1); 1574 1575 if (iodir == XFERDATAOUT) 1576 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1577 else 1578 (void)bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1579 1580 sc->sc_state = TRM_XFERPAD; 1581 /* it's important for atn stop */ 1582 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1583 DO_DATALATCH); 1584 1585 /* 1586 * SCSI command 1587 */ 1588 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1589 (iodir == XFERDATAOUT) ? 1590 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1591 } 1592 } 1593 } 1594 1595 static void 1596 trm_status_phase0(struct trm_softc *sc) 1597 { 1598 bus_space_tag_t iot = sc->sc_iot; 1599 bus_space_handle_t ioh = sc->sc_ioh; 1600 struct trm_srb *srb; 1601 1602 srb = sc->sc_actsrb; 1603 if (srb == NULL) { 1604 DPRINTF(("trm_status_phase0: no active srb\n")); 1605 return; 1606 } 1607 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1608 sc->sc_state = TRM_COMPLETED; 1609 /* it's important for atn stop */ 1610 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1611 1612 /* 1613 * SCSI command 1614 */ 1615 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1616 } 1617 1618 static void 1619 trm_status_phase1(struct trm_softc *sc) 1620 { 1621 bus_space_tag_t iot = sc->sc_iot; 1622 bus_space_handle_t ioh = sc->sc_ioh; 1623 1624 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1625 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1626 & SCSI_FIFO_EMPTY) == 0) 1627 bus_space_write_2(iot, ioh, 1628 TRM_SCSI_CONTROL, DO_CLRFIFO); 1629 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1630 & DMA_FIFO_EMPTY) == 0) 1631 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1632 } else { 1633 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1634 & DMA_FIFO_EMPTY) == 0) 1635 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1636 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1637 & SCSI_FIFO_EMPTY) == 0) 1638 bus_space_write_2(iot, ioh, 1639 TRM_SCSI_CONTROL, DO_CLRFIFO); 1640 } 1641 sc->sc_state = TRM_STATUS; 1642 /* it's important for atn stop */ 1643 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1644 1645 /* 1646 * SCSI command 1647 */ 1648 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1649 } 1650 1651 static void 1652 trm_msgin_phase0(struct trm_softc *sc) 1653 { 1654 bus_space_tag_t iot = sc->sc_iot; 1655 bus_space_handle_t ioh = sc->sc_ioh; 1656 struct trm_srb *srb; 1657 struct scsipi_periph *periph; 1658 struct trm_tinfo *ti; 1659 int index; 1660 uint8_t msgin_code; 1661 1662 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1663 if (sc->sc_state != TRM_EXTEND_MSGIN) { 1664 DPRINTF(("msgin: code = %02x\n", msgin_code)); 1665 switch (msgin_code) { 1666 case MSG_DISCONNECT: 1667 sc->sc_state = TRM_DISCONNECTED; 1668 break; 1669 1670 case MSG_SAVEDATAPOINTER: 1671 break; 1672 1673 case MSG_EXTENDED: 1674 case MSG_SIMPLE_Q_TAG: 1675 case MSG_HEAD_OF_Q_TAG: 1676 case MSG_ORDERED_Q_TAG: 1677 sc->sc_state = TRM_EXTEND_MSGIN; 1678 /* extended message (01h) */ 1679 sc->sc_msgbuf[0] = msgin_code; 1680 1681 sc->sc_msgcnt = 1; 1682 /* extended message length (n) */ 1683 sc->sc_msg = &sc->sc_msgbuf[1]; 1684 1685 break; 1686 case MSG_MESSAGE_REJECT: 1687 /* Reject message */ 1688 srb = sc->sc_actsrb; 1689 if (srb == NULL) { 1690 DPRINTF(("trm_msgin_phase0: " 1691 " message reject without actsrb\n")); 1692 break; 1693 } 1694 periph = srb->xs->xs_periph; 1695 ti = &sc->sc_tinfo[periph->periph_target]; 1696 1697 if (ti->flag & WIDE_NEGO_ENABLE) { 1698 /* do wide nego reject */ 1699 ti->flag |= WIDE_NEGO_DONE; 1700 ti->flag &= 1701 ~(SYNC_NEGO_DONE | WIDE_NEGO_ENABLE); 1702 if ((ti->flag & SYNC_NEGO_ENABLE) && 1703 (ti->flag & SYNC_NEGO_DONE) == 0) { 1704 /* Set ATN, in case ATN was clear */ 1705 sc->sc_state = TRM_MSGOUT; 1706 bus_space_write_2(iot, ioh, 1707 TRM_SCSI_CONTROL, DO_SETATN); 1708 } else 1709 /* Clear ATN */ 1710 bus_space_write_2(iot, ioh, 1711 TRM_SCSI_CONTROL, DO_CLRATN); 1712 } else if (ti->flag & SYNC_NEGO_ENABLE) { 1713 /* do sync nego reject */ 1714 bus_space_write_2(iot, ioh, 1715 TRM_SCSI_CONTROL, DO_CLRATN); 1716 if (ti->flag & SYNC_NEGO_DOING) { 1717 ti->flag &=~(SYNC_NEGO_ENABLE | 1718 SYNC_NEGO_DONE); 1719 ti->synctl = 0; 1720 ti->offset = 0; 1721 bus_space_write_1(iot, ioh, 1722 TRM_SCSI_SYNC, ti->synctl); 1723 bus_space_write_1(iot, ioh, 1724 TRM_SCSI_OFFSET, ti->offset); 1725 } 1726 } 1727 break; 1728 1729 case MSG_IGN_WIDE_RESIDUE: 1730 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1731 (void)bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1732 break; 1733 1734 default: 1735 /* 1736 * Restore data pointer message 1737 * Save data pointer message 1738 * Completion message 1739 * NOP message 1740 */ 1741 break; 1742 } 1743 } else { 1744 /* 1745 * when extend message in: sc->sc_state = TRM_EXTEND_MSGIN 1746 * Parsing incoming extented messages 1747 */ 1748 *sc->sc_msg++ = msgin_code; 1749 sc->sc_msgcnt++; 1750 1751 DPRINTF(("extended_msgin: cnt = %d, ", sc->sc_msgcnt)); 1752 DPRINTF(("msgbuf = %02x %02x %02x %02x %02x %02x\n", 1753 sc->sc_msgbuf[0], sc->sc_msgbuf[1], sc->sc_msgbuf[2], 1754 sc->sc_msgbuf[3], sc->sc_msgbuf[4], sc->sc_msgbuf[5])); 1755 1756 switch (sc->sc_msgbuf[0]) { 1757 case MSG_SIMPLE_Q_TAG: 1758 case MSG_HEAD_OF_Q_TAG: 1759 case MSG_ORDERED_Q_TAG: 1760 /* 1761 * is QUEUE tag message : 1762 * 1763 * byte 0: 1764 * HEAD QUEUE TAG (20h) 1765 * ORDERED QUEUE TAG (21h) 1766 * SIMPLE QUEUE TAG (22h) 1767 * byte 1: 1768 * Queue tag (00h - FFh) 1769 */ 1770 if (sc->sc_msgcnt == 2 && sc->sc_actsrb == NULL) { 1771 /* XXX XXX XXX */ 1772 struct trm_linfo *li; 1773 int tagid; 1774 1775 sc->sc_flag &= ~WAIT_TAGMSG; 1776 tagid = sc->sc_msgbuf[1]; 1777 ti = &sc->sc_tinfo[sc->resel_target]; 1778 li = ti->linfo[sc->resel_lun]; 1779 srb = li->queued[tagid]; 1780 if (srb != NULL) { 1781 sc->sc_actsrb = srb; 1782 sc->sc_state = TRM_DATA_XFER; 1783 break; 1784 } else { 1785 aprint_error_dev(&sc->sc_dev, "invalid tag id\n"); 1786 } 1787 1788 sc->sc_state = TRM_UNEXPECT_RESEL; 1789 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 1790 sc->sc_msgcnt = 1; 1791 bus_space_write_2(iot, ioh, 1792 TRM_SCSI_CONTROL, DO_SETATN); 1793 } else 1794 sc->sc_state = TRM_IDLE; 1795 break; 1796 1797 case MSG_EXTENDED: 1798 srb = sc->sc_actsrb; 1799 if (srb == NULL) { 1800 DPRINTF(("trm_msgin_phase0: " 1801 "extended message without actsrb\n")); 1802 break; 1803 } 1804 periph = srb->xs->xs_periph; 1805 ti = &sc->sc_tinfo[periph->periph_target]; 1806 1807 if (sc->sc_msgbuf[2] == MSG_EXT_WDTR && 1808 sc->sc_msgcnt == 4) { 1809 /* 1810 * is Wide data xfer Extended message : 1811 * ====================================== 1812 * WIDE DATA TRANSFER REQUEST 1813 * ====================================== 1814 * byte 0 : Extended message (01h) 1815 * byte 1 : Extended message length (02h) 1816 * byte 2 : WIDE DATA TRANSFER code (03h) 1817 * byte 3 : Transfer width exponent 1818 */ 1819 if (sc->sc_msgbuf[1] != MSG_EXT_WDTR_LEN) { 1820 /* Length is wrong, reject it */ 1821 ti->flag &= ~(WIDE_NEGO_ENABLE | 1822 WIDE_NEGO_DONE); 1823 sc->sc_state = TRM_MSGOUT; 1824 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1825 sc->sc_msgcnt = 1; 1826 bus_space_write_2(iot, ioh, 1827 TRM_SCSI_CONTROL, DO_SETATN); 1828 break; 1829 } 1830 1831 if ((ti->flag & WIDE_NEGO_ENABLE) == 0) 1832 sc->sc_msgbuf[3] = 1833 MSG_EXT_WDTR_BUS_8_BIT; 1834 1835 if (sc->sc_msgbuf[3] > 1836 MSG_EXT_WDTR_BUS_32_BIT) { 1837 /* reject_msg: */ 1838 ti->flag &= ~(WIDE_NEGO_ENABLE | 1839 WIDE_NEGO_DONE); 1840 sc->sc_state = TRM_MSGOUT; 1841 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1842 sc->sc_msgcnt = 1; 1843 bus_space_write_2(iot, ioh, 1844 TRM_SCSI_CONTROL, DO_SETATN); 1845 break; 1846 } 1847 if (sc->sc_msgbuf[3] == MSG_EXT_WDTR_BUS_32_BIT) 1848 /* do 16 bits */ 1849 sc->sc_msgbuf[3] = 1850 MSG_EXT_WDTR_BUS_16_BIT; 1851 if ((ti->flag & WIDE_NEGO_DONE) == 0) { 1852 ti->flag |= WIDE_NEGO_DONE; 1853 ti->flag &= ~(SYNC_NEGO_DONE | 1854 WIDE_NEGO_ENABLE); 1855 if (sc->sc_msgbuf[3] != 1856 MSG_EXT_WDTR_BUS_8_BIT) 1857 /* is Wide data xfer */ 1858 ti->synctl |= WIDE_SYNC; 1859 trm_update_xfer_mode(sc, 1860 periph->periph_target); 1861 } 1862 1863 sc->sc_state = TRM_MSGOUT; 1864 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1865 DO_SETATN); 1866 break; 1867 1868 } else if (sc->sc_msgbuf[2] == MSG_EXT_SDTR && 1869 sc->sc_msgcnt == 5) { 1870 /* 1871 * is 8bit transfer Extended message : 1872 * ================================= 1873 * SYNCHRONOUS DATA TRANSFER REQUEST 1874 * ================================= 1875 * byte 0 : Extended message (01h) 1876 * byte 1 : Extended message length (03) 1877 * byte 2 : SYNC DATA TRANSFER code (01h) 1878 * byte 3 : Transfer period factor 1879 * byte 4 : REQ/ACK offset 1880 */ 1881 if (sc->sc_msgbuf[1] != MSG_EXT_SDTR_LEN) { 1882 /* reject_msg */ 1883 sc->sc_state = TRM_MSGOUT; 1884 sc->sc_msgbuf[0] = MSG_MESSAGE_REJECT; 1885 sc->sc_msgcnt = 1; 1886 bus_space_write_2(iot, ioh, 1887 TRM_SCSI_CONTROL, DO_SETATN); 1888 break; 1889 } 1890 1891 if ((ti->flag & SYNC_NEGO_DONE) == 0) { 1892 ti->flag &= 1893 ~(SYNC_NEGO_ENABLE|SYNC_NEGO_DOING); 1894 ti->flag |= SYNC_NEGO_DONE; 1895 if (sc->sc_msgbuf[3] >= TRM_MAX_PERIOD) 1896 sc->sc_msgbuf[3] = 0; 1897 if (sc->sc_msgbuf[4] > TRM_MAX_OFFSET) 1898 sc->sc_msgbuf[4] = 1899 TRM_MAX_OFFSET; 1900 1901 if (sc->sc_msgbuf[3] == 0 || 1902 sc->sc_msgbuf[4] == 0) { 1903 /* set async */ 1904 ti->synctl = 0; 1905 ti->offset = 0; 1906 } else { 1907 /* set sync */ 1908 /* Transfer period factor */ 1909 ti->period = sc->sc_msgbuf[3]; 1910 /* REQ/ACK offset */ 1911 ti->offset = sc->sc_msgbuf[4]; 1912 for (index = 0; 1913 index < NPERIOD; 1914 index++) 1915 if (ti->period <= 1916 trm_clock_period[ 1917 index]) 1918 break; 1919 1920 ti->synctl |= ALT_SYNC | index; 1921 } 1922 /* 1923 * program SCSI control register 1924 */ 1925 bus_space_write_1(iot, ioh, 1926 TRM_SCSI_SYNC, ti->synctl); 1927 bus_space_write_1(iot, ioh, 1928 TRM_SCSI_OFFSET, ti->offset); 1929 trm_update_xfer_mode(sc, 1930 periph->periph_target); 1931 } 1932 sc->sc_state = TRM_IDLE; 1933 } 1934 break; 1935 default: 1936 break; 1937 } 1938 } 1939 1940 /* it's important for atn stop */ 1941 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1942 1943 /* 1944 * SCSI command 1945 */ 1946 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1947 } 1948 1949 static void 1950 trm_msgin_phase1(struct trm_softc *sc) 1951 { 1952 bus_space_tag_t iot = sc->sc_iot; 1953 bus_space_handle_t ioh = sc->sc_ioh; 1954 1955 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1956 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1957 if (sc->sc_state != TRM_MSGIN && sc->sc_state != TRM_EXTEND_MSGIN) { 1958 sc->sc_state = TRM_MSGIN; 1959 } 1960 1961 /* it's important for atn stop */ 1962 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1963 1964 /* 1965 * SCSI command 1966 */ 1967 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1968 } 1969 1970 static void 1971 trm_disconnect(struct trm_softc *sc) 1972 { 1973 bus_space_tag_t iot = sc->sc_iot; 1974 bus_space_handle_t ioh = sc->sc_ioh; 1975 struct trm_srb *srb; 1976 int s; 1977 1978 s = splbio(); 1979 1980 srb = sc->sc_actsrb; 1981 DPRINTF(("trm_disconnect...............\n")); 1982 1983 if (srb == NULL) { 1984 DPRINTF(("trm_disconnect: no active srb\n")); 1985 DELAY(1000); /* 1 msec */ 1986 1987 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1988 DO_CLRFIFO | DO_HWRESELECT); 1989 return; 1990 } 1991 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1992 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1993 DO_CLRFIFO | DO_HWRESELECT); 1994 DELAY(100); 1995 1996 switch (sc->sc_state) { 1997 case TRM_UNEXPECT_RESEL: 1998 sc->sc_state = TRM_IDLE; 1999 break; 2000 2001 case TRM_ABORT_SENT: 2002 goto finish; 2003 2004 case TRM_START: 2005 case TRM_MSGOUT: 2006 { 2007 /* Selection time out - discard all LUNs if empty */ 2008 struct scsipi_periph *periph; 2009 struct trm_tinfo *ti; 2010 struct trm_linfo *li; 2011 int lun; 2012 2013 DPRINTF(("selection timeout\n")); 2014 2015 srb->tastat = SCSI_SEL_TIMEOUT; /* XXX Ok? */ 2016 2017 periph = srb->xs->xs_periph; 2018 ti = &sc->sc_tinfo[periph->periph_target]; 2019 for (lun = 0; lun < TRM_MAX_LUNS; lun++) { 2020 li = ti->linfo[lun]; 2021 if (li != NULL && 2022 li->untagged == NULL && li->used == 0) { 2023 ti->linfo[lun] = NULL; 2024 free(li, M_DEVBUF); 2025 } 2026 } 2027 } 2028 goto finish; 2029 2030 case TRM_DISCONNECTED: 2031 sc->sc_actsrb = NULL; 2032 sc->sc_state = TRM_IDLE; 2033 goto sched; 2034 2035 case TRM_COMPLETED: 2036 goto finish; 2037 } 2038 2039 out: 2040 splx(s); 2041 return; 2042 2043 finish: 2044 sc->sc_state = TRM_IDLE; 2045 trm_done(sc, srb); 2046 goto out; 2047 2048 sched: 2049 trm_sched(sc); 2050 goto out; 2051 } 2052 2053 static void 2054 trm_reselect(struct trm_softc *sc) 2055 { 2056 bus_space_tag_t iot = sc->sc_iot; 2057 bus_space_handle_t ioh = sc->sc_ioh; 2058 struct trm_tinfo *ti; 2059 struct trm_linfo *li; 2060 int target, lun; 2061 2062 DPRINTF(("trm_reselect.................\n")); 2063 2064 if (sc->sc_actsrb != NULL) { 2065 /* arbitration lost but reselection win */ 2066 sc->sc_state = TRM_READY; 2067 target = sc->sc_actsrb->xs->xs_periph->periph_target; 2068 ti = &sc->sc_tinfo[target]; 2069 } else { 2070 /* Read Reselected Target Id and LUN */ 2071 target = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2072 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2073 ti = &sc->sc_tinfo[target]; 2074 li = ti->linfo[lun]; 2075 DPRINTF(("target = %d, lun = %d\n", target, lun)); 2076 2077 /* 2078 * Check to see if we are running an un-tagged command. 2079 * Otherwise ack the IDENTIFY and wait for a tag message. 2080 */ 2081 if (li != NULL) { 2082 if (li->untagged != NULL && li->busy) { 2083 sc->sc_actsrb = li->untagged; 2084 sc->sc_state = TRM_DATA_XFER; 2085 } else { 2086 sc->resel_target = target; 2087 sc->resel_lun = lun; 2088 /* XXX XXX XXX */ 2089 sc->sc_flag |= WAIT_TAGMSG; 2090 } 2091 } 2092 2093 if ((ti->flag & USE_TAG_QUEUING) == 0 && 2094 sc->sc_actsrb == NULL) { 2095 printf("%s: reselect from target %d lun %d " 2096 "without nexus; sending abort\n", 2097 device_xname(&sc->sc_dev), target, lun); 2098 sc->sc_state = TRM_UNEXPECT_RESEL; 2099 sc->sc_msgbuf[0] = MSG_ABORT_TAG; 2100 sc->sc_msgcnt = 1; 2101 bus_space_write_2(iot, ioh, 2102 TRM_SCSI_CONTROL, DO_SETATN); 2103 } 2104 } 2105 sc->sc_phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2106 /* 2107 * Program HA ID, target ID, period and offset 2108 */ 2109 /* target ID */ 2110 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, target); 2111 2112 /* host ID */ 2113 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2114 2115 /* period */ 2116 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, ti->synctl); 2117 2118 /* offset */ 2119 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, ti->offset); 2120 2121 /* it's important for atn stop */ 2122 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2123 /* 2124 * SCSI command 2125 */ 2126 /* to rls the /ACK signal */ 2127 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2128 } 2129 2130 /* 2131 * Complete execution of a SCSI command 2132 * Signal completion to the generic SCSI driver 2133 */ 2134 static void 2135 trm_done(struct trm_softc *sc, struct trm_srb *srb) 2136 { 2137 struct scsipi_xfer *xs = srb->xs; 2138 2139 DPRINTF(("trm_done..................\n")); 2140 2141 if (xs == NULL) 2142 return; 2143 2144 if ((xs->xs_control & XS_CTL_POLL) == 0) 2145 callout_stop(&xs->xs_callout); 2146 2147 if (xs->xs_control & (XS_CTL_DATA_IN | XS_CTL_DATA_OUT) || 2148 srb->flag & AUTO_REQSENSE) { 2149 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2150 srb->dmap->dm_mapsize, 2151 ((xs->xs_control & XS_CTL_DATA_IN) || 2152 (srb->flag & AUTO_REQSENSE)) ? 2153 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2154 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2155 } 2156 2157 /* 2158 * target status 2159 */ 2160 xs->status = srb->tastat; 2161 2162 DPRINTF(("xs->status = 0x%02x\n", xs->status)); 2163 2164 switch (xs->status) { 2165 case SCSI_OK: 2166 /* 2167 * process initiator status...... 2168 * Adapter (initiator) status 2169 */ 2170 if ((srb->hastat & H_OVER_UNDER_RUN) != 0) { 2171 printf("%s: over/under run error\n", 2172 device_xname(&sc->sc_dev)); 2173 srb->tastat = 0; 2174 /* Illegal length (over/under run) */ 2175 xs->error = XS_DRIVER_STUFFUP; 2176 } else if ((srb->flag & PARITY_ERROR) != 0) { 2177 aprint_error_dev(&sc->sc_dev, "parity error\n"); 2178 /* Driver failed to perform operation */ 2179 xs->error = XS_DRIVER_STUFFUP; /* XXX */ 2180 } else if ((srb->flag & SRB_TIMEOUT) != 0) { 2181 xs->resid = srb->buflen; 2182 xs->error = XS_TIMEOUT; 2183 } else { 2184 /* No error */ 2185 xs->resid = srb->buflen; 2186 srb->hastat = 0; 2187 if (srb->flag & AUTO_REQSENSE) { 2188 /* there is no error, (sense is invalid) */ 2189 xs->error = XS_SENSE; 2190 } else { 2191 srb->tastat = 0; 2192 xs->error = XS_NOERROR; 2193 } 2194 } 2195 break; 2196 2197 case SCSI_CHECK: 2198 if ((srb->flag & AUTO_REQSENSE) != 0 || 2199 trm_request_sense(sc, srb) != 0) { 2200 aprint_error_dev(&sc->sc_dev, "request sense failed\n"); 2201 xs->error = XS_DRIVER_STUFFUP; 2202 break; 2203 } 2204 xs->error = XS_SENSE; 2205 return; 2206 2207 case SCSI_SEL_TIMEOUT: 2208 srb->hastat = H_SEL_TIMEOUT; 2209 srb->tastat = 0; 2210 xs->error = XS_SELTIMEOUT; 2211 break; 2212 2213 case SCSI_QUEUE_FULL: 2214 case SCSI_BUSY: 2215 xs->error = XS_BUSY; 2216 break; 2217 2218 case SCSI_RESV_CONFLICT: 2219 DPRINTF(("%s: target reserved at ", device_xname(&sc->sc_dev))); 2220 DPRINTF(("%s %d\n", __FILE__, __LINE__)); 2221 xs->error = XS_BUSY; 2222 break; 2223 2224 default: 2225 srb->hastat = 0; 2226 printf("%s: trm_done(): unknown status = %02x\n", 2227 device_xname(&sc->sc_dev), xs->status); 2228 xs->error = XS_DRIVER_STUFFUP; 2229 break; 2230 } 2231 2232 trm_dequeue(sc, srb); 2233 if (srb == sc->sc_actsrb) { 2234 sc->sc_actsrb = NULL; 2235 trm_sched(sc); 2236 } 2237 2238 TAILQ_INSERT_TAIL(&sc->sc_freesrb, srb, next); 2239 2240 /* Notify cmd done */ 2241 scsipi_done(xs); 2242 } 2243 2244 static int 2245 trm_request_sense(struct trm_softc *sc, struct trm_srb *srb) 2246 { 2247 struct scsipi_xfer *xs; 2248 struct scsipi_periph *periph; 2249 struct trm_tinfo *ti; 2250 struct trm_linfo *li; 2251 struct scsi_request_sense *ss = (struct scsi_request_sense *)srb->cmd; 2252 int error; 2253 2254 DPRINTF(("trm_request_sense...\n")); 2255 2256 xs = srb->xs; 2257 periph = xs->xs_periph; 2258 2259 srb->flag |= AUTO_REQSENSE; 2260 2261 /* Status of initiator/target */ 2262 srb->hastat = 0; 2263 srb->tastat = 0; 2264 2265 memset(ss, 0, sizeof(*ss)); 2266 ss->opcode = SCSI_REQUEST_SENSE; 2267 ss->byte2 = periph->periph_lun << SCSI_CMD_LUN_SHIFT; 2268 ss->length = sizeof(struct scsi_sense_data); 2269 2270 srb->buflen = sizeof(struct scsi_sense_data); 2271 srb->sgcnt = 1; 2272 srb->sgindex = 0; 2273 srb->cmdlen = sizeof(struct scsi_request_sense); 2274 2275 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2276 &xs->sense.scsi_sense, srb->buflen, NULL, 2277 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2278 return error; 2279 } 2280 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2281 srb->buflen, BUS_DMASYNC_PREREAD); 2282 2283 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2284 srb->sgentry[0].length = htole32(sizeof(struct scsi_sense_data)); 2285 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2286 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2287 2288 ti = &sc->sc_tinfo[periph->periph_target]; 2289 li = ti->linfo[periph->periph_lun]; 2290 if (li->busy > 0) 2291 li->busy = 0; 2292 trm_dequeue(sc, srb); 2293 li->untagged = srb; /* must be executed first to fix C/A */ 2294 li->busy = 2; 2295 2296 if (srb == sc->sc_actsrb) 2297 trm_select(sc, srb); 2298 else { 2299 TAILQ_INSERT_HEAD(&sc->sc_readysrb, srb, next); 2300 if (sc->sc_actsrb == NULL) 2301 trm_sched(sc); 2302 } 2303 return 0; 2304 } 2305 2306 static void 2307 trm_dequeue(struct trm_softc *sc, struct trm_srb *srb) 2308 { 2309 struct scsipi_periph *periph; 2310 struct trm_tinfo *ti; 2311 struct trm_linfo *li; 2312 2313 periph = srb->xs->xs_periph; 2314 ti = &sc->sc_tinfo[periph->periph_target]; 2315 li = ti->linfo[periph->periph_lun]; 2316 2317 if (li->untagged == srb) { 2318 li->busy = 0; 2319 li->untagged = NULL; 2320 } 2321 if (srb->tag[0] != 0 && li->queued[srb->tag[1]] != NULL) { 2322 li->queued[srb->tag[1]] = NULL; 2323 li->used--; 2324 } 2325 } 2326 2327 static void 2328 trm_reset_scsi_bus(struct trm_softc *sc) 2329 { 2330 bus_space_tag_t iot = sc->sc_iot; 2331 bus_space_handle_t ioh = sc->sc_ioh; 2332 int timeout, s; 2333 2334 DPRINTF(("trm_reset_scsi_bus.........\n")); 2335 2336 s = splbio(); 2337 2338 sc->sc_flag |= RESET_DEV; 2339 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2340 for (timeout = 20000; timeout >= 0; timeout--) { 2341 DELAY(1); 2342 if ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2343 INT_SCSIRESET) == 0) 2344 break; 2345 } 2346 if (timeout == 0) 2347 printf(": scsibus reset timeout\n"); 2348 2349 splx(s); 2350 } 2351 2352 static void 2353 trm_scsi_reset_detect(struct trm_softc *sc) 2354 { 2355 bus_space_tag_t iot = sc->sc_iot; 2356 bus_space_handle_t ioh = sc->sc_ioh; 2357 int s; 2358 2359 DPRINTF(("trm_scsi_reset_detect...............\n")); 2360 DELAY(1000000); /* delay 1 sec */ 2361 2362 s = splbio(); 2363 2364 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2365 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2366 2367 if (sc->sc_flag & RESET_DEV) { 2368 sc->sc_flag |= RESET_DONE; 2369 } else { 2370 sc->sc_flag |= RESET_DETECT; 2371 sc->sc_actsrb = NULL; 2372 sc->sc_flag = 0; 2373 trm_sched(sc); 2374 } 2375 splx(s); 2376 } 2377 2378 /* 2379 * read seeprom 128 bytes to struct eeprom and check checksum. 2380 * If it is wrong, update with default value. 2381 */ 2382 static void 2383 trm_check_eeprom(struct trm_softc *sc, struct trm_nvram *eeprom) 2384 { 2385 struct nvram_target *target; 2386 uint16_t *ep; 2387 uint16_t chksum; 2388 int i; 2389 2390 DPRINTF(("trm_check_eeprom......\n")); 2391 trm_eeprom_read_all(sc, eeprom); 2392 ep = (uint16_t *)eeprom; 2393 chksum = 0; 2394 for (i = 0; i < 64; i++) 2395 chksum += le16toh(*ep++); 2396 2397 if (chksum != TRM_NVRAM_CKSUM) { 2398 DPRINTF(("TRM_S1040 EEPROM Check Sum ERROR (load default).\n")); 2399 /* 2400 * Checksum error, load default 2401 */ 2402 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2403 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2404 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2405 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2406 eeprom->subclass = 0x00; 2407 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 2408 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 2409 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 2410 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 2411 eeprom->reserved0 = 0x00; 2412 2413 for (i = 0, target = eeprom->target; 2414 i < TRM_MAX_TARGETS; 2415 i++, target++) { 2416 target->config0 = 0x77; 2417 target->period = 0x00; 2418 target->config2 = 0x00; 2419 target->config3 = 0x00; 2420 } 2421 2422 eeprom->scsi_id = 7; 2423 eeprom->channel_cfg = 0x0F; 2424 eeprom->delay_time = 0; 2425 eeprom->max_tag = 4; 2426 eeprom->reserved1 = 0x15; 2427 eeprom->boot_target = 0; 2428 eeprom->boot_lun = 0; 2429 eeprom->reserved2 = 0; 2430 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 2431 2432 chksum = 0; 2433 ep = (uint16_t *)eeprom; 2434 for (i = 0; i < 63; i++) 2435 chksum += le16toh(*ep++); 2436 2437 chksum = TRM_NVRAM_CKSUM - chksum; 2438 eeprom->checksum0 = chksum & 0xFF; 2439 eeprom->checksum1 = chksum >> 8; 2440 2441 trm_eeprom_write_all(sc, eeprom); 2442 } 2443 } 2444 2445 /* 2446 * write struct eeprom 128 bytes to seeprom 2447 */ 2448 static void 2449 trm_eeprom_write_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2450 { 2451 bus_space_tag_t iot = sc->sc_iot; 2452 bus_space_handle_t ioh = sc->sc_ioh; 2453 uint8_t *sbuf = (uint8_t *)eeprom; 2454 uint8_t addr; 2455 2456 /* Enable SEEPROM */ 2457 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2458 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2459 2460 /* 2461 * Write enable 2462 */ 2463 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2464 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2465 trm_eeprom_wait(); 2466 2467 for (addr = 0; addr < 128; addr++, sbuf++) 2468 trm_eeprom_set_data(sc, addr, *sbuf); 2469 2470 /* 2471 * Write disable 2472 */ 2473 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2474 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2475 trm_eeprom_wait(); 2476 2477 /* Disable SEEPROM */ 2478 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2479 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2480 } 2481 2482 /* 2483 * write one byte to seeprom 2484 */ 2485 static void 2486 trm_eeprom_set_data(struct trm_softc *sc, uint8_t addr, uint8_t data) 2487 { 2488 bus_space_tag_t iot = sc->sc_iot; 2489 bus_space_handle_t ioh = sc->sc_ioh; 2490 int i; 2491 uint8_t send; 2492 2493 /* 2494 * Send write command & address 2495 */ 2496 trm_eeprom_write_cmd(sc, 0x05, addr); 2497 /* 2498 * Write data 2499 */ 2500 for (i = 0; i < 8; i++, data <<= 1) { 2501 send = NVR_SELECT; 2502 if (data & 0x80) /* Start from bit 7 */ 2503 send |= NVR_BITOUT; 2504 2505 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2506 trm_eeprom_wait(); 2507 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2508 trm_eeprom_wait(); 2509 } 2510 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2511 trm_eeprom_wait(); 2512 /* 2513 * Disable chip select 2514 */ 2515 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2516 trm_eeprom_wait(); 2517 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2518 trm_eeprom_wait(); 2519 /* 2520 * Wait for write ready 2521 */ 2522 for (;;) { 2523 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2524 NVR_SELECT | NVR_CLOCK); 2525 trm_eeprom_wait(); 2526 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2527 trm_eeprom_wait(); 2528 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2529 break; 2530 } 2531 /* 2532 * Disable chip select 2533 */ 2534 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2535 } 2536 2537 /* 2538 * read seeprom 128 bytes to struct eeprom 2539 */ 2540 static void 2541 trm_eeprom_read_all(struct trm_softc *sc, struct trm_nvram *eeprom) 2542 { 2543 bus_space_tag_t iot = sc->sc_iot; 2544 bus_space_handle_t ioh = sc->sc_ioh; 2545 uint8_t *sbuf = (uint8_t *)eeprom; 2546 uint8_t addr; 2547 2548 /* 2549 * Enable SEEPROM 2550 */ 2551 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2552 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2553 2554 for (addr = 0; addr < 128; addr++) 2555 *sbuf++ = trm_eeprom_get_data(sc, addr); 2556 2557 /* 2558 * Disable SEEPROM 2559 */ 2560 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2561 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2562 } 2563 2564 /* 2565 * read one byte from seeprom 2566 */ 2567 static uint8_t 2568 trm_eeprom_get_data(struct trm_softc *sc, uint8_t addr) 2569 { 2570 bus_space_tag_t iot = sc->sc_iot; 2571 bus_space_handle_t ioh = sc->sc_ioh; 2572 int i; 2573 uint8_t read, data = 0; 2574 2575 /* 2576 * Send read command & address 2577 */ 2578 trm_eeprom_write_cmd(sc, 0x06, addr); 2579 2580 for (i = 0; i < 8; i++) { /* Read data */ 2581 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2582 NVR_SELECT | NVR_CLOCK); 2583 trm_eeprom_wait(); 2584 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2585 /* 2586 * Get data bit while falling edge 2587 */ 2588 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2589 data <<= 1; 2590 if (read & NVR_BITIN) 2591 data |= 1; 2592 2593 trm_eeprom_wait(); 2594 } 2595 /* 2596 * Disable chip select 2597 */ 2598 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2599 return (data); 2600 } 2601 2602 /* 2603 * write SB and Op Code into seeprom 2604 */ 2605 static void 2606 trm_eeprom_write_cmd(struct trm_softc *sc, uint8_t cmd, uint8_t addr) 2607 { 2608 bus_space_tag_t iot = sc->sc_iot; 2609 bus_space_handle_t ioh = sc->sc_ioh; 2610 int i; 2611 uint8_t send; 2612 2613 /* Program SB+OP code */ 2614 for (i = 0; i < 3; i++, cmd <<= 1) { 2615 send = NVR_SELECT; 2616 if (cmd & 0x04) /* Start from bit 2 */ 2617 send |= NVR_BITOUT; 2618 2619 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2620 trm_eeprom_wait(); 2621 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2622 trm_eeprom_wait(); 2623 } 2624 2625 /* Program address */ 2626 for (i = 0; i < 7; i++, addr <<= 1) { 2627 send = NVR_SELECT; 2628 if (addr & 0x40) /* Start from bit 6 */ 2629 send |= NVR_BITOUT; 2630 2631 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2632 trm_eeprom_wait(); 2633 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2634 trm_eeprom_wait(); 2635 } 2636 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2637 trm_eeprom_wait(); 2638 } 2639
Indexes created Mon Oct 13 14:09:54 GMT 2025