trm.c revision 1.3
1 /* $NetBSD: trm.c,v 1.3 2001/11/11 05:28:55 tsutsui Exp $ */ 2 /* 3 * Device Driver for Tekram DC395U/UW/F, DC315/U 4 * PCI SCSI Bus Master Host Adapter 5 * (SCSI chip set used Tekram ASIC TRM-S1040) 6 * 7 * Copyright (c) 2001 Rui-Xiang Guo 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 /* 33 * Ported from 34 * dc395x_trm.c 35 * 36 * Written for NetBSD 1.4.x by 37 * Erich Chen (erich (at) tekram.com.tw) 38 * 39 * Provided by 40 * (C)Copyright 1995-1999 Tekram Technology Co., Ltd. All rights reserved. 41 */ 42 43 /* #define TRM_DEBUG */ 44 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/malloc.h> 48 #include <sys/buf.h> 49 #include <sys/kernel.h> 50 #include <sys/device.h> 51 52 #include <machine/bus.h> 53 #include <machine/intr.h> 54 55 #include <uvm/uvm_extern.h> 56 57 #include <dev/scsipi/scsi_all.h> 58 #include <dev/scsipi/scsi_message.h> 59 #include <dev/scsipi/scsipi_all.h> 60 #include <dev/scsipi/scsiconf.h> 61 62 #include <dev/pci/pcidevs.h> 63 #include <dev/pci/pcireg.h> 64 #include <dev/pci/pcivar.h> 65 #include <dev/pci/trmreg.h> 66 67 /* 68 * feature of chip set MAX value 69 */ 70 #define TRM_MAX_TARGETS 16 71 #define TRM_MAX_SG_ENTRIES (MAXPHYS / PAGE_SIZE + 1) 72 #define TRM_MAX_SRB 32 73 74 /* 75 * Segment Entry 76 */ 77 struct trm_sg_entry { 78 u_int32_t address; 79 u_int32_t length; 80 }; 81 82 #define TRM_SG_SIZE (sizeof(struct trm_sg_entry) * TRM_MAX_SG_ENTRIES) 83 84 /* 85 ********************************************************************** 86 * The SEEPROM structure for TRM_S1040 87 ********************************************************************** 88 */ 89 struct nvram_target { 90 u_int8_t config0; /* Target configuration byte 0 */ 91 #define NTC_DO_WIDE_NEGO 0x20 /* Wide negotiate */ 92 #define NTC_DO_TAG_QUEUING 0x10 /* Enable SCSI tag queuing */ 93 #define NTC_DO_SEND_START 0x08 /* Send start command SPINUP */ 94 #define NTC_DO_DISCONNECT 0x04 /* Enable SCSI disconnect */ 95 #define NTC_DO_SYNC_NEGO 0x02 /* Sync negotiation */ 96 #define NTC_DO_PARITY_CHK 0x01 /* (it should define at NAC) Parity check enable */ 97 u_int8_t period; /* Target period */ 98 u_int8_t config2; /* Target configuration byte 2 */ 99 u_int8_t config3; /* Target configuration byte 3 */ 100 }; 101 102 struct trm_nvram { 103 u_int8_t subvendor_id[2]; /* 0,1 Sub Vendor ID */ 104 u_int8_t subsys_id[2]; /* 2,3 Sub System ID */ 105 u_int8_t subclass; /* 4 Sub Class */ 106 u_int8_t vendor_id[2]; /* 5,6 Vendor ID */ 107 u_int8_t device_id[2]; /* 7,8 Device ID */ 108 u_int8_t reserved0; /* 9 Reserved */ 109 struct nvram_target target[TRM_MAX_TARGETS]; 110 /* 10,11,12,13 111 * 14,15,16,17 112 * .... 113 * 70,71,72,73 */ 114 u_int8_t scsi_id; /* 74 Host Adapter SCSI ID */ 115 u_int8_t channel_cfg; /* 75 Channel configuration */ 116 #define NAC_SCANLUN 0x20 /* Include LUN as BIOS device */ 117 #define NAC_DO_PARITY_CHK 0x08 /* Parity check enable */ 118 #define NAC_POWERON_SCSI_RESET 0x04 /* Power on reset enable */ 119 #define NAC_GREATER_1G 0x02 /* > 1G support enable */ 120 #define NAC_GT2DRIVES 0x01 /* Support more than 2 drives */ 121 u_int8_t delay_time; /* 76 Power on delay time */ 122 u_int8_t max_tag; /* 77 Maximum tags */ 123 u_int8_t reserved1; /* 78 */ 124 u_int8_t boot_target; /* 79 */ 125 u_int8_t boot_lun; /* 80 */ 126 u_int8_t reserved2; /* 81 */ 127 u_int8_t reserved3[44]; /* 82,..125 */ 128 u_int8_t checksum0; /* 126 */ 129 u_int8_t checksum1; /* 127 */ 130 #define TRM_NVRAM_CKSUM 0x1234 131 }; 132 133 /* Nvram Initiater bits definition */ 134 #define MORE2_DRV 0x00000001 135 #define GREATER_1G 0x00000002 136 #define RST_SCSI_BUS 0x00000004 137 #define ACTIVE_NEGATION 0x00000008 138 #define NO_SEEK 0x00000010 139 #define LUN_CHECK 0x00000020 140 141 #define trm_wait_30us() DELAY(30) 142 143 /* 144 *----------------------------------------------------------------------- 145 * SCSI Request Block 146 *----------------------------------------------------------------------- 147 */ 148 struct trm_srb { 149 struct trm_srb *next; 150 struct trm_dcb *dcb; 151 152 struct trm_sg_entry *sgentry; 153 struct trm_sg_entry tempsg; /* Temp sgentry when Request Sense */ 154 /* 155 * the scsipi_xfer for this cmd 156 */ 157 struct scsipi_xfer *xs; 158 bus_dmamap_t dmap; 159 bus_size_t sgoffset; /* Xfer buf offset */ 160 161 u_int32_t buflen; /* Total xfer length */ 162 u_int32_t templen; /* Temp buflen when Request Sense */ 163 u_int32_t sgaddr; /* SGList physical starting address */ 164 165 u_int state; /* SRB State */ 166 #define SRB_FREE 0x0000 167 #define SRB_WAIT 0x0001 168 #define SRB_READY 0x0002 169 #define SRB_MSGOUT 0x0004 /* arbitration+msg_out 1st byte */ 170 #define SRB_MSGIN 0x0008 171 #define SRB_EXTEND_MSGIN 0x0010 172 #define SRB_COMMAND 0x0020 173 #define SRB_START_ 0x0040 /* arbitration+msg_out+command_out */ 174 #define SRB_DISCONNECT 0x0080 175 #define SRB_DATA_XFER 0x0100 176 #define SRB_XFERPAD 0x0200 177 #define SRB_STATUS 0x0400 178 #define SRB_COMPLETED 0x0800 179 #define SRB_ABORT_SENT 0x1000 180 #define SRB_DO_SYNC_NEGO 0x2000 181 #define SRB_DO_WIDE_NEGO 0x4000 182 #define SRB_UNEXPECT_RESEL 0x8000 183 u_int8_t *msg; 184 185 int sgcnt; 186 int sgindex; 187 188 int phase; /* SCSI phase */ 189 int hastat; /* Host Adapter Status */ 190 #define H_STATUS_GOOD 0x00 191 #define H_SEL_TIMEOUT 0x11 192 #define H_OVER_UNDER_RUN 0x12 193 #define H_UNEXP_BUS_FREE 0x13 194 #define H_TARGET_PHASE_F 0x14 195 #define H_INVALID_CCB_OP 0x16 196 #define H_LINK_CCB_BAD 0x17 197 #define H_BAD_TARGET_DIR 0x18 198 #define H_DUPLICATE_CCB 0x19 199 #define H_BAD_CCB_OR_SG 0x1A 200 #define H_ABORT 0xFF 201 int tastat; /* Target SCSI Status Byte */ 202 int flag; /* SRBFlag */ 203 #define DATAOUT 0x0080 204 #define DATAIN 0x0040 205 #define RESIDUAL_VALID 0x0020 206 #define ENABLE_TIMER 0x0010 207 #define RESET_DEV0 0x0004 208 #define ABORT_DEV 0x0002 209 #define AUTO_REQSENSE 0x0001 210 int srbstat; /* SRB Status */ 211 #define SRB_OK 0x01 212 #define ABORTION 0x02 213 #define OVER_RUN 0x04 214 #define UNDER_RUN 0x08 215 #define PARITY_ERROR 0x10 216 #define SRB_ERROR 0x20 217 int tagnum; /* Tag number */ 218 int retry; /* Retry Count */ 219 int msgcnt; 220 221 int cmdlen; /* SCSI command length */ 222 u_int8_t cmd[12]; /* SCSI command */ 223 u_int8_t tempcmd[6]; /* Temp cmd when Request Sense */ 224 225 u_int8_t msgin[6]; 226 u_int8_t msgout[6]; 227 }; 228 229 /* 230 *----------------------------------------------------------------------- 231 * Device Control Block 232 *----------------------------------------------------------------------- 233 */ 234 struct trm_dcb { 235 struct trm_dcb *next; 236 237 struct trm_srb *waitsrb; 238 struct trm_srb *last_waitsrb; 239 240 struct trm_srb *gosrb; 241 struct trm_srb *last_gosrb; 242 243 struct trm_srb *actsrb; 244 245 int gosrb_cnt; 246 u_int maxcmd; /* Max command */ 247 248 int id; /* SCSI Target ID (SCSI Only) */ 249 int lun; /* SCSI Log. Unit (SCSI Only) */ 250 251 u_int8_t tagmask; /* Tag mask */ 252 253 u_int8_t tacfg; /* Target Config */ 254 u_int8_t idmsg; /* Identify Msg */ 255 u_int8_t period; /* Max Period for nego. */ 256 257 u_int8_t synctl; /* Sync control for reg. */ 258 u_int8_t offset; /* Sync offset for reg. and nego.(low nibble) */ 259 u_int8_t mode; /* Sync mode ? (1 sync):(0 async) */ 260 #define SYNC_NEGO_ENABLE 0x01 261 #define SYNC_NEGO_DONE 0x02 262 #define WIDE_NEGO_ENABLE 0x04 263 #define WIDE_NEGO_DONE 0x08 264 #define EN_TAG_QUEUING 0x10 265 #define EN_ATN_STOP 0x20 266 #define SYNC_NEGO_OFFSET 15 267 u_int8_t flag; 268 #define ABORT_DEV_ 0x01 269 #define SHOW_MESSAGE_ 0x02 270 u_int8_t type; /* Device Type */ 271 }; 272 273 /* 274 *----------------------------------------------------------------------- 275 * Adapter Control Block 276 *----------------------------------------------------------------------- 277 */ 278 struct trm_softc { 279 struct device sc_dev; 280 281 bus_space_tag_t sc_iot; 282 bus_space_handle_t sc_ioh; 283 bus_dma_tag_t sc_dmat; 284 bus_dmamap_t sc_dmamap; /* Map the control structures */ 285 286 struct trm_dcb *sc_linkdcb; 287 struct trm_dcb *sc_roundcb; 288 289 struct trm_dcb *sc_actdcb; 290 struct trm_dcb *sc_dcb[TRM_MAX_TARGETS][8]; 291 292 struct trm_srb *sc_freesrb; 293 struct trm_srb *sc_srb; /* SRB array */ 294 struct trm_srb sc_tempsrb; 295 296 struct trm_sg_entry *sc_sglist; 297 298 int maxid; 299 int maxtag; /* Max Tag number */ 300 /* 301 * Link to the generic SCSI driver 302 */ 303 struct scsipi_channel sc_channel; 304 struct scsipi_adapter sc_adapter; 305 306 int sc_id; /* Adapter SCSI Target ID */ 307 308 int devcnt; /* Device Count */ 309 310 int devflag[TRM_MAX_TARGETS][8]; /* flag of initDCB for device */ 311 312 int devscan[TRM_MAX_TARGETS][8]; 313 int devscan_end; 314 int cur_offset; /* Current Sync offset */ 315 316 struct trm_nvram sc_eeprom; 317 int sc_config; 318 #define HCC_WIDE_CARD 0x20 319 #define HCC_SCSI_RESET 0x10 320 #define HCC_PARITY 0x08 321 #define HCC_AUTOTERM 0x04 322 #define HCC_LOW8TERM 0x02 323 #define HCC_UP8TERM 0x01 324 int sc_flag; 325 #define RESET_DEV 0x01 326 #define RESET_DETECT 0x02 327 #define RESET_DONE 0x04 328 }; 329 330 /* 331 * SCSI Status codes not defined in scsi_all.h 332 */ 333 #define SCSI_COND_MET 0x04 /* Condition Met */ 334 #define SCSI_INTERM_COND_MET 0x14 /* Intermediate condition met */ 335 #define SCSI_UNEXP_BUS_FREE 0xFD /* Unexpect Bus Free */ 336 #define SCSI_BUS_RST_DETECT 0xFE /* Scsi Bus Reset detected */ 337 #define SCSI_SEL_TIMEOUT 0xFF /* Selection Time out */ 338 339 static void trm_rewait_srb(struct trm_dcb *, struct trm_srb *); 340 static void trm_wait_srb(struct trm_softc *); 341 static void trm_reset_device(struct trm_softc *); 342 static void trm_recover_srb(struct trm_softc *); 343 static int trm_start_scsi(struct trm_softc *, struct trm_dcb *, 344 struct trm_srb *); 345 static int trm_intr(void *); 346 347 static void trm_dataout_phase0(struct trm_softc *, struct trm_srb *, int *); 348 static void trm_datain_phase0(struct trm_softc *, struct trm_srb *, int *); 349 static void trm_command_phase0(struct trm_softc *, struct trm_srb *, int *); 350 static void trm_status_phase0(struct trm_softc *, struct trm_srb *, int *); 351 static void trm_msgout_phase0(struct trm_softc *, struct trm_srb *, int *); 352 static void trm_msgin_phase0(struct trm_softc *, struct trm_srb *, int *); 353 static void trm_dataout_phase1(struct trm_softc *, struct trm_srb *, int *); 354 static void trm_datain_phase1(struct trm_softc *, struct trm_srb *, int *); 355 static void trm_command_phase1(struct trm_softc *, struct trm_srb *, int *); 356 static void trm_status_phase1(struct trm_softc *, struct trm_srb *, int *); 357 static void trm_msgout_phase1(struct trm_softc *, struct trm_srb *, int *); 358 static void trm_msgin_phase1(struct trm_softc *, struct trm_srb *, int *); 359 static void trm_nop0(struct trm_softc *, struct trm_srb *, int *); 360 static void trm_nop1(struct trm_softc *, struct trm_srb *, int *); 361 362 static void trm_set_xfer_rate(struct trm_softc *, struct trm_srb *, 363 struct trm_dcb *); 364 static void trm_dataio_xfer(struct trm_softc *, struct trm_srb *, int); 365 static void trm_disconnect(struct trm_softc *); 366 static void trm_reselect(struct trm_softc *); 367 static void trm_srb_done(struct trm_softc *, struct trm_dcb *, 368 struct trm_srb *); 369 static void trm_doing_srb_done(struct trm_softc *); 370 static void trm_scsi_reset_detect(struct trm_softc *); 371 static void trm_reset_scsi_bus(struct trm_softc *); 372 static void trm_request_sense(struct trm_softc *, struct trm_dcb *, 373 struct trm_srb *); 374 static void trm_msgout_abort(struct trm_softc *, struct trm_srb *); 375 static void trm_timeout(void *); 376 static void trm_reset(struct trm_softc *); 377 static void trm_send_srb(struct scsipi_xfer *, struct trm_softc *, 378 struct trm_srb *); 379 static int trm_init(struct trm_softc *); 380 static void trm_init_adapter(struct trm_softc *); 381 static void trm_init_dcb(struct trm_softc *, struct trm_dcb *, 382 struct scsipi_xfer *); 383 static void trm_link_srb(struct trm_softc *); 384 static void trm_init_sc(struct trm_softc *); 385 static void trm_check_eeprom(struct trm_softc *, struct trm_nvram *); 386 static void trm_release_srb(struct trm_softc *, struct trm_dcb *, 387 struct trm_srb *); 388 void trm_scsipi_request(struct scsipi_channel *, scsipi_adapter_req_t, void *); 389 390 static void trm_eeprom_read_all(struct trm_softc *, struct trm_nvram *); 391 static void trm_eeprom_write_all(struct trm_softc *, struct trm_nvram *); 392 static void trm_eeprom_set_data(struct trm_softc *, u_int8_t, u_int8_t); 393 static void trm_eeprom_write_cmd(struct trm_softc *, u_int8_t, u_int8_t); 394 static u_int8_t trm_eeprom_get_data(struct trm_softc *, u_int8_t); 395 396 static int trm_probe(struct device *, struct cfdata *, void *); 397 static void trm_attach(struct device *, struct device *, void *); 398 399 struct cfattach trm_ca = { 400 sizeof(struct trm_softc), trm_probe, trm_attach 401 }; 402 403 404 /* 405 * state_v = (void *) trm_scsi_phase0[phase] 406 */ 407 static void *trm_scsi_phase0[] = { 408 trm_dataout_phase0, /* phase:0 */ 409 trm_datain_phase0, /* phase:1 */ 410 trm_command_phase0, /* phase:2 */ 411 trm_status_phase0, /* phase:3 */ 412 trm_nop0, /* phase:4 */ 413 trm_nop1, /* phase:5 */ 414 trm_msgout_phase0, /* phase:6 */ 415 trm_msgin_phase0, /* phase:7 */ 416 }; 417 418 /* 419 * state_v = (void *) trm_scsi_phase1[phase] 420 */ 421 static void *trm_scsi_phase1[] = { 422 trm_dataout_phase1, /* phase:0 */ 423 trm_datain_phase1, /* phase:1 */ 424 trm_command_phase1, /* phase:2 */ 425 trm_status_phase1, /* phase:3 */ 426 trm_nop0, /* phase:4 */ 427 trm_nop1, /* phase:5 */ 428 trm_msgout_phase1, /* phase:6 */ 429 trm_msgin_phase1, /* phase:7 */ 430 }; 431 432 /* real period: */ 433 static const u_int8_t trm_clock_period[] = { 434 13, /* 52 ns 20.0 MB/sec */ 435 18, /* 72 ns 13.3 MB/sec */ 436 25, /* 100 ns 10.0 MB/sec */ 437 31, /* 124 ns 8.0 MB/sec */ 438 37, /* 148 ns 6.6 MB/sec */ 439 43, /* 172 ns 5.7 MB/sec */ 440 50, /* 200 ns 5.0 MB/sec */ 441 62 /* 248 ns 4.0 MB/sec */ 442 }; 443 444 /* 445 * Q back to pending Q 446 */ 447 static void 448 trm_rewait_srb(dcb, srb) 449 struct trm_dcb *dcb; 450 struct trm_srb *srb; 451 { 452 struct trm_srb *psrb1; 453 int s; 454 455 s = splbio(); 456 457 dcb->gosrb_cnt--; 458 psrb1 = dcb->gosrb; 459 if (srb == psrb1) 460 dcb->gosrb = psrb1->next; 461 else { 462 while (srb != psrb1->next) 463 psrb1 = psrb1->next; 464 465 psrb1->next = srb->next; 466 if (srb == dcb->last_gosrb) 467 dcb->last_gosrb = psrb1; 468 } 469 if (dcb->waitsrb) { 470 srb->next = dcb->waitsrb; 471 dcb->waitsrb = srb; 472 } else { 473 srb->next = NULL; 474 dcb->waitsrb = srb; 475 dcb->last_waitsrb = srb; 476 } 477 dcb->tagmask &= ~(1 << srb->tagnum); /* Free TAG number */ 478 479 splx(s); 480 } 481 482 static void 483 trm_wait_srb(sc) 484 struct trm_softc *sc; 485 { 486 struct trm_dcb *ptr, *ptr1; 487 struct trm_srb *srb; 488 int s; 489 490 s = splbio(); 491 492 if (sc->sc_actdcb == NULL && 493 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV)) == 0) { 494 ptr = sc->sc_roundcb; 495 if (ptr == NULL) { 496 ptr = sc->sc_linkdcb; 497 sc->sc_roundcb = ptr; 498 } 499 for (ptr1 = ptr; ptr1 != NULL;) { 500 sc->sc_roundcb = ptr1->next; 501 if (ptr1->maxcmd <= ptr1->gosrb_cnt || 502 (srb = ptr1->waitsrb) == NULL) { 503 if (sc->sc_roundcb == ptr) 504 break; 505 ptr1 = ptr1->next; 506 } else { 507 if (trm_start_scsi(sc, ptr1, srb) == 0) { 508 /* 509 * If trm_start_scsi return 0 : 510 * current interrupt status is 511 * interrupt enable. It's said that 512 * SCSI processor is unoccupied 513 */ 514 ptr1->gosrb_cnt++; 515 if (ptr1->last_waitsrb == srb) { 516 ptr1->waitsrb = NULL; 517 ptr1->last_waitsrb = NULL; 518 } else 519 ptr1->waitsrb = srb->next; 520 521 srb->next = NULL; 522 if (ptr1->gosrb != NULL) 523 ptr1->last_gosrb->next = srb; 524 else 525 ptr1->gosrb = srb; 526 527 ptr1->last_gosrb = srb; 528 } 529 break; 530 } 531 } 532 } 533 splx(s); 534 } 535 536 static void 537 trm_send_srb(xs, sc, srb) 538 struct scsipi_xfer *xs; 539 struct trm_softc *sc; 540 struct trm_srb *srb; 541 { 542 struct trm_dcb *dcb; 543 int s; 544 545 #ifdef TRM_DEBUG 546 printf("trm_send_srb..........\n"); 547 #endif 548 s = splbio(); 549 550 /* 551 * now get the DCB from upper layer( OS ) 552 */ 553 dcb = srb->dcb; 554 555 if (dcb->maxcmd <= dcb->gosrb_cnt || 556 sc->sc_actdcb != NULL || 557 (sc->sc_flag & (RESET_DETECT | RESET_DONE | RESET_DEV))) { 558 if (dcb->waitsrb != NULL) { 559 dcb->last_waitsrb->next = srb; 560 dcb->last_waitsrb = srb; 561 srb->next = NULL; 562 } else { 563 dcb->waitsrb = srb; 564 dcb->last_waitsrb = srb; 565 } 566 splx(s); 567 return; 568 } 569 if (dcb->waitsrb != NULL) { 570 dcb->last_waitsrb->next = srb; 571 dcb->last_waitsrb = srb; 572 srb->next = NULL; 573 /* srb = GetWaitingSRB(dcb); */ 574 srb = dcb->waitsrb; 575 dcb->waitsrb = srb->next; 576 srb->next = NULL; 577 } 578 if (trm_start_scsi(sc, dcb, srb) == 0) { 579 /* 580 * If trm_start_scsi return 0: current interrupt status 581 * is interrupt enable. It's said that SCSI processor is 582 * unoccupied. 583 */ 584 dcb->gosrb_cnt++; /* stack waiting SRB */ 585 if (dcb->gosrb != NULL) { 586 dcb->last_gosrb->next = srb; 587 dcb->last_gosrb = srb; 588 } else { 589 dcb->gosrb = srb; 590 dcb->last_gosrb = srb; 591 } 592 } else { 593 /* 594 * If trm_start_scsi return 1: current interrupt status 595 * is interrupt disreenable. It's said that SCSI processor 596 * has more one SRB need to do we need reQ back SRB. 597 */ 598 if (dcb->waitsrb != NULL) { 599 srb->next = dcb->waitsrb; 600 dcb->waitsrb = srb; 601 } else { 602 srb->next = NULL; 603 dcb->waitsrb = srb; 604 dcb->last_waitsrb = srb; 605 } 606 } 607 608 splx(s); 609 } 610 611 /* 612 * Called by GENERIC SCSI driver 613 * enqueues a SCSI command 614 */ 615 void 616 trm_scsipi_request(chan, req, arg) 617 struct scsipi_channel *chan; 618 scsipi_adapter_req_t req; 619 void *arg; 620 { 621 bus_space_tag_t iot; 622 bus_space_handle_t ioh; 623 struct trm_softc *sc; 624 struct trm_dcb *dcb = NULL; 625 struct trm_srb *srb; 626 struct scsipi_xfer *xs; 627 int error, i, id, lun, s; 628 629 sc = (struct trm_softc *)chan->chan_adapter->adapt_dev; 630 iot = sc->sc_iot; 631 ioh = sc->sc_ioh; 632 633 switch (req) { 634 case ADAPTER_REQ_RUN_XFER: 635 xs = arg; 636 id = xs->xs_periph->periph_target; 637 lun = xs->xs_periph->periph_lun; 638 #ifdef TRM_DEBUG 639 printf("trm_scsipi_request.....\n"); 640 printf("%s: id= %d lun= %d\n", sc->sc_dev.dv_xname, id, lun); 641 printf("sc->devscan[id][lun]= %d\n", sc->devscan[id][lun]); 642 #endif 643 if ((id > sc->maxid) || (lun > 7)) { 644 xs->error = XS_DRIVER_STUFFUP; 645 return; 646 } 647 dcb = sc->sc_dcb[id][lun]; 648 if (sc->devscan[id][lun] != 0 && sc->devflag[id][lun] == 0) { 649 /* 650 * Scan SCSI BUS => trm_init_dcb 651 */ 652 if (sc->devcnt < TRM_MAX_TARGETS) { 653 #ifdef TRM_DEBUG 654 printf("trm_init_dcb: dcb=%8x, ", (int) dcb); 655 printf("ID=%2x, LUN=%2x\n", id, lun); 656 #endif 657 sc->devflag[id][lun] = 1; 658 trm_init_dcb(sc, dcb, xs); 659 } else { 660 printf("%s: ", sc->sc_dev.dv_xname); 661 printf("sc->devcnt >= TRM_MAX_TARGETS\n"); 662 xs->error = XS_DRIVER_STUFFUP; 663 return; 664 } 665 } 666 667 if (xs->xs_control & XS_CTL_RESET) { 668 trm_reset(sc); 669 xs->error = XS_NOERROR | XS_RESET; 670 return; 671 } 672 if (xs->xs_status & XS_STS_DONE) { 673 printf("%s: Is it done?\n", sc->sc_dev.dv_xname); 674 xs->xs_status &= ~XS_STS_DONE; 675 } 676 xs->error = 0; 677 xs->status = 0; 678 xs->resid = 0; 679 680 s = splbio(); 681 682 /* Get SRB */ 683 srb = sc->sc_freesrb; 684 if (srb != NULL) { 685 sc->sc_freesrb = srb->next; 686 srb->next = NULL; 687 #ifdef TRM_DEBUG 688 printf("srb = %8p sc->sc_freesrb= %8p\n", 689 srb, sc->sc_freesrb); 690 #endif 691 } else { 692 xs->error = XS_RESOURCE_SHORTAGE; 693 scsipi_done(xs); 694 splx(s); 695 return; 696 } 697 /* 698 * XXX BuildSRB(srb ,dcb); XXX 699 */ 700 srb->dcb = dcb; 701 srb->xs = xs; 702 srb->cmdlen = xs->cmdlen; 703 /* 704 * Move layer of CAM command block to layer of SCSI 705 * Request Block for SCSI processor command doing. 706 */ 707 memcpy(srb->cmd, xs->cmd, xs->cmdlen); 708 if (xs->datalen > 0) { 709 #ifdef TRM_DEBUG 710 printf("xs->datalen...\n"); 711 printf("sc->sc_dmat=%x\n", (int) sc->sc_dmat); 712 printf("srb->dmap=%x\n", (int) srb->dmap); 713 printf("xs->data=%x\n", (int) xs->data); 714 printf("xs->datalen=%x\n", (int) xs->datalen); 715 #endif 716 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 717 xs->data, xs->datalen, NULL, 718 (xs->xs_control & XS_CTL_NOSLEEP) ? 719 BUS_DMA_NOWAIT : BUS_DMA_WAITOK)) != 0) { 720 printf("%s: DMA transfer map unable to load, " 721 "error = %d\n", sc->sc_dev.dv_xname, error); 722 xs->error = XS_DRIVER_STUFFUP; 723 /* 724 * free SRB 725 */ 726 srb->next = sc->sc_freesrb; 727 sc->sc_freesrb = srb; 728 splx(s); 729 return; 730 } 731 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 732 srb->dmap->dm_mapsize, 733 (xs->xs_control & XS_CTL_DATA_IN) ? 734 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 735 736 /* Set up the scatter gather list */ 737 for (i = 0; i < srb->dmap->dm_nsegs; i++) { 738 srb->sgentry[i].address = 739 htole32(srb->dmap->dm_segs[i].ds_addr); 740 srb->sgentry[i].length = 741 htole32(srb->dmap->dm_segs[i].ds_len); 742 } 743 srb->buflen = xs->datalen; 744 srb->sgcnt = srb->dmap->dm_nsegs; 745 } else { 746 srb->sgentry[0].address = 0; 747 srb->sgentry[0].length = 0; 748 srb->buflen = 0; 749 srb->sgcnt = 0; 750 } 751 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 752 srb->sgoffset, TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 753 754 if (dcb->type != T_SEQUENTIAL) 755 srb->retry = 1; 756 else 757 srb->retry = 0; 758 759 srb->sgindex = 0; 760 srb->hastat = 0; 761 srb->tastat = 0; 762 srb->msgcnt = 0; 763 srb->srbstat = 0; 764 srb->flag = 0; 765 srb->state = 0; 766 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 767 768 trm_send_srb(xs, sc, srb); 769 splx(s); 770 771 if ((xs->xs_control & XS_CTL_POLL) == 0) { 772 int timeout = xs->timeout; 773 timeout = (timeout > 100000) ? 774 timeout / 1000 * hz : timeout * hz / 1000; 775 callout_reset(&xs->xs_callout, timeout, 776 trm_timeout, srb); 777 } else { 778 s = splbio(); 779 do { 780 while (--xs->timeout) { 781 DELAY(1000); 782 if (bus_space_read_2(iot, ioh, 783 TRM_SCSI_STATUS) & SCSIINTERRUPT) 784 break; 785 } 786 if (xs->timeout == 0) { 787 trm_timeout(srb); 788 break; 789 } else 790 trm_intr(sc); 791 } while ((xs->xs_status & XS_STS_DONE) == 0); 792 splx(s); 793 } 794 return; 795 796 case ADAPTER_REQ_GROW_RESOURCES: 797 /* XXX Not supported. */ 798 return; 799 800 case ADAPTER_REQ_SET_XFER_MODE: 801 /* XXX XXX XXX */ 802 return; 803 } 804 } 805 806 static void 807 trm_reset_device(sc) 808 struct trm_softc *sc; 809 { 810 struct trm_dcb *dcb, *pdcb; 811 struct trm_nvram *eeprom; 812 int index; 813 814 dcb = sc->sc_linkdcb; 815 if (dcb == NULL) 816 return; 817 818 pdcb = dcb; 819 do { 820 dcb->mode &= ~(SYNC_NEGO_DONE | WIDE_NEGO_DONE); 821 dcb->synctl = 0; 822 dcb->offset = 0; 823 eeprom = &sc->sc_eeprom; 824 dcb->tacfg = eeprom->target[dcb->id].config0; 825 index = eeprom->target[dcb->id].period & 0x07; 826 dcb->period = trm_clock_period[index]; 827 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && 828 (sc->sc_config & HCC_WIDE_CARD)) 829 dcb->mode |= WIDE_NEGO_ENABLE; 830 831 dcb = dcb->next; 832 } 833 while (pdcb != dcb); 834 } 835 836 static void 837 trm_recover_srb(sc) 838 struct trm_softc *sc; 839 { 840 struct trm_dcb *dcb, *pdcb; 841 struct trm_srb *psrb, *psrb2; 842 int i; 843 844 dcb = sc->sc_linkdcb; 845 if (dcb == NULL) 846 return; 847 848 pdcb = dcb; 849 do { 850 psrb = pdcb->gosrb; 851 for (i = 0; i < pdcb->gosrb_cnt; i++) { 852 psrb2 = psrb; 853 psrb = psrb->next; 854 if (pdcb->waitsrb) { 855 psrb2->next = pdcb->waitsrb; 856 pdcb->waitsrb = psrb2; 857 } else { 858 pdcb->waitsrb = psrb2; 859 pdcb->last_waitsrb = psrb2; 860 psrb2->next = NULL; 861 } 862 } 863 pdcb->gosrb_cnt = 0; 864 pdcb->gosrb = NULL; 865 pdcb->tagmask = 0; 866 pdcb = pdcb->next; 867 } 868 while (pdcb != dcb); 869 } 870 871 /* 872 * perform a hard reset on the SCSI bus (and TRM_S1040 chip). 873 */ 874 static void 875 trm_reset(sc) 876 struct trm_softc *sc; 877 { 878 bus_space_tag_t iot = sc->sc_iot; 879 bus_space_handle_t ioh = sc->sc_ioh; 880 int s; 881 882 #ifdef TRM_DEBUG 883 printf("%s: SCSI RESET.........", sc->sc_dev.dv_xname); 884 #endif 885 s = splbio(); 886 887 /* disable SCSI and DMA interrupt */ 888 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 889 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 890 891 trm_reset_scsi_bus(sc); 892 DELAY(500000); 893 894 /* Enable SCSI interrupt */ 895 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 896 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 897 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 898 899 /* Enable DMA interrupt */ 900 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 901 902 /* Clear DMA FIFO */ 903 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 904 905 /* Clear SCSI FIFO */ 906 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 907 908 trm_reset_device(sc); 909 trm_doing_srb_done(sc); 910 sc->sc_actdcb = NULL; 911 sc->sc_flag = 0; /* RESET_DETECT, RESET_DONE, RESET_DEV */ 912 trm_wait_srb(sc); 913 914 splx(s); 915 } 916 917 static void 918 trm_timeout(arg) 919 void *arg; 920 { 921 struct trm_srb *srb = (struct trm_srb *)arg; 922 struct scsipi_xfer *xs = srb->xs; 923 struct scsipi_periph *periph = xs->xs_periph; 924 struct trm_softc *sc; 925 int s; 926 927 if (xs == NULL) 928 printf("trm_timeout called with xs == NULL\n"); 929 930 else { 931 scsipi_printaddr(xs->xs_periph); 932 printf("SCSI OpCode 0x%02x timed out\n", xs->cmd->opcode); 933 } 934 935 sc = (void *)periph->periph_channel->chan_adapter->adapt_dev; 936 937 s = splbio(); 938 trm_reset_scsi_bus(sc); 939 callout_stop(&xs->xs_callout); 940 splx(s); 941 } 942 943 static int 944 trm_start_scsi(sc, dcb, srb) 945 struct trm_softc *sc; 946 struct trm_dcb *dcb; 947 struct trm_srb *srb; 948 { 949 bus_space_tag_t iot = sc->sc_iot; 950 bus_space_handle_t ioh = sc->sc_ioh; 951 int tagnum; 952 u_int32_t tagmask; 953 u_int8_t scsicmd, idmsg; 954 955 srb->tagnum = 31; 956 957 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 958 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, dcb->id); 959 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 960 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 961 srb->phase = PH_BUS_FREE; /* initial phase */ 962 /* Flush FIFO */ 963 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 964 965 idmsg = dcb->idmsg; 966 967 if ((srb->cmd[0] == INQUIRY) || 968 (srb->cmd[0] == REQUEST_SENSE) || 969 (srb->flag & AUTO_REQSENSE)) { 970 if (((dcb->mode & WIDE_NEGO_ENABLE) && 971 (dcb->mode & WIDE_NEGO_DONE) == 0) || 972 ((dcb->mode & SYNC_NEGO_ENABLE) && 973 (dcb->mode & SYNC_NEGO_DONE) == 0)) { 974 if ((dcb->idmsg & 7) == 0 || srb->cmd[0] != INQUIRY) { 975 scsicmd = SCMD_SEL_ATNSTOP; 976 srb->state = SRB_MSGOUT; 977 goto polling; 978 } 979 } 980 /* Send identify message */ 981 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 982 idmsg & ~MSG_IDENTIFY_DISCFLAG); 983 scsicmd = SCMD_SEL_ATN; 984 srb->state = SRB_START_; 985 } else { /* not inquiry,request sense,auto request sense */ 986 /* Send identify message */ 987 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, idmsg); 988 DELAY(30); 989 scsicmd = SCMD_SEL_ATN; 990 srb->state = SRB_START_; 991 if (dcb->mode & EN_TAG_QUEUING) { 992 /* Send Tag message, get tag id */ 993 tagmask = 1; 994 tagnum = 0; 995 while (tagmask & dcb->tagmask) { 996 tagmask = tagmask << 1; 997 tagnum++; 998 } 999 /* Send Tag id */ 1000 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1001 MSG_SIMPLE_Q_TAG); 1002 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, tagnum); 1003 1004 dcb->tagmask |= tagmask; 1005 srb->tagnum = tagnum; 1006 1007 scsicmd = SCMD_SEL_ATN3; 1008 srb->state = SRB_START_; 1009 } 1010 } 1011 polling: 1012 /* 1013 * Send CDB ..command block... 1014 */ 1015 if (srb->flag & AUTO_REQSENSE) { 1016 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, REQUEST_SENSE); 1017 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1018 dcb->idmsg << SCSI_CMD_LUN_SHIFT); 1019 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1020 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1021 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1022 sizeof(struct scsipi_sense_data)); 1023 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1024 } else 1025 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1026 srb->cmd, srb->cmdlen); 1027 1028 if (bus_space_read_2(iot, ioh, TRM_SCSI_STATUS) & SCSIINTERRUPT) { 1029 /* 1030 * If trm_start_scsi return 1: current interrupt status 1031 * is interrupt disreenable. It's said that SCSI processor 1032 * has more one SRB need to do, SCSI processor has been 1033 * occupied by one SRB. 1034 */ 1035 srb->state = SRB_READY; 1036 dcb->tagmask &= ~(1 << srb->tagnum); 1037 return (1); 1038 } else { 1039 /* 1040 * If trm_start_scsi return 0: current interrupt status 1041 * is interrupt enable. It's said that SCSI processor is 1042 * unoccupied. 1043 */ 1044 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 1045 sc->sc_actdcb = dcb; 1046 dcb->actsrb = srb; 1047 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1048 DO_DATALATCH | DO_HWRESELECT); 1049 /* it's important for atn stop */ 1050 /* 1051 * SCSI command 1052 */ 1053 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, scsicmd); 1054 return (0); 1055 } 1056 } 1057 1058 /* 1059 * Catch an interrupt from the adapter 1060 * Process pending device interrupts. 1061 */ 1062 static int 1063 trm_intr(vsc) 1064 void *vsc; 1065 { 1066 bus_space_tag_t iot; 1067 bus_space_handle_t ioh; 1068 struct trm_softc *sc; 1069 struct trm_dcb *dcb; 1070 struct trm_srb *srb; 1071 void (*state_v) (struct trm_softc *, struct trm_srb *, int *); 1072 int phase, intstat, stat = 0; 1073 1074 #ifdef TRM_DEBUG 1075 printf("trm_intr......\n"); 1076 #endif 1077 sc = (struct trm_softc *)vsc; 1078 iot = sc->sc_iot; 1079 ioh = sc->sc_ioh; 1080 1081 if (sc == NULL) 1082 return (0); 1083 1084 stat = bus_space_read_2(iot, ioh, TRM_SCSI_STATUS); 1085 if ((stat & SCSIINTERRUPT) == 0) 1086 return (0); 1087 1088 #ifdef TRM_DEBUG 1089 printf("stat=%2x,", stat); 1090 #endif 1091 intstat = bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 1092 1093 #ifdef TRM_DEBUG 1094 printf("intstat=%2x,", intstat); 1095 #endif 1096 if (intstat & (INT_SELTIMEOUT | INT_DISCONNECT)) { 1097 trm_disconnect(sc); 1098 return (1); 1099 } 1100 if (intstat & INT_RESELECTED) { 1101 trm_reselect(sc); 1102 return (1); 1103 } 1104 if (intstat & INT_SCSIRESET) { 1105 trm_scsi_reset_detect(sc); 1106 return (1); 1107 } 1108 if (intstat & (INT_BUSSERVICE | INT_CMDDONE)) { 1109 dcb = sc->sc_actdcb; 1110 srb = dcb->actsrb; 1111 if (dcb != NULL) 1112 if (dcb->flag & ABORT_DEV_) { 1113 srb->msgout[0] = MSG_ABORT; 1114 trm_msgout_abort(sc, srb); 1115 } 1116 /* 1117 * software sequential machine 1118 */ 1119 phase = srb->phase; /* phase: */ 1120 1121 /* 1122 * 62037 or 62137 call trm_scsi_phase0[]... "phase 1123 * entry" handle every phase before start transfer 1124 */ 1125 state_v = (void *)trm_scsi_phase0[phase]; 1126 state_v(sc, srb, &stat); 1127 1128 /* 1129 * if there were any exception occured 1130 * stat will be modify to bus free phase new 1131 * stat transfer out from ... prvious state_v 1132 * 1133 */ 1134 /* phase:0,1,2,3,4,5,6,7 */ 1135 srb->phase = stat & PHASEMASK; 1136 phase = stat & PHASEMASK; 1137 1138 /* 1139 * call trm_scsi_phase1[]... "phase entry" handle every 1140 * phase do transfer 1141 */ 1142 state_v = (void *)trm_scsi_phase1[phase]; 1143 state_v(sc, srb, &stat); 1144 return (1); 1145 } 1146 return (0); 1147 } 1148 1149 static void 1150 trm_msgout_phase0(sc, srb, pstat) 1151 struct trm_softc *sc; 1152 struct trm_srb *srb; 1153 int *pstat; 1154 { 1155 1156 if (srb->state & (SRB_UNEXPECT_RESEL | SRB_ABORT_SENT)) 1157 *pstat = PH_BUS_FREE; /* .. initial phase */ 1158 } 1159 1160 static void 1161 trm_msgout_phase1(sc, srb, pstat) 1162 struct trm_softc *sc; 1163 struct trm_srb *srb; 1164 int *pstat; 1165 { 1166 bus_space_tag_t iot = sc->sc_iot; 1167 bus_space_handle_t ioh = sc->sc_ioh; 1168 struct trm_dcb *dcb; 1169 1170 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1171 dcb = sc->sc_actdcb; 1172 if ((srb->state & SRB_MSGOUT) == 0) { 1173 if (srb->msgcnt > 0) { 1174 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1175 srb->msgout, srb->msgcnt); 1176 srb->msgcnt = 0; 1177 if ((dcb->flag & ABORT_DEV_) && 1178 (srb->msgout[0] == MSG_ABORT)) 1179 srb->state = SRB_ABORT_SENT; 1180 } else { 1181 if ((srb->cmd[0] == INQUIRY) || 1182 (srb->cmd[0] == REQUEST_SENSE) || 1183 (srb->flag & AUTO_REQSENSE)) 1184 if (dcb->mode & SYNC_NEGO_ENABLE) 1185 goto mop1; 1186 1187 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, MSG_ABORT); 1188 } 1189 } else { 1190 mop1: /* message out phase */ 1191 if ((srb->state & SRB_DO_WIDE_NEGO) == 0 && 1192 (dcb->mode & WIDE_NEGO_ENABLE)) { 1193 /* 1194 * WIDE DATA TRANSFER REQUEST code (03h) 1195 */ 1196 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP); 1197 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1198 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1199 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1200 MSG_EXTENDED); /* (01h) */ 1201 1202 /* Message length (02h) */ 1203 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1204 MSG_EXT_WDTR_LEN); 1205 1206 /* wide data xfer (03h) */ 1207 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1208 MSG_EXT_WDTR); 1209 1210 /* width: 0(8bit), 1(16bit) ,2(32bit) */ 1211 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1212 MSG_EXT_WDTR_BUS_16_BIT); 1213 1214 srb->state |= SRB_DO_WIDE_NEGO; 1215 } else if ((srb->state & SRB_DO_SYNC_NEGO) == 0 && 1216 (dcb->mode & SYNC_NEGO_ENABLE)) { 1217 /* 1218 * SYNCHRONOUS DATA TRANSFER REQUEST code (01h) 1219 */ 1220 if ((dcb->mode & WIDE_NEGO_DONE) == 0) 1221 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1222 dcb->idmsg & ~MSG_IDENTIFY_DISCFLAG); 1223 1224 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1225 MSG_EXTENDED); /* (01h) */ 1226 1227 /* Message length (03h) */ 1228 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1229 MSG_EXT_SDTR_LEN); 1230 1231 /* SYNCHRONOUS DATA TRANSFER REQUEST code (01h) */ 1232 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1233 MSG_EXT_SDTR); 1234 1235 /* Transfer peeriod factor */ 1236 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, dcb->period); 1237 1238 /* REQ/ACK offset */ 1239 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1240 SYNC_NEGO_OFFSET); 1241 srb->state |= SRB_DO_SYNC_NEGO; 1242 } 1243 } 1244 /* it's important for atn stop */ 1245 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1246 1247 /* 1248 * SCSI cammand 1249 */ 1250 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1251 } 1252 1253 static void 1254 trm_command_phase0(sc, srb, pstat) 1255 struct trm_softc *sc; 1256 struct trm_srb *srb; 1257 int *pstat; 1258 { 1259 1260 } 1261 1262 static void 1263 trm_command_phase1(sc, srb, pstat) 1264 struct trm_softc *sc; 1265 struct trm_srb *srb; 1266 int *pstat; 1267 { 1268 bus_space_tag_t iot = sc->sc_iot; 1269 bus_space_handle_t ioh = sc->sc_ioh; 1270 struct trm_dcb *dcb; 1271 1272 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRATN | DO_CLRFIFO); 1273 if (srb->flag & AUTO_REQSENSE) { 1274 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, REQUEST_SENSE); 1275 dcb = sc->sc_actdcb; 1276 /* target id */ 1277 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1278 dcb->idmsg << SCSI_CMD_LUN_SHIFT); 1279 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1280 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1281 /* sizeof(struct scsi_sense_data) */ 1282 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 1283 sizeof(struct scsipi_sense_data)); 1284 bus_space_write_1(iot, ioh, TRM_SCSI_FIFO, 0); 1285 } else 1286 bus_space_write_multi_1(iot, ioh, TRM_SCSI_FIFO, 1287 srb->cmd, srb->cmdlen); 1288 1289 srb->state = SRB_COMMAND; 1290 /* it's important for atn stop */ 1291 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1292 1293 /* 1294 * SCSI cammand 1295 */ 1296 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_OUT); 1297 } 1298 1299 static void 1300 trm_dataout_phase0(sc, srb, pstat) 1301 struct trm_softc *sc; 1302 struct trm_srb *srb; 1303 int *pstat; 1304 { 1305 bus_space_tag_t iot = sc->sc_iot; 1306 bus_space_handle_t ioh = sc->sc_ioh; 1307 struct trm_dcb *dcb; 1308 struct trm_sg_entry *sg; 1309 int sgindex; 1310 u_int32_t xferlen, leftcnt = 0; 1311 1312 dcb = srb->dcb; 1313 1314 if ((srb->state & SRB_XFERPAD) == 0) { 1315 if (*pstat & PARITYERROR) 1316 srb->srbstat |= PARITY_ERROR; 1317 1318 if ((*pstat & SCSIXFERDONE) == 0) { 1319 /* 1320 * when data transfer from DMA FIFO to SCSI FIFO 1321 * if there was some data left in SCSI FIFO 1322 */ 1323 leftcnt = bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) & 1324 SCSI_FIFOCNT_MASK; 1325 if (dcb->synctl & WIDE_SYNC) 1326 /* 1327 * if WIDE scsi SCSI FIFOCNT unit is word 1328 * so need to * 2 1329 */ 1330 leftcnt <<= 1; 1331 } 1332 /* 1333 * caculate all the residue data that not yet tranfered 1334 * SCSI transfer counter + left in SCSI FIFO data 1335 * 1336 * .....TRM_SCSI_XCNT (24bits) 1337 * The counter always decrement by one for every SCSI 1338 * byte transfer. 1339 * .....TRM_SCSI_FIFOCNT ( 5bits) 1340 * The counter is SCSI FIFO offset counter 1341 */ 1342 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1343 if (leftcnt == 1) { 1344 leftcnt = 0; 1345 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1346 DO_CLRFIFO); 1347 } 1348 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1349 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1350 DMAXFERCOMP) == 0) 1351 ; 1352 1353 srb->buflen = 0; 1354 } else { /* Update SG list */ 1355 /* 1356 * if transfer not yet complete 1357 * there were some data residue in SCSI FIFO or 1358 * SCSI transfer counter not empty 1359 */ 1360 if (srb->buflen != leftcnt) { 1361 /* data that had transferred length */ 1362 xferlen = srb->buflen - leftcnt; 1363 1364 /* next time to be transferred length */ 1365 srb->buflen = leftcnt; 1366 1367 /* 1368 * parsing from last time disconnect sgindex 1369 */ 1370 sg = srb->sgentry + srb->sgindex; 1371 for (sgindex = srb->sgindex; 1372 sgindex < srb->sgcnt; 1373 sgindex++, sg++) { 1374 /* 1375 * find last time which SG transfer 1376 * be disconnect 1377 */ 1378 if (xferlen >= le32toh(sg->length)) 1379 xferlen -= le32toh(sg->length); 1380 else { 1381 /* 1382 * update last time 1383 * disconnected SG list 1384 */ 1385 /* residue data length */ 1386 sg->length = htole32( 1387 le32toh(sg->length) 1388 - xferlen); 1389 /* residue data pointer */ 1390 sg->address = htole32( 1391 le32toh(sg->address) 1392 + xferlen); 1393 srb->sgindex = sgindex; 1394 break; 1395 } 1396 } 1397 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1398 srb->sgoffset, TRM_SG_SIZE, 1399 BUS_DMASYNC_PREWRITE); 1400 } 1401 } 1402 } 1403 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 1404 } 1405 1406 static void 1407 trm_dataout_phase1(sc, srb, pstat) 1408 struct trm_softc *sc; 1409 struct trm_srb *srb; 1410 int *pstat; 1411 { 1412 1413 /* 1414 * do prepare befor transfer when data out phase 1415 */ 1416 trm_dataio_xfer(sc, srb, XFERDATAOUT); 1417 } 1418 1419 static void 1420 trm_datain_phase0(sc, srb, pstat) 1421 struct trm_softc *sc; 1422 struct trm_srb *srb; 1423 int *pstat; 1424 { 1425 bus_space_tag_t iot = sc->sc_iot; 1426 bus_space_handle_t ioh = sc->sc_ioh; 1427 struct trm_sg_entry *sg; 1428 int sgindex; 1429 u_int32_t xferlen, leftcnt = 0; 1430 1431 if ((srb->state & SRB_XFERPAD) == 0) { 1432 if (*pstat & PARITYERROR) 1433 srb->srbstat |= PARITY_ERROR; 1434 1435 leftcnt += bus_space_read_4(iot, ioh, TRM_SCSI_XCNT); 1436 if ((leftcnt == 0) || (*pstat & SCSIXFERCNT_2_ZERO)) { 1437 while ((bus_space_read_1(iot, ioh, TRM_DMA_STATUS) & 1438 DMAXFERCOMP) == 0) 1439 ; 1440 1441 srb->buflen = 0; 1442 } else { /* phase changed */ 1443 /* 1444 * parsing the case: 1445 * when a transfer not yet complete 1446 * but be disconnected by uper layer 1447 * if transfer not yet complete 1448 * there were some data residue in SCSI FIFO or 1449 * SCSI transfer counter not empty 1450 */ 1451 if (srb->buflen != leftcnt) { 1452 /* 1453 * data that had transferred length 1454 */ 1455 xferlen = srb->buflen - leftcnt; 1456 1457 /* 1458 * next time to be transferred length 1459 */ 1460 srb->buflen = leftcnt; 1461 1462 /* 1463 * parsing from last time disconnect sgindex 1464 */ 1465 sg = srb->sgentry + srb->sgindex; 1466 for (sgindex = srb->sgindex; 1467 sgindex < srb->sgcnt; 1468 sgindex++, sg++) { 1469 /* 1470 * find last time which SG transfer 1471 * be disconnect 1472 */ 1473 if (xferlen >= le32toh(sg->length)) 1474 xferlen -= le32toh(sg->length); 1475 else { 1476 /* 1477 * update last time 1478 * disconnected SG list 1479 */ 1480 /* residue data length */ 1481 sg->length = htole32( 1482 le32toh(sg->length) 1483 - xferlen); 1484 /* residue data pointer */ 1485 sg->address = htole32( 1486 le32toh(sg->address) 1487 + xferlen); 1488 srb->sgindex = sgindex; 1489 break; 1490 } 1491 } 1492 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, 1493 srb->sgoffset, TRM_SG_SIZE, 1494 BUS_DMASYNC_PREWRITE); 1495 } 1496 } 1497 } 1498 } 1499 1500 static void 1501 trm_datain_phase1(sc, srb, pstat) 1502 struct trm_softc *sc; 1503 struct trm_srb *srb; 1504 int *pstat; 1505 { 1506 1507 /* 1508 * do prepare befor transfer when data in phase 1509 */ 1510 trm_dataio_xfer(sc, srb, XFERDATAIN); 1511 } 1512 1513 static void 1514 trm_dataio_xfer(sc, srb, iodir) 1515 struct trm_softc *sc; 1516 struct trm_srb *srb; 1517 int iodir; 1518 { 1519 bus_space_tag_t iot = sc->sc_iot; 1520 bus_space_handle_t ioh = sc->sc_ioh; 1521 struct trm_dcb *dcb = srb->dcb; 1522 1523 if (srb->sgindex < srb->sgcnt) { 1524 if (srb->buflen > 0) { 1525 /* 1526 * load what physical address of Scatter/Gather 1527 * list table want to be transfer 1528 */ 1529 srb->state = SRB_DATA_XFER; 1530 bus_space_write_4(iot, ioh, TRM_DMA_XHIGHADDR, 0); 1531 bus_space_write_4(iot, ioh, TRM_DMA_XLOWADDR, 1532 srb->sgaddr + 1533 srb->sgindex * sizeof(struct trm_sg_entry)); 1534 /* 1535 * load how many bytes in the Scatter/Gather list table 1536 */ 1537 bus_space_write_4(iot, ioh, TRM_DMA_XCNT, 1538 (srb->sgcnt - srb->sgindex) 1539 * sizeof(struct trm_sg_entry)); 1540 /* 1541 * load total xfer length (24bits) max value 16Mbyte 1542 */ 1543 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, srb->buflen); 1544 /* Start DMA transfer */ 1545 bus_space_write_1(iot, ioh, TRM_DMA_COMMAND, 1546 iodir | SGXFER); 1547 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, 1548 STARTDMAXFER); 1549 1550 /* Start SCSI transfer */ 1551 /* it's important for atn stop */ 1552 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1553 DO_DATALATCH); 1554 1555 /* 1556 * SCSI cammand 1557 */ 1558 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1559 (iodir == XFERDATAOUT) ? 1560 SCMD_DMA_OUT : SCMD_DMA_IN); 1561 } else { /* xfer pad */ 1562 if (srb->sgcnt) { 1563 srb->hastat = H_OVER_UNDER_RUN; 1564 srb->srbstat |= OVER_RUN; 1565 } 1566 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1567 (dcb->synctl & WIDE_SYNC) ? 2 : 1); 1568 1569 if (iodir == XFERDATAOUT) 1570 bus_space_write_2(iot, ioh, TRM_SCSI_FIFO, 0); 1571 else 1572 bus_space_read_2(iot, ioh, TRM_SCSI_FIFO); 1573 1574 srb->state |= SRB_XFERPAD; 1575 /* it's important for atn stop */ 1576 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1577 DO_DATALATCH); 1578 1579 /* 1580 * SCSI cammand 1581 */ 1582 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, 1583 (iodir == XFERDATAOUT) ? 1584 SCMD_FIFO_OUT : SCMD_FIFO_IN); 1585 } 1586 } 1587 } 1588 1589 static void 1590 trm_status_phase0(sc, srb, pstat) 1591 struct trm_softc *sc; 1592 struct trm_srb *srb; 1593 int *pstat; 1594 { 1595 bus_space_tag_t iot = sc->sc_iot; 1596 bus_space_handle_t ioh = sc->sc_ioh; 1597 1598 srb->tastat = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1599 srb->state = SRB_COMPLETED; 1600 *pstat = PH_BUS_FREE; /* .. initial phase */ 1601 /* it's important for atn stop */ 1602 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1603 1604 /* 1605 * SCSI cammand 1606 */ 1607 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1608 } 1609 1610 static void 1611 trm_status_phase1(sc, srb, pstat) 1612 struct trm_softc *sc; 1613 struct trm_srb *srb; 1614 int *pstat; 1615 { 1616 bus_space_tag_t iot = sc->sc_iot; 1617 bus_space_handle_t ioh = sc->sc_ioh; 1618 1619 if (bus_space_read_1(iot, ioh, TRM_DMA_COMMAND) & XFERDATAIN) { 1620 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1621 & SCSI_FIFO_EMPTY) == 0) 1622 bus_space_write_2(iot, ioh, 1623 TRM_SCSI_CONTROL, DO_CLRFIFO); 1624 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1625 & DMA_FIFO_EMPTY) == 0) 1626 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1627 } else { 1628 if ((bus_space_read_1(iot, ioh, TRM_DMA_FIFOSTATUS) 1629 & DMA_FIFO_EMPTY) == 0) 1630 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, CLRXFIFO); 1631 if ((bus_space_read_1(iot, ioh, TRM_SCSI_FIFOCNT) 1632 & SCSI_FIFO_EMPTY) == 0) 1633 bus_space_write_2(iot, ioh, 1634 TRM_SCSI_CONTROL, DO_CLRFIFO); 1635 } 1636 srb->state = SRB_STATUS; 1637 /* it's important for atn stop */ 1638 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1639 1640 /* 1641 * SCSI cammand 1642 */ 1643 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_COMP); 1644 } 1645 1646 static void 1647 trm_msgin_phase0(sc, srb, pstat) 1648 struct trm_softc *sc; 1649 struct trm_srb *srb; 1650 int *pstat; 1651 { 1652 bus_space_tag_t iot = sc->sc_iot; 1653 bus_space_handle_t ioh = sc->sc_ioh; 1654 struct trm_dcb *dcb = sc->sc_actdcb; 1655 struct trm_srb *tempsrb; 1656 int syncxfer, tagid, index; 1657 u_int8_t msgin_code; 1658 1659 msgin_code = bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1660 if ((srb->state & SRB_EXTEND_MSGIN) == 0) { 1661 if (msgin_code == MSG_DISCONNECT) { 1662 srb->state = SRB_DISCONNECT; 1663 goto min6; 1664 } else if (msgin_code == MSG_SAVEDATAPOINTER) { 1665 goto min6; 1666 } else if ((msgin_code == MSG_EXTENDED) || 1667 ((msgin_code >= MSG_SIMPLE_Q_TAG) && 1668 (msgin_code <= MSG_ORDERED_Q_TAG))) { 1669 srb->state |= SRB_EXTEND_MSGIN; 1670 /* extended message (01h) */ 1671 srb->msgin[0] = msgin_code; 1672 1673 srb->msgcnt = 1; 1674 /* extended message length (n) */ 1675 srb->msg = &srb->msgin[1]; 1676 1677 goto min6; 1678 } else if (msgin_code == MSG_MESSAGE_REJECT) { 1679 /* Reject message */ 1680 /* do wide nego reject */ 1681 if (dcb->mode & WIDE_NEGO_ENABLE) { 1682 dcb = srb->dcb; 1683 dcb->mode |= WIDE_NEGO_DONE; 1684 dcb->mode &= ~(SYNC_NEGO_DONE | EN_ATN_STOP | 1685 WIDE_NEGO_ENABLE); 1686 srb->state &= ~(SRB_DO_WIDE_NEGO | SRB_MSGIN); 1687 if ((dcb->mode & SYNC_NEGO_ENABLE) && 1688 (dcb->mode & SYNC_NEGO_DONE) == 0) { 1689 /* Set ATN, in case ATN was clear */ 1690 srb->state |= SRB_MSGOUT; 1691 bus_space_write_2(iot, ioh, 1692 TRM_SCSI_CONTROL, DO_SETATN); 1693 } else 1694 /* Clear ATN */ 1695 bus_space_write_2(iot, ioh, 1696 TRM_SCSI_CONTROL, DO_CLRATN); 1697 } else if (dcb->mode & SYNC_NEGO_ENABLE) { 1698 /* do sync nego reject */ 1699 bus_space_write_2(iot, ioh, 1700 TRM_SCSI_CONTROL, DO_CLRATN); 1701 if (srb->state & SRB_DO_SYNC_NEGO) { 1702 dcb = srb->dcb; 1703 dcb->mode &= ~(SYNC_NEGO_ENABLE | 1704 SYNC_NEGO_DONE); 1705 dcb->synctl = 0; 1706 dcb->offset = 0; 1707 goto re_prog; 1708 } 1709 } 1710 goto min6; 1711 } else if (msgin_code == MSG_IGN_WIDE_RESIDUE) { 1712 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1713 bus_space_read_1(iot, ioh, TRM_SCSI_FIFO); 1714 goto min6; 1715 } else { 1716 /* 1717 * Restore data pointer message 1718 * Save data pointer message 1719 * Completion message 1720 * NOP message 1721 */ 1722 goto min6; 1723 } 1724 } else { 1725 /* 1726 * when extend message in:srb->state = SRB_EXTEND_MSGIN 1727 * Parsing incomming extented messages 1728 */ 1729 *srb->msg = msgin_code; 1730 srb->msgcnt++; 1731 srb->msg++; 1732 #ifdef TRM_DEBUG 1733 printf("srb->msgin[0]=%2x\n", srb->msgin[0]); 1734 printf("srb->msgin[1]=%2x\n", srb->msgin[1]); 1735 printf("srb->msgin[2]=%2x\n", srb->msgin[2]); 1736 printf("srb->msgin[3]=%2x\n", srb->msgin[3]); 1737 printf("srb->msgin[4]=%2x\n", srb->msgin[4]); 1738 #endif 1739 if ((srb->msgin[0] >= MSG_SIMPLE_Q_TAG) && 1740 (srb->msgin[0] <= MSG_ORDERED_Q_TAG)) { 1741 /* 1742 * is QUEUE tag message : 1743 * 1744 * byte 0: 1745 * HEAD QUEUE TAG (20h) 1746 * ORDERED QUEUE TAG (21h) 1747 * SIMPLE QUEUE TAG (22h) 1748 * byte 1: 1749 * Queue tag (00h - FFh) 1750 */ 1751 if (srb->msgcnt == 2) { 1752 srb->state = 0; 1753 tagid = srb->msgin[1]; 1754 srb = dcb->gosrb; 1755 tempsrb = dcb->last_gosrb; 1756 if (srb) { 1757 for (;;) { 1758 if (srb->tagnum != tagid) { 1759 if (srb == tempsrb) 1760 goto mingx0; 1761 1762 srb = srb->next; 1763 } else 1764 break; 1765 } 1766 if (dcb->flag & ABORT_DEV_) { 1767 srb->state = SRB_ABORT_SENT; 1768 srb->msgout[0] = MSG_ABORT; 1769 trm_msgout_abort(sc, srb); 1770 } 1771 if ((srb->state & SRB_DISCONNECT) == 0) 1772 goto mingx0; 1773 1774 dcb->actsrb = srb; 1775 srb->state = SRB_DATA_XFER; 1776 } else { 1777 mingx0: 1778 srb = &sc->sc_tempsrb; 1779 srb->state = SRB_UNEXPECT_RESEL; 1780 dcb->actsrb = srb; 1781 srb->msgout[0] = MSG_ABORT_TAG; 1782 trm_msgout_abort(sc, srb); 1783 } 1784 } 1785 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1786 (srb->msgin[2] == MSG_EXT_WDTR) && 1787 (srb->msgcnt == 4)) { 1788 /* 1789 * is Wide data xfer Extended message : 1790 * ====================================== 1791 * WIDE DATA TRANSFER REQUEST 1792 * ====================================== 1793 * byte 0 : Extended message (01h) 1794 * byte 1 : Extended message length (02h) 1795 * byte 2 : WIDE DATA TRANSFER code (03h) 1796 * byte 3 : Transfer width exponent 1797 */ 1798 dcb = srb->dcb; 1799 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_WIDE_NEGO); 1800 if ((srb->msgin[1] != MSG_EXT_WDTR_LEN)) { 1801 /* Length is wrong, reject it */ 1802 dcb->mode &= 1803 ~(WIDE_NEGO_ENABLE | WIDE_NEGO_DONE); 1804 srb->msgcnt = 1; 1805 srb->msgin[0] = MSG_MESSAGE_REJECT; 1806 bus_space_write_2(iot, ioh, 1807 TRM_SCSI_CONTROL, DO_SETATN); 1808 goto min6; 1809 } 1810 if (dcb->mode & WIDE_NEGO_ENABLE) { 1811 /* Do wide negoniation */ 1812 if (srb->msgin[3] > MSG_EXT_WDTR_BUS_32_BIT) { 1813 /* reject_msg: */ 1814 dcb->mode &= ~(WIDE_NEGO_ENABLE | 1815 WIDE_NEGO_DONE); 1816 srb->msgcnt = 1; 1817 srb->msgin[0] = MSG_MESSAGE_REJECT; 1818 bus_space_write_2(iot, ioh, 1819 TRM_SCSI_CONTROL, DO_SETATN); 1820 goto min6; 1821 } 1822 if (srb->msgin[3] == MSG_EXT_WDTR_BUS_32_BIT) 1823 /* do 16 bits */ 1824 srb->msgin[3] = MSG_EXT_WDTR_BUS_16_BIT; 1825 else { 1826 if ((dcb->mode & WIDE_NEGO_DONE) == 0) { 1827 srb->state &= 1828 ~(SRB_DO_WIDE_NEGO | 1829 SRB_MSGIN); 1830 dcb->mode |= WIDE_NEGO_DONE; 1831 dcb->mode &= 1832 ~(SYNC_NEGO_DONE | 1833 EN_ATN_STOP | 1834 WIDE_NEGO_ENABLE); 1835 if (srb->msgin[3] != 1836 MSG_EXT_WDTR_BUS_8_BIT) 1837 /* is Wide data xfer */ 1838 dcb->synctl |= 1839 WIDE_SYNC; 1840 } 1841 } 1842 } else 1843 srb->msgin[3] = MSG_EXT_WDTR_BUS_8_BIT; 1844 1845 srb->state |= SRB_MSGOUT; 1846 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1847 DO_SETATN); 1848 goto min6; 1849 } else if ((srb->msgin[0] == MSG_EXTENDED) && 1850 (srb->msgin[2] == MSG_EXT_SDTR) && 1851 (srb->msgcnt == 5)) { 1852 /* 1853 * is 8bit transfer Extended message : 1854 * ================================= 1855 * SYNCHRONOUS DATA TRANSFER REQUEST 1856 * ================================= 1857 * byte 0 : Extended message (01h) 1858 * byte 1 : Extended message length (03) 1859 * byte 2 : SYNCHRONOUS DATA TRANSFER code (01h) 1860 * byte 3 : Transfer period factor 1861 * byte 4 : REQ/ACK offset 1862 */ 1863 srb->state &= ~(SRB_EXTEND_MSGIN | SRB_DO_SYNC_NEGO); 1864 if (srb->msgin[1] != MSG_EXT_SDTR_LEN) { 1865 /* reject_msg: */ 1866 srb->msgcnt = 1; 1867 srb->msgin[0] = MSG_MESSAGE_REJECT; 1868 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 1869 DO_SETATN); 1870 } else if (srb->msgin[3] == 0 || srb->msgin[4] == 0) { 1871 /* set async */ 1872 dcb = srb->dcb; 1873 /* disable sync & sync nego */ 1874 dcb->mode &= 1875 ~(SYNC_NEGO_ENABLE | SYNC_NEGO_DONE); 1876 dcb->synctl = 0; 1877 dcb->offset = 0; 1878 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1879 (dcb->lun == 0)) { 1880 printf("%s: target %d, Sync period=0 " 1881 "or Sync offset=0 to be " 1882 "asynchronous transfer\n", 1883 sc->sc_dev.dv_xname, dcb->id); 1884 dcb->flag |= SHOW_MESSAGE_; 1885 } 1886 goto re_prog; 1887 } else { /* set sync */ 1888 dcb = srb->dcb; 1889 dcb->mode |= SYNC_NEGO_ENABLE | SYNC_NEGO_DONE; 1890 1891 /* Transfer period factor */ 1892 dcb->period = srb->msgin[3]; 1893 1894 /* REQ/ACK offset */ 1895 dcb->offset = srb->msgin[4]; 1896 for (index = 0; index < 7; index++) 1897 if (srb->msgin[3] <= 1898 trm_clock_period[index]) 1899 break; 1900 1901 dcb->synctl |= (index | ALT_SYNC); 1902 /* 1903 * show negotiation message 1904 */ 1905 if (((dcb->flag & SHOW_MESSAGE_) == 0) && 1906 (dcb->lun == 0)) { 1907 syncxfer = 100000 / 1908 (trm_clock_period[index] * 4); 1909 if (dcb->synctl & WIDE_SYNC) { 1910 printf("%s: target %d, " 1911 "16bits Wide transfer\n", 1912 sc->sc_dev.dv_xname, 1913 dcb->id); 1914 syncxfer = syncxfer * 2; 1915 } else 1916 printf("%s: target %d, " 1917 "8bits Narrow transfer\n", 1918 sc->sc_dev.dv_xname, 1919 dcb->id); 1920 1921 printf("%s: target %d, " 1922 "Sync transfer %d.%01d MB/sec, " 1923 "Offset %d\n", sc->sc_dev.dv_xname, 1924 dcb->id, syncxfer / 100, 1925 syncxfer % 100, dcb->offset); 1926 dcb->flag |= SHOW_MESSAGE_; 1927 } 1928 re_prog: 1929 /* 1930 * program SCSI control register 1931 */ 1932 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, 1933 dcb->synctl); 1934 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 1935 dcb->offset); 1936 trm_set_xfer_rate(sc, srb, dcb); 1937 } 1938 } 1939 } 1940 min6: 1941 *pstat = PH_BUS_FREE; /* .. initial phase */ 1942 /* it's important for atn stop */ 1943 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1944 1945 /* 1946 * SCSI cammand 1947 */ 1948 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 1949 } 1950 1951 static void 1952 trm_msgin_phase1(sc, srb, pstat) 1953 struct trm_softc *sc; 1954 struct trm_srb *srb; 1955 int *pstat; 1956 { 1957 bus_space_tag_t iot = sc->sc_iot; 1958 bus_space_handle_t ioh = sc->sc_ioh; 1959 1960 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 1961 bus_space_write_4(iot, ioh, TRM_SCSI_XCNT, 1); 1962 if ((srb->state & SRB_MSGIN) == 0) { 1963 srb->state &= SRB_DISCONNECT; 1964 srb->state |= SRB_MSGIN; 1965 } 1966 /* it's important for atn stop */ 1967 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 1968 1969 /* 1970 * SCSI cammand 1971 */ 1972 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_FIFO_IN); 1973 } 1974 1975 static void 1976 trm_nop0(sc, srb, pstat) 1977 struct trm_softc *sc; 1978 struct trm_srb *srb; 1979 int *pstat; 1980 { 1981 1982 } 1983 1984 static void 1985 trm_nop1(sc, srb, pstat) 1986 struct trm_softc *sc; 1987 struct trm_srb *srb; 1988 int *pstat; 1989 { 1990 1991 } 1992 1993 static void 1994 trm_set_xfer_rate(sc, srb, dcb) 1995 struct trm_softc *sc; 1996 struct trm_srb *srb; 1997 struct trm_dcb *dcb; 1998 { 1999 struct trm_dcb *tempdcb; 2000 int i; 2001 2002 /* 2003 * set all lun device's (period, offset) 2004 */ 2005 #ifdef TRM_DEBUG 2006 printf("trm_set_xfer_rate............\n"); 2007 #endif 2008 if ((dcb->idmsg & 0x07) == 0) { 2009 if (sc->devscan_end == 0) 2010 sc->cur_offset = dcb->offset; 2011 else { 2012 tempdcb = sc->sc_linkdcb; 2013 for (i = 0; i < sc->devcnt; i++) { 2014 /* 2015 * different LUN but had same target ID 2016 */ 2017 if (tempdcb->id == dcb->id) { 2018 tempdcb->synctl = dcb->synctl; 2019 tempdcb->offset = dcb->offset; 2020 tempdcb->mode = dcb->mode; 2021 } 2022 tempdcb = tempdcb->next; 2023 } 2024 } 2025 } 2026 } 2027 2028 static void 2029 trm_disconnect(sc) 2030 struct trm_softc *sc; 2031 { 2032 bus_space_tag_t iot = sc->sc_iot; 2033 bus_space_handle_t ioh = sc->sc_ioh; 2034 struct trm_dcb *dcb; 2035 struct trm_srb *srb, *psrb; 2036 int i, s; 2037 2038 #ifdef TRM_DEBUG 2039 printf("trm_disconnect...............\n"); 2040 #endif 2041 s = splbio(); 2042 2043 dcb = sc->sc_actdcb; 2044 if (dcb == NULL) { 2045 DELAY(1000); /* 1 msec */ 2046 2047 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2048 DO_CLRFIFO | DO_HWRESELECT); 2049 return; 2050 } 2051 srb = dcb->actsrb; 2052 sc->sc_actdcb = 0; 2053 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2054 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, 2055 DO_CLRFIFO | DO_HWRESELECT); 2056 DELAY(100); 2057 if (srb->state & SRB_UNEXPECT_RESEL) { 2058 srb->state = 0; 2059 trm_wait_srb(sc); 2060 } else if (srb->state & SRB_ABORT_SENT) { 2061 dcb->tagmask = 0; 2062 dcb->flag &= ~ABORT_DEV_; 2063 srb = dcb->gosrb; 2064 for (i = 0; i < dcb->gosrb_cnt; i++) { 2065 psrb = srb->next; 2066 srb->next = sc->sc_freesrb; 2067 sc->sc_freesrb = srb; 2068 srb = psrb; 2069 } 2070 dcb->gosrb_cnt = 0; 2071 dcb->gosrb = 0; 2072 trm_wait_srb(sc); 2073 } else { 2074 if ((srb->state & (SRB_START_ | SRB_MSGOUT)) || 2075 (srb->state & (SRB_DISCONNECT | SRB_COMPLETED)) == 0) { 2076 /* Selection time out */ 2077 if (sc->devscan_end) { 2078 srb->state = SRB_READY; 2079 trm_rewait_srb(dcb, srb); 2080 } else { 2081 srb->tastat = SCSI_SEL_TIMEOUT; 2082 goto disc1; 2083 } 2084 } else if (srb->state & SRB_DISCONNECT) { 2085 /* 2086 * SRB_DISCONNECT 2087 */ 2088 trm_wait_srb(sc); 2089 } else if (srb->state & SRB_COMPLETED) { 2090 disc1: 2091 /* 2092 * SRB_COMPLETED 2093 */ 2094 if (dcb->maxcmd > 1) { 2095 /* free tag mask */ 2096 dcb->tagmask &= ~(1 << srb->tagnum); 2097 } 2098 dcb->actsrb = 0; 2099 srb->state = SRB_FREE; 2100 trm_srb_done(sc, dcb, srb); 2101 } 2102 } 2103 splx(s); 2104 } 2105 2106 static void 2107 trm_reselect(sc) 2108 struct trm_softc *sc; 2109 { 2110 bus_space_tag_t iot = sc->sc_iot; 2111 bus_space_handle_t ioh = sc->sc_ioh; 2112 struct trm_dcb *dcb; 2113 struct trm_srb *srb; 2114 int id, lun; 2115 2116 #ifdef TRM_DEBUG 2117 printf("trm_reselect.................\n"); 2118 #endif 2119 dcb = sc->sc_actdcb; 2120 if (dcb != NULL) { /* Arbitration lost but Reselection win */ 2121 srb = dcb->actsrb; 2122 srb->state = SRB_READY; 2123 trm_rewait_srb(dcb, srb); 2124 } 2125 /* Read Reselected Target Id and LUN */ 2126 id = bus_space_read_1(iot, ioh, TRM_SCSI_TARGETID); 2127 lun = bus_space_read_1(iot, ioh, TRM_SCSI_IDMSG) & 0x07; 2128 dcb = sc->sc_linkdcb; 2129 while (id != dcb->id && lun != dcb->lun) 2130 /* get dcb of the reselect id */ 2131 dcb = dcb->next; 2132 2133 sc->sc_actdcb = dcb; 2134 if (dcb->mode & EN_TAG_QUEUING) { 2135 srb = &sc->sc_tempsrb; 2136 dcb->actsrb = srb; 2137 } else { 2138 srb = dcb->actsrb; 2139 if (srb == NULL || (srb->state & SRB_DISCONNECT) == 0) { 2140 /* 2141 * abort command 2142 */ 2143 srb = &sc->sc_tempsrb; 2144 srb->state = SRB_UNEXPECT_RESEL; 2145 dcb->actsrb = srb; 2146 srb->msgout[0] = MSG_ABORT; 2147 trm_msgout_abort(sc, srb); 2148 } else { 2149 if (dcb->flag & ABORT_DEV_) { 2150 srb->state = SRB_ABORT_SENT; 2151 srb->msgout[0] = MSG_ABORT; 2152 trm_msgout_abort(sc, srb); 2153 } else 2154 srb->state = SRB_DATA_XFER; 2155 } 2156 } 2157 srb->phase = PH_BUS_FREE; /* SCSI bus free Phase */ 2158 /* 2159 * Program HA ID, target ID, period and offset 2160 */ 2161 /* target ID */ 2162 bus_space_write_1(iot, ioh, TRM_SCSI_TARGETID, id); 2163 2164 /* host ID */ 2165 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 2166 2167 /* period */ 2168 bus_space_write_1(iot, ioh, TRM_SCSI_SYNC, dcb->synctl); 2169 2170 /* offset */ 2171 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, dcb->offset); 2172 2173 /* it's important for atn stop */ 2174 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_DATALATCH); 2175 DELAY(30); 2176 /* 2177 * SCSI cammand 2178 */ 2179 /* to rls the /ACK signal */ 2180 bus_space_write_1(iot, ioh, TRM_SCSI_COMMAND, SCMD_MSGACCEPT); 2181 } 2182 2183 /* 2184 * Complete execution of a SCSI command 2185 * Signal completion to the generic SCSI driver 2186 */ 2187 static void 2188 trm_srb_done(sc, dcb, srb) 2189 struct trm_softc *sc; 2190 struct trm_dcb *dcb; 2191 struct trm_srb *srb; 2192 { 2193 struct scsipi_xfer *xs = srb->xs; 2194 struct scsipi_inquiry_data *ptr; 2195 struct trm_dcb *tempdcb; 2196 int i, j, id, lun, s, tastat; 2197 u_int8_t bval; 2198 2199 #ifdef TRM_DEBUG 2200 printf("trm_srb_done..................\n"); 2201 #endif 2202 if ((xs->xs_control & XS_CTL_POLL) == 0) 2203 callout_stop(&xs->xs_callout); 2204 2205 if (xs == NULL) 2206 return; 2207 2208 /* 2209 * target status 2210 */ 2211 tastat = srb->tastat; 2212 2213 if (srb->flag & AUTO_REQSENSE) { 2214 /* 2215 * status of auto request sense 2216 */ 2217 srb->flag &= ~AUTO_REQSENSE; 2218 srb->hastat = 0; 2219 srb->tastat = SCSI_CHECK; 2220 if (tastat == SCSI_CHECK) { 2221 xs->error = XS_TIMEOUT; 2222 goto ckc_e; 2223 } 2224 memcpy(srb->cmd, srb->tempcmd, sizeof(srb->tempcmd)); 2225 2226 srb->buflen = srb->templen; 2227 srb->sgentry[0].address = srb->tempsg.address; 2228 srb->sgentry[0].length = srb->tempsg.length; 2229 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2230 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2231 xs->status = SCSI_CHECK; 2232 goto ckc_e; 2233 } 2234 /* 2235 * target status 2236 */ 2237 if (tastat) 2238 switch (tastat) { 2239 case SCSI_CHECK: 2240 trm_request_sense(sc, dcb, srb); 2241 return; 2242 case SCSI_QUEUE_FULL: 2243 dcb->maxcmd = dcb->gosrb_cnt - 1; 2244 trm_rewait_srb(dcb, srb); 2245 srb->hastat = 0; 2246 srb->tastat = 0; 2247 goto ckc_e; 2248 case SCSI_SEL_TIMEOUT: 2249 srb->hastat = H_SEL_TIMEOUT; 2250 srb->tastat = 0; 2251 xs->error = XS_TIMEOUT; 2252 break; 2253 case SCSI_BUSY: 2254 xs->error = XS_BUSY; 2255 break; 2256 case SCSI_RESV_CONFLICT: 2257 #ifdef TRM_DEBUG 2258 printf("%s: target reserved at ", sc->sc_dev.dv_xname); 2259 printf("%s %d\n", __FILE__, __LINE__); 2260 #endif 2261 xs->error = XS_BUSY; 2262 break; 2263 default: 2264 srb->hastat = 0; 2265 if (srb->retry) { 2266 srb->retry--; 2267 srb->tastat = 0; 2268 srb->sgindex = 0; 2269 if (trm_start_scsi(sc, dcb, srb)) 2270 /* 2271 * If trm_start_scsi return 1 : 2272 * current interrupt status is 2273 * interrupt disreenable. It's said 2274 * that SCSI processor has more one 2275 * SRB need to do. 2276 */ 2277 trm_rewait_srb(dcb, srb); 2278 return; 2279 } else { 2280 #ifdef TRM_DEBUG 2281 printf("%s: driver stuffup at %s %d\n", 2282 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2283 #endif 2284 xs->error = XS_DRIVER_STUFFUP; 2285 break; 2286 } 2287 } 2288 else { 2289 /* 2290 * process initiator status...... 2291 * Adapter (initiator) status 2292 */ 2293 if (srb->hastat & H_OVER_UNDER_RUN) { 2294 srb->tastat = 0; 2295 /* Illegal length (over/under run) */ 2296 xs->error = XS_DRIVER_STUFFUP; 2297 } else if (srb->srbstat & PARITY_ERROR) { 2298 #ifdef TRM_DEBUG 2299 printf("%s: driver stuffup at %s %d\n", 2300 sc->sc_dev.dv_xname, __FILE__, __LINE__); 2301 #endif 2302 /* Driver failed to perform operation */ 2303 xs->error = XS_DRIVER_STUFFUP; 2304 } else { /* No error */ 2305 srb->hastat = 0; 2306 srb->tastat = 0; 2307 xs->error = XS_NOERROR; 2308 /* there is no error, (sense is invalid) */ 2309 } 2310 } 2311 ckc_e: 2312 id = srb->xs->xs_periph->periph_target; 2313 lun = srb->xs->xs_periph->periph_lun; 2314 if (sc->devscan[id][lun]) { 2315 /* 2316 * if SCSI command in "scan devices" duty 2317 */ 2318 if (srb->cmd[0] == TEST_UNIT_READY) { 2319 /* SCSI command phase: test unit ready */ 2320 #ifdef TRM_DEBUG 2321 printf("srb->cmd[0] == TEST_UNIT_READY....\n"); 2322 #endif 2323 } else if (srb->cmd[0] == INQUIRY) { 2324 /* 2325 * SCSI command phase: inquiry scsi device data 2326 * (type,capacity,manufacture.... 2327 */ 2328 if (xs->error == XS_TIMEOUT) 2329 goto NO_DEV; 2330 2331 ptr = (struct scsipi_inquiry_data *)xs->data; 2332 bval = ptr->device & SID_TYPE; 2333 /* 2334 * #define T_NODEVICE 0x1f Unknown or no device type 2335 */ 2336 if (bval == T_NODEVICE) { 2337 NO_DEV: 2338 #ifdef TRM_DEBUG 2339 printf("trm_srb_done NO Device: "); 2340 printf("id= %d ,lun= %d\n", id, lun); 2341 #endif 2342 s = splbio(); 2343 /* 2344 * dcb Q link 2345 * move the head of DCB to temdcb 2346 */ 2347 tempdcb = sc->sc_linkdcb; 2348 2349 /* 2350 * search current DCB for pass link 2351 */ 2352 while (tempdcb->next != dcb) 2353 tempdcb = tempdcb->next; 2354 2355 /* 2356 * when the current DCB been found 2357 * than connect current DCB tail 2358 * to the DCB tail that before current DCB 2359 */ 2360 tempdcb->next = dcb->next; 2361 2362 /* 2363 * if there was only one DCB ,connect his 2364 * tail to his head 2365 */ 2366 if (sc->sc_linkdcb == dcb) 2367 sc->sc_linkdcb = tempdcb->next; 2368 2369 if (sc->sc_roundcb == dcb) 2370 sc->sc_roundcb = tempdcb->next; 2371 2372 /* 2373 * if no device than free this device DCB 2374 * free( dcb, M_DEVBUF); 2375 */ 2376 sc->devcnt--; 2377 #ifdef TRM_DEBUG 2378 printf("sc->devcnt=%d\n", sc->devcnt); 2379 #endif 2380 if (sc->devcnt == 0) { 2381 sc->sc_linkdcb = NULL; 2382 sc->sc_roundcb = NULL; 2383 } 2384 /* no device set scan device flag=0 */ 2385 sc->devscan[id][lun] = 0; 2386 i = 0; 2387 j = 0; 2388 while (i <= sc->maxid) { 2389 while (j < 8) { 2390 if (sc->devscan[i][j] == 1) { 2391 sc->devscan_end = 0; 2392 splx(s); 2393 goto exit; 2394 } else 2395 sc->devscan_end = 1; 2396 2397 j++; 2398 } 2399 j = 0; 2400 i++; 2401 } 2402 splx(s); 2403 } else { 2404 dcb->type = bval; 2405 if (bval == T_DIRECT || bval == T_OPTICAL) { 2406 if ((((ptr->version & 0x07) >= 2) || 2407 ((ptr->response_format & 0x0F) 2408 == 2)) && 2409 (ptr->flags3 & SID_CmdQue) && 2410 (dcb->tacfg & NTC_DO_TAG_QUEUING) && 2411 (dcb->tacfg & NTC_DO_DISCONNECT)) { 2412 dcb->maxcmd = sc->maxtag; 2413 dcb->mode |= EN_TAG_QUEUING; 2414 dcb->tagmask = 0; 2415 } else 2416 dcb->mode |= EN_ATN_STOP; 2417 } 2418 } 2419 /* srb->cmd[0] == INQUIRY */ 2420 } 2421 /* sc->devscan[id][lun] */ 2422 } 2423 exit: 2424 if (xs->datalen > 0) { 2425 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2426 srb->dmap->dm_mapsize, (xs->xs_control & XS_CTL_DATA_IN) ? 2427 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 2428 bus_dmamap_unload(sc->sc_dmat, srb->dmap); 2429 } 2430 trm_release_srb(sc, dcb, srb); 2431 trm_wait_srb(sc); 2432 xs->xs_status |= XS_STS_DONE; 2433 /* Notify cmd done */ 2434 scsipi_done(xs); 2435 } 2436 2437 static void 2438 trm_release_srb(sc, dcb, srb) 2439 struct trm_softc *sc; 2440 struct trm_dcb *dcb; 2441 struct trm_srb *srb; 2442 { 2443 struct trm_srb *psrb; 2444 int s; 2445 2446 s = splbio(); 2447 if (srb == dcb->gosrb) 2448 dcb->gosrb = srb->next; 2449 else { 2450 psrb = dcb->gosrb; 2451 while (psrb->next != srb) 2452 psrb = psrb->next; 2453 2454 psrb->next = srb->next; 2455 if (srb == dcb->last_gosrb) 2456 dcb->last_gosrb = psrb; 2457 } 2458 srb->next = sc->sc_freesrb; 2459 sc->sc_freesrb = srb; 2460 dcb->gosrb_cnt--; 2461 splx(s); 2462 return; 2463 } 2464 2465 static void 2466 trm_doing_srb_done(sc) 2467 struct trm_softc *sc; 2468 { 2469 struct trm_dcb *dcb, *pdcb; 2470 struct trm_srb *psrb, *psrb2; 2471 struct scsipi_xfer *xs; 2472 int i; 2473 2474 dcb = sc->sc_linkdcb; 2475 if (dcb == NULL) 2476 return; 2477 2478 pdcb = dcb; 2479 do { 2480 psrb = pdcb->gosrb; 2481 for (i = 0; i < pdcb->gosrb_cnt; i++) { 2482 psrb2 = psrb->next; 2483 xs = psrb->xs; 2484 xs->error = XS_TIMEOUT; 2485 /* ReleaseSRB( dcb, srb ); */ 2486 psrb->next = sc->sc_freesrb; 2487 sc->sc_freesrb = psrb; 2488 scsipi_done(xs); 2489 psrb = psrb2; 2490 } 2491 pdcb->gosrb_cnt = 0;; 2492 pdcb->gosrb = NULL; 2493 pdcb->tagmask = 0; 2494 pdcb = pdcb->next; 2495 } 2496 while (pdcb != dcb); 2497 } 2498 2499 static void 2500 trm_reset_scsi_bus(sc) 2501 struct trm_softc *sc; 2502 { 2503 bus_space_tag_t iot = sc->sc_iot; 2504 bus_space_handle_t ioh = sc->sc_ioh; 2505 int s; 2506 2507 s = splbio(); 2508 2509 sc->sc_flag |= RESET_DEV; 2510 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTSCSI); 2511 while ((bus_space_read_2(iot, ioh, TRM_SCSI_INTSTATUS) & 2512 INT_SCSIRESET) == 0) 2513 ; 2514 2515 splx(s); 2516 } 2517 2518 static void 2519 trm_scsi_reset_detect(sc) 2520 struct trm_softc *sc; 2521 { 2522 bus_space_tag_t iot = sc->sc_iot; 2523 bus_space_handle_t ioh = sc->sc_ioh; 2524 int s; 2525 2526 #ifdef TRM_DEBUG 2527 printf("trm_scsi_reset_detect...............\n"); 2528 #endif 2529 DELAY(1000000); /* delay 1 sec */ 2530 2531 s = splbio(); 2532 2533 bus_space_write_1(iot, ioh, TRM_DMA_CONTROL, STOPDMAXFER); 2534 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_CLRFIFO); 2535 2536 if (sc->sc_flag & RESET_DEV) { 2537 sc->sc_flag |= RESET_DONE; 2538 } else { 2539 sc->sc_flag |= RESET_DETECT; 2540 trm_reset_device(sc); 2541 /* trm_doing_srb_done( sc ); ???? */ 2542 trm_recover_srb(sc); 2543 sc->sc_actdcb = NULL; 2544 sc->sc_flag = 0; 2545 trm_wait_srb(sc); 2546 } 2547 splx(s); 2548 } 2549 2550 static void 2551 trm_request_sense(sc, dcb, srb) 2552 struct trm_softc *sc; 2553 struct trm_dcb *dcb; 2554 struct trm_srb *srb; 2555 { 2556 struct scsipi_xfer *xs = srb->xs; 2557 struct scsipi_sense *ss; 2558 int error, lun = xs->xs_periph->periph_lun; 2559 2560 srb->flag |= AUTO_REQSENSE; 2561 memcpy(srb->tempcmd, srb->cmd, sizeof(srb->tempcmd)); 2562 2563 srb->templen = srb->buflen; 2564 srb->tempsg.address = srb->sgentry[0].address; 2565 srb->tempsg.length = srb->sgentry[0].length; 2566 2567 /* Status of initiator/target */ 2568 srb->hastat = 0; 2569 srb->tastat = 0; 2570 2571 ss = (struct scsipi_sense *)srb->cmd; 2572 ss->opcode = REQUEST_SENSE; 2573 ss->byte2 = lun << SCSI_CMD_LUN_SHIFT; 2574 ss->unused[0] = ss->unused[1] = 0; 2575 ss->length = sizeof(struct scsipi_sense_data); 2576 ss->control = 0; 2577 2578 srb->buflen = sizeof(struct scsipi_sense_data); 2579 srb->sgcnt = 1; 2580 srb->sgindex = 0; 2581 srb->cmdlen = sizeof(struct scsipi_sense); 2582 2583 if ((error = bus_dmamap_load(sc->sc_dmat, srb->dmap, 2584 &xs->sense.scsi_sense, srb->buflen, NULL, 2585 BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 2586 printf("trm_request_sense: can not bus_dmamap_load()\n"); 2587 xs->error = XS_DRIVER_STUFFUP; 2588 return; 2589 } 2590 bus_dmamap_sync(sc->sc_dmat, srb->dmap, 0, 2591 srb->buflen, BUS_DMASYNC_PREREAD); 2592 2593 srb->sgentry[0].address = htole32(srb->dmap->dm_segs[0].ds_addr); 2594 srb->sgentry[0].length = htole32(sizeof(struct scsipi_sense_data)); 2595 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap, srb->sgoffset, 2596 TRM_SG_SIZE, BUS_DMASYNC_PREWRITE); 2597 2598 if (trm_start_scsi(sc, dcb, srb)) 2599 /* 2600 * If trm_start_scsi return 1: current interrupt status 2601 * is interrupt disreenable. It's said that SCSI processor 2602 * has more one SRB need to do. 2603 */ 2604 trm_rewait_srb(dcb, srb); 2605 } 2606 2607 static void 2608 trm_msgout_abort(sc, srb) 2609 struct trm_softc *sc; 2610 struct trm_srb *srb; 2611 { 2612 bus_space_tag_t iot = sc->sc_iot; 2613 bus_space_handle_t ioh = sc->sc_ioh; 2614 2615 srb->msgcnt = 1; 2616 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_SETATN); 2617 srb->dcb->flag &= ~ABORT_DEV_; 2618 } 2619 2620 /* 2621 * initialize the internal structures for a given DCB 2622 */ 2623 static void 2624 trm_init_dcb(sc, dcb, xs) 2625 struct trm_softc *sc; 2626 struct trm_dcb *dcb; 2627 struct scsipi_xfer *xs; 2628 { 2629 struct trm_nvram *eeprom; 2630 struct trm_dcb *tempdcb; 2631 int index, id, lun, s; 2632 2633 id = xs->xs_periph->periph_target; 2634 lun = xs->xs_periph->periph_lun; 2635 2636 s = splbio(); 2637 if (sc->sc_linkdcb == 0) { 2638 sc->sc_linkdcb = dcb; 2639 /* 2640 * RunRobin impersonate the role that let each device had 2641 * good proportion about SCSI command proceeding. 2642 */ 2643 sc->sc_roundcb = dcb; 2644 dcb->next = dcb; 2645 } else { 2646 tempdcb = sc->sc_linkdcb; 2647 /* search the last nod of DCB link */ 2648 while (tempdcb->next != sc->sc_linkdcb) 2649 tempdcb = tempdcb->next; 2650 2651 /* connect current DCB with last DCB tail */ 2652 tempdcb->next = dcb; 2653 /* connect current DCB tail to this DCB Q head */ 2654 dcb->next = sc->sc_linkdcb; 2655 } 2656 splx(s); 2657 2658 sc->devcnt++; 2659 dcb->id = id; 2660 dcb->lun = lun; 2661 dcb->waitsrb = NULL; 2662 dcb->gosrb = NULL; 2663 dcb->gosrb_cnt = 0; 2664 dcb->actsrb = NULL; 2665 dcb->tagmask = 0; 2666 dcb->maxcmd = 1; 2667 dcb->flag = 0; 2668 2669 eeprom = &sc->sc_eeprom; 2670 dcb->tacfg = eeprom->target[id].config0; 2671 /* 2672 * disconnect enable? 2673 */ 2674 dcb->idmsg = MSG_IDENTIFY(lun, dcb->tacfg & NTC_DO_DISCONNECT); 2675 /* 2676 * tag Qing enable? 2677 * wide nego, sync nego enable? 2678 */ 2679 dcb->synctl = 0; 2680 dcb->offset = 0; 2681 index = eeprom->target[id].period & 0x07; 2682 dcb->period = trm_clock_period[index]; 2683 dcb->mode = 0; 2684 if ((dcb->tacfg & NTC_DO_WIDE_NEGO) && (sc->sc_config & HCC_WIDE_CARD)) 2685 /* enable wide nego */ 2686 dcb->mode |= WIDE_NEGO_ENABLE; 2687 2688 if ((dcb->tacfg & NTC_DO_SYNC_NEGO) && (lun == 0 || sc->cur_offset > 0)) 2689 /* enable sync nego */ 2690 dcb->mode |= SYNC_NEGO_ENABLE; 2691 } 2692 2693 static void 2694 trm_link_srb(sc) 2695 struct trm_softc *sc; 2696 { 2697 struct trm_srb *srb; 2698 int i; 2699 2700 sc->sc_srb = malloc(sizeof(struct trm_srb) * TRM_MAX_SRB, 2701 M_DEVBUF, M_NOWAIT); 2702 if (sc->sc_srb == NULL) { 2703 printf("%s: can not allocate SRB\n", sc->sc_dev.dv_xname); 2704 return; 2705 } 2706 memset(sc->sc_srb, 0, sizeof(struct trm_srb) * TRM_MAX_SRB); 2707 2708 for (i = 0, srb = sc->sc_srb; i < TRM_MAX_SRB; i++, srb++) { 2709 srb->sgentry = sc->sc_sglist + TRM_MAX_SG_ENTRIES * i; 2710 srb->sgoffset = TRM_SG_SIZE * i; 2711 srb->sgaddr = sc->sc_dmamap->dm_segs[0].ds_addr + srb->sgoffset; 2712 /* 2713 * map all SRB space to SRB_array 2714 */ 2715 if (bus_dmamap_create(sc->sc_dmat, 2716 MAXPHYS, TRM_MAX_SG_ENTRIES, MAXPHYS, 0, 2717 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW, &srb->dmap)) { 2718 printf("%s: unable to create DMA transfer map...\n", 2719 sc->sc_dev.dv_xname); 2720 free(sc->sc_srb, M_DEVBUF); 2721 return; 2722 } 2723 if (i != TRM_MAX_SRB - 1) { 2724 /* 2725 * link all SRB 2726 */ 2727 srb->next = srb + 1; 2728 #ifdef TRM_DEBUG 2729 printf("srb->next = %8x ", (int) (srb + 1)); 2730 #endif 2731 } else { 2732 /* 2733 * load NULL to NextSRB of the last SRB 2734 */ 2735 srb->next = NULL; 2736 } 2737 #ifdef TRM_DEBUG 2738 printf("srb = %8x\n", (int) srb); 2739 #endif 2740 } 2741 return; 2742 } 2743 2744 /* 2745 * initialize the internal structures for a given SCSI host 2746 */ 2747 static void 2748 trm_init_sc(sc) 2749 struct trm_softc *sc; 2750 { 2751 bus_space_tag_t iot = sc->sc_iot; 2752 bus_space_handle_t ioh = sc->sc_ioh; 2753 struct trm_nvram *eeprom; 2754 int i, j; 2755 2756 eeprom = &sc->sc_eeprom; 2757 sc->maxid = 7; 2758 sc->sc_config = HCC_AUTOTERM | HCC_PARITY; 2759 if (bus_space_read_1(iot, ioh, TRM_GEN_STATUS) & WIDESCSI) { 2760 sc->sc_config |= HCC_WIDE_CARD; 2761 sc->maxid = 15; 2762 } 2763 if (eeprom->channel_cfg & NAC_POWERON_SCSI_RESET) 2764 sc->sc_config |= HCC_SCSI_RESET; 2765 2766 sc->sc_linkdcb = NULL; 2767 sc->sc_roundcb = NULL; 2768 sc->sc_actdcb = NULL; 2769 sc->sc_id = eeprom->scsi_id; 2770 sc->devcnt = 0; 2771 sc->maxtag = 2 << eeprom->max_tag; 2772 sc->sc_flag = 0; 2773 sc->devscan_end = 0; 2774 /* 2775 * link all device's SRB Q of this adapter 2776 */ 2777 trm_link_srb(sc); 2778 sc->sc_freesrb = sc->sc_srb; 2779 /* allocate DCB array for scan device */ 2780 for (i = 0; i <= sc->maxid; i++) 2781 if (sc->sc_id != i) 2782 for (j = 0; j < 8; j++) { 2783 sc->devscan[i][j] = 1; 2784 sc->devflag[i][j] = 0; 2785 sc->sc_dcb[i][j] = 2786 malloc(sizeof(struct trm_dcb), 2787 M_DEVBUF, M_WAITOK); 2788 } 2789 2790 #ifdef TRM_DEBUG 2791 printf("sizeof(struct trm_dcb)= %8x\n", sizeof(struct trm_dcb)); 2792 printf("sizeof(struct trm_softc)= %8x\n", sizeof(struct trm_softc)); 2793 printf("sizeof(struct trm_srb)= %8x\n", sizeof(struct trm_srb)); 2794 #endif 2795 sc->sc_adapter.adapt_dev = &sc->sc_dev; 2796 sc->sc_adapter.adapt_nchannels = 1; 2797 sc->sc_adapter.adapt_openings = TRM_MAX_SRB; 2798 sc->sc_adapter.adapt_max_periph = TRM_MAX_SRB; 2799 sc->sc_adapter.adapt_request = trm_scsipi_request; 2800 sc->sc_adapter.adapt_minphys = minphys; 2801 2802 sc->sc_channel.chan_adapter = &sc->sc_adapter; 2803 sc->sc_channel.chan_bustype = &scsi_bustype; 2804 sc->sc_channel.chan_channel = 0; 2805 sc->sc_channel.chan_ntargets = sc->maxid + 1; 2806 sc->sc_channel.chan_nluns = 8; 2807 sc->sc_channel.chan_id = sc->sc_id; 2808 } 2809 2810 /* 2811 * write sc_eeprom 128 bytes to seeprom 2812 */ 2813 static void 2814 trm_eeprom_write_all(sc, eeprom) 2815 struct trm_softc *sc; 2816 struct trm_nvram *eeprom; 2817 { 2818 bus_space_tag_t iot = sc->sc_iot; 2819 bus_space_handle_t ioh = sc->sc_ioh; 2820 u_int8_t *buf = (u_int8_t *)eeprom; 2821 u_int8_t addr; 2822 2823 /* Enable SEEPROM */ 2824 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2825 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2826 2827 /* 2828 * Write enable 2829 */ 2830 trm_eeprom_write_cmd(sc, 0x04, 0xFF); 2831 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2832 trm_wait_30us(); 2833 2834 for (addr = 0; addr < 128; addr++, buf++) 2835 trm_eeprom_set_data(sc, addr, *buf); 2836 2837 /* 2838 * Write disable 2839 */ 2840 trm_eeprom_write_cmd(sc, 0x04, 0x00); 2841 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2842 trm_wait_30us(); 2843 2844 /* Disable SEEPROM */ 2845 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2846 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2847 } 2848 2849 /* 2850 * write one byte to seeprom 2851 */ 2852 static void 2853 trm_eeprom_set_data(sc, addr, data) 2854 struct trm_softc *sc; 2855 u_int8_t addr; 2856 u_int8_t data; 2857 { 2858 bus_space_tag_t iot = sc->sc_iot; 2859 bus_space_handle_t ioh = sc->sc_ioh; 2860 int i; 2861 u_int8_t send; 2862 2863 /* 2864 * Send write command & address 2865 */ 2866 trm_eeprom_write_cmd(sc, 0x05, addr); 2867 /* 2868 * Write data 2869 */ 2870 for (i = 0; i < 8; i++, data <<= 1) { 2871 send = NVR_SELECT; 2872 if (data & 0x80) /* Start from bit 7 */ 2873 send |= NVR_BITOUT; 2874 2875 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2876 trm_wait_30us(); 2877 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2878 trm_wait_30us(); 2879 } 2880 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2881 trm_wait_30us(); 2882 /* 2883 * Disable chip select 2884 */ 2885 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2886 trm_wait_30us(); 2887 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2888 trm_wait_30us(); 2889 /* 2890 * Wait for write ready 2891 */ 2892 for (;;) { 2893 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2894 NVR_SELECT | NVR_CLOCK); 2895 trm_wait_30us(); 2896 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2897 trm_wait_30us(); 2898 if (bus_space_read_1(iot, ioh, TRM_GEN_NVRAM) & NVR_BITIN) 2899 break; 2900 } 2901 /* 2902 * Disable chip select 2903 */ 2904 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2905 } 2906 2907 /* 2908 * read seeprom 128 bytes to sc_eeprom 2909 */ 2910 static void 2911 trm_eeprom_read_all(sc, eeprom) 2912 struct trm_softc *sc; 2913 struct trm_nvram *eeprom; 2914 { 2915 bus_space_tag_t iot = sc->sc_iot; 2916 bus_space_handle_t ioh = sc->sc_ioh; 2917 u_int8_t *buf = (u_int8_t *)eeprom; 2918 u_int8_t addr; 2919 2920 /* 2921 * Enable SEEPROM 2922 */ 2923 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2924 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) | EN_EEPROM); 2925 2926 for (addr = 0; addr < 128; addr++, buf++) 2927 *buf = trm_eeprom_get_data(sc, addr); 2928 2929 /* 2930 * Disable SEEPROM 2931 */ 2932 bus_space_write_1(iot, ioh, TRM_GEN_CONTROL, 2933 bus_space_read_1(iot, ioh, TRM_GEN_CONTROL) & ~EN_EEPROM); 2934 } 2935 2936 /* 2937 * read one byte from seeprom 2938 */ 2939 static u_int8_t 2940 trm_eeprom_get_data(sc, addr) 2941 struct trm_softc *sc; 2942 u_int8_t addr; 2943 { 2944 bus_space_tag_t iot = sc->sc_iot; 2945 bus_space_handle_t ioh = sc->sc_ioh; 2946 int i; 2947 u_int8_t read, data = 0; 2948 2949 /* 2950 * Send read command & address 2951 */ 2952 trm_eeprom_write_cmd(sc, 0x06, addr); 2953 2954 for (i = 0; i < 8; i++) { /* Read data */ 2955 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 2956 NVR_SELECT | NVR_CLOCK); 2957 trm_wait_30us(); 2958 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 2959 /* 2960 * Get data bit while falling edge 2961 */ 2962 read = bus_space_read_1(iot, ioh, TRM_GEN_NVRAM); 2963 data <<= 1; 2964 if (read & NVR_BITIN) 2965 data |= 1; 2966 2967 trm_wait_30us(); 2968 } 2969 /* 2970 * Disable chip select 2971 */ 2972 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, 0); 2973 return (data); 2974 } 2975 2976 /* 2977 * write SB and Op Code into seeprom 2978 */ 2979 static void 2980 trm_eeprom_write_cmd(sc, cmd, addr) 2981 struct trm_softc *sc; 2982 u_int8_t cmd; 2983 u_int8_t addr; 2984 { 2985 bus_space_tag_t iot = sc->sc_iot; 2986 bus_space_handle_t ioh = sc->sc_ioh; 2987 int i; 2988 u_int8_t send; 2989 2990 /* Program SB+OP code */ 2991 for (i = 0; i < 3; i++, cmd <<= 1) { 2992 send = NVR_SELECT; 2993 if (cmd & 0x04) /* Start from bit 2 */ 2994 send |= NVR_BITOUT; 2995 2996 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 2997 trm_wait_30us(); 2998 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 2999 trm_wait_30us(); 3000 } 3001 3002 /* Program address */ 3003 for (i = 0; i < 7; i++, addr <<= 1) { 3004 send = NVR_SELECT; 3005 if (addr & 0x40) /* Start from bit 6 */ 3006 send |= NVR_BITOUT; 3007 3008 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send); 3009 trm_wait_30us(); 3010 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, send | NVR_CLOCK); 3011 trm_wait_30us(); 3012 } 3013 bus_space_write_1(iot, ioh, TRM_GEN_NVRAM, NVR_SELECT); 3014 trm_wait_30us(); 3015 } 3016 3017 /* 3018 * read seeprom 128 bytes to sc_eeprom and check checksum. 3019 * If it is wrong, updated with default value. 3020 */ 3021 static void 3022 trm_check_eeprom(sc, eeprom) 3023 struct trm_softc *sc; 3024 struct trm_nvram *eeprom; 3025 { 3026 struct nvram_target *target; 3027 u_int16_t *ep; 3028 u_int16_t chksum; 3029 int i; 3030 3031 #ifdef TRM_DEBUG 3032 printf("\n trm_check_eeprom......\n"); 3033 #endif 3034 trm_eeprom_read_all(sc, eeprom); 3035 ep = (u_int16_t *)eeprom; 3036 chksum = 0; 3037 for (i = 0; i < 64; i++) 3038 chksum += le16toh(*ep++); 3039 3040 if (chksum != TRM_NVRAM_CKSUM) { 3041 #ifdef TRM_DEBUG 3042 printf("TRM_S1040 EEPROM Check Sum ERROR (load default).\n"); 3043 #endif 3044 /* 3045 * Checksum error, load default 3046 */ 3047 eeprom->subvendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 3048 eeprom->subvendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 3049 eeprom->subsys_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 3050 eeprom->subsys_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 3051 eeprom->subclass = 0x00; 3052 eeprom->vendor_id[0] = PCI_VENDOR_TEKRAM2 & 0xFF; 3053 eeprom->vendor_id[1] = PCI_VENDOR_TEKRAM2 >> 8; 3054 eeprom->device_id[0] = PCI_PRODUCT_TEKRAM2_DC315 & 0xFF; 3055 eeprom->device_id[1] = PCI_PRODUCT_TEKRAM2_DC315 >> 8; 3056 eeprom->reserved0 = 0x00; 3057 3058 for (i = 0, target = eeprom->target; 3059 i < TRM_MAX_TARGETS; 3060 i++, target++) { 3061 target->config0 = 0x77; 3062 target->period = 0x00; 3063 target->config2 = 0x00; 3064 target->config3 = 0x00; 3065 } 3066 3067 eeprom->scsi_id = 7; 3068 eeprom->channel_cfg = 0x0F; 3069 eeprom->delay_time = 0; 3070 eeprom->max_tag = 4; 3071 eeprom->reserved1 = 0x15; 3072 eeprom->boot_target = 0; 3073 eeprom->boot_lun = 0; 3074 eeprom->reserved2 = 0; 3075 memset(eeprom->reserved3, 0, sizeof(eeprom->reserved3)); 3076 3077 chksum = 0; 3078 ep = (u_int16_t *)eeprom; 3079 for (i = 0; i < 63; i++) 3080 chksum += le16toh(*ep++); 3081 3082 chksum = TRM_NVRAM_CKSUM - chksum; 3083 eeprom->checksum0 = chksum & 0xFF; 3084 eeprom->checksum1 = chksum >> 8; 3085 3086 trm_eeprom_write_all(sc, eeprom); 3087 } 3088 } 3089 3090 /* 3091 * initialize the SCSI chip ctrl registers 3092 */ 3093 static void 3094 trm_init_adapter(sc) 3095 struct trm_softc *sc; 3096 { 3097 bus_space_tag_t iot = sc->sc_iot; 3098 bus_space_handle_t ioh = sc->sc_ioh; 3099 u_int8_t bval; 3100 3101 /* program configuration 0 */ 3102 bval = PHASELATCH | INITIATOR | BLOCKRST; 3103 if (sc->sc_config & HCC_PARITY) 3104 bval |= PARITYCHECK; 3105 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG0, bval); 3106 3107 /* program configuration 1 */ 3108 bus_space_write_1(iot, ioh, TRM_SCSI_CONFIG1, 3109 ACTIVE_NEG | ACTIVE_NEGPLUS); 3110 3111 /* 250ms selection timeout */ 3112 bus_space_write_1(iot, ioh, TRM_SCSI_TIMEOUT, SEL_TIMEOUT); 3113 3114 /* Mask all the interrupt */ 3115 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, 0); 3116 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 0); 3117 3118 /* Reset SCSI module */ 3119 bus_space_write_2(iot, ioh, TRM_SCSI_CONTROL, DO_RSTMODULE); 3120 3121 /* program Host ID */ 3122 bus_space_write_1(iot, ioh, TRM_SCSI_HOSTID, sc->sc_id); 3123 3124 /* set ansynchronous transfer */ 3125 bus_space_write_1(iot, ioh, TRM_SCSI_OFFSET, 0); 3126 3127 /* Trun LED control off */ 3128 bus_space_write_2(iot, ioh, TRM_GEN_CONTROL, 3129 bus_space_read_2(iot, ioh, TRM_GEN_CONTROL) & ~EN_LED); 3130 3131 /* DMA config */ 3132 bus_space_write_2(iot, ioh, TRM_DMA_CONFIG, 3133 bus_space_read_2(iot, ioh, TRM_DMA_CONFIG) | DMA_ENHANCE); 3134 3135 /* Clear pending interrupt status */ 3136 bus_space_read_1(iot, ioh, TRM_SCSI_INTSTATUS); 3137 3138 /* Enable SCSI interrupt */ 3139 bus_space_write_1(iot, ioh, TRM_SCSI_INTEN, 3140 EN_SELECT | EN_SELTIMEOUT | EN_DISCONNECT | EN_RESELECTED | 3141 EN_SCSIRESET | EN_BUSSERVICE | EN_CMDDONE); 3142 bus_space_write_1(iot, ioh, TRM_DMA_INTEN, EN_SCSIINTR); 3143 } 3144 3145 /* 3146 * initialize the internal structures for a given SCSI host 3147 */ 3148 static int 3149 trm_init(sc) 3150 struct trm_softc *sc; 3151 { 3152 bus_dma_segment_t seg; 3153 int error, rseg, all_sgsize; 3154 3155 /* 3156 * EEPROM CHECKSUM 3157 */ 3158 trm_check_eeprom(sc, &sc->sc_eeprom); 3159 /* 3160 * MEMORY ALLOCATE FOR ADAPTER CONTROL BLOCK 3161 * allocate the space for all SCSI control blocks (SRB) for DMA memory 3162 */ 3163 all_sgsize = TRM_MAX_SRB * TRM_SG_SIZE; 3164 if ((error = bus_dmamem_alloc(sc->sc_dmat, all_sgsize, PAGE_SIZE, 3165 0, &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 3166 printf("%s: unable to allocate SCSI REQUEST BLOCKS, " 3167 "error = %d\n", sc->sc_dev.dv_xname, error); 3168 return (-1); 3169 } 3170 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 3171 all_sgsize, (caddr_t *) &sc->sc_sglist, 3172 BUS_DMA_NOWAIT | BUS_DMA_COHERENT)) != 0) { 3173 printf("%s: unable to map SCSI REQUEST BLOCKS, " 3174 "error = %d\n", sc->sc_dev.dv_xname, error); 3175 return (-1); 3176 } 3177 if ((error = bus_dmamap_create(sc->sc_dmat, all_sgsize, 1, 3178 all_sgsize, 0, BUS_DMA_NOWAIT, &sc->sc_dmamap)) != 0) { 3179 printf("%s: unable to create SRB DMA maps, " 3180 "error = %d\n", sc->sc_dev.dv_xname, error); 3181 return (-1); 3182 } 3183 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, 3184 sc->sc_sglist, all_sgsize, NULL, BUS_DMA_NOWAIT)) != 0) { 3185 printf("%s: unable to load SRB DMA maps, " 3186 "error = %d\n", sc->sc_dev.dv_xname, error); 3187 return (-1); 3188 } 3189 #ifdef TRM_DEBUG 3190 printf("\n\n%s: all_sgsize=%x\n", sc->sc_dev.dv_xname, all_sgsize); 3191 #endif 3192 memset(sc->sc_sglist, 0, all_sgsize); 3193 trm_init_sc(sc); 3194 trm_init_adapter(sc); 3195 trm_reset(sc); 3196 return (0); 3197 } 3198 3199 /* 3200 * attach and init a host adapter 3201 */ 3202 static void 3203 trm_attach(parent, self, aux) 3204 struct device *parent; 3205 struct device *self; 3206 void *aux; 3207 { 3208 struct pci_attach_args *const pa = aux; 3209 struct trm_softc *sc = (void *) self; 3210 bus_space_tag_t iot; /* bus space tag */ 3211 bus_space_handle_t ioh; /* bus space handle */ 3212 pci_intr_handle_t ih; 3213 pcireg_t command; 3214 const char *intrstr; 3215 3216 /* 3217 * These cards do not allow memory mapped accesses 3218 * pa_pc: chipset tag 3219 * pa_tag: pci tag 3220 */ 3221 command = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG); 3222 if ((command & (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) != 3223 (PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE)) { 3224 command |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MASTER_ENABLE; 3225 pci_conf_write(pa->pa_pc, pa->pa_tag, 3226 PCI_COMMAND_STATUS_REG, command); 3227 } 3228 /* 3229 * mask for get correct base address of pci IO port 3230 */ 3231 if (pci_mapreg_map(pa, PCI_MAPREG_START, PCI_MAPREG_TYPE_IO, 0, 3232 &iot, &ioh, NULL, NULL)) { 3233 printf("%s: unable to map registers\n", sc->sc_dev.dv_xname); 3234 return; 3235 } 3236 /* 3237 * test checksum of eeprom..& initial "ACB" adapter control block... 3238 */ 3239 sc->sc_iot = iot; 3240 sc->sc_ioh = ioh; 3241 sc->sc_dmat = pa->pa_dmat; 3242 if (trm_init(sc)) { 3243 /* 3244 * Error during initialization! 3245 */ 3246 printf(": Error during initialization\n"); 3247 return; 3248 } 3249 /* 3250 * Now try to attach all the sub-devices 3251 */ 3252 if (sc->sc_config & HCC_WIDE_CARD) 3253 printf(": Tekram DC395UW/F (TRM-S1040) Fast40 " 3254 "Ultra Wide SCSI Adapter\n"); 3255 else 3256 printf(": Tekram DC395U, DC315/U (TRM-S1040) Fast20 " 3257 "Ultra SCSI Adapter\n"); 3258 3259 printf("%s: Adapter ID=%d, Max tag number=%d, %d SCBs\n", 3260 sc->sc_dev.dv_xname, sc->sc_id, sc->maxtag, TRM_MAX_SRB); 3261 /* 3262 * Now tell the generic SCSI layer about our bus. 3263 * map and establish interrupt 3264 */ 3265 if (pci_intr_map(pa, &ih)) { 3266 printf("%s: couldn't map interrupt\n", sc->sc_dev.dv_xname); 3267 return; 3268 } 3269 intrstr = pci_intr_string(pa->pa_pc, ih); 3270 3271 if (pci_intr_establish(pa->pa_pc, ih, IPL_BIO, trm_intr, sc) == NULL) { 3272 printf("%s: couldn't establish interrupt", sc->sc_dev.dv_xname); 3273 if (intrstr != NULL) 3274 printf(" at %s", intrstr); 3275 printf("\n"); 3276 return; 3277 } 3278 if (intrstr != NULL) 3279 printf("%s: interrupting at %s\n", 3280 sc->sc_dev.dv_xname, intrstr); 3281 config_found(&sc->sc_dev, &sc->sc_channel, scsiprint); 3282 } 3283 3284 /* 3285 * match pci device 3286 */ 3287 static int 3288 trm_probe(parent, match, aux) 3289 struct device *parent; 3290 struct cfdata *match; 3291 void *aux; 3292 { 3293 struct pci_attach_args *pa = aux; 3294 3295 if (PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TEKRAM2) 3296 switch (PCI_PRODUCT(pa->pa_id)) { 3297 case PCI_PRODUCT_TEKRAM2_DC315: 3298 return (1); 3299 } 3300 return (0); 3301 } 3302
Indexes created Thu Sep 25 02:09:54 GMT 2025